SST39VF100-70-4I-B3KE [SILICON]
Flash, 64KX16, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, MO-210AB-1, TFBGA-48;型号: | SST39VF100-70-4I-B3KE |
厂家: | SILICON |
描述: | Flash, 64KX16, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, MO-210AB-1, TFBGA-48 内存集成电路 |
文件: | 总22页 (文件大小:691K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1 Mbit (64K x16) Multi-Purpose Flash
SST39LF100 / SST39VF100
SST39LF/VF1003.0 & 2.7V 1Mb (x16) MPF memories
Data Sheet
FEATURES:
•
•
Organized as 64K x16
Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF100
– 2.7-3.6V for SST39VF100
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
– Active Current: 20 mA (typical)
– Standby Current: 3 µA (typical)
•
Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 1 second (typical)
•
•
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Sets
Packages Available
•
•
Sector-Erase Capability
– Uniform 2 KWord sectors
Fast Read Access Time
– 40-lead TSOP (10mm x 14mm)
– 48-ball TFBGA (6mm x 8mm)
– 45 ns for SST39LF100
– 70 ns for SST39VF100
•
Latched Address and Data
PRODUCT DESCRIPTION
The SST39LF/VF100 devices are 64K x16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39LF/VF100 write (Pro-
gram or Erase) with a single voltage power supply of 3.0-
3.6V and 2.7-3.6V, respectively.
performance and reliability, while lowering power consump-
tion. The SST39LF/VF100 inherently use less energy dur-
ing Erase and Program than alternative flash technologies.
The total energy consumed is a function of the applied volt-
age, current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. The SST39LF/
VF100 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
Featuring high performance Word-Program, the
SST39LF/VF100 devices provide a typical Word-Program
time of 14 µsec. The devices use Toggle Bit or Data# Poll-
ing to detect the completion of the Program or Erase oper-
ation. To protect against inadvertent write, the SST39LF/
VF100 have on-chip hardware and software data protec-
tion schemes. Designed, manufactured, and tested for a
wide spectrum of applications, the SST39LF/VF100 are
offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
The SST39LF/VF100 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, the SST39LF/VF100 significantly improve
To meet surface mount requirements, the SST39LF/VF100
are offered in 40-lead TSOP and 48-ball TFBGA packages.
See Figure 1 for pinout.
©2002 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Multi-Purpose Flash and MPF are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71129-02-000 2/02
1
363
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address lines
A11-A15 are used to determine the sector address. The
sector address is latched on the falling edge of the sixth
WE# pulse, while the command (30H) is latched on the ris-
ing edge of the sixth WE# pulse. The internal Erase opera-
tion begins after the sixth WE# pulse. The End-of-Erase
operation can be determined using either Data# Polling or
Toggle Bit methods. See Figure 8 for timing waveforms.
Any commands issued during the Sector-Erase operation
are ignored.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF/VF100 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is deselected and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 2).
Chip-Erase Operation
The SST39LF/VF100 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 7 for timing diagram,
and Figure 16 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Word-Program Operation
The SST39LF/VF100 are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 20
µs. See Figures 3 and 4 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 13 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored.
Write Operation Status Detection
The SST39LF/VF100 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 2 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
2
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST39LF/VF100 are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase opera-
tion, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling
timing diagram and Figure 14 for a flowchart.
The SST39LF/VF100 provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST39LF/VF100 devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode within TRC. The
contents of DQ15-DQ8 can be VIL or VIH, but no other value,
during any SDP command sequence.
Product Identification
Toggle Bit (DQ6)
The Product Identification mode identifies the devices as
SST39LF/VF100 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple manu-
facturers in the same socket. For details, see Table 4 for
software operation, Figure 9 for the Software ID Entry and
Read timing diagram, and Figure 15 for the Software ID
Entry command sequence flowchart.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or
Chip-Erase, the Toggle Bit is valid after the rising edge of
sixth WE# (or CE#) pulse. See Figure 6 for Toggle Bit tim-
ing diagram and Figure 14 for a flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Data Protection
The SST39LF/VF100 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Manufacturer’s ID
Device ID
0000H
00BFH
SST39LF/VF100
0001H
2788H
T1.3 363
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to Read mode. Please
note that the Software ID Exit command is ignored during
an internal Program or Erase operation. See Table 4 for
software command codes, Figure 10 for timing waveform,
and Figure 15 for a flowchart.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent Writes during power-up or power-down.
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
3
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SuperFlash
Memory
X-Decoder
A -A
0 15
Address Buffer & Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ - DQ
15
0
363 ILL B1.2
A9
A10
A11
A12
A13
A14
A15
NC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Standard Pinout
WE#
9
V
10
11
12
13
14
15
16
17
18
19
20
DD
NC
Top View
Die Up
CE#
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
SST39LF100/SST39VF100
363 ILL F01.3
TOP VIEW (balls facing down)
SST39LF/VF100
6
5
4
3
2
1
A13 A12 A14 A15 NC NC DQ15 V
SS
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# NC
NC NC
A7 NC
NC
NC
A6
A2
NC DQ5 DQ12
V
DQ4
DD
NC DQ2 DQ10 DQ11 DQ3
A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A1
A0 CE# OE# V
SS
A
B
C
D
E F G H
FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP AND 48-BALL TFBGA
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
4
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A15-A0
Address Inputs
To provide memory addresses.
During Sector-Erase A15-A11 address lines will select the sector.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
3.0-3.6V for SST39LF100
2.7-3.6V for SST39VF100
VSS
NC
Ground
No Connection
Unconnected pins.
T2.2 363
TABLE 3: OPERATION MODES SELECTION
Mode
Read
CE# OE# WE# DQ
Address
AIN
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
DOUT
DIN
X1
Program
Erase
AIN
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.2 363
1. X can be VIL or VIH, but no other value.
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
5555H AAH 2AAAH 55H 5555H A0H Data
WA3
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Word-Program
Sector-Erase
Chip-Erase
4
SAX
30H
Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit7
Software ID Exit7
XXH
F0H
5555H AAH 2AAAH 55H 5555H F0H
T4.5 363
1. Address format A14-A0 (Hex), Addresses A15 can be VIL or VIH, but no other value, for the Command sequence
2. DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A15-A11 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With A15-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39LF/VF100 Device ID = 2788H, is read with A0 = 1
7. Both Software ID Exit operations are equivalent
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
5
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE: SST39LF100
OPERATING RANGE: SST39VF100
Range
Ambient Temp
VDD
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
0°C to +70°C
3.0-3.6V
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF100
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF100
See Figures 11 and 12
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
6
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF100 AND 2.7-3.6V FOR SST39VF100
Limits
Symbol Parameter
Min
Max Units Test Conditions
Address input=VIL/VIH, at f=1/TRC Min,
IDD
Power Supply Current
VDD=VDD Max
Read
30
30
20
1
mA
mA
µA
µA
µA
CE#=OE#=VIL,WE#=VIH, all I/Os open
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
Program and Erase
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
ISB
ILI
ILO
10
0.8
VIL
VIH
VIHC
VOL
VOH
0.7VDD
V
V
V
V
VDD=VDD Max
VDD-0.3
VDD=VDD Max
0.2
IOL=5.8 mA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
VDD-0.2
T5.5 363
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
µs
µs
1
TPU-WRITE
100
T6.0 363
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T7.0 363
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.1 363
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
7
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF100 AND 2.7-3.6V FOR SST39VF100
SST39LF100-45 SST39VF100-70
Symbol
TRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
45
70
TCE
Chip Enable Access Time
Address Access Time
45
45
20
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
TCLZ
0
0
0
0
ns
1
TOLZ
ns
1
TCHZ
15
15
20
20
ns
1
TOHZ
ns
1
TOH
0
0
ns
T9.4 363
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter
Min
Max
Units
TBP
Word-Program Time
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
TAH
TCS
TCH
TOES
TOEH
TCP
0
0
10
40
40
30
30
30
0
TWP
WE# Pulse Width
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
1
TCPH
TDS
1
TDH
Data Hold Time
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
TSE
TBE
Block-Erase
25
TSCE
Chip-Erase
100
T10.1 363
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
8
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
T
T
AA
RC
ADDRESS A
15-0
CE#
OE#
T
CE
T
OE
T
T
OHZ
V
IH
OLZ
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
363 ILL F03.1
FIGURE 2: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
15-0
T
AH
T
DH
T
WP
WE#
OE#
CE#
T
T
AS
DS
T
WPH
T
CH
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
363 ILL F04.2
Note: X can be V or V , but no other value
IL IH
FIGURE 3: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
15-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
T
CH
WE#
T
CS
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
WORD
(ADDR/DATA)
363 ILL F05.2
Note: X can be V or V , but no other value
IL IH
FIGURE 4: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
15-0
T
CE
CE#
T
OES
T
OEH
OE#
WE#
T
OE
DQ
7
DATA
DATA#
DATA#
DATA
363 ILL F06.1
FIGURE 5: DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
ADDRESS A
15-0
T
CE
CE#
T
OES
T
T
OE
OEH
OE#
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
363 ILL F07.1
FIGURE 6: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
15-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
363 ILL F08.5
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and
CE# signals are interchageable as long as minimum timings are met. (See Table 10)
X can be V or V , but no other value.
IL IH
FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
2AAA 5555 5555 2AAA
5555
SA
X
ADDRESS A
15-0
CE#
OE#
T
WP
WE#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
363 ILL F18.4
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 10)
SA = Sector Address
X
X can be V or V , but no other value.
IL IH
FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX90
SW2
00BFH
Device ID
363 ILL F09.4
Device ID = 2788H for SST39LF/VF100
X can be V or V , but no other value.
IL IH
FIGURE 9: SOFTWARE ID ENTRY AND READ
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
DQ
14-0
XXAA
XX55
XXF0
15-0
T
IDA
CE#
OE#
T
WP
WE#
T
WHP
363 ILL F10.1
SW0
SW1
SW2
X can be V or V , but no other value.
IL IH
FIGURE 10: SOFTWARE ID EXIT
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
V
IHT
V
V
IT
INPUT
REFERENCE POINTS
OUTPUT
OT
V
ILT
363 ILL F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 11: AC INPUT/OUTPUT REFERENCE WAVEFORMS
1.3 V
1N914
TO TESTER
3.3 KΩ
TO DUT
C
L
363 ILL F12.2
FIGURE 12: A TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
363 ILL F13.3
X can be V or V but no other value.
IL IH
FIGURE 13: WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
363 ILL F14.0
FIGURE 14: WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Software ID Entry
Software ID Exit
Command Sequence
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait T
IDA
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait T
Wait T
IDA
IDA
Return to normal
operation
Read Software ID
363 ILL F15.2
X can be V or V , but no other value.
IL
IH
FIGURE 15: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
17
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Chip-Erase
Sector-Erase
Command Sequence
Command Sequence
Load data: XXAA
Address: 5555
Load data: XXAA
Address: 5555
Load data: XX55
Address: 2AAA
Load data: XX55
Address: 2AAA
Load data: XX80
Address: 5555
Load data: XX80
Address: 5555
Load data: XXAA
Address: 5555
Load data: XXAA
Address: 5555
Load data: XX55
Address: 2AAA
Load data: XX55
Address: 2AAA
Load data: XX10
Address: 5555
Load data: XX30
Address: SA
X
Wait T
Wait T
SE
SCE
Chip erased
to FFFFH
Sector erased
to FFFFH
X can be V or V , but no other value.
363 ILL F16.3
IL
IH
FIGURE 16: ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST39xF100
-
XXX
-
XX
-
XX
Package Modifier
I = 40 leads
K = 48 balls
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
W = TSOP (type 1, die up, 10mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
45 = 45 ns
70 = 70 ns
Device Density
100 = 1 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Valid combinations for SST39LF100
SST39LF100-45-4C-WI SST39LF100-45-4C-B3K
Valid combinations for SST39VF100
SST39VF100-70-4C-WI
SST39VF100-70-4I-WI
SST39VF100-70-4C-B3K
SST39VF100-70-4I-B3K
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
10.10
9.90
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
40-tsop-WI-7
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM
SST PACKAGE CODE: WI
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
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1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
BOTTOM VIEW
8.00 0.20
5.60
0.80
TOP VIEW
0.45 0.05
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
48-tfbga-B3K-6x8-450mic-2
1mm
SEATING PLANE
0.35 0.05
Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1',
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. The actual shape of the corners may be slightly different than as portrayed in the drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
21
1 Mbit Multi-Purpose Flash
SST39LF100 / SST39VF100
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2002 Silicon Storage Technology, Inc.
S71129-02-000 2/02 363
22
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