SST49LF004B-33-4C-WHE [SILICON]
Flash, 512KX8, 11ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, MO-142BA, TSOP1-32;
| 型号： | SST49LF004B-33-4C-WHE |
| 厂家： | 
SILICON |
| 描述： | Flash, 512KX8, 11ns, PDSO32, 8 X 14 MM, ROHS COMPLIANT, MO-142BA, TSOP1-32 光电二极管 内存集成电路 |
| 文件： | 总39页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 Mbit LPC Firmware Flash
SST49LF004B
SST49LF004B4Mb LPC Firmware memory
Data Sheet
FEATURES:
•
•
SST49LF004B: 512K x8 (4 Mbit)
•
•
Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
Conforms to Intel LPC Interface Specification 1.1
– Supports Single-Byte LPC Memory and
Firmware Memory Cycle Types
production programming
•
Flexible Erase Capability
LPC Interface Mode
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
– 5-signal LPC bus interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Registers for individual block
write-lock and lock-down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
•
•
Single 3.0-3.6V Read and Write Operations
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
•
•
Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
•
Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming in-system on
programmer equipment
•
•
CMOS and PCI I/O Compatibility
Packages Available
– 32-lead PLCC
– 40-lead TSOP (10mm x 20mm)
PRODUCT DESCRIPTION
The SST49LF004B flash memory device is designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS applications. The
SST49LF004B device complies with Intel’s LPC Interface
Specification 1.1, supporting single-byte Firmware Memory
and LPC Memory cycle types.
pared with alternative approaches. The SST49LF004B
device significantly improves performance and reliability,
while lowering power consumption. The SST49LF004B
device writes (Program or Erase) with a single 3.0-3.6V
power supply.
The SST49LF004B provides a maximum Byte-Program
time of 20 µsec. The entire memory can be erased and
programmed byte-by-byte in 8 seconds when using status
detection features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent writes, the SST49LF004B device has
on-chip hardware and software write protection schemes. It
is offered with a typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST49LF004B is backward compatible to the
SST49LF00xA Firmware Hub and the SST49LF0x0A LPC
Flash. In this document, FWH mode in the SST49LF00xA
specification is referenced as the Firmware Memory Read/
Write cycle and LPC mode in the SST49LF0x0A specifica-
tion is referenced as the LPC Memory Read/Write cycle.
Two interface modes are supported by the SST49LF004B:
LPC mode (Firmware Memory and LPC Memory cycle
types) for in-system operations and Parallel Programming
(PP) mode to interface with programming equipment.
The SST49LF004B uses less energy during Erase and
Program than alternative flash memory technologies. The
total energy consumed is a function of the applied voltage,
current and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
The SST49LF004B flash memory device is manufactured
with SST’s proprietary, high-performance SuperFlash tech-
nology. The split-gate cell design and thick-oxide tunneling
injector attain greater reliability and manufacturability com-
©2003 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
S71232-02-000
1
12/03
These specifications are subject to change without notice.
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies.
or hardware does not have to be calibrated or correlated to
the cumulative number of Erase cycles as is necessary
with alternative flash memory technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. This means the system software
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input Communication Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Mode Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Identification Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect / Top Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Row / Column Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
No Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DEVICE MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PRODUCT IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MODE SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
2
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Firmware Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LPC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LPC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Response to Invalid Fields for Firmware Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Response to Invalid Fields for LPC
Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Protection (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Characteristics (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC Characteristics (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
3
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LIST OF FIGURES
FIGURE 1: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 2: Pin Assignments for 40-lead TSOP (10mm x 20mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FIGURE 3: Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FIGURE 4: Firmware Memory Read Cycle Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FIGURE 5: Firmware Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FIGURE 6: LPC Memory Read Cycle Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FIGURE 7: LPC Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FIGURE 8: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FIGURE 9: Output Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIGURE 10: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FIGURE 11: Reset Timing Diagram (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FIGURE 12: Reset Timing Diagram (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIGURE 13: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 14: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
FIGURE 15: Data# Polling Timing Diagram (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 16: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FIGURE 17: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 18: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
FIGURE 19: Block-Erase Timing Diagram (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 20: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FIGURE 21: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 22: Software ID Exit (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIGURE 23: AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FIGURE 24: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
4
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LIST OF TABLES
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TABLE 3: Firmware and LPC Memory Cycles START Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 5: Firmware Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 6: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 7: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 8: Firmware Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 9: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 10: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 11: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 12: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TABLE 13: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 14: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 15: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 16: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 17: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 18: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TABLE 19: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 20: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 21: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 22: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 23: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TABLE 24: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 25: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 26: Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
5
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
TBL#
WP#
INIT#
SuperFlash
Memory
X-Decoder
LAD[3:0]
LCLK
FWH/LPC
Address Buffers & Latches
LFRAME#
Interface
Y-Decoder
ID[3:0]
GPI[4:0]
R/C#
I/O Buffers and Data Latches
Control Logic
A[10:0]
Programmer
DQ[7:0]
Interface
OE#
WE#
MODE RST#
1232 ILL B1.0
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
6
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
PIN ASSIGNMENTS
4
3
2
1
32 31 30
29
5
A7(GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
MODE (MODE)
(V
6
28
27
26
25
24
23
22
21
V
)
SS SS
7
NC
NC
8
32-lead PLCC
Top View
9
V
(V )
DD DD
10
11
12
13
A2 (ID2)
OE# (INIT#)
WE# (LFRAME#)
NC
A1 (ID1)
A0 (ID0)
DQ0 (LAD0)
DQ7 (RES)
14 15 16 17 18 19 20
1232 32-plcc P1.0
( ) Designates LPC Mode
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
V
NC (NC)
MODE (MODE)
NC (NC)
SS
DD
2
3
(LFRAME#) WE#
(INIT#) OE#
(NC) NC
4
NC (NC)
5
NC (NC)
6
(RES) DQ7
(RES) DQ6
(RES) DQ5
(RES) DQ4
(NC) NC
NC (NC)
7
A10 (GPI4)
NC (NC)
8
Standard Pinout
Top View
9
R/C# (LCLK)
10
11
12
13
14
15
16
17
18
19
20
V
DD
NC (NC)
RST# (RST#)
NC (NC)
V
SS
V
SS
Die Up
(LAD3) DQ3
(LAD2) DQ2
(LAD1) DQ1
(LAD0) DQ0
(ID0) A0
NC (NC)
A9 (GPI3)
A8 (GPI2)
A7 (GPI1)
A6 (GPI0)
A5 (WP#)
A4 (TBL#)
(ID1) A1
(ID2) A2
(ID3) A3
1232 40-tsop P2.0
( ) Designates LPC Mode
FIGURE 2: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM X 20MM)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
7
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
PIN DESCRIPTIONS
TABLE 1: PIN DESCRIPTION
Interface
Symbol
LCLK
Pin Name
Type1 PP LPC Functions
Clock
I
X
X
To provide a clock input to the control unit
LAD[3:0]
Address and
Data
I/O
To provide LPC bus information such as addresses and command
inputs/outputs data.
LFRAME# Frame
I
I
X
X
To indicate start of a data transfer operation; also used to abort an LPC
cycle in progress.
MODE
Interface
X
X
This pin determines which interface is operational. When held high, program-
mer mode is enabled and when held low, LPC mode is enabled. This pin must
be set at power-up or before returning from reset and must not change during
device operation. This pin must be held high (VIH) for PP mode and low (VIL)
for LPC mode. This pin is internally pulled-down with a resistor between 20-
100 KΩ.
Mode Select
RST#
INIT#
Reset
I
I
X
X
To reset the operation of the device
Initialize
This is the second reset pin for in-system use.
This pin functions identically to RST#.
ID[3:0]
Identification
Inputs
I
X
These four pins are part of the mechanism that allows multiple parts to be
attached to the same bus. The strapping of these pins is used to identify the
component. The boot device must have ID[3:0]=0000, all subsequent devices
should use sequential count-up strapping. These pins are internally pulled-down
with a resistor between 20-100 KΩ.
GPI[4:0]
General
Purpose Inputs
I
X
These individual inputs can be used for additional board flexibility. The state of
these pins can be read through LPC registers. These inputs should be at their
desired state before the start of the LPC clock cycle during which the read is
attempted, and should remain in place until the end of the Read cycle.
Unused GPI pins must not be floated.
TBL#
WP#
Top Block Lock
Write Protect
I
I
X
X
When low, prevents programming to the boot block sectors at the top of the
device memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
When low, prevents programming to all but the highest addressable blocks.
When WP# is high it disables hardware write protection for these blocks. This
pin cannot be left unconnected.
R/C#
Row/Column
Select
I
I
X
X
Select for the Programming interface, this pin determines whether the
address pins are pointing to the row addresses, or to the column addresses.
A10-A0
Address
Inputs for low-order addresses during Read and Write operations. Addresses
are internally latched during a Write cycle. For the programming interface,
these addresses are latched by R/C# and share the same pins as the high-
order address inputs.
DQ7-DQ0 Data
I/O
X
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# is high.
OE#
WE#
RES
VDD
VSS
Output Enable
I
I
X
X
To gate the data output buffers.
To control the Write operations.
These pins must be left unconnected.
To provide power supply (3.0-3.6V)
Circuit ground (0V reference)
Write Enable
Reserved
X
X
X
Power Supply
Ground
PWR
PWR
X
X
NC
No Connection
N/A N/A Unconnected pins.
T1.0 1232
1. I = Input, O = Output
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
8
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Clock
General Purpose Inputs
The LCLK pin accepts a clock input from the host controller.
The General Purpose Inputs (GPI[4:0]) can be used as dig-
ital inputs for the CPU to read. The GPI register holds the
values on these pins. The data on the GPI pins must be
stable before the start of a GPI register Read and remain
stable until the Read cycle is complete. The pins must be
driven low, VIL, or high, VIH but not left unconnected (float).
Input/Output Communications
The LAD[3:0] pins are used to serially communicate cycle
information such as cycle type, cycle direction, ID selection,
address, data, and sync fields.
Write Protect / Top Block Lock
Input Communication Frame
The Top Boot Lock (TBL#) and Write Protect (WP#) pins
are provided for hardware write protection of device mem-
ory in the SST49LF004B. The TBL# pin is used to write pro-
tect 64 KByte at the highest memory address range for the
SST49LF004B. WP# pin write protects the remaining sec-
tors in the flash memory. An active low signal at the TBL#
pin prevents Program and Erase operations of the top boot
block. When TBL# pin is held high, the hardware write pro-
tection of the top boot block is disabled. The WP# pin
serves the same function for the remaining blocks of the
device memory. The TBL# and WP# pins write protection
functions operate independently of one another. Both TBL#
and WP# pins must be set to their required protection states
prior to starting a Program or Erase operation. A logic level
change occurring at the TBL# or WP# pin during a Program
or Erase operation could cause unpredictable results.
The LFRAME# pin is used to indicate start of a LPC bus
cycle. The pin is also used to abort an LPC bus cycle in
progress.
Interface Mode Select
The MODE pin is used to set the interface mode. If the
mode pin is set to logic high, the device is in PP mode. If
the mode pin is set low, the device is in the LPC mode. The
mode selection pin must be configured prior to device oper-
ation. The mode pin is internally pulled down if the pin is left
unconnected.
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT#
and RST# pins have the same function internally. It is
required to drive INIT# or RST# pins low during a system
reset to ensure proper CPU initialization. During a Read
operation, driving INIT# or RST# pins low deselects the
device and places the output drivers, LAD[3:0], in a high
impedance state. The reset signal must be held low for a
minimum of time TRSTP. A reset latency occurs if a reset pro-
cedure is performed during a Program or Erase operation.
See Table 22 and Table 23, Reset Timing Parameters, for
more information. A device reset during an active Program
or Erase operation will abort the operation and memory
contents may become invalid due to data being altered or
corrupted from an incomplete Erase or Program operation.
Row / Column Select
The R/C# pin is used to control the multiplex address
inputs in Parallel Programming (PP) mode. The column
addresses are mapped to the higher internal addresses
(A18-11), and the row addresses are mapped to the lower
internal address (A10-0).
Output Enable
The OE# pin is used to gate the output data buffers in PP
mode.
Write Enable
Identification Inputs
The WE# pin is used to control the write operations in PP
mode.
These pins are part of a mechanism that allows multiple
devices to be attached to the same bus. The strapping of
these pins is used to identify the component. The boot
device must have ID[3:0] = 0; all subsequent devices
should use sequential count-up strapping. These pins are
internally pulled-down with a resistor between 20-100 KΩ.
No Connection
These pins are not connected internally.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
9
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
DEVICE MEMORY MAP
7FFFFH
Boot Block
TBL#
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
70000H
6FFFFH
60000H
5FFFFH
50000H
4FFFFH
40000H
3FFFFH
WP#
30000H
2FFFFH
20000H
1FFFFH
10000H
0F000H
0EFFFH
03000H
02000H
01000H
00000H
4 KByte Sector 15
Block 0
(64 KByte)
4 KByte Sector 2
4 KByte Sector 1
4 KByte Sector 0
1232 F02.0
FIGURE 3: DEVICE MEMORY MAP
DESIGN CONSIDERATIONS
PRODUCT IDENTIFICATION
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
The Product Identification mode identifies the device as the
SST49LF004B and manufacturer as SST.
VSS less than 1 cm away from the VDD pin of the device.
Additionally, a low frequency 4.7 µF electrolytic capacitor
from VDD to VSS should be placed within 1 cm of the VDD
pin. If a socket is used for programming purposes, an addi-
tional 1-10 µF should be added next to each socket.
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
PP Mode
LPC Mode1
Manufacturer’s ID
Device ID
0000H
FFBC 0000H BFH
The RST# and INIT# pins must remain stable at VIH for the
entire duration of an Erase or Program operation. WP#
must remain stable at VIH for the entire duration of the
Erase and Program operations for non-Boot Block sectors.
To write data to the top Boot Block sectors, the TBL# pin
must also remain stable at VIH for the entire duration of the
Erase and Program operations.
SST49LF004B
0001H
FFBC 0001H 60H2
T2.0 1232
1. Address shown in this column is for boot device only.
Address locations should appear elsewhere in the 4
GByte system memory map depending on ID strapping
values on ID[3:0] pins when multiple LPC memory
devices are used in a system.
2. The device ID for SST49LF004B is the same as
SST49LF004A.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
10
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
MODE SELECTION
LPC MODE
The SST49LF004B flash memory device operates in two
distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. In LPC mode, communication
between the Host and the SST49LF004B occurs via the 4-
bit I/O communication signals, LAD[3:0], and LFRAME#. In
PP mode, the device is controlled via the 11 addresses,
A10-A0, and 8 I/O, DQ7-DQ0, signals. The address inputs
are multiplexed in row and column selected by control sig-
nal R/C# pin. The row addresses are mapped to the lower
internal addresses (A10-0), and the column addresses are
mapped to the higher internal addresses (A18-11). See Fig-
ure 3, Device Memory Map, for address assignments.
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF004B supports both single-byte Firmware
Memory Read/Write cycles and single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification, Revision 1.1. The host drives
LFRAME# low for one or more clock cycles to initiate an
LPC cycle. The last latched value of LAD[3:0] before
LFRAME# is the START value. The START value deter-
mines whether the SST49LF004B will respond to a Firm-
ware Memory Read/Write cycle or a LPC Memory Read/
Write cycle as defined in Table 3.
TABLE 3: FIRMWARE AND LPC MEMORY CYCLES
START FIELD DEFINITION
START
Value Definition
0000
Start of an LPC memory cycle. The direction
(Read or Write) is determined by the second field
of the LPC cycle.
1101
1110
Start of a Firmware Memory Read cycle
Start of a Firmware Memory Write cycle
T3.0 1232
See following sections for details of Firmware Memory and
LPC Memory cycle types. JEDEC standard SDP (Soft-
ware Data Protection) Program and Erase command
sequences are used to initiate Firmware and LPC Memory
Program and Erase operations. See Table 12 for a listing
of Program and Erase commands. Chip-Erase is only
available in PP mode.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
11
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Firmware Memory Read Cycle
TABLE 4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
LAD[3:0]
Direction
Field Contents
LAD[3:0]1
Comments
1
START
1101
IN
LFRAME# must be active (low) for the device to respond.
Only the last field latched before LFRAME# transitions high
will be recognized. The START field contents (1101b) indi-
cate a Firmware Memory Read cycle.
2
IDSEL
MADDR
MSIZE
TAR0
0000 to 1111
YYYY
IN
IN
IN
Indicates which SST49LF004B device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], the device
will respond to the LPC bus cycle.
3-9
10
11
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
0000 (1 Byte)
1111
The MSIZE field indicates how many bytes will be trans-
ferred during multi-byte operations. The SST49LF004B only
supports single-byte operation. MSIZE=0000b
IN then Float In this clock cycle, the master (Intel ICH) has driven the bus
to all ‘1’s and then floats the bus, prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
12
13
TAR1
1111 (float)
Float then
OUT
The SST49LF004B takes control of the bus during this
cycle.
RSYNC
0000 (READY)
OUT
During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input
data.
14
15
16
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
OUT
OUT
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
OUT then
Float
In this clock cycle, the SST49LF004B drives the bus to all
ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then IN The host resumes control of the bus during this cycle.
T4.0 1232
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
DATA
D[3:0] D[7:4]
Start
IDSEL
0000b
MADDR
MSIZE TAR0 TAR1 RSYNC
0000b 1111b Tri-State 0000b
1101b
A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
A[3:0]
TAR
LAD[3:0]
1232 F03.0
FIGURE 4: FIRMWARE MEMORY READ CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
12
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Firmware Memory Write Cycle
TABLE 5: FIRMWARE MEMORY WRITE CYCLE
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
LAD[3:0]
Direction
Comments
1
START
1110
IN
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (1110b) indicate a Firmware Memory Write
cycle.
2
IDSEL
0000 to 1111
IN
Indicates which SST49LF004B device should
respond. If the IDSEL (ID select) field matches the
value of ID[3:0], the device will respond to the mem-
ory cycle.
3-9
10
MADDR
MSIZE
YYYY
IN
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
0000 (1 Byte)
The MSIZE field indicates how many bytes will be
transferred during multi-byte operations. The device
only supports single-byte writes. MSIZE=0000b
11
12
13
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
IN
IN
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
IN then Float
In this clock cycle, the host drives the bus to all '1's and
then floats the bus prior to the next clock cycle. This is
the first part of the bus “turnaround cycle.”
14
15
TAR1
1111 (float)
0000
Float then OUT The SST49LF004B takes control of the bus during this
cycle.
RSYNC
OUT
During this clock cycle, the device generates a “ready
sync” (RSYNC) indicating that the device has received
the input data.
16
TAR0
1111
OUT then Float In this clock cycle, the SST49LF004B drives the bus to
all '1's and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle.”
17
TAR1
1111 (float)
Float then IN
The host resumes control of the bus during this cycle.
T5.0 1232
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
Start
IDSEL
0000b
MADDR
MSIZE
0000b
DATA
D[7:4]
TAR0 TAR1 RSYNC
1111b Tri-State 0000b
1110b
A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
A[3:0]
TAR
D[3:0]
LAD[3:0]
1232 F04.0
FIGURE 5: FIRMWARE MEMORY WRITE CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
13
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LPC Memory Read Cycle
TABLE 6: LPC MEMORY READ CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
LAD[3:0]
Direction
Field Contents
LAD[3:0]1
Comments
1
START
0000
IN
LFRAME# must be active (low) for the device to respond. Only
the last field latched before LFRAME# transitions high will be
recognized. The START field contents (0000b) indicate an LPC
Memory cycle.
2
CYCTYPE
+ DIR
010X
IN
IN
Indicates the type of LPC Memory cycle. Bits 3:2 must be “01b” for
memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is
reserved.
3-10
ADDR
YYYY
Address Phase for Memory Cycle. LPC protocol supports a 32-
bit address phase. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
11
12
13
TAR0
TAR1
SYNC
1111
1111 (float)
0000
IN
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
then Float
Float
then OUT
The SST49LF004B takes control of the bus during this cycle.
OUT
The SST49LF004B outputs the value 0000b indicating that it
has received data.
14
15
16
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
OUT
OUT
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
IN
In this clock cycle, the host drives the bus to all 1s and then
floats the bus. This is the first part of the bus “turnaround cycle.”
then Float
17
TAR1
1111 (float)
Float
The SST49LF004B takes control of the bus during this cycle.
then OUT
T6.0 1232
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
CYCTYPE
+
Start
Address
TAR0
TAR1
Sync
Data
DIR
0000b 010Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Address in 8 Clocks
A[7:4]
A[3:0]
1111b Tri-State 0000b
2 Clocks
D[3:0]
D[7:4]
TAR
LAD[3:0]
1 Clock Data Out 2 Clocks
1232 F05.1
FIGURE 6: LPC MEMORY READ CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
14
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
LPC Memory Write Cycle
TABLE 7: LPC MEMORY WRITE CYCLE FIELD DEFINITIONS
Clock
Cycle
Field
Name
Field Contents
LAD[3:0]1
LAD[3:0]
Direction
Comments
1
START
0000
IN
LFRAME# must be active (low) for the device to
respond. Only the last field latched before LFRAME#
transitions high will be recognized. The START field
contents (0000b) indicate an LPC Memory cycle.
2
CYCTYPE +
DIR
011X
IN
IN
Indicates the type of LPC Memory cycle. Bits 3:2
must be “01b” for memory cycle. Bit 1 indicates the
type of transfer “1” for Write. Bit 0 is reserved.
3-10
ADDR
YYYY
Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of
the entire address. Addresses are transferred most
significant nibble first.
11
12
13
DATA
DATA
TAR0
ZZZZ
ZZZZ
1111
IN
IN
IN
ZZZZ is the least-significant nibble of the data byte.
ZZZZ is the most-significant nibble of the data byte.
In this clock cycle, the host drives the bus to all '1's and
then floats the bus. This is the first part of the bus “turn-
around cycle.”
14
15
16
TAR1
SYNC
TAR0
1111 (float)
0000
Float then OUT The SST49LF004B takes control of the bus during this
cycle.
OUT
The SST49LF004B outputs the values 0000, indicating
that it has received data or a flash command.
1111
OUT then Float In this clock cycle, the SST49LF004B drives the bus to
all '1's and then floats the bus. This is the first part of
the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then IN
Host resumes control of the bus during this cycle.
T7.0 1232
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
CYCTYPE
+
Start
Address
Data
Data
TAR0
TAR1
Sync
DIR
TAR
0000b 011Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4]
Load Address in 8 Clocks
A[3:0]
D[3:0] D[7:4]
1111b Tri-State 0000b
2 Clocks 1 Clock
LAD[3:0]
Load Data in 2 Clocks
1232 F06.1
FIGURE 7: LPC MEMORY WRITE CYCLE WAVEFORM
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
15
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Abort Mechanism
Response to Invalid Fields for LPC
Memory Cycle
If LFRAME# is driven low for one or more clock cycles after
the start of a bus cycle, the cycle will be terminated. The
host may drive LAD[3:0] with '1111b' (ABORT nibble) to
return the interface to ready mode. The ABORT only
affects the current bus cycle. For a multi-cycle command
sequence, such as the Erase or Program SDP commands,
ABORT doesn't interrupt the entire command sequence,
only the current bus cycle of the command sequence. The
host can re-send the bus cycle for the aborted command
and continue the SDP command sequence after the device
is ready again.
ID mismatch: ID information is included in the address bits
of every LPC Memory cycle. Address bits A23, A21:A19 are
used to select the device with proper IDs. The
SST49LF004B will compare the ID bits in the address field
with ID[3:0]. If the ID bits in the address do not correspond
to the hardware ID pins the device will ignore the cycle. See
Multiple Device Selection section for details.
Address out of range: The address sequence is 8 fields
long (32 bits). Address bits A23, A21:A19 are used to select
the device with proper IDs. The SST49LF004B responds to
address range FFFF FFFFH to FF80 0000H and
000F FFFFH to 000E 0000H during LPC memory cycle
transfers. Address A22 has the special function of directing
reads and writes to the flash core (A22=1) or to the register
space (A22=0).
Response to Invalid Fields for Firmware
Memory Cycle
The SST49LF004B will not explicitly indicate that it has
received invalid field sequences. The response to specific
invalid fields or sequences is as follows:
Once valid START, CYCTYPE + DIR, and address range
(including ID bits) are received, the SST49LF004B will
always complete the bus cycle. However, if the device is
busy performing a flash Erase or Program operation, no
new internal Write command (memory Write or register
Write) will be executed. As long as the states of LAD[3:0]
and LFRAME# are known, the response of the
SST49LF004B to signals received during the LPC cycle
should be predictable.
ID mismatch: If the IDSEL field does not match ID[3:0],
the device will ignore the cycle. See Multiple Device Selec-
tion section for details.
Address out of range: The address sequence is 7
fields long (28 bits) for Firmware Memory bus cycles, but
only A22 and A18:A0 will be decoded by SST49LF004B.
Address A22 has the special function of directing reads and
writes to the flash core (A22=1) or to the register space
(A22=0).
Invalid MSIZE field: If the device receives an invalid
MSIZE field during a Firmware Memory Read or Write
cycle, the device will reset and no operation will be
attempted. The SST49LF004B will not generate any kind
of response in this situation. Invalid size fields for a Firm-
ware Memory cycle are any data other than 0000b.
Once valid START, IDSEL, and MSIZE fields are received,
the SST49LF004B will always complete the bus cycle.
However, if the device is busy performing a flash Erase or
Program operation, no new Write command (memory write
or register write) will be executed.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
16
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Multiple Device Selection for LPC Memory Cycle
Multiple Device Selection
For LPC Memory Read/Write cycles, ID information is
included in the address bits of every cycle. The ID bits in
the address field are the inverse of the hardware strapping.
The address bits (A23, A21:A19) are used to select the
device with proper IDs. See Table 9 for multiple device
selection configurations. The SST49LF004B will compare
these bits with ID[3:0]’s strapping values. If there is a mis-
match, the device will ignore the remainder of the cycle.
Multiple LPC flash devices may be strapped to increase
memory densities in a system. The four ID pins, ID[3:0],
allow up to 16 devices to be attached to the same bus by
using different ID strapping in a system. BIOS support, bus
loading, or the attaching bridge may limit this number. The
boot device must have an ID of 0000b (determined by
ID[3:0]); subsequent devices use incremental numbering.
Equal density must be used with multiple devices.
Multiple Device Selection for
Firmware Memory Cycle
TABLE 9: LPC MEMORY MULTIPLE DEVICE
SELECTION CONFIGURATION
For Firmware Memory Read/Write cycles, hardware strap-
ping values on ID[3:0] must match the values in IDSEL
field. See Table 8 for multiple device selection configura-
tions. The SST49LF004B will compare the IDSEL field with
ID[3:0]'s strapping values. If there is a mismatch, the device
will ignore the reminder of the cycle.
Device #
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A23, A21:A19
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
0 (Boot device)
1
2
3
4
5
TABLE 8: FIRMWARE MEMORY MULTIPLE DEVICE
SELECTION CONFIGURATION
6
7
Device #
ID[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IDSEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8
0 (Boot device)
9
1
10
11
12
13
14
15
2
3
4
5
6
7
T9.0 1232
8
9
10
11
12
13
14
15
T8.0 1232
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
17
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
isters appear at their respective address location in the 4
GByte system memory map. Unused register locations will
read as 00H. Any attempt to read or write any register dur-
ing an internal Write operation will be ignored.
Write Operation Status Detection
The SST49LF004B device provides two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling, D[7],
and Toggle Bit, D[6]. The End-of-Write detection mode is
incorporated into the Firmware Memory and LPC Memory
Read cycles. The actual completion of the nonvolatile write
is asynchronous with the system. Therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either D[7] or D[6]. In order to prevent
spurious rejection, if an erroneous result occurs, the soft-
ware routine should include a loop to read the accessed
location an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise
the rejection is valid.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes
the state of GPI[4:0] to the outputs. It is recommended that
the GPI[4:0] pins are in the desired state before LFRAME#
is brought low for the beginning of the bus cycle, and remain
in that state until the end of the cycle. There is no default
value since this is a pass-through register. The GPI register
for the boot device appears at FFBC0100H in the 4 GByte
system memory map, and will appear elsewhere if the
device is not the boot device. The register is not available to
be read when the device is in Erase/Program operation.
Block Locking Registers
SST49LF004B provides software controlled lock protection
through a set of Block Locking registers. The Block Locking
registers are Read/Write registers and are accessible
through standard addressable memory locations specified
in Table 10 and Table 11. Unused register locations will
read as 00H.
Data# Polling
When the SST49LF004B device is in the internal Program
operation, any attempt to read D[7] will produce the com-
plement of the true data. Once the Program operation is
completed, D[7] will produce true data. Note that even
though D[7] may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid. Valid data will appear on
the entire data bus in subsequent successive Read cycles
after an interval of 1 µs. During an internal Erase operation,
any attempt to read D[7] will produce a '0'. Once the inter-
nal Erase operation is completed, D[7] will produce a '1'.
Proper status will not be given using Data# Polling if the
address is in the invalid range.
Write Lock: The Write-Lock bit, bit 0, controls the lock
state. The default Write status of all blocks after power up is
write locked. When bit 0 of the Block Locking register is set,
Program and Erase operations for the corresponding block
are prevented. Clearing the Write-Lock bit will unprotect the
block. The Write-Lock bit must be cleared prior to starting a
Program or Erase operation since it is sampled at the
beginning of the operation. The Write-Lock bit functions in
conjunction with the hardware Write Lock pin TBL# for the
top Boot Block. When TBL# is low, it overrides the software
locking scheme. The top Boot Block Locking register does
not indicate the state of the TBL# pin. The Write-Lock bit
functions in conjunction with the hardware WP# pin for
blocks 0 to 6. When WP# is low, it overrides the software
locking scheme. The Block Locking registers do not indi-
cate the state of the WP# pin.
Toggle Bit
During the internal Program or Erase operation, any consec-
utive attempts to read D[6] will produce alternating 0s and
1s, i.e., toggling between 0 and 1. When the internal Pro-
gram or Erase operation is completed, the toggling will stop.
Note that even though D[6] may have valid data immediately
following the completion of an internal Write operation, the
remaining data outputs may still be invalid. Valid data will
appear on the entire data bus in subsequent successive
Read cycles after an interval of 1 µs. Proper status will not be
given using Toggle Bit if the address is in the invalid range.
Lock Down: The Lock-Down bit, bit 1, controls the Block
Locking registers. The default Lock Down status of all
blocks upon power-up is not locked down. Once the Lock-
Down bit is set, any future attempted changes to that Block
Locking register will be ignored. The Lock-Down bit is only
cleared upon a device reset with RST# or INIT# or power
down. Current Lock Down status of a particular block can
be determined by reading the corresponding Lock-Down
bit.
Registers
There are three types of registers available on the
SST49LF004B, the General Purpose Inputs register, Block
Locking registers, and the JEDEC ID registers. These reg-
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
18
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
TABLE 10: BLOCK LOCKING REGISTERS
Protected Memory
Address Package
Memory Map
Register
Block Size
Register Address
FFBF0002H
FFBE0002H
FFBD0002H
FFBC0002H
FFBB0002H
FFBA0002H
FFB90002H
FFB80002H
T_BLOCK_LK
T_MINUS01_LK
T_MINUS02_LK
T_MINUS03_LK
T_MINUS04_LK
T_MINUS05_LK
T_MINUS06_LK
T_MINUS07_LK
64K
64K
64K
64K
64K
64K
64K
64K
07FFFFH - 070000H
06FFFFH - 060000H
05FFFFH - 050000H
04FFFFH - 040000H
03FFFFH - 030000H
02FFFFH - 020000H
01FFFFH - 010000H
00FFFFH - 000000H
T10.0 1232
TABLE 11: BLOCK LOCKING REGISTER BITS
Reserved Bit [7..2]
000000
Lock-Down Bit [1]
Write-Lock Bit [0]
Lock Status
Full Access
0
0
1
1
0
1
0
1
000000
Write Locked (Default State at Power-Up)
Locked Open (Full Access Locked Down)
000000
000000
Write Locked Down
T11.0 1232
JEDEC ID Registers
The JEDEC ID registers provide access to the manufac-
turer and device ID information with a single Read cycle.
The JEDEC ID registers for the boot device appear at
FFBC0000H and FFBC0001H in the 4 GByte system
memory map, and will appear elsewhere if the device is not
the boot device. Registers are not available for read when
the device is in Erase/Program operation. Refer to Table 2
for product identification information.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
19
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
PARALLEL PROGRAMMING MODE
Block-Erase Operation
Device Operation
The Block-Erase Operation allows the system to erase any
of the 8 uniform 64 KByte blocks. The Block- Erase opera-
tion is initiated by executing a six-byte command load
sequence for Software Data Protection with Block-Erase
command (50H) and block address (BA) in the last bus
cycle. The internal Block-Erase operation begins after the
sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Fig-
ure 19 for timing waveforms. Any commands written during
the Block- Erase operation will be ignored.
Commands are used to initiate the memory operation func-
tions of the device. The data portion of the software com-
mand sequence is latched on the rising edge of WE#.
During the software command sequence the row address
is latched on the falling edge of R/C# and the column
address is latched on the rising edge of R/C#.
Read
The Read operation of the SST49LF004B device is con-
trolled by OE#. OE# is the output control and is used to
gate data from the output pins. Refer to the Read cycle tim-
ing diagram, Figure 13, for further details.
Chip-Erase Operation
The SST49LF004B device provides a Chip-Erase opera-
tion only in PP mode, which allows the user to erase the
entire memory array to the '1's state. This is useful when
the entire device must be quickly erased. The Chip-Erase
operation is initiated by executing a six- byte Software Data
Protection command sequence with Chip- Erase com-
mand (10H) with address 5555H in the last bus cycle. The
internal Erase operation begins with the rising edge of the
sixth WE#. During the internal Erase operation, the only
valid reads are Toggle Bit or Data# Polling. See Table 13 for
the command sequence, Figure 20 for timing diagram. Any
commands written during the Chip-Erase operation will be
ignored.
Reset
A VIL on RST# pin initiates a device reset.
Byte-Program Operation
The SST49LF004B device is programmed on a byte-by-
byte basis. Before programming, one must ensure that the
byte that is being programmed is fully erased. The Byte-
Program operation is initiated by executing a four-byte com-
mand load sequence for Software Data Protection with
address (PA) and data in the last bus cycle. During the
Byte-Program operation, the row address (A10-A0) is
latched on the falling edge of R/C# and the column
Address (A21-A11) is latched on the rising edge of R/C#.
The data bus is latched on the rising edge of WE#. The
Program operation, once initiated, will be completed, within
20 µs. See Figure 17 for timing waveforms. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands written
during the internal Program operation will be ignored.
Write Operation Status Detection
The SST49LF004B device provides two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE# which ini-
tiates the internal Program or Erase operation.
Sector-Erase Operation
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, the device
has completed the Write cycle, otherwise the rejection is
valid.
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Fig-
ure 18 for Sector-Erase timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
20
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
TABLE 12: OPERATION MODES SELECTION (PP MODE)
Mode
Read
RST#
VIH
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIH
VIH
VIH
AIN
VIH
VIL
Sector or Block address,
XXH for Chip-Erase
Reset
VIL
VIH
VIH
X
X
High Z
X
X
Write Inhibit
Product Identification
VIL
VIL
VIH
VIH
High Z/DOUT
Manufacturer’s ID (BFH) A18 - A1 = VIL, A0 = VIL
Device ID (60H) A18 - A1 = VIL, A0 = VIH
T12.0 1232
1. X can be VIL or VIH, but no other value.
Data# Polling (DQ7)
Data Protection (PP Mode)
When the SST49LF004B device is in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid. Valid data will appear on
the entire data bus in subsequent successive Read cycles
after an interval of 1 µs. During an internal Erase operation,
any attempt to read DQ7 will produce a '0'. Once the inter-
nal Erase operation is completed, DQ7 will produce a '1'.
Data# Polling is valid after the rising edge of the fourth WE#
pulse for the Program operation. For Sector-Erase, Block-
Erase, or Chip-Erase, the Data# Polling is valid after the ris-
ing edge of the sixth WE# pulse. See Figure 15 for Data#
Polling timing diagram. Proper status will not be given using
Data# Polling if the address is in the invalid range.
The SST49LF004B device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
Software Data Protection (SDP)
The SST49LF004B provides the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tion, i.e., Program and Erase. Any Program operation
requires the inclusion of a series of three-byte sequence.
The three-byte load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inadvert-
ent Write operations, e.g., during the system power-up or
power down. Any Erase operation requires the inclusion of
a five-byte load sequence.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating '0's
and '1's, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of the fourth WE#
pulse for Program operation. For Sector-Erase, Block-
Erase or Chip-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# pulse. See Figure 16 for Toggle Bit
timing diagram.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
21
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
SOFTWARE COMMAND SEQUENCE
TABLE 13: SOFTWARE COMMAND SEQUENCE
1st1
2nd1
3rd1
4th1
5th1
6th1
Cycle
Addr2
Cycle
Addr2
Cycle
Addr2
Cycle
Addr2
Cycle
Addr2
Cycle
Addr2
Command
Sequence
Data
Data
Data
Data
Data
Data
YYYY 5555H
YYYY 5555H
YYYY 5555H
YYYY 5555H
YYYY 5555H
AAH
YYYY 2AAAH
YYYY 2AAAH
YYYY 2AAAH
YYYY 2AAAH
YYYY 2AAAH
55H
YYYY 5555H
YYYY 5555H
YYYY 5555H
YYYY 5555H
YYYY 5555H
A0H
PA3
Data
Byte-Program
Sector-Erase
Block-Erase
Chip-Erase6
4
5
AAH
AAH
AAH
AAH
55H
55H
55H
55H
80H
80H
80H
90H
YYYY 5555H
YYYY 5555H
YYYY 5555H
AAH
AAH
AAH
YYYY 2AAAH
YYYY 2AAAH
YYYY 2AAAH
55H
55H
55H
SAX
BAX
30H
50H
10H
YYYY 5555H
Read ID7
Software
ID Entry
XXXX XXXXH
YYYY 5555H
F0H
AAH
Software
ID Exit8
YYYY 2AAAH
55H
YYYY 5555H
F0H
Software
ID Exit8
T13.0 1232
1. LPC mode use consecutive Write cycles to complete a command sequence; PP mode use consecutive bus cycles to complete a
command sequence.
2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within valid memory address range, see Address
out of range section for details. In PP mode, YYYY can be VIL or VIH, but no other value.
3. PA = Program Byte address
4. SAX for Sector-Erase Address
5. BAX for Block-Erase Address
6. Chip-Erase is supported in PP mode only
7. SST Manufacturer’s ID = BFH, is read with A18-A0 = 0.
SST49LF004B Device ID = 60H, is read with A18-A1 = 0, A0 = 1.
8. Both Software ID Exit operations are equivalent
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
22
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
ELECTRICAL SPECIFICATIONS
The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) are defined in Sec-
tion 4.2.2.4 of the PCI local bus specification, Rev. 2.1. Refer to Table 14 for the DC voltage and current specifications.
Refer to Tables 18 through 24 for the AC timing specifications for Clock, Read, Write, and Reset operations.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
VDD
Commercial
0°C to +85°C
3.0-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 23 and 24
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
23
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
DC Characteristics
TABLE 14: DC OPERATING CHARACTERISTICS (ALL INTERFACES)
Limits
Symbol Parameter
Min
Max
Units Test Conditions
1
IDD
Active VDD Current
LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT
at f=33 MHz (LPC mode) or 1/TRC min (PP mode)
All other inputs=VIL or VIH
Read
Write2
12
30
mA All outputs = open, VDD=VDD Max
mA See Note 2
ISB
Standby VDD Current
(LPC Interface)
100
µA
LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT
at f=33 MHz (LPC mode) or 1/TRC min (PP mode)
LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD
,
VDD=VDD Max, All other inputs ≥ 0.9 VDD or ≤0.1 VDD
3
IRY
Input Current for Mode
and
ID[3:0] pins
10
mA LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT
at f=33 MHz (LPC mode) or 1/TRC min (PP mode)
LFRAME#=VIL, f=33 MHz, VDD=VDD Max
All other inputs ≥ 0.9 VDD or ≤0.1 VDD
II
Input Leakage Current for
Mode
200
µA
VIN=GND to VDD, VDD=VDD Max
and ID[3:0] pins
ILI
Input Leakage Current
Output Leakage Current
INIT# Input High Voltage
INIT# Input Low Voltage
Input Low Voltage
1
1
µA
µA
V
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Max
ILO
VIHI
VILI
VIL
1.1
-0.5
-0.5
VDD+0.5
0.4
V
VDD=VDD Min
0.3 VDD
V
VDD=VDD Min
VIH
VOL
VOH
Input High Voltage
0.5 VDD VDD+0.5
0.1 VDD
V
VDD=VDD Max
Output Low Voltage
Output High Voltage
V
0.9 VDD
V
T14.2 1232
1. IDD active while a Read or Write (Program or Erase) operation is in progress.
2. For PP mode: OE# = WE# = VIH; For LPC mode: f = 1/TRC min, LFRAME# = VIH.
3. The device is in Ready mode when no activity is on the LPC bus.
TABLE 15: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T15.0 1232
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 16: PIN CAPACITANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O=0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN=0V
12 pF
T16.0 1232
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
24
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
TABLE 17: RELIABILITY CHARACTERISTICS
Minimum
Symbol
Parameter
Endurance
Data Retention
Latch Up
Specification
Units
Cycles
Years
mA
Test Method
1
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard 78
1
TDR
1
ILTH
100 + IDD
T17.0 1232
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 18: CLOCK TIMING PARAMETERS (LPC MODE)
Symbol
TCYC
THIGH
TLOW
-
Parameter
Min
30
11
11
1
Max
Units
ns
LCLK Cycle Time
LCLK High Time
ns
LCLK Low Time
ns
LCLK Slew Rate (peak-to-peak)
RST# or INIT# Slew Rate
4
V/ns
-
50
mV/ns
T18.0 1232
T
cyc
T
high
0.6 V
DD
T
low
0.5 V
DD
0.4 V
(minimum)
p-to-p
DD
0.4 V
DD
0.3 V
DD
0.2 V
DD
1232 F07.0
FIGURE 8: LCLK WAVEFORM (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
25
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
AC Characteristics (LPC Mode)
TABLE 19: READ/WRITE CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (LPC MODE)
Symbol
TCYC
TSU
Parameter
Min
30
7
Max
Units
ns
Clock Cycle Time
Data Set Up Time to Clock Rising
Clock Rising to Data Hold Time
Clock Rising to Data Valid
Byte Programming Time
ns
TDH
0
ns
1
TVAL
2
11
20
25
25
ns
TBP
TSE
TBE
TON
TOFF
µs
Sector-Erase Time
ms
ms
ns
Block-Erase Time
Clock Rising to Active (Float to Active Delay)
Clock Rising to Inactive (Active to Float Delay)
2
28
ns
T19.0 1232
1. Minimum and maximum times have different loads. See PCI spec
TABLE 20: AC INPUT/OUTPUT SPECIFICATIONS (LPC MODE)
Symbol
IOH(AC)
Parameter
Min
Max
Units
Conditions
Switching Current High
-12 VDD
mA
mA
0 < VOUT ≤0.3VDD
0.3VDD < VOUT < 0.9VDD
0.7VDD < VOUT < VDD
-17.1(VDD-VOUT
)
Equation C1
-32 VDD
(Test Point)
mA
VOUT = 0.7VDD
IOL(AC)
Switching Current Low
16 VDD
26.7 VOUT
Equation D1
mA
mA
VDD >VOUT ≥ 0.6VDD
0.6VDD > VOUT > 0.1VDD
0.18VDD > VOUT > 0
(Test Point)
38 VDD
mA
mA
VOUT = 0.18VDD
ICL
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-25+(VIN+1)/0.015
-3 < VIN ≤-1
ICH
25+(VIN-VDD-1)/0.015
mA
VDD+4 > VIN ≥ VDD+1
0.2VDD-0.6VDD load
0.6VDD-0.2VDD load
slewr
slewf
1
1
4
4
V/ns
V/ns
T20.0 1232
1. See PCI spec.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
26
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
V
V
TH
TL
V
TEST
LCLK
T
VAL
LAD [3:0]
(Valid Output Data)
LAD [3:0]
(Float Output Data)
T
ON
T
OFF
1232 F09.0
FIGURE 9: OUTPUT TIMING PARAMETERS (LPC MODE)
V
V
TH
TL
V
TEST
LCLK
T
SU
T
DH
LAD [3:0]
Inputs
Valid
V
MAX
(Valid Input Data)
1232 F10.0
FIGURE 10: INPUT TIMING PARAMETERS (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
27
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
TABLE 21: INTERFACE MEASUREMENT CONDITION PARAMETERS (LPC MODE)
Symbol
Value
0.6 VDD
0.2 VDD
0.4 VDD
0.4 VDD
1
Units
1
VTH
V
V
V
V
1
VTL
VTEST
1
VMAX
Input Signal Edge Rate
V/ns
T21.0 1232
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more over-
drive than this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use
different voltage values, but must correlate results back to these parameters.
TABLE 22: RESET TIMING PARAMETERS, VDD=3.0-3.6V (LPC MODE)
Symbol
TPRST
Parameter
Min
1
Max
Units
ms
µs
VDD stable to Reset Low
TKRST
TRSTP
TRSTF
Clock Stable to Reset Low
RST# Pulse Width
100
100
ns
RST# Low to Output Float
RST# High to LFRAME# Low
RST# Low to reset during Sector-/Block-Erase or Program
48
10
ns
1
TRST
1
µs
TRSTE
µs
T22.0 1232
1. There will be a latency due to TRSTE if a reset procedure is performed during a Program or Erase operation,
V
DD
T
PRST
CLK
T
KRST
T
RSTP
RST#/INIT#
Sector-/Block-Erase
T
RSTE
or Program operation
aborted
T
RST
T
RSTF
LAD[3:0]
LFRAME#
1232 F08.0
FIGURE 11: RESET TIMING DIAGRAM (LPC MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
28
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
TABLE 23: RESET TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
TPRST
TRSTP
TRSTF
Parameter
Min
1
Max
Units
ms
ns
VDD stable to Reset Low
RST# Pulse Width
100
RST# Low to Output Float
48
ns
1
TRST
RST# High to Row Address Setup
RST# Low to reset during Sector-/Block-Erase or Program
RST# Low to reset during Chip-Erase
1
µs
TRSTE
TRSTC
10
50
µs
µs
T23.0 1232
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a programming or erase operational.
V
T
DD
PRST
Addresses
R/C#
Row Address
T
RSTP
T
RST#
Sector-/Block-Erase
or Program operation
aborted
RSTE
T
Chip-Erase
aborted
RSTC
T
RST
T
RSTF
DQ
7-0
1232 F11.0
FIGURE 12: RESET TIMING DIAGRAM (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
29
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
AC Characteristics (PP Mode)
TABLE 24: READ CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
TRC
Parameter
Min
270
1
Max
Units
ns
Read Cycle Time
TRST
TAS
RST# High to Row Address Setup
R/C# Address Set-up Time
R/C# Address Hold Time
Address Access Time
µs
45
ns
TAH
45
ns
TAA
120
60
ns
TOE
TOLZ
TOHZ
TOH
Output Enable Access Time
OE# Low to Active Output
OE# High to High-Z Output
Output Hold from Address Change
ns
0
0
ns
35
ns
ns
T24.0 1232
TABLE 25: PROGRAM/ERASE CYCLE TIMING PARAMETERS, VDD=3.0-3.6V (PP MODE)
Symbol
Parameter
Min
1
Max
Units
µs
TRST
TAS
RST# High to Row Address Setup
R/C# Address Setup Time
R/C# Address Hold Time
R/C# to Write Enable High Time
OE# High Setup Time
OE# High Hold Time
OE# to Data# Polling Delay
OE# to Toggle Bit Delay
WE# Pulse Width
45
45
50
20
20
ns
TAH
ns
TCWH
TOES
TOEH
TOEP
TOET
TWP
TWPH
TDS
ns
ns
ns
60
60
ns
ns
100
100
50
ns
WE# Pulse Width High
Data Setup Time
ns
ns
TDH
Data Hold Time
5
ns
TIDA
TBP
Software ID Access and Exit Time
Byte Programming Time
Sector-Erase Time
150
20
ns
µs
TSE
25
ms
ms
ms
TBE
Block-Erase Time
25
TSCE
Chip-Erase Time
100
T25.0 1232
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
30
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
T
RST#
RST
T
RC
Row Address
Column Address
Row Address
Column Address
Addresses
R/C#
T
T
T
T
AH
AS
AH
AS
V
IH
WE#
OE#
T
AA
T
OH
T
T
OHZ
OE
T
OLZ
High-Z
High-Z
Data Valid
DQ
7-0
1232 F12.0
FIGURE 13: READ CYCLE TIMING DIAGRAM (PP MODE)
T
RST
RST#
Row Address
Column Address
Addresses
T
T
T
T
AS
AH
AS
AH
R/C#
OE#
WE#
T
T
T
CWH
OEH
T
OES
T
WPH
WP
T
DH
T
DS
DQ
7-0
Data Valid
1232 F13.0
FIGURE 14: WRITE CYCLE TIMING DIAGRAM (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
31
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
Row
Column
Addresses
R/C#
WE#
OE#
T
OEP
DQ
7
D
D#
D#
D
1232 F15.0
FIGURE 15: DATA# POLLING TIMING DIAGRAM (PP MODE)
Row Column
Addresses
R/C#
WE#
OE#
T
OET
DQ
6
D
D
1232 F15.0
FIGURE 16: TOGGLE BIT TIMING DIAGRAM (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
32
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
BA
R/C#
OE#
WE#
Internal Program Starts
AA
55
A0
DATA
DQ
7-0
BA = Byte-Program Address
= Most Significant Address
A
1232 F16.0
MS
FIGURE 17: BYTE-PROGRAM TIMING DIAGRAM (PP MODE)
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
5555
2AAA
SA
X
R/C#
OE#
WE#
Internal Erase Starts
55
AA
55
80
AA
30
DQ
7-0
1232 F17.0
SA = Sector Address
X
FIGURE 18: SECTOR-ERASE TIMING DIAGRAM (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
33
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
5555
2AAA
BA
X
R/C#
OE#
WE#
Internal Erase Starts
55
AA
55
80
AA
50
DQ
7-0
1232 F18.0
BA = Block Address
X
FIGURE 19: BLOCK-ERASE TIMING DIAGRAM (PP MODE)
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
5555
2AAA
5555
R/C#
OE#
WE#
Internal Erase Starts
55
AA
55
80
AA
10
DQ
7-0
1232 F19.0
FIGURE 20: CHIP-ERASE TIMING DIAGRAM (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
34
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
0000
0001
R/C#
OE#
WE#
T
WP
T
T
AA
IDA
T
WPH
55
Device ID
AA
BF
90
DQ
7-0
1232 F20.0
FIGURE 21: SOFTWARE ID ENTRY AND READ (PP MODE)
A
MS-0
14-0
(Internal A
)
5555
2AAA
5555
R/C#
OE#
WE#
T
IDA
55
AA
F0
DQ
7-0
1232 F21.0
FIGURE 22: SOFTWARE ID EXIT (PP MODE)
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
35
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1232 F22.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference
points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 23: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1232 F23.0
FIGURE 24: A TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
36
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
SST49LF004B - XXX
-
XX
-
XXX
Environmental Attribute
E = non-Pb
Package Modifier
H = 32 leads
I = 40 leads
Package Type
N = PLCC
E = TSOP (type 1, die up, 10mm x 20mm)
Operating Temperature
C = Commercial = 0°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Serial Access Clock Frequency
33 = 33 MHz
Device Density
004 = 4 Mbit
Voltage Range
L = 3.0-3.6V
Product Series
49 = LPC Firmware Memories
Valid combinations for SST49LF004B
SST49LF004B-33-4C-EI SST49LF004B-33-4C-NH
SST49LF004B-33-4C-EIE SST49LF004B-33-4C-NHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
37
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
SIDE VIEW
BOTTOM VIEW
.495
.485
.112
.106
.453
.447
Optional
Pin #1
Identifier
.048
.042
.029
.023
.040
.030
.020 R.
MAX.
x 30˚
R.
2
1
32
.042
.048
.021
.013
.400
BSC
.530
.490
.595 .553
.585 .547
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.032
.026
.140
.125
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
38
4 Mbit LPC Firmware Flash
SST49LF004B
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
10.10
9.90
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
40-tsop-EI-7
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 20MM
SST PACKAGE CODE: EI
TABLE 26: REVISION HISTORY
Number
00
Description
Date
Jan 2003
Jun 2003
•
•
•
•
Initial release
01
Added a footnote to Table 2 on page 10
Removed the CE# signal from Figures 6 and 7
Changes to Table 14 on page 24
– Changed VIHI values
– Updated the IDD Test Conditions
02
Dec 2003
•
•
2004 Data Book
Updated status to “Data Sheet”
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2003 Silicon Storage Technology, Inc.
S71232-02-000
12/03
39
相关型号：
SST49LF008A-33-4C-EIE
1M X 8 FLASH 3V PROM, 120 ns, PDSO40, 10 X 20 MM, ROHS COMPLIANT, MO-142CD, TSOP1-40
MICROCHIP
©2020 ICPDF网 联系我们和版权申明