SST49LF004C-33-4C-WH

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

004C/008C4 Mb/8 Mb LPC Firmware Flash

Advance Information

FEATURES:

•

Organized as 512K x8 / 1M x8

•

Protected Data Area

– 12-KByte Protected Data Area space

– Three 4-KByte User-Programmable flash mem-

ory sectors

– Read-lock, write-lock and lock-down protection

for each sector

Conforms to Intel^®LPC Interface Specification v1.1

– Support Multi-Byte Firmware Memory Read/

Write Cycles

Single 3.0-3.6V Read and Write Operations

LPC Mode

– 5-signal LPC bus interface for both in-system

and factory programming using programmer

equipment

– Multi-Byte Read capability allowing 15.6 MB/s

data transfer rate @ 33 MHz PCI clock

- Firmware Memory Read cycle supporting

1, 2, 4, 16, and 128 Byte Read

•

Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

Uniform 4 KByte sectors

– SST49LF004C: 11 Overlay Blocks:

- one 16-KByte Boot Block

- two 8-KByte Parameter Blocks

- one 32-Kbyte Parameter Block

- seven 64-KByte Main Blocks

– SST49LF008C: 19 Overlay Blocks:

- one 16-KByte Boot Block

- Firmware Memory Write cycle supporting

1, 2, and 4 Byte Write

– 33 MHz clock frequency operation

– WP#/AAI and TBL# pins provide hardware Write

protect for entire chip and/or top Boot Block

– Block Locking Registers for individual block Read-

Lock, Write-Lock, and Lock-Down protection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

– Multi-Byte capability registers

(read-only registers)

– Status register for End-of-Write detection

– Program-/Erase-Suspend

Read or Write to other blocks during

Program-/Erase-Suspend

Two-cycle Command Set

Security ID Feature

- two 8-KByte Parameter Blocks

- one 32-Kbyte Parameter Block

- 15 64-KByte Main Blocks

•

Fast Sector-Erase/Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Program Time: 7 µs (typical)

Auto Address Increment (AAI) for Rapid Factory

Programming (High Voltage Enabled)

– RY/BY# pin for End-of-Write detection

– Multi-Byte Program

– Chip Rewrite Time: (typical)

- SST49LF004C: 1 seconds

- SST49LF008C: 2 seconds

Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

All non-Pb (lead-free) devices are RoHS compliant

•

– 256-bit Secure ID space

- 64-bit Unique Factory Pre-programmed

Device Identifier

- 192-bit User-Programmable OTP

•

Low Power Consumption

– Active Read Current: 12 mA (typical)

- Standby Current: 10 µA (typical)

PRODUCT DESCRIPTION

The SST49LF00xC flash memory devices are designed to

interface with host controllers (chipsets) that support a low-

pin-count (LPC) interface for system firmware applications.

The SST49LF00xC device complies with Intel’s LPC Inter-

face Specification 1.1, supporting a Burst-Read (up to 128

bytes in a single operation) which enables a 15.6 MByte

per second data transfer. The LPC interface operates with

5 signal pins versus 28 pins of a 8-bit parallel flash memory.

This frees up pins on the ASIC host controller resulting in

lower ASIC costs and a reduction in overall system costs

due to simplified signal routing.

The SST49LF00xC use a 5-signal LPC interface to support

both in-system and rapid factory programming using pro-

grammer equipment. A high voltage pin (WP#/AAI) is used

to enable Auto Address Increment (AAI) mode. The

SST49LF00xC offers hardware block protection in addition

to individual block protection via software registers for criti-

cal system code and data. A 256-bit Security ID space with

a 64-bit factory pre-programmed unique number and a

192-bit user programmable OTP area as well as 12-KByte

Protected Data Area (PDA) enhances the user’s ability to

implement new security techniques and data protection

©200 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.

Intel is a registered trademark of Intel Corporation.

S71292-00-000

1

1/06

These specifications are subject to change without notice.

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

scheme. The PDA can be also used to store system con-

the cumulative number of erase cycles as is necessary with

alternative flash memory technologies, whose Erase and

Program time increase with accumulated Erase/Program

cycles. To protect against inadvertent write, the

SST49LF00xC device has on-chip hardware and software

write protection schemes. It is offered with a typical endur-

ance of 100,000 cycles. Data retention is rated at greater

than 100 years.

figuration

data

(EEPROM

replacement).

The

SST49LF00xC also provides general purpose inputs (GPI)

for system design flexibility.

The SST49LF00xC flash memory device is manufactured

with SST’s proprietary, high-performance SuperFlash tech-

nology. The split-gate cell design and thick-oxide tunneling

injector attain greater reliability and manufacturability com-

pared with alternative technology approaches. The

SST49LF00xC device significantly improves performance

and reliability, while lowering power consumption. The

SST49LF00xC device writes (Program or Erase) in-system

with a single 3.0-3.6V power supply. It uses less energy

during Erase and Program than alternative flash memory

technologies.

The SST49LF00xC product provides a maximum program

time of 10 µs per byte with a single-byte Program opera-

tion; effectively 5 µs per byte with a dual-byte Program

operation and 2.5 µs per byte with a quad-byte Program

operation. End-of-Write can be detected by the RY/BY# pin

output in AAI mode and by reading the software status reg-

ister during an in-system Program or Erase operation.

The total energy consumed is a function of the applied volt-

age, current and time of application. Since for any given

voltage range, the SuperFlash technology uses less cur-

rent to program and has a shorter erase time, the total

energy consumed during any Erase or Program operation

is less than alternative flash memory technologies.

The SST49LF00xC is offered in 32-PLCC, and 32-TSOP

packages. In addition, the SST49LF00xC devices are

offered in lead-free (non-Pb) package options to address

the growing need for non-Pb solutions in electronic compo-

nents. Non-Pb package versions can be obtained by order-

ing products with a package code suffix of “E” as the

environmental attribute in the product part number. See

Figures 3 and 4 for pin assignments and Table 1 for pin

descriptions.

The SuperFlash technology provides fixed Erase and Pro-

gram time, independent of the number of Erase/Program

cycles that have performed. Therefore the system software

or hardware does not have to be calibrated or correlated to

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

2

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE OF CONTENTS

PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DEVICE MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input/Output Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Input Communication Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Identification Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

General Purpose Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Protect / Top Block Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AAI Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ready/Busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Load Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

No Connection (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MODE SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

LPC MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

FIRMWARE MEMORY CYCLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Firmware Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Firmware Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Response to Invalid Fields for

Firmware Memory Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

3

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

DEVICE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read-Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read-Software-ID Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read-Status-Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clear-Status-Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sector-/Block-Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program-/Erase-Suspend or Program-/Erase-Resume Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Erase-Suspend/Erase-Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program-Suspend/Program-Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Security ID Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Multi-Byte Read/Write Configuration Registers (Firmware Memory Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . 21

General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block and PDA Sector Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Security ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AUTO-ADDRESS INCREMENT (AAI) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AAI Mode with Multi-byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

AAI Data Load Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

4

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

LIST OF FIGURES

FIGURE 1: Device Memory Map for SST49LF004C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FIGURE 2: Device Memory Map for SST49LF008C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FIGURE 3: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIGURE 4: Pin Assignments for 32-lead TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIGURE 5: Firmware Memory Read Cycle Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

FIGURE 6: Firmware Memory Write Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FIGURE 7: Erase-Suspend Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

FIGURE 8: AAI Load Protocol Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

FIGURE 9: LCLK Waveform (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FIGURE 10: Reset Timing Diagram (LPC MODE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

FIGURE 11: Output Timing parameters (LPC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE 12: Input Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FIGURE 13: Input Timing Parameters (AAI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

FIGURE 14: A Test Load Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

5

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

LIST OF TABLES

TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

TABLE 2: Transfer Size Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 3: Firmware Memory Cycles START Field Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TABLE 4: Firmware Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

TABLE 5: Firmware Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TABLE 6: Valid MSIZE field Values for Firmware Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TABLE 7: Firmware Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

TABLE 8: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TABLE 9: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TABLE 10: Software Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TABLE 11: Security ID Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TABLE 12: General Purpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TABLE 13: Multi-byte Read/Write Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TABLE 14: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

TABLE 15: Protected Data Area Sector Locking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

TABLE 16: Block/PDA Sector Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TABLE 17: Security ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TABLE 18: JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TABLE 19: LD# Input and RY/BY# Status inAAI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

TABLE 20: AAI Programming Cycle (initiated with WP#/AAI at V_HONLY) . . . . . . . . . . . . . . . . . . . . . . . . 26

TABLE 21: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TABLE 22: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TABLE 23: Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TABLE 25: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TABLE 24: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

TABLE 26: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

TABLE 27: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TABLE 28: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

TABLE 29: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

TABLE 30: Input Cycle Timing Parameters (AAI Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

TABLE 31: Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

6

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

FUNCTIONAL BLOCKS

FUNCTIONAL BLOCK DIAGRAM

PDA

X-Decoder

SuperFlash

Memory

TBL#

WP#

INIT#

LAD[3:0]

LCLK

LPC

Address Buffers & Latches

LFRAME#

ID[3:0]

Interface

Y-Decoder

GPI[4:0]

I/O Buffers and Data Latches

Control Logic

AAI

Interface

RY/BY#

LD#

RST#

1292 B1.1

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

7

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

DEVICE MEMORY MAPS

0FFFFFH

Boot Block

TBL#

Block 18

Block 17

Block 16

Block 15

7FFFFH

Boot Block

0FC000H

0FBFFFH

TBL#

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

7C000H

7BFFFH

0FA000H

0F9FFFH

7A000H

79FFFH

0F8000H

0F7FFFH

78000H

77FFFH

0F0000H

0EFFFFH

70000H

6FFFFH

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

0E0000H

0DFFFFH

60000H

5FFFFH

0D0000H

0CFFFFH

WP# for

Block 0–9

50000H

4FFFFH

0C0000H

0BFFFFH

40000H

3FFFFH

0B0000H

0AFFFFH

30000H

2FFFFH

WP# for

Block 0–18

0A0000H

09FFFFH

20000H

1FFFFH

090000H

08FFFFH

10000H

0F000H

080000H

07FFFFH

Block 0

(64 KByte)

070000H

06FFFFH

4 KByte Sector 2

4 KByte Sector 1

4 KByte Sector 0

02000H

01000H

00000H

060000H

05FFFFH

1292 F01.1

FIGURE 1: DEVICE MEMORY MAP FOR

SST49LF004C

050000H

04FFFFH

040000H

03FFFFH

030000H

02FFFFH

020000H

01FFFFH

010000H

00FFFFH

4 KByte Sector 15

Block 0

(64 KByte) 002000H

4 KByte Sector 2

4 KByte Sector 1

4 KByte Sector 0

001000H

000000H

1292 F02.1

FIGURE 2: DEVICE MEMORY MAP FOR

SST49LF008C

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

8

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

PIN ASSIGNMENTS

4

3

2

1

32 31 30

29

5

GPI1 (LD#)

GPI0 (RY/BY#)

WP#/AAI

TBL#

NC

6

28

27

26

25

24

23

22

21

7

8

32-lead PLCC

Top View

9

ID3

V

DD

INIT#

10

11

12

13

ID2

ID1

LFRAME#

NC

ID0

NC

LAD0

14 15 16 17 18 19 20

1292 32-plcc P2.0

( ) Designates AAI Mode

FIGURE 3: PIN ASSIGNMENTS FOR 32-LEAD PLCC

NC

GPI4

LCLK

NC

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

INIT#

LFRAME#

V

NC

(V )

DD DD

NC

LAD3

32-lead TSOP

Top View

9

V

(V )

SS SS

RST#

GPI3

GPI2

10

11

12

13

14

15

16

LAD2

LAD1

LAD0

ID0

ID1

ID2

GPI1 (LD#)

GPI0 (RY/BY#)

WP#/AAI

TBL#

ID3

1292 32-tsop P1.0

( ) Designates AAI Mode

FIGURE 4: PIN ASSIGNMENTS FOR 32-LEAD TSOP

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

9

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

PIN DESCRIPTIONS

TABLE 1: PIN DESCRIPTION

Interface

Symbol

Pin Name

Type¹AAI LPC Functions

LCLK

Clock

I

X

To accept a clock input from the control unit

LAD[3:0] Address

and Data

I/O

To provide LPC bus information,

such as addresses and command Inputs/Outputs data.

LFRAME# Frame

I

X

To indicate the start of a data transfer operation;

also used to abort an LPC cycle in progress.

RST#

INIT#

Reset

I

X

To reset the operation of the device

Initialize

This is the second reset pin for in-system use.

This pin is internally combined with the RST# pin.

If this pin or RST# pin is driven low, identical operation is exhibited.

ID[3:0]

GPI[4:0]

TBL#

Identification

Inputs

I

X

These four pins are part of the mechanism that allows multiple parts to be

attached to the same bus. The strapping of these pins is used to identify

the component. The boot device must have ID[3:0]=0000, all subsequent

devices should use sequential up-count strapping. These pins are inter-

nally pulled-down with a resistor between 20-100 KΩ. When in AAI mode,

these pins operate identically as in Firmware Memory cycles.

General

Purpose

Inputs

X

These individual inputs can be used for additional board flexibility.

The state of these pins can be read through LPC registers. These inputs

should be at their desired state before the start of the LPC clock cycle dur-

ing which the read is attempted, and should remain in place until the end

of the Read cycle. Unused GPI pins must not be floated.

GPI[2:4] are ignored when in AAI mode.

Top Block Lock

X

When low, prevents programming to the boot block sectors at top of device

memory. When TBL# is high it disables hardware write protection for the

top block sectors. This pin cannot be left unconnected.

TBL# setting is ignored when in AAI mode.

WP#/AAI Write Protect

WP#/AAI AAI Enable

I

When low, prevents programming to all but the highest addressable block

(Boot Block). When WP# is high it disables hardware write protection for

these blocks. This pin cannot be left unconnected.

X

When set to the Supervoltage V_H= 9V, configures the device to program

multiple bytes in AAI mode. When brought to V_IL/V_IH, returns device to

LPC mode.

RY/BY#

LD#

Ready/Busy#

Load-Enable#

O

I

Open drain output that indicates the device is ready to accept data in an

AAI mode, or that the internal cycle is complete.

Used in conjunction with LD# pin to switch between these two flag states.

Input pin which when low, indicates the host is loading data in an AAI pro-

gramming cycle. If LD# is high, the host signals the AAI interface that it is

terminating a command. LD# low/high switches the RY/BY# output from a

“buffer free” flag to a “programming complete” flag.

V_DD

V_SS

NC

Power Supply

Ground

PWR

X

To provide power supply (3.0-3.6V)

Circuit ground (0V reference)

No Connection

N/A N/A Unconnected pins.

T1.0 1292

1. I=Input, O=Output

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

10

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Clock

Write Protect / Top Block Lock

The LCLK pin accepts a clock input from the host controller.

The Top Boot Lock (TBL#) and Write Protect (WP#/AAI)

pins are provided for hardware write protection of device

memory in the SST49LF00xC. The TBL# pin is used to

write protect 16 KByte at the highest memory address

range for the SST49LF00xC. WP#/AAI pin write protects

the remaining sectors in the flash memory. An active low

signal at the TBL# pin prevents Program and Erase opera-

tions of the top Boot Block. When TBL# pin is held high,

write protection of the top Boot Block is then determined by

the Boot Block Locking registers. The WP#/AAI pin serves

the same function for the remaining sectors of the device

memory. The TBL# and WP#/AAI pins write protection

functions operate independently of one another. Both TBL#

and WP#/AAI pins must be set to their required protection

states prior to starting a Program or Erase operation. A

logic level change occurring at the TBL# or WP#/AAI pin

during a Program or Erase operation could cause unpre-

dictable results. TBL# and WP#/AAI pins cannot be left

unconnected.

Input/Output Communications

The LAD[3:0] pins are used to serially communicate cycle

information such as cycle type, cycle direction, ID selection,

address, data, and sync fields.

Input Communication Frame

The LFRAME# pin is used to indicate start of a LPC bus

cycle. The pin is also used to abort an LPC bus cycle in

progress.

Reset

A V_ILon INIT# or RST# pin initiates a device reset. INIT#

and RST# pins have the same function internally. It is

required to drive INIT# or RST# pins low during a system

reset to ensure proper CPU initialization. During a Read

operation, driving INIT# or RST# pins low deselects the

device and places the output drivers, LAD[3:0], in a high

impedance state. The reset signal must be held low for a

minimum of time T_RSTP.A reset latency occurs if a reset pro-

cedure is performed during a Program or Erase operation.

See Table 26, Reset Timing Parameters, for more informa-

tion. A device reset during an active Program or Erase oper-

ation will abort the operation and memory contents may

become invalid due to data being altered or corrupted from

an incomplete Erase or Program operation.

TBL# is internally OR’ed with the top Boot Block Locking

register. When TBL# is low, the top Boot Block is hardware

write protected regardless of the state of the Write-Lock bit

for the Boot Block Locking register. Clearing the Write-Pro-

tect bit in the register when TBL# is low will have no func-

tional effect, even though the register may indicate that the

block is no longer locked.

WP#/AAI is internally OR’ed with the Block Locking regis-

ter. When WP#/AAI is low, the blocks are hardware write

protected regardless of the state of the Write-Lock bit for

the corresponding Block Locking registers. Clearing the

Write-Protect bit in any register when WP#/AAI is low will

have no functional effect, even though the register may indi-

cate that the block is no longer locked.

Identification Inputs

These pins are part of a mechanism that allows multiple

devices to be attached to the same bus. The strapping of

these pins is used to identify the component. The boot

device must have ID[3:0] = 0; all subsequent devices

should use sequential count-up strapping. These pins are

internally pulled-down with a resistor between 20-100 KΩ.

The TBL# pin and WP# pin do not affect the protection of

the Protected Data Area. The PDA protection status is only

determined by the value of the PDA Sector Locking Regis-

ters. (See “Block and PDA Sector Locking Registers” on

page 22.)

General Purpose Inputs

The General Purpose Inputs (GPI[4:0]) can be used as dig-

ital inputs for the CPU to read. The GPI register holds the

values on these pins. The data on the GPI pins must be

stable before the start of a GPI register Read and remain

stable until the Read cycle is complete. The pins must be

driven low, V_IL, or high, V_IHbut not left unconnected (float).

AAI Enable

The AAI Enable pin (WP#/AAI) is used to enable the Auto

Address Increment (AAI) mode. When the WP#/AAI pin is

set to the Supervoltage V_H(9 0.5V), the device is in AAI

mode with Multi-Byte programming. When the WP#/AAI

pin is brought to V_IL/V_IHlevels, the device returns to LPC

mode.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

11

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Ready/Busy

LPC MODE

The Ready/Busy pin (RY/BY#), is an open drain output

which indicates the device is ready to accept data in an AAI

mode, or that the internal programming cycle is complete.

The pin is used in conjunction with the LD# pin to switch

between these two flag states (see Table 19).

Device Operation

The SST49LF00xC supports Multi-Byte Firmware Memory

Read and Write cycle types as defined in Intel Low Pin

Count Interface Specification, Revision 1.1. Table 2 shows

the size of transfer supported by the SST49LF00xC.

Load Enable

TABLE 2: TRANSFER SIZE SUPPORTED

The Load Enable pin (LD#), is an input pin which when low,

indicates the host is loading data in an AAI programming

cycle. Data is loaded in the SST49LF00xC at the rising

edge of the clock. If LD# is high, it signals the AAI interface

that the host is terminating the command. LD# low/high

switches the RY/BY# output from buffer free flag to pro-

gramming complete flag (see Table 19).

Cycle Type

Size of Transfer

1, 2, 4, 16, 128 Bytes

1, 2, 4 Bytes

Firmware Memory Read

Firmware Memory Write

T2.0 1292

The LPC mode uses a 5-signal communication interface:

one control line, LFRAME#, which is driven by the host to

start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used

to communicate cycle type, cycle direction, ID selection,

address, data and sync fields. The device enters standby

mode when LFRAME# is taken high and no internal opera-

tion is in progress.

No Connection (NC)

These pins are not connected internally.

DESIGN CONSIDERATIONS

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between V_DDand

The host drives LFRAME# signal from low-to-high to cap-

ture the start field of a LPC cycle. On the cycle in which

LFRAME# goes inactive, the last latched value is taken as

the START value. The START value determines whether

the SST49LF00xC will respond to a Firmware Memory

Read/Write cycle type as defined in Table 3.

V_SSless than 1 cm away from the V_DDpin of the device.

Additionally, a low frequency 4.7 µF electrolytic capacitor

from V_DDto V_SSshould be placed within 1 cm of the V_DD

pin. If you use a socket for programming purposes add an

additional 1-10 µF next to each socket. The RST# pin must

remain stable at V_IHfor the entire duration of an Erase

operation. WP#/AAI must remain stable at V_IHfor the entire

duration of the Erase and Program operations for non-Boot

Block sectors. To write data to the top Boot Block sectors,

the TBL# pin must also remain stable at V_IHfor the entire

duration of the Erase and Program operations.

TABLE 3: FIRMWARE MEMORY CYCLES START

FIELD DEFINITION

START

Value Definition

1101

1110

Start of a Firmware Memory Read cycle

Start of a Firmware Memory Write cycle

T3.0 1292

MODE SELECTION

See following sections on details of Firmware Memory

cycle types (Tables 4 and 5). Two-cycle Program and

Erase command sequences are used to initiate Firmware

Memory Program and Erase operations. See Table 8 for a

listing of Program and Erase commands.

The SST49LF00xC flash memory device operates in two

distinct interface modes: the LPC mode and the Auto

Address Increment (AAI) mode. The WP#/AAI pin is used

to set the interface mode selection. The device is in AAI

mode when the WP#/AAI pin is set to the Supervoltage V_H

(9 0.5V), and in the LPC mode when the WP#/AAI is set to

V_IL/V_IH.The mode selection must be configured prior to

device operation.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

12

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

FIRMWARE MEMORY CYCLES

Firmware Memory Read Cycle

TABLE 4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS

Clock

Cycle

Field

Name

LAD[3:0]

Direction

Field Contents

LAD[3:0]¹

Comments

1

START

1101

IN

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions high)

will be recognized. The START field contents (1101b) indi-

cate a Firmware Memory Read cycle.

2

IDSEL

0000 to 1111

IN

Indicates which SST49LF00xC device should respond.

If the IDSEL (ID select) field matches the value of ID[3:0],

then that particular device will respond to the LPC bus

cycle.

3-9

10

MADDR

MSIZE

YYYY

KKKK

IN

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

The MSIZE field indicates how many bytes will be trans-

ferred during multi-byte operations.

Device will execute multi-byte read of 2^MSIZEbytes.

SST49LF00xC supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4,

16, 128 Bytes), with KKKK=0000b, 0001b, 0010b, 0100b, or

0111b.

11

TAR0

1111

IN,

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

to all ‘1’s and then floats the bus, prior to the next clock

cycle. This is the first part of the bus “turnaround cycle.”

12

13

TAR1

1111 (float)

Float,

then OUT

The SST49LF00xC takes control of the bus during this

cycle.

RSYNC

0000 (READY)

OUT

During this clock cycle, the device generates a “ready sync”

(RSYNC) indicating that the device has received the input

data. The least-significant nibble of the least-significant byte

will be available during the next clock cycle.

14-A

DATA

TAR0

ZZZZ

1111

OUT

A=(13+2ⁿ⁺¹); n = MSIZE

Least significant nibbles outputs first.

(A+1)

OUT,

then Float

In this clock cycle, the SST49LF00xC drives the bus to all

ones and then floats the bus prior to the next clock cycle.

This is the first part of the bus “turnaround cycle.”

A=(13+2ⁿ⁺¹); n = MSIZE

(A+2)

TAR1

1111 (float)

Float,

then IN

The host resumes control of the bus during this cycle.

A=(13+2ⁿ⁺¹); n = MSIZE

T4.0 1292

1. Field contents are valid on the rising edge of the present clock cycle.

LCLK

LFRAME#

DATA

Start

IDSEL

MADDR

MSIZE TAR0 TAR1 RSYNC

KKKKb 1111b Tri-State 0000b

1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]

A[7:4]

A[3:0]

D

[3:0]

D

[7:4]

D

[3:0]

D [7:4]

n

TAR

0

n

LAD[3:0]

1292 F03.0

FIGURE 5: FIRMWARE MEMORY READ CYCLE WAVEFORM

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

13

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Firmware Memory Write Cycle

TABLE 5: FIRMWARE MEMORY WRITE CYCLE

Clock

Cycle

Field

Name

Field Contents

LAD[3:0]¹

LAD[3:0]

Direction

Comments

1

START

1110

IN

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions

high) will be recognized. The START field contents

(1110b) indicate a Firmware Memory Write cycle.

2

IDSEL

0000 to 1111

IN

Indicates which SST49LF00xC device should

respond. If the IDSEL (ID select) field matches the

value of ID[3:0], then that particular device will respond

to the whole bus cycle.

3-9

10

MADDR

MSIZE

YYYY

KKKK

IN

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

The MSIZE field indicates how many bytes will be

transferred during multi-byte operations.

Device supports 1, 2, and 4 Bytes write with MSIZE =

0, 1, or 2, and KKKK=0000b, 0001b, or 0010b.

11-A

DATA

TAR0

ZZZZ

1111

IN

A=(10+2ⁿ⁺¹); n = MSIZE

Least significant nibble entered first.

(A+1)

IN then Float

In this clock cycle, the master (Intel ICH) has driven the

bus to all ‘1’s and then floats the bus prior to the next

clock cycle. This is the first part of the bus “turnaround

cycle.” A=(10+2ⁿ⁺¹); n = MSIZE

(A+2)

(A+3)

TAR1

1111 (float)

0000

Float then OUT The SST49LF00xC takes control of the bus during this

cycle.

A=(10+2ⁿ⁺¹); n = MSIZE

RSYNC

OUT

During this clock cycle, the SST49LF00xC generates

a “ready sync” (RSYNC) and outputs the values 0000,

indicating that it has received data or a flash command.

A=(10+2ⁿ⁺¹); n = MSIZE

(A+4)

(A+5)

TAR0

TAR1

1111

OUT then Float In this clock cycle, the SST49LF00xC drives the bus to

all ‘1’s and then floats the bus prior to the next clock

cycle. This is the first part of the bus “turnaround

cycle”. A=(10+2ⁿ⁺¹); n = MSIZE

1111 (float)

Float then IN

The host resumes control of the bus during this cycle.

A=(10+2ⁿ⁺¹); n = MSIZE

T5.0 1292

1. Field contents are valid on the rising edge of the present clock cycle.

LCLK

LFRAME#

DATA

Start

IDSEL

MADDR

MSIZE

KKKKb

TAR0 TAR1 RSYNC

1111b Tri-State 0000b

1110b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]

A[7:4]

A[3:0]

D

[3:0]

D

[7:4]

Dn[3:0] Dn[7:4]

TAR

0

LAD[3:0]

1292 F04.0

FIGURE 6: FIRMWARE MEMORY WRITE CYCLE WAVEFORM

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

14

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Invalid MSIZE field: If the SST49LF00xC receives an

invalid size field during a Firmware Memory Read or Write

operation, the device will reset and no operation will be

attempted. The device will not generate any kind of

response in this situation. The SST49LF00xC will only

respond to values listed in Table 6.

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles after

the start of a bus cycle, the cycle will be terminated. The

host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to

return the interface to ready mode. The ABORT only

affects the current bus cycle. For a multi-cycle command

sequence, such as the Erase or Program commands,

ABORT doesn’t interrupt the entire command sequence,

only the current bus cycle of the command sequence. The

host can re-send the bus cycle for the aborted command

and continue the command sequence after the device is

ready again.

TABLE 6: VALID MSIZE FIELD VALUES FOR

FIRMWARE MEMORY CYCLES

MSIZE

0000

0001

0010

0100

0111

Direction

R/W

R

Size of Transfer

1 Byte

2 Byte

4 Byte

Response to Invalid Fields for

Firmware Memory Cycle

16 Byte

R

128 Byte

During an on-going Firmware Memory bus cycle, the

SST49LF00xC will not explicitly indicate that it has received

invalid field sequences. The response to specific invalid

fields or sequences is described as follows:

T6.0 1292

Once valid START, IDSEL, and MSIZE are received, the

SST49LF00xC will always complete the bus cycle. How-

ever, if the device is busy performing a flash Erase or Pro-

gram operation, no new internal memory Write will be

executed. As long as the states of LAD[3:0] and LFRAME#

are known, the response of the ST49LF00xC to signals

received during the cycle is predictable.

ID mismatch: If the IDSEL field does not match ID[3:0],

the device will ignore the cycle. See “Multiple Device Selec-

tion for Firmware Memory Cycle” on page 16 for details.

Address out of range: The address sequence is 7

fields long (28 bits) with Firmware Memory bus cycles.

Only some of the address fields bits are decoded by the

SST49LF00xC devices. SST49LF004c decodes A₀

through A₁₈and A_22,and SST49LF008C decodes A₀

through A₁₉and A₂₂. Address A₂₂has the special function

of directing reads and writes to the flash core (A₂₂=1) or to

the register space (A₂₂=0).

Non-boundary-aligned address: The SST49LF00xC

accepts multi-byte transfers for both Read and Write opera-

tions. The device address space is divided into uniform

page sizes 2, 4, 16, or 128 bytes wide, according to the

MSIZE value (see Table 6). The host issues only one

address in the MADDR field of the Firmware Memory

Cycle, but multiple bytes are read from or written to the

device. For this reason the MADDR address should be

page boundary-aligned. This means the address should be

aligned to a Word boundary (A₀= 0) for a 2-byte transfer, a

double Word boundary (e.g. A₀= 0, A₁= 0) for a 4-byte

transfer, and so on. If the address supplied by the host is

not page boundary-aligned, the SST49LF00xC will force a

boundary alignment, starting the multi-byte Read or Write

operation from the lower byte of the addressed page.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

15

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE 7: FIRMWARE MEMORY MULTIPLE DEVICE

SELECTION CONFIGURATION

Multiple Device Selection

Multiple LPC firmware flash devices may be strapped to

increase memory densities in a system. The four ID pins,

ID[3:0], allow up to 16 devices to be attached to the same

bus by using different ID strapping in a system. BIOS sup-

port, bus loading, or the attaching bridge may limit this num-

ber. The boot device must have an ID of 0000b (determined

by ID[3:0]); subsequent devices use incremental number-

ing. Equal density must be used with multiple devices.

Device #

ID[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

IDSEL

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 (Boot device)

1

2

3

4

5

Multiple Device Selection for

Firmware Memory Cycle

6

7

For Firmware Memory Read/Write cycles, hardware strap-

ping values on ID[3:0] must match the values in IDSEL

field. The SST49LF00xC will compare these bits with

ID[3:0]’s strapping values. If there is a mismatch, the device

will ignore the remainder of the cycle. See Table 7 for Multi-

ple Device Selection Configuration.

8

9

10

11

12

13

14

15

T7.0 1292

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

16

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

DEVICE COMMANDS

Device operation is controlled by commands written to the

Command User Interface (CUI). Execution of a specific

command is handled by internal functions after a CUI

receives and processes the command. After power-up or a

Reset operation the device enters Read mode. Commands

consist of one or two sequential Bus-Write operations. The

commands are summarized in Table 8, “Software Com-

mand Sequence”.

TABLE 8: SOFTWARE COMMAND SEQUENCE

Bus Cycles

First Bus Cycle

Second Bus Cycle

Command

Required

Oper

Write

Addr¹

Data

FFH

90H

Oper

Addr¹

Data

Read-Array/Reset

1

X

Read-Software-ID/

≥ 2

Read

IA⁵

X

ID⁶

Read-Security-ID^2,3,4

Read-Status-Register^3,4

Clear-Status-Register

Sector-Erase⁸

Block-Erase⁸

Program^8,10

2

1

2

Write

X

70H

50H

30H

20H

SRD⁷

Write

SAx⁹

BAx

WA¹¹

D0H

WD¹²

40H

or

10H

Program-/Erase-Suspend

Program-/Erase-Resume

User-Security-ID-Program¹³

User-Security-ID-Program-Lockout

Protected-Area-Sector-Erase^8,14

Program-Protected-Area^8,14

Open-Protected-Area¹⁵

1

2

1

Write

X

B0H

D0H

A5H

85H

32H

42H

62H

6DH

Write

WA¹¹

X

Data

00H

SA

D0H

Data

WA

Hide-Protected-Area¹⁵

T8.0 1292

1. This value must be a valid address within the device Memory Address Space. X can be V_IHor V_IL,but no other value.

2. SST Manufacturer’s ID = BFH, is read with A₁₉-A₀= 0.

SST49LF004C/008C Device ID = 54H/59H, is read with A₁₉-A₁= 0, A₀= 1.

Following the Read-Software-ID/Read-Security-ID command,

Read operations access Manufacturer’s ID and Device ID or Security ID.

3. Read-Software-ID/Read Security ID and Read Status Register will return ID/Register data until another valid command is written.

4. Following the Read-Software-ID/Read-Security-ID command, Read operations access manufacturer’s ID and Device ID or Security

ID. Read-Software-ID/Read-Security-ID and Read-Status-Register will return register data until another valid command is written.

5. IA = Device Identification Address/Security ID Address.

6. ID = Data read from identifier codes/Data read from Security ID

7. SRD = Data read from Status register

8. The sector or block must not be write-locked when attempting Erase or Program operations.

Attempts to issue an Erase or Program command to a write-locked sector/block will fail.

9. SA_Xfor Sector-Erase Address

BA_Xfor Block-Erase Address

10. The Program Command can operate on multiple bytes.

11. WA = Address of memory location to be written

12. WD = Data to be written at location WA

13. Valid addresses for the User Security ID space are from FFFC 0188H to FFFC 019FH.

14. Valid address WA of Protected Data Area location is from FFFC 8000H to FFFC AFFFH. For Sector Erase Command any address

within the sector in the Protected Data Area being erased can be used: PDA Sector 0 - SA+ FFC 8000H to FFFC 8FFFH. PDA Sec-

tor 1 - SA = FFFC 9000H to FFFC 9FFFH. PDA Sector 2 - SA = FFFC A000H to FFFC AFFFH.

15. After Open Protected Area command is executed the contents of the area can be read at addresses FFBC 8000H to FFBC AFFFH if

it is not read-locked. After Hide Protected Area command is executed the contents of the area is not accessible regardless of read-

lock status. By default (after Power On or reset) Protected Data Area is hidden.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

17

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE 9: PRODUCT IDENTIFICATION

Address¹

Read-Array Command

Data

Upon initial device power-up and after exit from reset, the

device defaults to the Read Array mode. This operation can

also be initiated by writing the Read-Array command. (See

Table 8.) The device remains available for array reads until

another command is written. Once an internal Program/

Erase operation starts, the device will not recognize the

Read-Array command until the operation is completed,

unless the operation is suspended via a Program-/Erase-

Suspend command.

Manufacturer’s ID

Device ID

FFFC 0000H

BFH

SST49LF004C

SST49LF008C

FFFC 0001H

54H

59H

T9.0 1292

1. Address shown in this column is for boot device only.

Address locations should appear elsewhere in the 4

GByte system memory map depending on ID strapping

values on ID[3:0] pins when multiple LPC memory

devices are used in a system.

Read-Software-ID Command

Read-Status-Register Command

The Read-Software-ID operation is initiated by writing the

Read-Software-ID command. Following the command, the

device will output the manufacturer’s ID and device ID from

the addresses shown in Table 9. Any other valid command

will terminate the Read-Software-ID operation.

The Status register may be read to determine when a Sec-

tor-/Block-Erase or Program completes, and whether the

operation completed successfully. The Status register may

be read at any time by writing the Read-Status-Register

command. After writing this command, all subsequent

Read operations will return data from the Status register

until another valid command is written.

The Read-Software-ID command is the same as the Read-

Security-ID command. See “Security ID Commands” on

page 20.

The default value of the Status register after device power-

up or reset is 80H.

Clear-Status-Register Command

The user can reset the Status register’s Block Protect Sta-

tus (BPS) bit to 0 by issuing a Clear-Status-Register com-

mand. Device power-up and hardware reset will also reset

BPS to 0.

TABLE 10: SOFTWARE STATUS REGISTER

Bit Name

Function

0

1

RES

BPS

Reserved for future use

Block Protect Status

The Block Write-Lock bit should be interrogated only after Erase or Program command is issued.

It informs the system whether or not the selected block is locked.

BPS does not provide a continuous indication of Write-Lock bit value.

0: Block Unlocked

1: Operation Aborted, Block Write-Lock bit set.

2:5 RES

Reserved for future use

6

ESS

Erase Suspend Status

0: Erase in progress/completed

1: Erase suspended

7

WSMS Write State Machine Status

Check WSMS to determine erase or program completion.

0: Busy

1: Ready

T10.0 1292

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

18

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Sector-/Block-Erase Command

Erase-Suspend/

Erase-Resume Commands

The Erase Command operates on one sector or block at a

time. This command requires an (arbitrary) address within

the sector or block to be erased. Note that a Sector/Block

Erase operation changes all Sector/Block byte data to FFh.

If a Read operation is performed after issuing the erase

command, the device will automatically output Status Reg-

ister data. The system can poll the Status Register in order

to verify the completion of the Sector/Block Erase operation

(please refer to Table 10, Status Register Definition). If a

Sector/Block Erase is attempted on a locked block, the

operation will fail and the data in the Sector/Block will not be

changed. In this case, the Status Register will report the

error (BPS=1).

The Erase Suspend command allows Sector-Erase or

Block-Erase interruption in order to read or program data

in another block of memory. Once the Erase-Suspend

command is executed, the device will suspend any on-

going Erase operation within time T_ES(10 µs). The device

outputs status register data when read after the Erase-

Suspend command is written. The system is able to deter-

mine when the Erase operation has been completed

(WSMS=1) by polling the status register. After an Erase-

Suspend, the device will set the status register ESS bit

(ESS=1) if the Erase has been successfully suspended

(refer to Table 10, “Software Status Register”). The Erase-

Resume command resumes the Erase operation that had

been previously suspended.

Program Command

The Program command operates on multiple bytes as

shown in Table 5. This command specifies the address and

data to be programmed. During the Program operation the

device automatically outputs the Status Register data when

read. The system can poll the Status Register in order to

verify the completion of the Program operation (refer to

Table 10, “Software Status Register”). If a Program opera-

tion is attempted on a locked block, the operation will fail

and the data in the addressed byte will not be changed. In

this case, the Status Register will report the error (BPS=1).

After a successful Erase-Suspend, a Read-Array com-

mand may be written to read data from a Sector/Block

other than the suspended Sector/Block. A Program com-

mand sequence may also be issued during Erase Sus-

pend to program data in memory locations other than the

Sector/Block currently in the Erase-Suspend mode. If a

Read-Array command is written to an address within the

suspended Sector/Block this may result in reading invalid

data. If a Program command is written to an address within

the suspended Sector/Block the command is acknowl-

edged but rejected. Other valid commands while erase is

suspended include Read-Status-Register, Read-Device-

ID, and Erase-Resume.

Program-/Erase-Suspend or

Program-/Erase-Resume Operations

The Erase-Resume command resumes the Erase process

in the suspended sector or block. After the Erase-Resume

command is written, the device will continue the Erase pro-

cess. Erase cannot resume until any Program operation ini-

tiated during Erase-Suspend has completed. Suspended

operations cannot be nested: the system needs to com-

plete or resume any previously suspended operation

before a new operation can be suspended. See Figure 7

for flowchart.

The Program-Suspend and Erase-Suspend operations

share the same software command sequence (B0H). The

Program-Resume and Erase-Resume operations share

the same software command sequence (D0H). See Table

8, “Software Command Sequence” on page 17.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

19

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Program-Suspend/

Program-Resume Command

Erase Sector/Block

The Program-Suspend and Program-Resume commands

have no influence on the device. Since the device requires

a maximum of T^BP(10 µs) in order to program a byte (see

Table 27), when a Program-Suspend command is written,

the suspended Byte Program operation will always be suc-

cessfully completed within the suspend latency time (T^ES=

T^BP= 10 µs).

Write B0H to any valid

device memory address

Erase-Suspend

Command

Write 70H to any valid

device memory address

Read-Status-Register

Command

Security ID Commands

Read Status Register

The SST49LF00xC device offers a 256-bit Security ID

space. The Security ID space is divided into two parts. One

64-bit segment is programmed at SST with a unique 64-bit

number: this number cannot be changed by the user. The

other segment is 192-bit wide and is left blank: this space is

available for customers and can be programmed as

desired.

No

WSMS = 1

Yes

The User-Security-ID-Program command is shown in

Table 8, “Software Command Sequence”. Use the memory

addresses specified in Table 11 for Security ID program-

ming. Once the customer segment is programmed, it can

be locked to prevent any alteration. The User-Security-ID-

Program-Lockout command is shown in Table 8, “Software

Command Sequence”.

Erase Completed

ESS = 1

Yes

No

Write the Read-Array

command to read from

another Sector/Block

or

In order to read the Security ID information, the user can

issue a Read Security ID Command (90H) to the device. At

this point the device enters the Read-Software-ID/Read-

Security-ID mode. The Security ID information can be read

at the memory addresses in Table 11.

Write the Program

command to program

another Sector/Block

No

Finished?

Yes

A Read-Array/Reset command (FFH) must then be issued

to the device in order to exit the Read-Software-ID/Read-

Security-ID mode and return to Read-Array mode.

Erase-Resume

Command

An alternate method to read the Security ID information is

to read the Security ID registers located into the register

space as described in the “Security ID Registers” section.

Write D0H to any valid

device memory address

Erase Resumed

1292 FC_Erase-Sus.0

FIGURE 7: ERASE-SUSPEND FLOW CHART

TABLE 11: SECURITY ID ADDRESSES

Address Range¹

Security ID Segment

Size

FFFC 0180 to FFFC 0187

FFFC 0188 to FFFC 019F

Factory-Programmed

User-Programmed

8 bytes – 64 bit

24 bytes – 192 bit

T11.0 1292

1. Address shown is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory map depending

on ID strapping values on ID[3:0} pins according with multiple device selection mechanism.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

20

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

REGISTERS

There are five types of registers available on the

SST49LF00xC, the multi-byte Read/Write configuration

registers, General Purpose Inputs registers, Block Locking

registers, Security ID register, and the JEDEC ID registers.

These registers appear at their respective address location

in the 4 GByte system memory map. Unused register loca-

tions will read as 00H. Any attempt to read or write any reg-

ister during an internal Write operation will be ignored.

In case of multi-byte Firmware Memory register reads, the

device will return register data for the addressed register

until the command finishes, or is aborted.

General Purpose Inputs Register

The General Purpose Inputs register (GPI_REG) passes

the state of GPI[4:0] pins on the SST49LF00xC. It is rec-

ommended that the GPI[4:0] pins be in the desired state

before LFRAME# is brought low for the beginning of the

bus cycle, and remain in that state until the end of the cycle.

There is no default value since this is a pass-through regis-

ter. The GPI_REG register for the boot device appears at

FFBC0100H in the 4 GByte system memory map, and will

appear elsewhere if the device is not the boot device (see

Table 12). This register is not available to be read when the

device is in an Erase/Program operation. In case of multi-

byte Firmware Memory cycle register reads, the device will

return register data for the addressed register until the com-

mand finishes, or is aborted.

Read or write access to the register during an internal Pro-

gram/Erase operation will be completed as follows:

•

Multi-byte Read/Write Configuration registers,

General Purpose Inputs register, and Block Lock-

ing registers can be accessed normally

•

Security ID register and the JEDEC ID registers

can not be accessed (reading these registers will

return unused register data 00H).

Multi-Byte Read/Write Configuration Reg-

isters (Firmware Memory Cycle)

The multi-byte read/write configuration (MBR) registers are

four 8-bit read-only registers located at addresses

FFBC0005-FFBC0008 for boot configured device (see

Table 13). These registers are accessible using Firmware

Memory Read cycle only. These registers contain informa-

tion about multi-byte read and write access sizes that will

be accepted for Firmware Memory multi-byte Read com-

mands. The registers are not available in AAI mode.

TABLE 12: GENERAL PURPOSE REGISTER

Default

Register

Register Address¹

Value

Access

GPI_REG

FFBC 0100H

N/A

R

T12.0 1292

1. Address shown in this column is for boot device only.

Address locations should appear elsewhere in the 4

GByte system memory map depending on ID strapping

values on ID[3:0] pins according with multiple device

selection mechanism.

TABLE 13: MULTI-BYTE READ/WRITE CONFIGURATION REGISTERS

Register

Register Address¹

FFBC 0005H

FFBC 0006H

FFBC 0007H

FFBC 0008H

Data

Access Description

MULTI_BYTE_READ_L

MULTI_BYTE_READ_H

MULTI_BYTE_WRITE_L

MULTI_BYTE_WRITE_H

0100 1011b

0000 0000b

0000 0011b

0000 0000b

R

Device supports 1,2,4, 16, 128 Byte reads

Future Expansion for Read

Device supports 1, 2, 4 Byte Write

Future Expansion for Write

T13.0 1292

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory

map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

21

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

SST49LF00xC also provides PDA Sector Locking Regis-

ters at addresses shown in Table 15. These locking regis-

ters can be accessed only after Open Protected Area

command is executed. After Hide Protected Area com-

mand, as well as after Power On and Reset, read from

addresses specified in Table 15 returns unused register

space data 00H, and write to these addresses is ignored.

Block and PDA Sector Locking Registers

SST49LF00xC provides software controlled lock protection

through a set of Block Locking registers. The Block Locking

registers are read/write registers and they are accessible

through standard addressable memory locations specified

in Table 14. Unused register locations will return 00H if

read.

In case of multi-byte read of any locking register, the device

will return register data for the addressed register until the

command finishes, or is aborted.

In case of multi-byte register reads with Firmware Memory

cycle, the device will return register data for the addressed

register until the command finishes, or is aborted.

TABLE 14: BLOCK LOCKING REGISTERS

Block

Protected Memory Address¹Range

Memory Map

Register

Size

16K

8K

SST49LF004C

SST49LF008C

Register Address¹

T_BLOCK_LK

07FFFFH-07C000H

07BFFFH-07A000H

079FFFH-078000H

077FFFH-070000H

06FFFFH-060000H

05FFFFH-050000H

04FFFFH-040000H

03FFFFH-030000H

02FFFFH-020000H

01FFFFH-010000H

00FFFFH-000000H

0FFFFFH-0FC000H

0FBFFFH-0FA000H

0F9FFFH-0F8000H

0F7FFFH-0F0000H

0EFFFFH-0E0000H

0DFFFFH-0D0000H

0CFFFFH-0C0000H

0BFFFFH-0B0000H

0AFFFFH-0A0000H

09FFFFH-090000H

08FFFFH-080000H

07FFFFH-070000H

06FFFFH-060000H

05FFFFH-050000H

04FFFFH-040000H

03FFFFH-030000H

02FFFFH-020000H

01FFFFH-010000H

00FFFFH-000000H

FFBFC002H

FFBFA002H

FFBF8002H

FFBF0002H

FFBE0002H

FFBD0002H

FFBC0002H

FFBB0002H

FFBA0002H

FFB90002H

FFB80002H

FFB70002H

FFB60002H

FFB50002H

FFB40002H

FFB30002H

FFB20002H

FFB10002H

FFB00002H

T_MINUS01_LK

T_MINUS02_LK

T_MINUS03_LK

T_MINUS04_LK

T_MINUS05_LK

T_MINUS06_LK

T_MINUS07_LK

T_MINUS08_LK

T_MINUS09_LK

T_MINUS10_LK

T_MINUS11_LK

T_MINUS12_LK

T_MINUS13_LK

T_MINUS14_LK

T_MINUS15_LK

T_MINUS16_LK

T_MINUS17_LK

T_MINUS18_LK

8K

32K

64K

T14.0 1292

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory

map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.

TABLE 15: PROTECTED DATA AREA SECTOR LOCKING REGISTERS

SST49LF00xC PDA Protected Addresses¹

Sector

Size

Memory Map

Register

For Write Access

For Read Access

Register Address¹

T_PDA2_LK

T_PDA1_LK

T_PDA0_LK

4K

FFFC A000H–FFFC AFFFH

FFFC 9000H–FFFC 9FFFH

FFFC 8000H–FFFC 8FFFH

FFBC A000H–FFBC AFFFH

FFBC 9000H–FFBC 9FFFH

FFBC 8000H–FFBC 8FFFH

FFBC 2202H

FFBC 1202H

FFBC 0202H

T15.0 1292

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory

map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

22

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE 16: BLOCK/PDA SECTOR LOCKING REGISTER BITS

Reserved Bit Read-Lock Bit Lock-Down Bit Write-Lock Bit

[7:3]

[2]

[1]

[0]

Lock Status

00000

0

Full Access

0

1

Write Locked (Default State at Power-Up)

Locked Open (Full Access Locked Down)

Write Locked Down

0

1

0

1

0

Block Read Locked (Registers alterable)

Block Read & Write Lock (Registers alterable)

Block Read Locked Down (Registers not alterable)

1

0

1

0

1

Block Read & Write lock Down (Registers not alterable)

T16.0 1292

Write-Lock Bit

Lock-Down Bit

The Write-Lock bit, bit 0, controls the lock state described

in Table 16. The default Write status of all blocks after

power up is write locked. When bit 0 of the Block Locking

register is set, Program and Erase operations for the corre-

sponding block are prevented. Clearing the Write-Lock bit

will unprotect the block. The Write-Lock bit must be cleared

prior to starting a Program or Erase operation since it is

sampled at the beginning of the operation. The Write-Lock

bit functions in conjunction with the hardware Write Lock

pin TBL# for the top Boot Block. When TBL# is low, it over-

rides the software locking scheme. The top Boot Block

Locking register does not indicate the state of the TBL#

pin. The Write-Lock bit functions in conjunction with the

hardware WP#/AAI pin for the remaining blocks (Blocks 0

to 17 for 49LF008C and Blocks 0 to 9 for 49LF004C).

When WP#/AAI is low, it overrides the software locking

scheme. The Block Locking register does not indicate the

state of the WP#/AAI pin.

The Lock-Down bit, bit 1, controls the Block Locking regis-

ter as described in Table 16. When in LPC interface mode,

the default Lock Down status of all blocks upon power-up is

not locked down. Once the Lock-Down bit is set, any future

attempted changes to that Block Locking register will be

ignored. The Lock-Down bit is only cleared upon a device

reset with RST# or INIT# or power down. Current Lock

Down status of a particular block can be determined by

reading the corresponding Lock-Down bit. Once a block’s

Lock-Down bit is set, the Read-Lock and Write-Lock bits for

that block can no longer be modified: the block is locked

down in its current state of read/write accessibility.

Read-Lock Bit

The default read status of all blocks upon power-up is read-

unlocked. When a block’s read lock bit is set, data cannot

be read from that block. An attempted read from a read-

locked block will result in the data 00h. The read lock status

can be unlocked by clearing the read lock bit: this can only

be done provided that the block is not locked down. The

current read lock status of a particular block can be deter-

mined by reading the corresponding read-lock bit.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

23

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

Security ID Registers

The SST49LF0xxC devices offer a 256-bit Security ID reg-

ister space. The Security ID space is divided into two seg-

ments - one (64 bits) factory programmed segment and

one (192 bits) user programmed segment. The first seg-

ment is programmed and locked at SST with a unique 64-

bit number. The user segment (192-bits) is left blank (FFH)

for the customer to be programmed as desired. The user

can use standard Register read cycles to read the Security

ID space, or use the Security ID Program command to pro-

gram the space. Refer to Table 8, “Software Command

Sequence” for more details.

The Write Lock-out status of the Security ID space can be

read from the SEC_ID_WRITE_LOCK register (see Table

17). The SEC_ID_WRITE_LOCK register is a “read only”

register that is accessible at the address location specified

in Table 14. In the case of multi-byte register reads with

Firmware Memory cycle, for SEC_ID_WRITE_LOCK reg-

ister, the device will return register data for the addressed

register until the command finishes, or is aborted.

In the case of multi-byte register reads with Firmware Mem-

ory cycle, for the all the SEC_ID_BYTE registers, the

device will return page-aligned sequential register data with

wrap-around until the command finishes, or is aborted.

The Security ID Information and its Write Lock/Unlock sta-

tus can be Read in the Register Access Space for Execute-

In-Place (XIP) type of applications. (See Table 17.)

TABLE 17: SECURITY ID REGISTERS

Register

Register Address¹

Value

Access

Description

SEC_ID__WRITE_LOCK

FFBC0102H

0000 0000b

0000 0001b

R

Write Unlocked

Write Locked

SEC_ID_BYTE_0

SEC_ID_BYTE_1

SEC_ID_BYTE_2

SEC_ID_BYTE_3

…

FFBC0180H

FFBC0181H

FFBC0182H

FFBC0183H

…

R

…

R

…

R

Factory Programmed

…

SEC_ID_BYTE_7

SEC_ID_BYTE_8

SEC_ID_BYTE_9

…

FFBC0187H

FFBC0188H

FFBC0189H

…

Factory Programmed

User Programmed

…

SEC_ID_BYTE_30

SEC_ID_BYTE_31

FFBC019EH

FFBC019FH

User Programmed

T17.0 1292

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4GByte system memory

map depending on ID strapping values on ID[3:0] pins according with multiple device selection mechanism.

TABLE 18: JEDEC ID REGISTERS

JEDEC ID Registers

Register

Default

Value

The JEDEC ID registers for the boot device appear at

FFBC0000H and FFBC0001H in the 4 GByte system

memory map, and will appear elsewhere if the device is not

the boot device. This register is not available to be read

when the device is in Erase/Program operation. Unused

register location will read as 00H. See Table 18 for the

JEDEC device ID code. In case of multi-byte register reads

with Firmware Memory cycle, the device will return register

data for the addressed register until the command finishes,

or is aborted.

Register

Address¹

Access

MANUF_REG

DEV_REG

FFBC 0000H

BFH

R

SST49LF004C

SST49LF008C

FFBC 0001H

54H

59H

R

T18.0 1292

1. Address shown in this column is for boot device only.

Address locations should appear elsewhere in the 4

GByte system memory map depending on ID strapping

values on ID[3:0] pins when multiple LPC memory

devices are used in a system.

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

24

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

AUTO-ADDRESS INCREMENT (AAI) MODE

AAI Mode with Multi-byte Programming

AAI mode with multi-byte programming is provided for high-

speed production programming. Auto-Address Increment

mode requires only one address load for each 128-byte

page of data. The Multi-Byte Programming feature allows

simultaneous multi-byte programming. Note: The Security

ID area and the Protected Data Area cannot be pro-

grammed using AAI mode.

Data will be accepted by the device as long as LD# is low

and RY/BY# is high (until the last byte of the 128-byte page

has been entered). For partial data-loads (i.e., less than

128 Bytes), LD# may be taken high (V_IH) to end the data

loading. If LD# goes high before the full 128-byte page has

been entered, the device will program the data which has

been entered to that point, and then terminate the AAI

page programming command. Any incompletely loaded

data byte (nibble) will not be programmed. The device will

signify completion of the command by driving RY/BY# high.

Once RY/BY# goes high, LD# can be taken low to begin a

new AAI programming operation at a different address

location.

Taking the WP#/AAI pin to the Supervoltage V^Henables

the AAI mode. The AAI command is started as a normal

Firmware Memory cycle. LD# should be low (V_IL) as long

as data is being loaded into the device. In the MADDR field,

the host may input any address within the 128-byte page to

be programmed. The least significant seven bits of the

address field will be ignored and the device will begin pro-

gramming at the beginning of the 128-byte page (i.e., the

address will be page-aligned). The device Ready/Busy sta-

tus is output on the RY/BY# pin.

The RY/BY# pin will stay low while internal programming

completes. When the entire 128-byte page has been pro-

grammed, the device will return to the idle mode and the

RY/BY# pin will go high (V_IH) to indicate the AAI command

has been completed.

Data is accepted until the internal buffer is full. At that point

RY/BY# goes low (busy) to indicate that the internal buffer

is full and cannot accept any more data. When the device

is ready, RY/BY# pin goes high and indicates to the host

that more data (the next group of bytes) can be accepted

by the internal data buffer (see Table 19 and Figure 8).

TABLE 19: LD# INPUT AND RY/BY# STATUS IN

AAI MODE

LD# RY/BY# RY/BY#

state status

Flag indication

L

H

Device is Ready, can accept more data

until the last (128^th) byte.

LD# is taken high by the host after loading the final byte(s)

of the 128-byte page. the RY/BY# signal remains low until

the completion of internal programming. After the comple-

tion of programming, the part will go into idle mode and the

RY/BY# will go high indicating that the AAI command has

been completed (see Table 19). A subsequent AAI com-

mand may be initiated to begin programming the next 128-

byte page.

L

Device is Busy, cannot accept more data

H

Device is Ready for next operation if

previous data is the last (128^th) byte.

H

L

Device is Ready for next operation

Device is Busy programming

T19.0 1292

The user may terminate AAI programming by dropping the

WP#/AAI pin to TTL levels (V^IH/VIL) as long as LD# is high

and RY/BY# returns to high indicating the completion of the

AAI cycle. Software block-locking will be disabled in AAI

mode (all blocks will be write-unlocked). If AAI drops below

the Supervoltage V^Hbefore RY/BY# returns to high (and

LD# high), the contents of the page may be indeterminate.

S71292-00-000

1/06

25

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

AAI Data Load Protocol

TABLE 20: AAI PROGRAMMING CYCLE (INITIATED WITH WP#/AAI AT V_HONLY)

Clock Cycle Field Name

Field Contents

LAD[3:0]

Comments

1

2

START

IDSEL

1110

IN

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions

high) should be recognized. The START field contents

indicate a Firmware Memory Write cycle. (1110b)

0000b to 1111b

IN

ID works identically to Firmware Memory cycle.

This field indicates which SST49LF00xC device should

respond. If the IDSEL (ID select) field matches the

value of ID[3:0], then that particular device will

respond to the whole bus cycle.

3-9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

Only bits [19:7] for 8M, [18.7] for 4M of the total

address [27:0] are used for AAI mode. The rest are

“don’t care”.

10

MSIZE

DATA

KKKK

ZZZZ

IN

MSIZE field is don’t care when in AAI mode

11-266

Data is transmitted to the device least significant nib-

ble first, from byte 0 to byte 127 as long as the RY/BY#

is high and LD# low. The host will pause the clock and

data stream when RY/BY# goes low until it returns

high, signifying that the chip is ready for more data

T20.0 1292

V

H

WP#/AAI

1

2

3

4

5

6

7

8

9 10 11 12

264 266

LCLK

(Data Strobe Input)

LFRAME#

Start

MADDR

DATA

Byte N

DATA

DATA DATA

Address

LAD[3:0]

LD#

MSIZE

Byte 0

Byte

N+1

Byte

2N

Byte

126

Byte

127

IDSEL

RY/BY#

1292 F08.0

FIGURE 8: AAI Load Protocol Waveform

S71292-00-000

1/06

26

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

ELECTRICAL SPECIFICATIONS

The AC and DC specifications for the LPC interface signals (LAD[3:0], LFRAME#, LCLCK and RST#) as defined in Section

4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 21 for the DC voltage and current specifications. Refer to

Table 25 through Table 27 for the AC timing specifications for Clock, Read, Write, and Reset operations.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD+0.5V

Transient Voltage (<20 ns) on Any Pin (except WP#/AAI) to Ground Potential¹. . . . . . . . . . . . . . -2.0V to V_DD+2.0V

Voltage on WP#/AAI Pin to Ground Potential². . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11.0V

Package Power Dissipation Capability (T_A=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current⁴. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Do not violate processor or chipset specification regarding INIT# voltage.

2. The maximum DC voltage on WP#/AAI pin may reach 11V for periods <20ns.

3. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

4. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range

Ambient Temp

V_DD

Commercial

0°C to +85°C

3.0-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C_L= 30 pF

See Figure 14

S71292-00-000

1/06

27

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

DC Characteristics

TABLE 21: DC OPERATING CHARACTERISTICS (ALL INTERFACES)

Limits

Symbol Parameter

Min

Max

Units Test Conditions

1

I_DD

Active V_DDCurrent

LCLK (LPC mode)=V_ILT/V_IHTat f=33 MHz

All other inputs=V_ILor V_IH

Read

18

40

mA All outputs = open, V_DD=V_DDMax

mA f=33 MHz

Single-/Dual-Byte Program, Erase

Quad-Byte Program

60

mA f=33 MHz

I_SB

Standby V_DDCurrent

(LPC Interface)

100

µA

LCLK (LPC mode)=V_ILT/V_IHTat f=33 MHz

LFRAME#=.9V_DD, f=33 MHz,

V_DD=V_DDMax

All other inputs ≥ 0.9 V_DDor ≤ 0.1 V_DD

2

I_RY

Ready Mode V_DDCurrent

10

mA

LCLK (LPC mode)=V_ILT/V_IHTat f=33 MHz

LFRAME#=V_IL, f=33 MHz, V_DD=V_DDMax

All other inputs ≥ 0.9 V_DDor ≤ 0.1 V_DD

I_I

Input Leakage Current for ID[3:0] pins

Input Leakage Current

Output Leakage Current

Supervoltage Current for WP#/AAI

Supervoltage for WP#/AAI

INIT# Input High Voltage

INIT# Input Low Voltage

Input Low Voltage

200

1

µA

V

V_IN=GND to V_DD, V_DD=V_DDMax

V_OUT=GND to V_DD, V_DD=V_DDMax

I_LI

I_LO

I_H

1

200

VH

V_IHI

8.5

1.1

9.5

3

V_DD+0.5

0.4

V

V_DD=V_DDMax

3

V_ILI

V_IL

-0.5

V

V_DD=V_DDMin

0.3 V_DD

V

V_DD=V_DDMin

V_IH

V_OL

Input High Voltage

0.5 V_DDV_DD+0.5

0.1 V_DD

V

V_DD=V_DDMax

Output Low Voltage

V

I_OL=1500 µA, V_DD=V_DDMin

I_OH=-500 µA, V_DD=V_DDMin

V_OH

Output High Voltage

0.9 V_DD

V

T21.0 1292

1. I_DDactive while a Read or Write (Program or Erase) operation is in progress.

2. The device is in Ready mode when no activity is on the LPC bus.

3. Do not violate processor or chipset specification regarding INIT# voltage.

TABLE 22: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol

Parameter

Minimum

100

Units

µs

1

T_PU-READ

Power-up to Read Operation

Power-up to Write Operation

1

T_PU-WRITE

100

µs

T22.0 1292

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter

TABLE 23: PIN CAPACITANCE (V_DD=3.3V, T_A=25 °C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O=0V

Maximum

12 pF

1

C_I/O

I/O Pin Capacitance

Input Capacitance

Pin Inductance

1

C_IN

V_IN=0V

12 pF

2

L_PIN

20 nH

T23.0 1292

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. Refer to PCI spec.

S71292-00-000

1/06

28

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE 24: RELIABILITY CHARACTERISTICS

Minimum

Symbol

Parameter

Endurance

Data Retention

Latch Up

Specification

Units

Cycles

Years

mA

Test Method

1

N_END

10,000

100

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard 78

1

T_DR

1

I_LTH

100 + I_DD

T24.0 1292

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 25: CLOCK TIMING PARAMETERS (LPC MODE)

Symbol

T_CYC

T_HIGH

T_LOW

-

Parameter

Min

30

11

1

Max

Units

ns

Cycle Time

LCLK High Time

ns

LCLK Low Time

ns

LCLK Slew Rate (peak-to-peak)

RST# or INIT# Slew Rate

4

V/ns

-

50

mV/ns

T25.0 1292

T

CYC

T

HIGH

0.6 V

DD

T

LOW

0.5 V

DD

0.4 V

(minimum)

p-to-p

DD

0.4 V

DD

0.3 V

DD

0.2 V

DD

1292 F09.0

FIGURE 9: LCLK WAVEFORM (LPC MODE)

S71292-00-000

1/06

29

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

TABLE 26: RESET TIMING PARAMETERS, V_DD=3.0-3.6V (LPC MODE)

Symbol

T_PRST

T_RSTP

T_RSTF

Parameter

Min

100

Max

Units

V_DDstable to Reset High

µs

RST# Pulse Width

ns

RST# Low to Output Float

RST# High to LFRAME# Low

RST# Low to reset during Sector-/Block-Erase or Program

48

10

1

T_RST

5

LCLK cycles

T_RSTE

µs

T26.0 1292

1. There will be a latency due to T_RSTEif a reset procedure is performed during a Program or Erase operation,

V

DD

T

PRST

T

RSTP

RST#/INIT#

Sector-/Block-Erase

T

RSTE

or Program operation

aborted

T

RST

T

RSTF

LAD[3:0]

LFRAME#

1292 F10.0

FIGURE 10: RESET TIMING DIAGRAM (LPC MODE)

S71292-00-000

1/06

30

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

AC Characteristics

TABLE 27: READ/WRITE CYCLE TIMING PARAMETERS, V_DD=3.0-3.6V (LPC MODE)

Symbol

T_CYC

T_SU

Parameter

Min

30

7

Max

Units

ns

Clock Cycle Time

Data Set Up Time to Clock Rising

Clock Rising to Data Hold Time

Clock Rising to Data Valid

Byte Programming Time

ns

T_DH

0

ns

1

T_VAL

2

11

10

25

10

ns

T_BP

T_SE

T_BE

T_ES

T_ON

T_OFF

µs

Sector-Erase Time

ms

µs

Block-Erase Time

Program/Erase-Suspend Latency

Clock Rising to Active (Float to Active Delay)

Clock Rising to Inactive (Active to Float Delay)

2

ns

28

ns

T27.0 1292

1. Minimum and maximum times have different loads. See PCI spec

TABLE 28: AC INPUT/OUTPUT SPECIFICATIONS (LPC MODE)

Symbol

I_OH(AC)

Parameter

Min

Max

Units

mA

Conditions

Switching Current High

-12 V_DD

0 < V_OUT≤ 0.3V_DD

0.3V_DD< V_OUT< 0.9V_DD

0.7V_DD< V_OUT< V_DD

V_OUT= 0.7V_DD

-17.1(V_DD-V_OUT

)

mA

Equation C¹

-32 V_DD

(Test Point)

mA

I_OL(AC)

Switching Current Low

16 V_DD

26.7 V_OUT

Equation D¹

mA

V_DD>V_OUT≥ 0.6V_DD

0.6V_DD> V_OUT> 0.1V_DD

0.18V_DD> V_OUT> 0

(Test Point)

38 V_DD

mA

V_OUT= 0.18V_DD

I_CL

Low Clamp Current

High Clamp Current

Output Rise Slew Rate

Output Fall Slew Rate

-25+(V_IN+1)/0.015

-3 < V_IN≤-1

I_CH

25+(V_IN-V_DD-1)/0.015

mA

V_DD+4 > V_IN≥ V_DD+1

0.2V_DD-0.6V_DDload

0.6V_DD-0.2V_DDload

slewr²

slewf²

1

4

V/ns

T28.0 1292

1. See PCI spec.

2. PCI specification output load is used.

S71292-00-000

1/06

31

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

V

TH

TL

V

TEST

LCLK

T

VAL

LAD [3:0]

(Valid Output Data)

LAD [3:0]

(Float Output Data)

T

ON

T

OFF

1292 F11.0

FIGURE 11: OUTPUT TIMING PARAMETERS (LPC MODE)

V

TH

TL

V

LCLK

TEST

T

SU

T

DH

LAD [3:0]

(Valid Input Data)

Inputs

Valid

V

MAX

1292 F12.0

FIGURE 12: INPUT TIMING PARAMETERS (LPC MODE)

TABLE 29: INTERFACE MEASUREMENT CONDITION PARAMETERS (LPC MODE)

Symbol

Value

0.6 V_DD

0.2 V_DD

0.4 V_DD

1

Units

1,2

V_TH

V

1,2

V_TL

V_TEST

V

1,2

V_MAX

V

Input Signal Edge Rate

V/ns

T29.0 1292

1. The input test environment is done with 0.1 V_DDof overdrive over V_IHand V_IL. Timing parameters must be met with no more over-

drive than this. V_MAXspecifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use

different voltage values, but must correlate results back to these parameters.

2. In the case of multi-byte read, V_TL= 0.1 V_DDand V_TH= 0.9V_DD

S71292-00-000

1/06

32

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

V

H

WP#/AAI

T

ACYC

V

TH

TL

V

TEST

LCLK

T

ASU

T

ADH

LAD [3:0]

(Valid Input Data)

V

Inputs Valid

MAX

T

LDSU

T

LDDH

LD#

T

RB

RY/BY#

1292 F13.0

FIGURE 13: INPUT TIMING PARAMETERS (AAI MODE)

TABLE 30: INPUT CYCLE TIMING PARAMETERS, V_DD=3.0-3.6V (AAI MODE)

Symbol

T_ACYC

T_ASU

Parameter

Min

135

25

Max

Units

ns

Clock Cycle Time

Data Set Up Time to Clock Rising

Clock Rising to Data Hold Time

RY/BY# LD# Falling

LD# Set Up Time

ns

T_ADH

25

ns

T_RB

25

ns

T_LDSU

T_LDDH

25

ns

LD# Hold Time

25

ns

T30.0 1292

TO TESTER

TO DUT

C

L

1292 F15.0

FIGURE 14: A TEST LOAD EXAMPLE

S71292-00-000

1/06

33

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

PRODUCT ORDERING INFORMATION

SST49LF 008C

-

33

-

4C

-

WH E

SST49LF xxxC

-

XXX

-

XX

-

XX X

Environmental Attribute

E¹= non-Pb

Package Modifier

H = 32 leads

Package Type

N = PLCC

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Operating Frequency

33 = 33 MHz

Device Density

008 = 8 Mbit

004 = 4 Mbit

Voltage

L = 3.0-3.6V

Product Series

49 = LPC Serial Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

Valid combinations for SST49LF004C

SST49LF004C-33-4C-NHE SST49LF004C-33-4C-WHE

Valid combinations for SST49LF008C

SST49LF008C-33-4C-NHE SST49LF008C-33-4C-WHE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

S71292-00-000

1/06

34

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

BOTTOM VIEW

PACKAGING DIAGRAMS

TOP VIEW

SIDE VIEW

.495

.485

.112

.106

.453

.447

Optional

Pin #1

Identifier

.048

.042

.029

.023

.040

.030

.020 R.

MAX.

x 30˚

R.

2

1

32

.042

.048

.021

.013

.400

BSC

.530

.490

.595 .553

.585 .547

.032

.026

.050

BSC

.015 Min.

.095

.075

.050

BSC

.032

.026

.140

.125

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

32-plcc-NH-3

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

S71292-00-000

1/06

35

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

Advance Information

1.05

0.95

Pin # 1 Identifier

0.50

BSC

8.10

7.90

0.27

0.17

0.15

0.05

12.50

12.30

DETAIL

1.20

max.

0.70

0.50

14.20

13.80

0˚- 5˚

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

32-tsop-WH-7

1mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

TABLE 31: REVISION HISTORY

Revision

Description

Date

00

Jan 2006

•

Initial release of data sheet

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036

www.SuperFlash.com or www.sst.com

S71292-00-000

1/06

36


型号：	SST49LF004C-33-4C-WH
厂家：	SILICON
描述：	Flash, 512KX8, 11ns, PDSO32, 8 X 14 MM, MO-142BA, TSOP1-32 光电二极管
文件：	总36页 (文件大小：509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SST49LF004C-33-4C-WH [SILICON]

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