Si4770 [SILICON]
HIGH-PERFORMANCE CONSUMER ELECTRONICS; 高性能消费电子
| 型号： | Si4770 |
| 厂家： | 
SILICON |
| 描述： | HIGH-PERFORMANCE CONSUMER ELECTRONICS |
| 文件： | 总54页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4770/77-A20
HIGH-PERFORMANCE CONSUMER ELECTRONICS
BROADCAST RADIO RECEIVER AND HD RADIO TUNER
Features
Worldwide FM band support
AM/FM hi-cut control
AM lo-cut filter
(64–108 MHz)
Worldwide AM band support
2
L/R analog and digital (I S) audio
(520–1710 kHz)
outputs
AM/FM HD Radio support
Digital Low-IF architecture
(Si4777 only)
Frequency synthesizer with fully
Comprehensive signal quality
metrics: RSSI, SNR, multipath
interference, frequency offset,
adjacent channel RSSI,
frequency deviation, and image
RSSI
integrated PLL-VCO
Fully integrated AM/FM front-end
including high performance LNA,
AGC with integrated resistor and
capacitor banks, and RF and IF
peak detectors
Ordering Information:
See page 49.
Pin Assignments
Si4770/77-A20
Advanced patented RDS soft-
Integrated crystal oscillator
decision decoder
2
Digital (I S) Zero-IF AM/FM I/Q
Advanced, patented FM channel
equalizer for multipath
interference
outputs (Si4777 only)
1.2 to 5 V power supplies
QFN 40-pin, 6x6x0.85 mm
Pb-free/RoHS compliant
Dynamic AM/FM channel
bandwidth control
1
2
30
29
28
27
26
25
24
23
22
21
NC
FMXIP
FMXIN
RFGND
RFREG
FMO
NC/BLEND
DCLK
Programmable AM/FM soft mute
FM stereo-mono blend
FM hi-blend control
3
DFS
4
DOUT
5
NC/QOUT
NC/IOUT
NC/IQFS
NC/IQCLK
VIO2
GND PAD
6
7
FMI
8
NC
Applications
9
NC
10
AMI
DBYP
Audio/video receivers
Consumer electronics
Boom boxes
Home theater systems
Description
Patents pending
The Si4770/77-A20 broadcast receiver and HD Radio tuner (Si4777 only)
employs an advanced, proven digital low-IF architecture to bring
outstanding receiver performance to high-performance consumer
electronics.
Rev. 0.9 6/12
Copyright © 2012 by Silicon Laboratories
Si4770/77-A20
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si4770/77-A20
Functional Block Diagram
Si4770/77
LOUT/
MPXOUT
ADC
DAC
DAC
FMXIP
FMXIN
DSP
IF PKD
RF PKD
ADC
ROUT
RFREG
REG
LNA
RL
DCLK
DFS
DOUT
FMO
FMI
0°/90°
RDS
RF PKD
RF PKD
INTB
RSTB
VIO1
VIO2
AMI
LNA
CNTRL
ClK
Gen
RFGND
2
Rev. 0.9
Si4770/77-A20
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.2. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.3. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.4. FM Receiver Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.5. AM Receiver Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.6. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.7. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.8. Channel Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.9. Digital ZIF I/Q Interface (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.10. IBOC Blend Mode for HD Radio (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.11. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.12. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.13. Analog Audio and FM MPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.14. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.15. AM/FM Dynamic Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.16. Seek and Valid Station Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.17. AM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.18. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.19. FM Hi-Blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.20. AM Lo-Cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5. RDS/RBDS Advanced Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
6. Programming Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2
7. I C Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2
7.1. I C Device Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2
7.2. I C Standard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
8. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
9. Pin Descriptions: Si4770/77-A20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
11. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
13. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.1. Si4770/77-A20 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
13.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Rev. 0.9
3
Si4770/77-A20
1. Electrical Specifications
Table 1. Recommended Operation Conditions*
Parameter
Symbol
Test Condition
Min
4.5
2.7
1.7
1.2
Typ
5
Max
5.5
3.6
3.6
3.6
Unit
V
Analog Supply Voltage
Digital Supply Voltage
Interface Supply Voltage
V
—
—
—
—
A
V
3.3
3.3
3.3
V
D
V
V
V
IO1
IO2
V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VD = 3.3 V, VIO1 = 3.3 V, VIO2 = 3.3 V, VA = 5 V, and 25 °C unless otherwise stated. Parameters
are tested in production unless otherwise stated.
Table 2. DC Characteristics
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
FM Mode
Total Supply Power
671
121
47
850
130
60
1049
139
79
mW
mA
mA
µA
V Supply Current
I
VA
A
V Supply Current
I
VD
D
V Supply Power Down
I
20
90
170
A
VA
Current
V Supply Power Down
I
5
20
50
µA
D
VD
Current
AM Mode
Total Supply Power
707
129
47
900
140
60
1100
147
81
mW
mA
mA
µA
V Supply Current
I
VA
A
V Supply Current
I
VD
D
V Supply Power Down
I
20
90
170
A
VA
Current
V Supply Power Down
I
5
20
50
µA
D
VD
Current
*Note: See "7. I2C Control Bus" on page 44.
4
Rev. 0.9
Si4770/77-A20
Table 2. DC Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Interface Supplies
V
V
V
Supply Current
I
I
0.1
0.1
0.5
0.2
0.82
0.5
mA
mA
µA
IO1
IO2
IO1
VIO1
Supply Current
VIO2
Supply Power Down
I
I
150
250
420
PD
PD
Current*
V
Supply Power Down
5
20
150
µA
IO2
Current*
Inputs Pins SCL, SDA, RSTB, A0, A1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
V
0.7 x V
—
—
—
—
—
—
V
V
IH
IO1
V
0.3xV
10
IL
IO1
I
V
= V = 3.6 V
–10
µA
µA
IH
IN
I01
I
V
= 0 = V,
= 3.6 V
–10
10
IL
IN
V
I01
Input Pins DCLK, DFS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
V
0.7 x V
—
—
—
—
—
—
V
V
IH
IO2
V
0.3 x V
10
IL
IO2
I
V
= V = 3.6 V
–10
µA
µA
IH
IN
I02
I
V
= 0 V,
IN
–10
10
IL
V
= 3.6 V
I02
Input Pins GPIO1, GPIO2
GPIO1 and GPIO2
are internally regu-
lated at 3.6 V
High Level Input Voltage
V
2.52
—
—
V
IH
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Output Pins INTB
V
—
—
—
—
1.08
10
V
IL
I
V
= 3.6 V
IN
–10
–10
μA
μA
IH
I
V
= 0 V
IN
10
IL
Output is common
drain output with
internal 10 k pull-
High Level Output Voltage
V
0.8xV
—
—
—
—
V
V
OH
IO1
up to V
IO1
Low Level Output Voltage
V
I
= –500 μA
0.2xV
IO1
OL
OUT
*Note: See "7. I2C Control Bus" on page 44.
Rev. 0.9
5
Si4770/77-A20
Table 2. DC Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Pins SDA
Output is common
drain output with
external 4.7 k
High Level Output Voltage
V
0.8xV
—
—
—
—
V
V
OH
IO1
pull-up to V
IO1
Low Level Output Voltage
V
I
= –500 μA
0.2xV
—
OL
OUT
IO1
Output Pins GPIO1, GPIO2
GPIO1 and GPIO2
are internally regu-
lated at 3.6 V,
High Level Output Voltage
Low Level Output Voltage
V
2.88
—
—
—
V
V
OH
IOUT = +500 μA
V
I
= –500 μA
OUT
0.72
OL
Output Pins IQCLK, IQFS, IOUT, QOUT, DFS, DCLK, DOUT
High Level Output Voltage
Low Level Output Voltage
V
I
= 500 µA
0.8 x V
—
—
—
—
V
V
OH
OUT
IO2
V
I
= –500 µA
0.2 x V
IO2
OL
OUT
*Note: See "7. I2C Control Bus" on page 44.
6
Rev. 0.9
Si4770/77-A20
Table 3. Digital Audio Interface Characteristics*
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DCLK Input Cycle Time
t
70
—
—
ns
CYC: DCLK
DCLK Input Pulse Width
High
t
0.4 x t
—
—
0.6 x t
ns
ns
HI: DCLK
CYC:DCLK
CYC:DCLK
DCLK Input Pulse Width
Low
t
0.4 x t
0.6 x t
CYC:DCLK
LO: DCLK
CYC:DCLK
DFS Setup Time
DFS Hold Time
t
10
5
—
—
—
—
—
—
—
35
10
15
ns
ns
ns
SU:DFS
t
HD:DFS
DOUT ouTput Delay
t
0
PD:DOUT
VIO < 1.33 V
—
—
2
Capacitive Loading
C
pF
B
VIO > 1.33 V
2
*Note: Guaranteed by characterization.
tCYC:DCLK
tHI:DCLK tLO:DCLK
DCLK in
tSU:DFS
tHD:DFS
DFS in
tPD:DOUT
DOUT out
Figure 1. Digital Audio
Rev. 0.9
7
Si4770/77-A20
Table 4. Digital Zero-IF I/Q Interface Characteristics (Si4777 Only)1
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test
Min
Typ
Max
Unit
Condition
2
IQCLK Output Cycle Time
IQCLK Output Pulse Width High
IQCLK Output Pulse Width Low
IQFS Output Delay
t
0.8 x per
0.22 x per
0.41 x per
0
per
1.2 x per
0.59 x per
0.78 x per
(0.5 x per) + 18
—
ns
ns
ns
ns
ns
CYC:IQCLK
t
—
—
—
—
HI:IQCLK
t
LO:IQCLK
t
PD:IQFS
SU:IQFS
IQFS Output Setup to IQCLK
t
(0.5 x per) – 18
3
Rise
IOUT Output Delay
t
0
—
—
—
—
(0.5 x per) + 18
ns
ns
ns
ns
PD:IOUT
QOUT Output Delay
t
0
(0.5 x per) + 18
PD:QOUT
3
IOUT Output Setup to IQCLK rise
t
(0.5 x per) – 18
(0.5 x per) – 18
—
—
SU:IOUT
QOUT Output Setup to IQCLK
t
SU:QOUT
3
Rise
Notes:
1. Guaranteed by characterization.
2. per is the IQCLK I/Q bit clock period. Refer to Table 15 on page 35 for IQCLK bit clock frequencies.
3. Minimum time the Si4770/77-A20 will produce between valid output and the next rising edge of IQCLK
t
CYC:IQCLK Max
tCYC:IQCLK Min
IQCLK out
tHI:IQCLK MIN
tLO:IQCLK MAX
tLO:IQCLK MIN
tHI:IQCLK MAX
tPD:IQFS MAX
tPD:IQFS MIN
tSU:IQFS
tSU:IOUT
tSU:QOUT
IQFS out
IOUT out
QOUT out
tPD:IOUT MAX
t
PD:IOUT MIN
tPD:QOUT MAX
tPD:QOUT MIN
Figure 2. Digital Zero-IF I/Q
8
Rev. 0.9
Si4770/77-A20
Table 5. Reference Clock and Crystal Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reference Clock, Pin RCLK
RCLK Supported
Frequencies
—
36.4
37.8
—
MHz
37.209375
–100
—
100
ppm
RCLK Frequency
Tolerance
RCLK = 36.4 MHz, 37.8 MHz, 37.209375 MHz
Phase Noise
100 Hz offset
1 kHz offset
10 kHz offset
—
—
—
—
—
—
—
—
—
7
–86
–101
–108
–122
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
pF
≥ 100 kHz offset
Input Capacitance
Input Voltage
AC coupling capacitor = 1 µF
Square wave input
400
mV
PP
AC coupling capacitor = 1 µF
Sine wave input
300
—
—
900
—
mV
PP
Crystal Oscillator, Pins XTAL1, XTAL2
Crystal Frequency
36.4
37.8
MHz
37.209375
–100
5
—
—
100
ppm
pF
Crystal Frequency
Tolerance
Load Capacitance, Pro-
grammable, Each Pin to
GND
21.8
Rev. 0.9
9
Si4770/77-A20
Table 6. I2C Control Interface Characteristics
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Pins SCL, SDA
SCL Frequency
SCL Low Time
SCL High Time
f
0
—
—
—
—
400
—
kHz
µs
SCL
t
1.3
0.6
0.6
LOW
t
—
µs
HIGH
SCL Input to SDA Setup
(START)
t
t
—
µs
SU:STA
SCL Input from SDA Hold
0.6
—
—
µs
HD:STA
(START)
SDA Input to SCL Setup
SDA Input from SCL Hold
SDA Output Delay
t
t
100
0
—
—
—
—
ns
ns
ns
SU:DAT
900
900
HD:DAT
t
300
PD:DAT
SCL Input to SDA Setup
(STOP)
t
0.6
1.3
—
—
µs
SU:STO
STOP to START Time
SDA Output Fall Time
t
—
—
—
µs
ns
BUF
t
250
f:OUT
CB
----------
20 + 0.1
1pF
SDA Input, SCL Rise/Fall
Time
t
t
—
300
ns
f:IN, r:IN
CB
----------
1pF
20 + 0.1
Capacitive Loading
C
—
—
—
—
50
50
pF
ns
B
Pulse Width Rejected by
Input Filter
t
SP
10
Rev. 0.9
Si4770/77-A20
tSU:STA tHD:STA
tLOW
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
SCL
SDA
70%
30%
tf:IN,
tf:OUT
START
tHD:DAT tSU:DAT
tPD:DAT
tr:IN
STOP
START
Figure 3. I2C Control Interface Read and Write Timing Parameters
SCL
Command
7-0
Arg1
7-0
SDA
(Write)
A6-A0, 0
START
START
ADDRESS + R/W
ACK
ACK
DATA
ACK
ACK
DATA
ACK
ACK
STOP
Status
7-0
Response
7-0
SDA
(Read)
A6-A0, 1
ADDRESS + R/W
DATA
DATA
STOP
Figure 4. I2C Control Interface Read and Write Timing Diagram
Rev. 0.9
11
Si4770/77-A20
Table 7. FM Receiver Characteristics
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, FM modulation (L = R), FMOD = 1 kHz, FDEV = 22.5 kHz, Deemphasis = 75 µsec, RF level = 60 dBµV, and
FRF = 98 MHz in application circuit unless otherwise specified)
Parameter
Test Condition
Min
64
Typ
—
Max
108
200
Unit
MHz
kHz
Input Frequency
Frequency Step
Resolution
10
—
1,2
Powerup Time
—
—
100
ms
RCLK or Crystal = 36.4 MHz, 37.8 MHz,
37.209375 MHz
1
Tune time
—
—
—
1.5
20
—
—
—
ms
ms
1
Seek Time/Channel
Max Frequency
At LOUT and ROUT pins
Audio THD <1%,
over-deviation handling enabled
150
kHz
1
Deviation
RF AGC Range
AGC Gain
Resolution
—
—
40
2
—
—
dB
dB
3
RF AGC Threshold
Accuracy
2
1
—
—
dB
dB
3
IF AGC Threshold
3
Accuracy
Following FM Receiver Specifications Refer to Si4770/77-A20 Application Circuit Input
6
IP3
Blockers at 400/800 kHz offset
AGC disabled (Max RF gain)
115
—
117
—
dBµV
dBµV
6
Sensitivity
Audio SINAD = 26 dB
–3.5
–2
AGC disabled (Max RF gain)
1
Image Rejection
Deviation = 22.5 kHz
Audio SINAD = 26 dB
65
63
70
65
—
—
dB
dB
Adjacent Channel
1,6
Rejection
Desired = 40dBµV, F
= 1 kHz,
MOD
F
= 22.5 kHz
DEV
Undesired at ±100 kHz offset, F
= 400 Hz,
MOD
F
= 22.5 kHz
DEV
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. Guaranteed by design.
4. IP3 measured at the FMXIP and FMXIN pins reflects IP3 for mixer stage and all subsequent downstream blocks.
5. Refer to FM test circuit in Figure 5.
6. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
7. Input resistance is software configurable.
8. IP3 measured at the FMI input pin reflects IP3 for FMI LNA stage.
9. RDS Synchronization Persistence is the minimum RF level at which the tuner loses synchronization to the RDS PI code
as the RF level decreases from high to low levels.
10. RDS Synchronization Stability is the minimum RF level at which the tuner achieves synchronization to the RDS PI code
as the RF level increases from low to high levels.
11. Noise integrated from 30 Hz to 120 kHz for audio SINAD and SNR measurements.
12
Rev. 0.9
Si4770/77-A20
Table 7. FM Receiver Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, FM modulation (L = R), FMOD = 1 kHz, FDEV = 22.5 kHz, Deemphasis = 75 µsec, RF level = 60 dBµV, and
FRF = 98 MHz in application circuit unless otherwise specified)
Parameter
Test Condition
Min
Typ
Max
Unit
Alternate Channel
Rejection
Audio SINAD = 26 dB
65
72
—
dB
6
Desired = 40 dBµV, F
= 1 kHz,
MOD
F
= 22.5 kHz
DEV
Undesired at ±200 kHz offset, F
= 400 Hz,
MOD
F
= 22.5 kHz
DEV
THD
F
= 75 kHz
—
66
64
0.05
75
0.1
—
%
DEV
6
Mono (S+N)/N
dB
dB
6
Stereo (S+N)/N
Stereo modulation (L = 1, R = 0),
deviation = 67.5 kHz,
70
—
pilot deviation = 6.75 kHz
1
AM Suppression
AM: m = 0.3/Fmod = 1 kHz, RF level = 60 dBµV
50
70
45
–1
40
55
75
50
—
43
—
80
54
1
dB
µsec
µsec
dB
De-Emphasis Time
3
Constant
L/R Imbalance
Deviation = 75 kHz
Stereo Separation
Stereo modulation (L = 1, R = 0),
—
dB
Deviation = 67.5 kHz, pilot deviation = 6.75 kHz
Stereo THD
Stereo modulation (L = 1, R = 0),
Deviation = 67.5 kHz, pilot deviation = 6.75 kHz
—
—
0.1
55
0.2
—
%
Pilot Signal
Stereo modulation (L = 1, R = 0),
Deviation = 67.5 kHz, pilot deviation = 6.75 kHz
dB
1
Rejection
1
RDS Sensitivity
f = 2 kHz, RDS BLER < 5%
—
—
13
70
14.5
—
dBµV
ms
RDSSynchronization
f = 2 kHz
RF input = 60 dBµV
1
Time
1
RDS PI Lock Time
f = 2 kHz
—
85
—
ms
RF input = 60 dBµV
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. Guaranteed by design.
4. IP3 measured at the FMXIP and FMXIN pins reflects IP3 for mixer stage and all subsequent downstream blocks.
5. Refer to FM test circuit in Figure 5.
6. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
7. Input resistance is software configurable.
8. IP3 measured at the FMI input pin reflects IP3 for FMI LNA stage.
9. RDS Synchronization Persistence is the minimum RF level at which the tuner loses synchronization to the RDS PI code
as the RF level decreases from high to low levels.
10. RDS Synchronization Stability is the minimum RF level at which the tuner achieves synchronization to the RDS PI code
as the RF level increases from low to high levels.
11. Noise integrated from 30 Hz to 120 kHz for audio SINAD and SNR measurements.
Rev. 0.9
13
Si4770/77-A20
Table 7. FM Receiver Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, FM modulation (L = R), FMOD = 1 kHz, FDEV = 22.5 kHz, Deemphasis = 75 µsec, RF level = 60 dBµV, and
FRF = 98 MHz in application circuit unless otherwise specified)
Parameter
Test Condition
Min
Typ
Max
Unit
FM Mixer Inputs: Pins FMXIP, FMXIN
Maximum RF Input
Voltage
1 dB compression point of mixer
—
—
—
—
—
112
8
—
—
—
—
—
dBµV
k
3
Mixer Input
Resistance
3
Mixer Input
Capacitance
6
pF
3
4,5,6
IP3
Blockers at 400/800 kHz offset,
Max Gain (AGC disabled)
123
3.5
dBµV
dBµV
5,6
Sensitivity
Audio SINAD = 26 dB
Max Gain (AGC disabled)
FM Resistor Banks: FMAGC1, FMAGC2
FMAGC1 Min
—
—
—
—
—
—
2.5
800
800
2.5
—
—
—
—
—
—
FMAGC1 Max
FMAGC1 Step Size
FMAGC2 Min
Maximum parallel resistance change
FMAGC2 Max
800
800
FMAGC2 Step Size
FM LNA: Pins FMI, FMO
Single Receiver Mode
FMI Input
Maximum parallel resistance change
—
—
50
2
—
—
3,7
Resistance
FMI Input
Capacitance
pF
dB
3
3
FMI Return Loss
64 MHz < F < 108 MHz
—
—
15
—
—
FMI Input Referred
0.73
3
nV/ Hz
dBµV
Noise
3,8
FMI LNA IP3
Blockers at 400/800 kHz offset, Max Gain
—
128
—
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. Guaranteed by design.
4. IP3 measured at the FMXIP and FMXIN pins reflects IP3 for mixer stage and all subsequent downstream blocks.
5. Refer to FM test circuit in Figure 5.
6. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
7. Input resistance is software configurable.
8. IP3 measured at the FMI input pin reflects IP3 for FMI LNA stage.
9. RDS Synchronization Persistence is the minimum RF level at which the tuner loses synchronization to the RDS PI code
as the RF level decreases from high to low levels.
10. RDS Synchronization Stability is the minimum RF level at which the tuner achieves synchronization to the RDS PI code
as the RF level increases from low to high levels.
11. Noise integrated from 30 Hz to 120 kHz for audio SINAD and SNR measurements.
14
Rev. 0.9
Si4770/77-A20
Table 7. FM Receiver Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, FM modulation (L = R), FMOD = 1 kHz, FDEV = 22.5 kHz, Deemphasis = 75 µsec, RF level = 60 dBµV, and
FRF = 98 MHz in application circuit unless otherwise specified)
Parameter
Test Condition
Min
Typ
Max
Unit
FMO Output
Resistance
Nominal FMI to FMO gain = 8 dB,
—
125
—
3
Source load = 50
FMO Output
Capacitance
—
2
—
pF
3
Dual Receiver Mode
FMI Input
Resistance
—
—
100
1.5
—
—
7,3
FMI Input
Capacitance
pF
dB
3
3
FMI Return Loss
64 MHz < F < 108 MHz
—
—
15
—
—
FMI Input Referred
1.20
3
nV/ Hz
dBµV
Noise
3,8
FMI LNA IP3
Blockers at 400/800 kHz offset, Max Gain
—
—
126
250
—
—
FMO Output
Resistance
Nominal FMI to FMO gain = 8dB,
3
Source load = 50
FMO Output
Capacitance
—
2
—
pF
3
Audio Outputs: Pins LOUT and ROUT
Audio Frequency
Response Low
±3 dB
±3 dB
—
15
—
—
—
—
30
—
—
50
Hz
kHz
1,2
Audio Frequency
1,2
Response High
Output Load
At LOUT and ROUT pins
At LOUT and ROUT pins
10 k
—
3
Resistance
Output Load
Capacitance
pF
3
Output Voltage
Deviation = 22.5 kHz
99
—
112
45
125
—
mVRMS
dB
Power Supply
Rejection Ratio
100 Hz ripple on power supply lines.
Ripple voltage = 100 mV of power supply
PP
3
(PSRR)
voltage
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. Guaranteed by design.
4. IP3 measured at the FMXIP and FMXIN pins reflects IP3 for mixer stage and all subsequent downstream blocks.
5. Refer to FM test circuit in Figure 5.
6. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
7. Input resistance is software configurable.
8. IP3 measured at the FMI input pin reflects IP3 for FMI LNA stage.
9. RDS Synchronization Persistence is the minimum RF level at which the tuner loses synchronization to the RDS PI code
as the RF level decreases from high to low levels.
10. RDS Synchronization Stability is the minimum RF level at which the tuner achieves synchronization to the RDS PI code
as the RF level increases from low to high levels.
11. Noise integrated from 30 Hz to 120 kHz for audio SINAD and SNR measurements.
Rev. 0.9
15
Si4770/77-A20
Table 7. FM Receiver Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, FM modulation (L = R), FMOD = 1 kHz, FDEV = 22.5 kHz, Deemphasis = 75 µsec, RF level = 60 dBµV, and
FRF = 98 MHz in application circuit unless otherwise specified)
Parameter
Test Condition
Min
Typ
Max
Unit
FM MPX Output: Pins MPXOUT
F
= 83 MHz, RF level = 65 dBµV,
RF
F
1
= 3 kHz, F
= 76 kHz
Output Voltage
14
16
—
mVRMS
DEV
MOD
unless otherwise noted
Output Load
Resistance
—
—
10
50
—
—
k
3
Output Load
Capacitance
pF
3
100 Hz ripple on power supply lines.
3
PSRR
—
45
—
—
—
dB
Ripple voltage = 100 mV of power supply volt-
PP
age
1
Bandwidth
110
kHz
Following FM MPX Specifications Refer to Si4770/77-A20 Application Circuit
F
= 83 MHz, RF level = 65 dBµV,
RF
F
1,11
= 3 kHz, F
= 76 kHz
(S+N)/N
25
—
30
19
—
dB
DEV
MOD
unless otherwise noted
= 83 MHz, F = 3 kHz, F = 76 kHz
MOD
F
RF
DEV
1,11
unless otherwise noted,
Sensitivity
25
dBµV
SINAD = 5 dB
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. Guaranteed by design.
4. IP3 measured at the FMXIP and FMXIN pins reflects IP3 for mixer stage and all subsequent downstream blocks.
5. Refer to FM test circuit in Figure 5.
6. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
7. Input resistance is software configurable.
8. IP3 measured at the FMI input pin reflects IP3 for FMI LNA stage.
9. RDS Synchronization Persistence is the minimum RF level at which the tuner loses synchronization to the RDS PI code
as the RF level decreases from high to low levels.
10. RDS Synchronization Stability is the minimum RF level at which the tuner achieves synchronization to the RDS PI code
as the RF level increases from low to high levels.
11. Noise integrated from 30 Hz to 120 kHz for audio SINAD and SNR measurements.
16
Rev. 0.9
Si4770/77-A20
Signal Generator
50
FMXIP
FMXIN
Si477x
Figure 5. FM Test Circuit for Mixer Input IP3 and Sensitivity Measurement
Table 8. AM Receiver Characteristics
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, AM modulation = 30%, FMOD = 1 kHz, RF level = 74 dBµV, and FRF = 1 MHz unless otherwise specified)
Parameter
Test Condition
Min Typ Max
Unit
kHz
kHz
Input Frequency
520
1
—
—
1710
10
Frequency Step
Resolution
1,2
Powerup Time
RCLK or Crystal = 36.4 MHz, 37.8 MHz,
37.209375 MHz
—
—
100
ms
1
Tune Time
—
—
—
15
55
93
—
—
—
ms
ms
1
Seek Time/Channel
At LOUT and ROUT pins
Maximum RF Input
Mod = 90%, Fmod = 1 kHz, SINAD = 57 dB
dBµV
1,2
Voltage
1,3
Image Rejection
68
57
72
62
—
—
dB
dB
Adjacent Channel
SINAD = 20 dB
1,3
Rejection
Desired = 40 dBµV, F
= 1 kHz, MOD = 30%
MOD
Undesired at ±9 kHz offset, F
MOD = 30%
= 400 Hz,
MOD
Alternate Channel
Rejection
SINAD = 20 dB
Desired = 40dBµV, F = 1 kHz, MOD = 30%
59
62
—
—
dB
1,3
MOD
Undesired at ±18 kHz offset, F
MOD = 30%
= 400 Hz,
MOD
1,3
IP3
Blockers at 40/80 kHz, AGC disabled (Max gain)
110 120
dBµV
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
4. Guaranteed by design.
Rev. 0.9
17
Si4770/77-A20
Table 8. AM Receiver Characteristics (Continued)
(TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V. Typical values measured at
TAMB = 25 °C, AM modulation = 30%, FMOD = 1 kHz, RF level = 74 dBµV, and FRF = 1 MHz unless otherwise specified)
Parameter
Test Condition
Min Typ Max
Unit
1,3
IP2
Desired = 700 kHz,
Undesired = 1000 kHz, 1700 kHz
AGC disabled (Max gain)
142 146
—
dBµV
RF AGC Range
—
50
2
—
dB
dB
dB
AGC Step Resolution
RF AGC Threshold
—
—
2
—
—
4
Accuracy
IF AGC Threshold
2
dB
4
Accuracy
1,3
Sensitivity
SINAD = 20 dB, AGC Disabled (Max RF Gain)
—
—
14
0.1
0.2
65
17
—
dBµV EMF
1,3
THD
Mod = 30%
Mod = 90%
Mod = 30%
%
%
—
—
1,3
Audio SNR
60
—
dB
µH
3
Antenna Inductance
180
—
540
Audio Outputs: Pins LOUT and ROUT
Audio Output Resistance
Load
10k
—
—
—
—
Ω
4
Audio Output
Capacitance Load
Single Ended
50
pF
4
Audio Output Voltage
96
—
108
45
121
—
mVRMS
dB
PSRR at Audio Output
Ripple test should be for 100 Hz ripple on power
supply lines
4
Pins
Ripple voltage = 100 mV of power supply voltage
PP
Notes:
1. Guaranteed by characterization.
2. Measured at TAMB = 25 °C.
3. No A-weighting. Noise integrated from 30 Hz to 15 kHz for audio SINAD and SNR measurements.
4. Guaranteed by design.
18
Rev. 0.9
Si4770/77-A20
Table 9. Thermal Conditions
Parameter
Symbol
Test Conditions
Min
–40
—
Typ
25
Max
85
Unit
°C
Ambient Temperature
Junction Temperature
T
—
—
—
AMB
T
—
115
—
°C
J
*
Delta from Junction to Ambient
θ
—
27
°C/W
JA
*Note: The θJA is layout-dependent, and, therefore, PCB layout must provide adequate heat-sink capability. The θJA is
specified assuming adequate ground plane.
Table 10. Absolute Maximum Ratings1
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–0.5
–10
–0.3
–10
–0.3
–40
–55
–1
Max
5.9
3.9
3.9
3.9
10
Unit
V
Analog Supply Voltage
Digital Supply Voltage
I/O 1 Supply Voltage
I/O 2 Supply Voltage
V
A
V
V
D
V
V
V
IO1
IO2
IN1
V
2
I/O 1 Input Current
I
µA
V
2
I/O 1 Input Voltage
V
V
V
+ 0.3
I01
IN1
IN2
3
I/O 2 Input Current
I
10
+ 0.3
µA
V
3
I/O 2 Input Voltage
V
IN2
OP
I02
Operating Temperature
Storage Temperature
T
95
°C
°C
V
T
150
STG
RFIN
RFIN
4
AM RF Input Level
V
V + 1
A
4
AM RF Input Current
I
–100
–1
100
1
mA
V
5
FM RF Input Level
V
RFIN
RFIN
5
FM RF Input Current
I
–100
–2
100
2
mA
kV
V
HBM ESD
MM ESD
V
HBM
V
–200
–500
–750
200
500
750
MM
6
CDM ESD
V
V
V
CDM
CDM
7
CDM ESD
V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. For input pins SCL, SDA, RSTB, A0, A1, GPIO1, GPIO2.
3. For input pins DCLK and DFS.
4. At RF input pins AM1.
5. At RF input pins FMXIN, FMXIP, FMI, FMAGC1, FMAGC2.
6. All pins.
7. Corner pins.
Rev. 0.9
19
Si4770/77-A20
2. Typical Application Schematic
Figure 6 shows the proposed application schematic.
2 0
V A
V D
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
L O U T
R O U T
X T A L 2
X T A L 1
V I O 1
I N T B
S C L
S D A
R S T B
N C
D A C R E F
G P I O 2
G P I O 1
F M A G C 2
F M A G C 1
3 . 2 x 2 . 5
N C
A 1
A 0
4 1
G N D _ P A D
20
Rev. 0.9
Si4770/77-A20
3. Bill of Materials
Table 11. Si4770/77-A20 Bill of Materials
Item
Qty
1
Ref
T2
Package
Transformer, Thru-hole
BALUN, 1:1, Toko
CAP, SM, 0402
CAP, SM, 0402
CAP, SM, 0402
CAP, SM, 0402
CAP, SM, 0402
Value
Mfr
Part Number
1
2
3
5
6
7
8
Silicon Laboratories
Toko
SL755TF01
1
T1
458PT1566
2
C13, C21
C1
0.1 µF
100 pF
18 pF
1 nF
Murata
GRM155R71A204KA01D
GRM1555C1H101JZ01
GRM1555C1H180JZ01
GRM155R61H102KA01
GRM155R71H222KA01
1
Murata
1
C10
C8
Murata
1
Murata
5
C2, C3,
2.2 nF
Murata
C4, C5, C7
9
1
2
1
1
C9
C6, C20
J1
CAP, SM, 0402
CAP, SM, 0603
62 pF
10 µF
Murata
Digikey
GRM1555C1H620JD01
490-3896-2-ND
10
11
12
CONN, SMA, Edgemount
AEP Connectors
Samtec
JP1
CONN, TH, HEADER,
.100 PITCH,1X2
HTSW-101-07-G-D
13
14
2
1
D1, D3
U1
ESD Protector, SM
TE Connectivity
PESD0402-140
Si4770/77
IC, SM, Si4770/77-A20,
QFN40
Silicon Laboratories
15
16
17
18
21
1
1
1
1
1
L9
L3
L1
L2
X1
IND, SM, 0603
IND, SM, 0603
10 nH
150 nH
Murata
Murata
LQW18ANR15G00
LQW18ANR22G00
LQW18AN47NG00
See Table 12
IND, SM, 0603
220 nH
Murata
IND, SM, 0603
47 nH
Murata
XTAL, SM, 3.2 x 2.5 mm
See Table 12
See Table 12
Rev. 0.9
21
Si4770/77-A20
Table 12. Crystal Options
Series
Frequency
(MHz)
Mfr
P/N
36.400000
37.800000
37.209375
36.400000
37.800000
37.209375
36.400000
NDK
NDK
NX3225SA
NX3225SA
EXS00A-CS02420
EXS00A-CS02421
EXS00A-CS02422
TZ1514A
NDK
NX3225SA
TaiSaw
TaiSaw
TaiSaw
Jauch
SMD 3.2x2.5 36.4 MHz Crystal Unit
SMD 3.2x2.5 37.8 MHz Crystal Unit
SMD 3.2x2.5 37.209375 MHz Crystal Unit
JXE115
TZ1517A
TZ1522A
Q36,40-JAS32P4-12-10/20-
T1-LF
37.800000
37.209375
Jauch
Jauch
JXE115
JXE115
Q37,80-JAS32P4-12-10/20-
T1-LF
Q37,209375-JAS32P4-12-10/
20-T1-LF
36.400000
37.800000
37.209375
Epson Toyocom
Epson Toyocom
Epson Toyocom
TSX-3225
TSX-3225
TSX-3225
OUTD-2B-0541
OUTD-2B-0541
OUTD-2B-0541
22
Rev. 0.9
Si4770/77-A20
4. Functional Description
4.1. Overview
Si4770/77
LOUT/
DAC
ADC
MPXOUT
FMXIP
RF PKD
FMXIN
DSP
IF PKD
ADC
DAC
ROUT
RFREG
REG
RL
DCLK
DFS
DOUT
LNA
FMO
FMI
0°/90°
RDS
RF PKD
RF PKD
INTB
RSTB
VIO1
VIO2
AMI
LNA
CNTRL
ClK
Gen
RFGND
Figure 7. Si4770/77-A20 Block Diagram
The Si4770/77-A20 radio receiver family employs 100% The proven digital techniques provide excellent
RF CMOS technology to bring outstanding receiver sensitivity in weak signal environments and superb
performance to the consumer electronics industry. The selectivity and intermodulation immunity in strong signal
Si4770/77-A20 receiver family supports worldwide radio environments. The solution offers dynamic AM/FM
reception. The Si4770/77-A20 incorporates a digital pre- channel bandwidth control, auto-calibrated digital
processor for the European Radio Data System (RDS) tuning, and proven AM/FM seek functionality based on
and the North American Radio Broadcast Data System multiple signal quality and band parameters. The family
(RBDS) including all required symbol decoding, block offers highly flexible and advanced audio processing
synchronization, error detection, and error correction including programmable softmute, FM stereo-mono
functions. The Si4777 supports AM/FM HD radio blend, dynamic AM/FM channel bandwidth, AM/FM hi-
2
channel reception with digital (I S) Zero-IF (ZIF) I/Q cut, FM hi-blend, and AM lo-cut filters. In addition, the
outputs for interface to an HD radio processor.
Si4770/77-A20 provides an integrated clock oscillator or
accepts a reference clock and an I C-compatible, 2-wire
2
The family leverages Silicon Laboratories’ patented low-
IF digital architecture, delivering superior RF
performance and interference rejection. The low-IF
architecture delivers superior performance while
integrating the great majority of external components
required by competing solutions.
control interface. The Si4770/77-A20 receiver system
specifies a minimal bill of materials, resulting in a small
board space requirement and making the solution ideal
for any consumer electronics application from single
tuner radios to multiple tuner radios.
Rev. 0.9
23
Si4770/77-A20
Table 13. Part Number Descriptions
Si4770
Si4777
AM/FM RDS,
VICS
AM/FM RDS,
VICS, HD Tuner
24
Rev. 0.9
Si4770/77-A20
4.2. Clocking
4.3. Tuning
The Si4770/77-A20 generates all internal clocking from The Si4770/77-A20 includes a complete on-chip PLL-
an external crystal using an on-chip oscillator or an VCO frequency synthesizer to generate the quadrature
external programmable reference clock. The reference LO input to the image-reject AM and FM mixers. The
clock of Si4770/77-A20 is a sinusoidal or rectangular Si4770/77-A20 employs a single-conversion mix (down
clock provided by an external source on pin RCLK. The conversion) to a fixed low IF center frequency. An
supported crystal and external clock source frequencies innovative high-performance image reject mixer
are selected frequencies in the 36–38 MHz range.
architecture allows for IF center frequencies below
300 kHz, thereby eliminating ceramic filters required in
10.7 MHz IF tuner architectures. The tune command
automatically programs the LO frequency to the center
of the desired channel plus (minus) the output center IF
frequency when using a high-side (low-side) mix. The
Si4770/77-A20 supports 50, 100, or 200 kHz channel
spacing for FM, 9 or 10 kHz for AM.
The power up command enables the selection of an
external crystal or reference clock. The reference clock
and/or crystal accuracy should be ±100 ppm. In a multi-
receiver system, a single crystal can be shared between
all Si4770/77-A20 receivers. The Si4770/77-A20 family
features programmable loading capacitors for the on-
chip crystal oscillator, eliminating external loading
capacitors.
CLK
Si477x
Audio Receiver 1
CLK
Si477x
Audio Receiver 2
Figure 8. Xtal Share between Two Tuners
Rev. 0.9
25
Si4770/77-A20
4.4. FM Receiver Front-End
The Si4770/77-A20 provides a very flexible front-end
interface to accommodate a wide range of applications
from cost-sensitive to high-performance.
An advanced AGC on the Si4770/77-A20 is
implemented with the use of internal RF peak and IF
peak detectors with programmable thresholds (trip
points). The AGC adjusts the resistor values
automatically. Attack and release rates for the AGC are
programmable, providing flexible fast attack and slow
release AGC performance.
FMXIP
FMXIN
RF Pkd
Reg
For cost-effective performance and superior FM
sensitivity, the antenna output can be received on the
FMI pin (Figure 9). The FM band can be received on the
FMI pin via an input coupling network. This input
coupling network isolates the FM band for best
performance. An internal LNA provides gain for the
signal. The LNA output is routed externally to the FM
mixer input pins. The LNA gain is regulated with an
internal voltage regulator supply via an internal resistor
RFREG
FMO
RL
LNA
50
FMI
RF Pkd
Si477x
Figure 10. Conceptual Illustration of the
Lowest-Cost Configuration
bank, R . The AGC circuit automatically controls the
L
4.4.1. FMI LNA for FM Loop-Through Usage
LNA gain, resistor banks FMAGC1, FMAGC2, and R to
L
optimize sensitivity and strong signal handling.
In dual receiver applications, two receivers (Figure 11)
can be attached to a single antenna. The dual receiver
solution allows for independent radio station listening in
different rooms.
The FMI LNA input impedance is software-configurable
and provides two options: 50 and 100 . Configuring
the input impedance for 100 facilitates a Si4770/77-
A20 receiver 1 and the Si4770/77-A20 receiver 2 to be
interfaced to the antenna output in parallel, providing a
matched 50 input impedance. AGC is coordinated
between both receivers whereby the resistor banks,
FMXIP
RF Pkd
FMAGC1, FMAGC2, and R , from one receiver are
L
used to optimize sensitivity and strong signal handling.
FMXIN
RFREG
Reg
RL
LNA
FMO
50
FMI
RF Pkd
Si477x
Figure 9. Conceptual Illustration of the Use of
the FMI LNA for Cost-Optimized and Superior
FM Sensitivity Performance
Cost can be further reduced by eliminating the 1:1 balun
and directly interfacing the signal to the FM mixer by
programming the mixer for single-ended input mode
(Figure 10). The trade-off is a drop in linearity of 6 dBµV
in IP3.
26
Rev. 0.9
Si4770/77-A20
4.5. AM Receiver Front-End
The Si4770/77-A20 contains an integrated LNA,
providing an AM receive chain from antenna to audio
out. There are few external components and no manual
alignment required. The AM signal is received on the
AMI pin. An advanced AGC on the Si4770/77-A20 is
implemented with the use of internal RF peak and IF
peak detectors with programmable thresholds (trip
points). Attack and release rates for the AGC are
programmable providing flexible fast attack and slow
release AGC performance.
FMXIP
RF Pkd
FMXIN
RFREG
Reg
LNA
The Si4770/77-A20 provides highly-accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180~688 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance of the air loop. Using a 1:5 turn
ratio inductor, the inductance is increased by 25 times
and easily supports all typical AM air loop antennas
which generally vary between 10 and 20 µH.
RL
FMO
FMI
50
100
RF Pkd
Si477x
FMXIP
RF Pkd
FMXIN
RFREG
Reg
LNA
RL
FMO
FMI
100
RF Pkd
Si477x
Figure 11. Conceptual Illustration of Si4770/77-
A20 Receivers Interfaced to a Single Antenna
Using the FMI LNA in Loop-Through Mode
Rev. 0.9
27
Si4770/77-A20
4.7.1. Audio Data Formats
4.6. Received Signal Qualifiers
2
In I S format, by default the MSB is captured on the
A tuned signal's quality can vary with the environmental
conditions, time of day, and geographical location
among many other factors. To adequately manage the
audio output and avoid unpleasant audible effects to the
end-user, the Si4770/77-A20 monitors and provides
indicators of signal quality, allowing the on-chip DSP
second rising edge of DCLK following each DFS
transition. The remaining bits of the word are sent in
order, down to the LSB. The left channel is transferred
first when the DFS is low, and the right channel is
transferred when the DFS is high.
and host processor (if required) to perform signal In Left-Justified format, by default, the MSB is captured
processing. The Si4770/77-A20 monitors and reports a on the first rising edge of DCLK following each DFS
set of industry-standard signal quality metrics including transition. The remaining bits of the word are sent in
on-channel RSSI, adjacent channel RSSI (100 kHz and order, down to the LSB. The left channel is transferred
200 kHz), image RSSI, SNR, multi-path interference on first when the DFS is high, and the right channel is
FM signal, ultra-sonic noise, and FM pilot detection. As transferred when the DFS is low.
with other Si4770/77-A20 features, how these variables
In Right-Justified format, by default, the LSB is captured
are used to improve audio performance can be left to
on the last rising edge of DCLK in each valid DFS
the Silicon Labs on-chip algorithms (recommended), or
interval. The left channel is transferred first when the
they can be brought out for host-processor instructions.
DFS is high, and the right channel is transferred when
the DFS is low.
4.7. Digital Audio Interface
In DSP format, the DFS becomes a pulse with a width of
The digital audio 3-pin interface consists of data serial
one DCLK period. The left channel is transferred first,
lines containing audio data, a bit clock, and a word
followed right away by the right channel. There are two
frame for left and right channel data. The digital audio
options in transferring the digital audio data in DSP
interface operates in slave mode and supports five
format; the MSB of the left channel can be transferred
different audio data formats:
on the first rising edge of DCLK following the DFS pulse
(left-justified DSP format) or on the second rising edge.
2
I S Audio
Left-Justified Audio
Right-Justified Audio
DSP Audio
In all audio formats, depending on the word size, DCLK
frequency, and sample rates, there may be unused
DCLK cycles after the LSB of each word before the next
DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16,
20, or 24 bits.
DSP Left-Justified Audio
4.7.2. Audio Sample Rates
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz.
28
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Si4770/77-A20
Rev. 0.9
29
Si4770/77-A20
30
Rev. 0.9
Si4770/77-A20
4.9.1. ZIF I/Q Data Formats
4.8. Channel Equalizer
2
In I S format, by default, the MSB is captured on the
The Si4770/77-A20 supports advanced FM multi-path
channel equalization. Multi-path interference results in
fading of the FM signal at the receiver. Frequency
selective fading causes different frequencies of an input
second rising edge of IQCLK following each IQFS
transition. The remaining bits of the word are sent in
order, down to the LSB.
signal to be attenuated and phase shifted differently in a In Left-Justified format, by default, the MSB is captured
channel. Frequency selective fading gives rise to on the first rising edge of IQCLK following each IQFS
notches in the frequency response of the channel. The transition. The remaining bits of the word are sent in
Si4770/77-A20 channel equalizer performs blind order, down to the LSB.
equalization utilizing proprietary constant modulus
algorithm (CMA) to restore the flat response of the
on the last rising edge of IQCLK in each valid IQFS
channel.
In Right-Justified format, by default, the LSB is captured
interval.
In DSP format, the IQFS becomes a pulse with a width
of 1 IQCLK period. There are two options in transferring
4.9. Digital ZIF I/Q Interface
(Si4777 Only)
the digital baseband I/Q data in DSP format: the MSB of
The digital ZIF I/Q output can provide the down
I and Q data can be transferred on the first rising edge
converted channelized AM/FM signal at baseband to a
of IQCLK following the IQFS pulse (left-justified DSP
third-party processor for AM/FM HD radio processor for
format) or on the second rising edge.
IBOC signal processing. The Si4777 provide a 500 kHz
In all data formats, depending on the word size, IQCLK
BW signal for FM IBOC signal processing and a 30 kHz
frequency, and sample rates, there may be unused
BW signal for AM IBOC signal processing. The ZIF I/Q
IQCLK cycles after the LSB of each word before the
4-pin interface consists of two data serial lines
next IQFS transition and MSB of the next word. In
containing I and Q data, a bit clock, and a word frame
addition, if preferred, the user can configure the MSB to
for each data sample. The interface operates in master
be captured on the falling edge of IQCLK via properties.
mode and supports five different data formats:
The number of baseband I/Q bits is configured for 16
2
I S ZIF
bits.
Left-Justified ZIF
Right-Justified ZIF
DSP ZIF
DSP Left-Justified ZIF
Table 14. ZIF I/Q Interface Description
Pin
Description
IOUT
QOUT
IQFS
16-bit baseband I word
16-bit baseband Q word
Word frame sync for I and Q words
Bit clock for I and Q data
IQCLK
Rev. 0.9
31
Si4770/77-A20
32
Rev. 0.9
Si4770/77-A20
Rev. 0.9
33
Si4770/77-A20
34
Rev. 0.9
Si4770/77-A20
4.9.2. ZIF I/Q Sample Rates and Clocking Requirements
The device supports a number of industry-standard sampling rates including 650, 675, and 744.1875 kHz.
The external crystal and/or reference clock frequency must be the following to support the following ZIF I/Q
samples rates for interface to an HD radio demodulator/decoder or DSP.
Table 15. Crystal/Reference Clock Frequency Requirements for the ZIF I/Q Sample Rates and
Bit Clock Rates Supported
RCLK/XTAL
Frequency (MHz)
IQFS ZIF I/Q
Sample Rate (kHz)
IQCLK
I/Q Bit Clock (MHz)
Broadcast Reception
Modes
650.0000
325.0000
40.6250
10.4000
5.2000
2.2750
10.8000
5.4000
2.3625
14.88375
7.4419
1.8605
AM/FM HD-Radio
FM Analog
36.4000
37.8000
AM Analog/HD-Radio
AM/FM HD-Radio
FM Analog
675.0000
337.5000
42.1875
AM Analog/HD-Radio
AM/FM HD-Radio
FM Analog
744.1875
372.0938
46.5117
37.209375
AM Analog/HD-Radio
Rev. 0.9
35
Si4770/77-A20
The blended audio can be output on the analog output
pins, LOUT and ROUT and/or a digital audio port to a
third party audio DSP.
4.10. IBOC Blend Mode for HD Radio
(Si4777 Only)
For HD-Radio reception IBOC blend is supported on the
Si4777. This feature supports the ability to blend
between analog and digital audio. When the bit error
rate (BER) of the HD-Radio digital signal falls below a
predefined threshold (set by the HD-Radio
demodulator) and the digital audio fades out, the analog
audio is blended in. This prevents the received audio
from muting when the digital signal is lost. The audio will
"blend to digital" upon reacquisition of the digital signal.
Figure 22 illustrates the system implementation with a
third party HD-Radio demodulator. ZIF I/Q data is output
to the HD-Radio demodulator. The HD-Radio
demodulator demodulates and decodes the received
An on-chip asynchronous re-sampling converter
(ASRC) allows the Si4777 to be slaved to the Audio
DSP’s digital frame sync and bit clock from 32 kHz to
48 kHz.
Audio level alignment and calibration is implemented in
the Si4777 by multiplying the input HD-R audio signal
by a scaling constant (determined at manufacturing time
in the factory) and a dynamic constant that is HD-R
station-dependent. The dynamic constant is determined
by the HD-R demodulator during reception and is
relayed to the Si4777 by the host controller for the
blend.
2
2
HD-Radio signal. It outputs digital audio (I S three-wire
4.10.1. IBOC Blend and I C Device Address
mode) to the Si4777 where the IBOC blend is
performed. An on-chip asynchronous resampling
converter (ASRC) allows the Si4777 to be slaved to the
HD-Radio demodulator digital audio output at any
sample rate from 32 kHz to 48 kHz.
Selection
In applications not requiring HD-Radio reception and
IBOC blend, with the Si4777, two I C device addresses,
A0 and A1 (pins 11 and 12), are available, allowing up
to four Si4777 receivers to share the same I C bus (see
2
2
The HD-R demodulator sends a 1-bit "BLEND" signal to
the Silicon Labs tuner. When this signal is "1", the
Si4777 initiates a crossover from full AM/FM analog
audio into full HD-R audio following a time ramp at a
programmable ramp rate. This process continues until
HD-R audio is fully blended to analog or until the
BLEND bit becomes a "0". When the BLEND bit is "0",
the reverse crossover occurs (crossover from HD-R to
AM/FM analog following a programmable ramp rate).
This process continues until AM/FM is fully blended or
until BLEND becomes "1".
"7. I2C Control Bus" on page 44). However in utilizing
IBOC blend for HD-radio reception on the Si4777, only
one device address A0 (pin 11) is available. Pin 12 is
repurposed for the Interrupt output INTB, whilst Pin 18
is repurposed for the digital audio clock input DFS2.
The 7-bit device address consists of a fixed part (6
MSBs), followed by a programmable 1-bit part. The LSB
of the device address signals whether a read or write
2
I C operation occurs. The voltage on the A0 pin is used
to set the programmable 1-bit part of the device
address. The A0 pin is tied to ground and or is left to
2
float for address selection. The various I C device
addresses can be selected as summarized in Table 16.
Table 16. I2C Device Address Selection in IBOC Blend Mode for Si4777
Device Address [6…1]
110001
Device Address [0]
A0 Voltage (Pin connection)
1
0
VIO1
GND
110001
36
Rev. 0.9
Si4770/77-A20
HD Radio Demod
QOUT (Pin 26)
IOUT (Pin 25)
IQFS (Pin24)
IQCLK (Pin 23)
Digital I/Q ZIF
(I2S)
Audio /Data
Decoders
Demod
Master
4-wire mode
Master
3-wire mode
Si4777
AM/FM Analog demodulation
Weak signal processing
X
Blend Flag
Digital bit clock
BLEND (Pin 30)
DCLK (Pin 29)
DFS (Pin 28)
DIN (Pin 27)
IBOC
Digital frame sync
HD audio (MP1)
ASRC
ASRC
blend
PLL
AM/FM
audio
Blended
audio
Blended audio
DOUT2 (Pin 14)
Digital bit clock
DSP
DCLK2 (Pin 13)
DFS2 (Pin 18)
Digital frame sync
Master
Figure 22. System Implementation of HD-Radio Reception with IBOC Blend on the Si4777
Rev. 0.9
37
Si4770/77-A20
1
2
30
29
28
27
26
25
24
23
22
21
NC
BLEND
DCLK
DFS
FMXIP
FMXIN
RFGND
RFREG
FMO
3
4
DIN
5
QOUT
IOUT
IQFS
GND PAD
6
7
FMI
8
NC
IQCLK
VIO2
9
NC
10
AMI
DBYP
Figure 23. Si4777 Pin Descriptions for IBOC Blend Mode
Table 17. Pin Descriptions for Si4777 for IBOC Blend Mode
Pin Number
Name
NC
I/O
Description
1
2
I
I
I
No connect: Leave floating
FMXIP
FMXIN
RFGND
RFREG
FMO
FMI
Balanced input to FM mixer (positive)
Balanced input to FM mixer (negative)
RF Ground
3
4
5
O
O
I
FM LNA regulator
6
FM LNA output
7
FM LNA input
8
NC
No connect: Leave floating
No connect: Leave floating
AM single-ended input
9
NC
10
11
12
13
14
AMI
I
I
2
A0
I C Address 0
INTB
DCLK2
DOUT2
O
I
Interrupt active low (Si4777 for IBOC blend mode)
Digital audio bit clock input (Si4777 for IBOC blend mode)
Digital audio output (Si4777 for IBOC blend mode)
O
38
Rev. 0.9
Si4770/77-A20
Table 17. Pin Descriptions for Si4777 for IBOC Blend Mode (Continued)
Pin Number
Name
RSTB
I/O
Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PDL
I
Global Chip Reset
2
SDA
I/O I C Data input/output
2
SCL
I
I
I C clock
DFS2
Digital audio bit clock input (Si4777 for IBOC blend mode)
Host I/O Supply Voltage (all pads except digital audio and I/Q)
Digital Voltage Supply
VIO1
S
S
I
VD
DBYP
Digital bypass to Ground
VIO2
S
O
O
O
O
I
Digital audio and I/Q interface supply voltage
ZIF I/Q bit clock output (Si4777)
ZIF I/Q frame sync output (Si4777)
ZIF I data output (Si4777)
IQCLK
IQFS
IOUT
QOUT
DIN
ZIF Q data output (Si4777)
Digital audio data input (Si4777 for IBOC blend mode)
Digital audio frame sync input
DFS
I
DCLK
I
Digital audio bit clock input
BLEND
VA
I
Blend Flag Control
S
O
O
I
Analog Voltage Supply
LOUT/ MPXOUT
ROUT
XTAL2/RCLK
XTAL1
DACREF
GPIO2
GPIO1
FMAGC2
FMAGC1
GND PAD
Left audio line out / FM MPX output
Right audio line out
Crystal oscillator input/Reference clock input
Crystal oscillator output
O
I
Voltage Reference for analog outputs
I/O General-purpose input/output
I/O General-purpose input/output
I
I
I
FM automatic gain control 2
FM automatic gain control 1
Ground. Reference ground
Rev. 0.9
39
Si4770/77-A20
4.11.1. Stereo Decoder
4.11. Stereo Audio Processing
The Si4770/77-A20's integrated stereo decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and RDS/
RBDS data as shown in Figure 24.
4.11.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Signal metrics such as on-channel
RSSI, ultra-sonic noise (USN), and multi-path
interference are monitored simultaneously in forcing a
blend from stereo to mono. The metric, reflecting the
poorest signal quality, takes priority and the stereo
signal is blended appropriately. The thresholds for
activating stereo-mono blend are programmable, as are
the levels for a fully blended state. The attack and decay
rates for each metric are programmable. The pilot
detection metric is additionally available for read-out.
Mono Audio
Left + Right
Stereo
Pilot
Stereo Audio
Left - Right
RDS/
RBDS
0
15 19 23
38
53 57
Frequency (kHz)
Figure 24. MPX Signal Spectrum
Stereo thld
SNR (dB)
Mono thld
Stereo thld
RSSI (dBuV)
Mono thld
Mono thld
Multi-path %
Stereo thld
T< Trelease
Stereo
Blend level
Mono
Figure 25. Conceptual Illustration of Stereo-Mono Blend
40
Rev. 0.9
Si4770/77-A20
4.12. De-emphasis
4.16. Seek and Valid Station Qualification
Pre-emphasis and de-emphasis is a technique used by The seek function will search up or down the selected
FM broadcasters to improve the signal-to-noise ratio of frequency band for a valid channel. A valid channel is
FM receivers by reducing the effects of high-frequency qualified according to a series of programmable signal
interference and noise. When the FM signal is indicators and thresholds. The seek function can be
transmitted,
a
pre-emphasis filter is applied to made to stop at the band edge and provide an interrupt,
accentuate the high audio frequencies. The Si4770/77- or wrap the band and continue seeking until arriving at
A20 incorporate a de-emphasis filter which attenuates the original departure frequency. The device sets
high frequencies to restore a flat frequency response. interrupts with found valid stations or, if the seek results
Two time constants are used in various regions. The de- in zero found valid stations, the device indicates failure
emphasis time constant is programmable to 50 or and again sets an interrupt.
75 μs.
The Si4770/77-A20 seek functionality is performed
completely on-chip or can be brought out to a
4.13. Analog Audio and FM MPX
companion processor. The Si4770/77-A20 can provide
High-fidelity digital-to-analog converters (DACs) drive
base values for signal quality variables to a companion
analog audio signals or the FM MPX signal onto the
processor for qualification or can further process the
LOUT/MPXOUT and ROUT pins. At powerup time the
base values to qualify valid or invalid stations.
user can configure the analog outputs for either audio or
The Si4770/77-A20 uses RSSI, SNR, and frequency
MPX output. In applications where MPX and audio
offset to qualify stations. These variables have
outputs are required simultaneously, the analog MPX
programmable thresholds to tailor the seek function to
signal can be driven onto the MPXOUT pin and the
the subjective tastes of customers.
audio signals can be sourced from the digital audio
RSSI is employed first to screen all possible candidate
interface.
stations. SNR and frequency offset are subsequently
The audio output may be muted. Volume is adjusted
used in screening the RSSI qualified stations. The more
digitally. It is necessary that the volume be maintained
thresholds the system engages, the higher the
at maximum levels to ensure the highest dynamic range
confidence that any found stations will indeed be valid
audio outputs to the external audio processing stage in
broadcast stations; however, the more challenging
a car radio.
levels the thresholds are set to, the longer the overall
seek time as more stations and more qualifiers will be
assessed.
4.14. Soft Mute
The soft mute feature is available to attenuate the audio
It is recommended that RSSI be set to a midlevel
outputs and minimize audible noise in compromised
threshold in conjunction with an SNR threshold set to a
signal conditions. The Si4770/77-A20 triggers soft mute
level delivering acceptable audio performance. This
by monitoring signal metrics such as on-channel RSSI
trade-off will eliminate very low RSSI stations whilst
or SNR. The thresholds for activating soft mute are
keeping the seek time to acceptable levels. Generally,
programmable, as are soft mute attenuation levels and
the time to auto-scan and store valid channels for an
attack and decay rates. The Si4770/77-A20 provides
entire AM or FM band with all thresholds engaged is
the soft mute feature in FM and AM bands.
very short depending on the band content.
4.15. AM/FM Dynamic Bandwidth Control
Seek is initiated using the AM and FM seek commands.
The AM/FM IF channel bandwidth is dynamically The RSSI and SNR threshold settings are adjustable
optimized according to on-channel RSSI, and with the using properties.
aid of the adjacent and alternate channel RSSI metric.
Rev. 0.9
41
Si4770/77-A20
4.17. AM Hi-Cut Control
4.19. FM Hi-Blend
AM hi-cut control is employed on AM audio outputs with FM hi-blend control applies a low-pass filter on the (L-R)
degradation of signal quality. Signal metrics such as audio upon degradation of received signal quality.
SNR or on-channel RSSI activate the hi-cut filter. Signal metrics, such as USN, on-channel RSSI, and
Programmable minimum and maximum thresholds are multipath interference, activate the hi-blend filter.
available for all metrics. Attack and release rates for hi- Programmable minimum and maximum thresholds are
cut are programmable for all metrics.
available for all metrics. Attack and release rates for are
also programmable for all metrics. The level of hi-blend
applied can be monitored with the received signal
quality command. Further information is provided in the
Programming Guide.
The level of hi-cut applied can be monitored with the
received signal quality command. Hi-cut can be
disabled by setting the hi-cut filter setting to the default
audio bandwidth for AM. Further information is provided
in the Programming Guide.
4.20. AM Lo-Cut
4.18. FM Hi-Cut Control
AM lo-cut is employed on audio outputs for rejection of
power-supply 50/60 Hz interference. AM lo-cut is a high
pass filter. Lo-cut is enabled by default and can be
disabled by programming the filter to being switched off.
FM hi-cut control applies a low-pass filter on the (L+R)
audio upon degradation of received signal quality.
Signal metrics, such as USN, on-channel RSSI, and
multipath interference, activate the hi-cut filter.
Programmable minimum and maximum thresholds are
available for all metrics. Attack and release rates are
also programmable for all metrics. The level of hi-cut
applied can be monitored with the received signal
quality command. Further information is provided in the
Programming Guide.
42
Rev. 0.9
Si4770/77-A20
5. RDS/RBDS Advanced Processor
6. Programming Section
The Si4770/77-A20 implements an advanced, patented, To ease development time and offer maximum
high-performance RDS processor for demodulation, customization, the Si4770/77-A20 provides a simple
symbol decoding, block synchronization, error and powerful software command protocol in addition to
2
detection, and error correction. The RDS decoder the 2-wire I C serial interface to communicate with the
applies advanced decoding and statistical decision
host processor.The device is programmed using
commands, arguments, properties, and responses. To
perform an action, the user writes a command byte and
associated arguments, causing the chip to execute the
given command. Commands control actions such as
powerup, powerdown, or tune to a station. Arguments
are specific to a given command and are used to modify
the command. Properties are a special command +
argument used to modify the default chip operation and
are generally configured immediately after powerup.
Examples of properties are de-emphasis level, RSSI
seek threshold, and soft mute attenuation threshold.
Responses provide information and are echoed after a
command + argument is issued and processed. All
commands provide a one-byte status update indicating
interrupt and clear-to-send status information.
techniques to provide high-performance
synchronization at very noisy signal levels, and
excellent sensitivity at industry-standard block error rate
(BLER) levels (5%).
The
Si4770/77-A20’s
strong
synchronization
performance in very noisy/low SNR environments
minimizes the number of instances of lost
synchronization. Other less robust tuners must attempt
to resynchronize in low SNR environments, resulting in
lost data and lengthy delays in reestablishing data
reception.
The
Si4770/77-A20
maintains
synchronization to the RDS transmission, despite high
BLER. This results in fewer dropped connections,
minimal resynchronization time, and greater data
reliability in low SNR environments.
The
Si4770/77-A20
reports
RDS
decoder
synchronization status and detailed bit errors for each
RDS block. The range of reportable bit errors detected
and corrected are 0, 1-2, 3-5, and “not correctable.”
More than five errors indicate that the corresponding
block information word is non-correctable.
The Si4770/77-A20 also provides highly configurable
interrupts based on RDS-driven events and conditions.
The default settings provide an interrupt when RDS is
synchronized and when RDS group data has been
received. The configurable interrupts can be set to
provide frequent interrupts down to a single received
block with BLER. The configurable interrupts also can
be set to provide very infrequent interrupts, buffering up
to 25 complete RDS groups (100 blocks) with BLER
information by block in the on-chip FIFO. The Si4770/
77-A20 also provides configurable interrupts on
changes or receipt of the key RDS blocks A and B. This
flexibility allows adopters to either conduct extensive
RDS data processing on the host or reserve the host
processor in power-saving modes with minimal RDS
interrupts, allowing the Si4770/77-A20 to perform RDS
processing on-chip.
Rev. 0.9
43
Si4770/77-A20
7. I2C Control Bus
A serial port slave interface is provided, which allows an external controller to send commands and receive
responses from the Si4770/77-A20.
2
7.1. I C Device Address Selection
2
2
Two device I C addresses are available, allowing up to four Si4770/77-A20 receivers to share the same I C bus.
The 7-bit device address consists of a fixed part (5 MSBs), followed by a programmable 2-bit part. The LSB of the
device address signals whether a read or write I C operation occurs. The voltage on the A0 and A1 pins are used
2
to set the programmable 2-bit part of the device address. The A0 and A1 pins are tied to ground and are left to float
2
for address selection. The various I C device addresses can be selected as summarized in Table 18.
2
7.2. I C Standard Operation
2
The I C bus interface is provided for configuration and monitoring of all internal registers. The Si4770/77-A20
supports a 7-bit device addressing procedure and is capable of operating at clock rates up to 400 kHz. Individual
2
data transfers to and from the device are eight bits. The I C bus consists of two wires: a serial clock line (SCL) and
2
a serial data line (SDA). The device always operates as a bus slave. In order to be active, the I C block requires
that VIO1 and VD supplies be turned on.
A transaction begins with the START condition, which occurs when SDA falls while SCL is high. Next, the user
drives an 8-bit control byte serially on SDA, which is captured by the device on rising edges of SCL. The control
byte consists of a 7-bit device address followed by a read/write bit (read = 1, write = 0). The Si4770/77-A20
acknowledges the control word by driving SDA low on the next falling edge of SCL.
2
Read and write operations are performed in accordance with the I C bus specification. For write operations, the
host sends an 8-bit data byte on SDA, which is captured by the device on rising edges of SCL. The Si4770/77-A20
acknowledges each data byte by driving SDA low for one cycle, after the next falling edge of SCL. The host may
write any number of data bytes in a single two-wire transaction. The first byte is a command, and the next bytes are
arguments.
For read operations, after the Si4770/77-A20 has acknowledged the control byte, it drives an 8-bit data byte on
SDA, changing the state of SDA after the falling edge of SCL. The host acknowledges each data byte by driving
SDA low for one cycle, after the next falling edge of SCL. If a data byte is not acknowledged, the transaction ends.
The host may read any number of data bytes in a single two-wire transaction. These bytes contain the response
data from the Si4770/77-A20. A 2-wire transaction ends with the STOP condition, which occurs when SDA rises
while SCL is high.
Table 18. I2C Device Address Selection
Device Address [6…2] Device Address [1:0]
A1 Voltage
A0 Voltage
(Pin Connection) (Pin Connection)
11000
11000
11000
11000
11
10
01
00
Floating
Floating
GND
Floating
GND
Floating
GND
GND
44
Rev. 0.9
Si4770/77-A20
Write Operation
...
S
Device Addr W A
Command
Status
A
A
ARG 1
A
A
ARG 2
A
A
A
A
P
P
...
Read Operation
...
...
S
Device Addr
R
A
Response 1
Response 2
Slave
Master
A= Acknowledge
R = Read
S = Start condition
P = Stop condition
W = Write
Figure 26. I2C Command/Response Protocol
Rev. 0.9
45
Si4770/77-A20
8. Reset, Powerup, and Powerdown
Setting the RSTB pin low will disable analog and digital circuitry, reset the registers to their default settings, and
disable the bus. Setting the RSTB pin high will bring the device out of reset.
The powerup mode powers up the device and provides mode selection. Mode selections include the following:
AM, FM reception (Si4770/77-A20 only).
Crystal oscillator or reference clock input
A powerdown mode is available to reduce power consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry while keeping the bus active.
VIO1
VIO2
VD
VA
100 µsec min
RSTB
100 µsec min
SCL
SDA
POWER_UP Command
Figure 27. Startup Timing
46
Rev. 0.9
Si4770/77-A20
9. Pin Descriptions: Si4770/77-A20
1
30
29
28
27
26
25
24
23
22
21
NC
NC
2
FMXIP
DCLK
3
FMXIN
DFS
4
RFGND
DOUT
5
RFREG
NC/QOUT
NC/IOUT
NC/IQFS
NC/IQCLK
VIO2
GND PAD
6
FMO
7
8
FMI
NC
9
NC
10
AMI
DBYP
Figure 28. Si4770/77 Pin Descriptions
Table 19. Pin Descriptions for Si4770/77
Pin Number
Name
NC
I/O
Description
1
2
I
I
I
No connect: Leave floating
Balanced input to FM mixer (positive)
Balanced input to FM mixer (negative)
RF Ground
FMXIP
FMXIN
RFGND
RFREG
FMO
FMI
3
4
5
O
O
I
FM LNA regulator
6
FM LNA output
7
FM LNA input
8
NC
No connect: Leave floating
No connect: Leave floating
AM single-ended input
9
NC
10
11
12
13
AMI
I
I
I
2
A0
I C Address 0
2
A1
I C Address 1
NC
No connect: Leave floating
Rev. 0.9
47
Si4770/77-A20
Table 19. Pin Descriptions for Si4770/77 (Continued)
Pin Number
Name
NC
I/O
Description
14
15
16
17
18
19
20
21
22
23
24
No connect: Leave floating
RSTB
SDA
I
Global Chip Reset
2
I/O I C Data input/output
2
SCL
I
I C clock
INTB
O
S
S
I
Interrupt, Active Low
VIO1
Host I/O Supply Voltage (all pads except digital audio and I/Q)
Digital Voltage Supply
VD
DBYP
VIO2
Digital bypass to Ground
S
O
O
Digital audio and I/Q interface supply voltage
No Connect: Leave floating (Si4770); ZIF I/Q bit clock output (Si4777)
NC/IQCLK
NC/IQFS
No Connect: Leave floating (Si4770); ZIF I/Q frame sync output
(Si4777)
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PDL
NC/IOUT
NC/QOUT
DOUT
O
O
O
I
No Connect: Leave floating (Si4770); ZIF I data output (Si4777)
No Connect: Leave floating (Si4770); ZIF Q data output (Si4777)
Digital audio data output
DFS
Digital audio frame sync input
DCLK
I
Digital audio bit clock input
NC
No Connect: Leave floating
VA
S
O
O
I
Analog Voltage Supply
LOUT/ MPXOUT
ROUT
Left audio line out / FM MPX output
Right audio line out
XTAL2/RCLK
XTAL1
Crystal oscillator input/Reference clock input
Crystal oscillator output
O
I
DACREF
GPIO2
Voltage Reference for analog outputs
I/O General-purpose input/output
I/O General-purpose input/output
GPIO1
FMAGC2
FMAGC1
GND PAD
I
I
I
FM automatic gain control 2
FM automatic gain control 1
Ground. Reference ground
48
Rev. 0.9
Si4770/77-A20
10. Ordering Guide
,
Description
Package
Type
Operating
Temperature
Part Number *
Si4770-A20-GM
AM/FM RDS Broadcast Radio Receiver
6 x 6 40-pin QFN
Pb-Free
–40 to 85 °C
–40 to 85 °C
Si4777-A20-GM
AM/FM RDS Broadcast Radio Receiver and HD
Radio Tuner
6 x 6 40-pin QFN
Pb-Free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.
Rev. 0.9
49
Si4770/77-A20
11. Package Outline
Figure 29. 40-Pin Quad Flat No-Lead (QFN)
Table 20. Package Dimensions
Dimensions
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
A
A1
0.02
b
D
0.25
6.00 BSC.
4.10
D2
3.95
4.25
e
0.50 BSC.
6.00 BSC.
4.10
E
E2
3.95
0.30
4.25
0.50
L
0.40
aaa
bbb
ccc
ddd
eee
Notes:
0.10
0.10
0.08
0.10
0.05
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, Variation VJJD-2.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
50
Rev. 0.9
Si4770/77-A20
12. PCB Land Pattern
Figure 30. PCB Land Pattern
Rev. 0.9
51
Si4770/77-A20
Table 21. PCB Land Pattern Dimensions
Dimensions
Min
Max
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls
should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter
pads.
9. A 4 x4 array of 0.80 mm square openings on 1.05 mm pitch should be used
for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
52
Rev. 0.9
Si4770/77-A20
13. Top Marking
13.1. Si4770/77-A20 Top Marking
13.2. Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.90 mm diameter
(Bottom-Left-Justified)
Font Size:
0.70 mm Right-Justified
Line 1 Mark Format: Device Number
4770 = Si4770
4777 = Si4777
A = Part Revision A
20 = Firmware Revision 2.0
Line 2 Mark Format: TTTTTT = Mfg Code
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format: YY = Year
Assigned by the Assembly House. Corresponds to the
year and work week of the assembly date.
WW = Work Week
Rev. 0.9
53
Si4770/77-A20
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: FMinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
54
Rev. 0.9
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