Si52208-A02AGM_技术文档

Si52212/Si52208/Si52204/Si52202 Data

Sheet

12/8/4/2-Output PCI-Express Gen 1/2/3/4 and SRIS Clock

Generator

KEY FEATURES OR KEY POINTS

• 12/8/4/2-output low-power, push-pull HCSL

compatible PCI-Express Gen 1, Gen 2,

Gen 3, Gen 4 and SRIS-compliant outputs

The Si522xx is the industry's highest performance and lowest power PCI Express clock

generator family for 1.5–1.8 V PCIe Gen1/2/3/4 and SRIS applications. The Si52212,

Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe differential

clock outputs, respectively, plus one 25 MHz LVCMOS reference clock output. The

Si52202 can source two 100 MHz PCIe clock outputs only. All differential clock outputs

are compliant to PCIe Gen1/2/3/4 common clock and separate reference clock architec-

tures specifications.

• Low jitter: 0.4 ps max

2

•

Individual hardware control pins and I C

controls for Output Enable, Spread

Spectrum Enable and Frequency Select

• Triangular spread spectrum for EMI

reduction, down spread 0.25% or 0.5%

The Si522xx features individual hardware control pins for enabling and disabling each

output, spread spectrum enable/disable for EMI reduction, and frequency select to se-

lect 133 MHz or 200 MHz differential output frequencies. These features can also be

controlled via I²C.

• Internal 100 Ω or 85 Ω line matching

• Adjustable output slew rate

• Power down (PWRDNb) function supports

Wake-on LAN (except Si52202)

The small footprint and low power consumption make this family of PCIe clock genera-

tors ideal for industrial and consumer applications.

• One non-spread, LVMCOS reference clock

output (except Si52202)

• Frequency Select to select 133 MHz or

200 MHz (except Si52202)

For more information about PCI-Express, Silicon Labs' complete PCIe portfolio, applica-

tion notes, and design tools, including the Silicon Labs PCIe Clock Jitter Tool for PCI-

Express compliance, please visit http://www.silabs.com/pcie-learningcenter.

• 25 MHz crystal input or clock input

2

•

I C support with readback capabilities

Applications

• Extended temperature: –40 to 85 °C

• Servers

• 1.5–1.8 V power supply, with separate

VDD and VDD_IO

• Storage

• Data Centers

• Small QFN packages

• PCIe Add-on Cards

• Network Interface Cards (NIC)

• Graphics Adapter Cards

• Multi-function Printers

• Digital Single-Lens Reflex (DSLR) Cameras

• Digital Still Cameras

• Digital Video Cameras

• Docking Stations

• Pb-free, RoHS-6 compliant

silabs.com | Building a more connected world.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.7

Si52212/Si52208/Si52204/Si52202 Data Sheet

Feature List

1. Feature List

• 12/8/4/2-output 100 MHz PCIe Gen1/2/3/4 and SRIS compliant clock generator, with push-pull HCSL output drivers

• High port count with push-pull HCSL outputs to support highly integrated solution, eliminating external resistors for the HCSL out-

put drivers

• Low jitter of 0.4 ps max to meet PCIe Gen4 specifications with design margin

• Low power consumption.

• Lowest power consumption in the industry for a 2-output PCIe clock generator

Individual hardware control pins and I²C controls for Output Enable, Spread Spectrum Enable and Frequency Select

• Output Enable function easily disables unused outputs for power saving

•

• Spread Enable function to turn on/off spread spectrum and to select spread levels, either down spread 0.25% or 0.5%

• Frequency Select function to select output frequency of 100 MHz, 133 MHz, or 200 MHz (except Si52202 where the output fre-

quency is limited to 100 MHz. Please contact Silicon Labs for 133 MHz or 200 MHz in Si52202)

All above functions are controlled by individual hardware pins or I²C

•

• Internal 100 Ω or 85 Ω line matching

• Eliminates external line matching resistor to reduce board space

• Adjustable slew rate to improve signal quality for different applications and board designs

• Power down (PWRDNb) function supports Wake-on LAN (except Si52202)

• One non-spread, 25 MHz LVMCOS reference clock output (except Si52202)

• A buffered 25 MHz LVCMOS clock output to drive ASICS or SoCs on board

• 25 MHz reference input

• Supports a standard crystal or clock input for flexibility

I²C support with readback capabilities

•

• 1.5–1.8 V power supply with separate VDD and VDD_IO

• Temperature range: –40 °C to 85 °C

• Small QFN packages to optimize board space. Smallest 2-output PCIe clock generator in the industry

• 64-pin QFN (9 x 9 mm) : 12-output

• 48-pin QFN (6 x 6 mm) : 8-output

• 32-pin QFN (5 x 5 mm) : 4-output

• 20-pin QFN (3 x 3 mm) : 2-output

• Pb-free, RoHS-6 compliant

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 2

Si52212/Si52208/Si52204/Si52202 Data Sheet

Ordering Guide

2. Ordering Guide

Table 2.1. Si522x Ordering Guide

Number of Outputs

Internal Termination

Part Number

Package Type

64-QFN

Temperature

Si52212-A01AGM

Si52212-A01AGMR

Si52212-A02AGM

Si52212-A02AGMR

Si52208-A01AGM

Si52208-A01AGMR

Si52208-A02AGM

Si52208-A02AGMR

Si52204-A01AGM

Si52204-A01AGMR

Si52204-A02AGM

Si52204-A02AGMR

Si52202-A01AGM

Si52202-A01AGMR

Si52202-A02AGM

Si52202-A02AGMR

Extended, –40 to 85 °C

100 Ω

85 Ω

64-QFN - Tape and Reel Extended, –40 to 85 °C

64-QFN Extended, –40 to 85 °C

64-QFN - Tape and Reel Extended, –40 to 85 °C

48-QFN Extended, –40 to 85 °C

48-QFN - Tape and Reel Extended, –40 to 85 °C

48-QFN Extended, –40 to 85 °C

48-QFN - Tape and Reel Extended, –40 to 85 °C

32-QFN Extended, –40 to 85 °C

32-QFN - Tape and Reel Extended, –40 to 85 °C

32-QFN Extended, –40 to 85 °C

32-QFN - Tape and Reel Extended, –40 to 85 °C

20-QFN Extended, –40 to 85 °C

20-QFN - Tape and Reel Extended, –40 to 85 °C

20-QFN Extended, –40 to 85 °C

20-QFN - Tape and Reel Extended, –40 to 85 °C

12-output

100 Ω

85 Ω

8-output

4-output

100 Ω

85 Ω

100 Ω

85 Ω

2-output

2.1 Technical Support

Table 2.2. Technical Support URLs

Frequently Asked Questions

PCIe Clock Jitter Tool

PCIe Learning Center

Development Kit

www.silabs.com/Si522xx-FAQ

www.silabs.com/products/timing/pci-express-learning-center

www.silabs.com/products/development-tools/timing/clock/si52204-evb-evaluation-kit.html

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 3

Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . .19

5.2 Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5.3 Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . .20

5.4 PWRGD/PWRDNb (Power Down) Pin. . . . . . . . . . . . . . . . . . . . . .21

5.5 PWRDNb (Power Down) Assertion . . . . . . . . . . . . . . . . . . . . . . .21

5.6 PWRDNb (Power Down) Deassertion . . . . . . . . . . . . . . . . . . . . . .21

5.7 OEb Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.8 OEb Assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.9 OEb Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5.10 FS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 23

7. PCIe Clock Jitter Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2

8.1 I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.2 Block Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.3 Block Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

8.4 Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.5 Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.6 Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8.8 Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8.9 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

8.9.1 Si52212 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .31

8.9.2 Si52208 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .34

8.9.3 Si52204 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .37

8.9.4 Si52202 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .40

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.1 Si52212 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .43

9.2 Si52208 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .46

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 4

9.3 Si52204 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .49

9.4 Si52202 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .51

10. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.1 Si52212 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

10.2 Si52212 Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . .54

10.3 Si52208 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

10.4 Si52208 Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . .57

10.5 Si52204 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

10.6 Si52204 Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . .61

10.7 Si52202 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

10.8 Si52202 Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . .64

10.9 Si52212 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .66

10.10 Si52208 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .67

10.11 Si52204 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .68

10.12 Si52202 Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . .69

11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

11.1 Revision 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 5

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Block Diagrams

3. Functional Block Diagrams

Si52212

XIN/CLKIN

XOUT

REF

PLL

(SSC)

DIFF[11:0]

Divider

FS

SCLK

SDA

Control

&

PWRGD/PWRDNb

SS_EN

Memory

OEb[11:0]

Figure 3.1. Si52212 Block Diagram 12-output, 64-QFN

Si52208

XIN/CLKIN

REF

XOUT

PLL

(SSC)

DIFF[7:0]

Divider

FS

SCLK

SDA

Control

&

Memory

PWRGD/PWRDNb

SS_EN

OEb[7:0]

Figure 3.2. Si52208 Block Diagram 8-output, 48-QFN

Si52204

XIN/CLKIN

REF

XOUT

PLL

(SSC)

DIFF[3:0]

Divider

FS

SCLK

SDA

Control

&

PWRGD/PWRDNb

SS_EN

Memory

OEb[3:0]

Figure 3.3. Si52204 Block Diagram 4-output, 32-QFN

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 6

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Block Diagrams

Si52202

PLL

(SSC)

XIN/CLKIN

XOUT

DIFF[1:0]

Divider

SCLK

SDA

Control

&

Memory

PWRGD/PWRDNb

SS_EN

OEb[1:0]

Figure 3.4. Si52202 Block Diagram 2-output, 20-QFN

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 7

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

4. Electrical Specifications

Table 4.1. DC Electrical Specifications (VDD = 1.5 V ±5%)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

1.5 V Operating Voltage

VDD core

VDDIO

1.5 V ±5%

1.425

1.5

1.575

V

Supply voltage for differential Low

Power outputs

Output Supply Voltage

1.5 V Input High Voltage

1.5V Input Mid Voltage

1.5 V Input Low Voltage

0.9975

0.75 VDD

0.4 VDD

–0.3

1.05–1.5

—

1.575

V

Control input pins, except SDATA,

SCLK

V_IH

V_IM

V_IL

VDD + 0.3

0.6 VDD

0.25 VDD

Tri-level control input pins, except

SDATA, SCLK

0.5 VDD

—

Control input pins, except SDA-

TA,SCLK

V_IHI2C

V_ILI2C

Input High Voltage

SDATA, SCLK

At VOL

1.14

—

3.3

0.6

V

Input Low Voltage

I_PULLUP

SDATA, SCLK Sink Current

4

mA

Single-ended inputs, VIN = GND,

VIN = VDD

I_IN

–5

—

5

uA

Single-ended inputs, VIN = 0 V, in-

puts with internal pull-up resistors

VIN = VDD, inputs with internal

pull-down resistors

Input current

I_INP

–200

—

200

uA

C_IN

C_OUT

LIN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

—

5

6

7

pF

nH

—

Si52212 Current Consumption (VDD = 1.5 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.3

0.4

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 2 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.0

mA

Wake-on LAN Current

PWRGD_PWRDNb = "0"

Byte 2, bit 2 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.6

0.3

mA

VDD_IO, all differential outputs off,

REF running

I_{DD_IOWOL}

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 8

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.5V_Total}

—

82

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at 100

MHz

I_{DD_OP}

—

17

mA

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs ac-

tive at 100 MHz

I_{DD_IOOP}

58

Si52208 Current Consumption (VDD = 1.5 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.3

0.4

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 2 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.0

mA

Wake-on LAN Current

PWRGD_PWRDNb = "0"

Byte 2, bit 2 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.6

0.3

mA

VDD_IO, all differential outputs off,

REF running

I_{DD_IOWOL}

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.5V_Total}

—

63

17

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at 100

MHz

I_{DD_OP}

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs ac-

tive at 100 MHz

I_{DD_IOOP}

39

Si52204 Current Consumption (VDD = 1.5 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.3

0.4

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 2 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.0

mA

Wake-on LAN Current

PWRGD_PWRDNb = "0"

Byte 2, bit 2 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.6

0.3

mA

VDD_IO, all differential outputs off,

REF running

I_{DD_IOWOL}

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 9

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.5V_Total}

—

44

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at 100

MHz

I_{DD_OP}

—

17

mA

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs ac-

tive at 100 MHz

I_{DD_IOOP}

20

Si52202 Current Consumption (VDD = 1.5 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.3

0.4

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 2 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.3

0.6

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.0

mA

Wake-on LAN Current

PWRGD_PWRDNb = "0"

Byte 2, bit 2 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.6

0.3

mA

VDD_IO, all differential outputs off,

REF running

I_{DD_IOWOL}

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.5V_Total}

—

34

17

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at 100

MHz

I_{DD_OP}

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs ac-

tive at 100 MHz

I_{DD_IOOP}

10

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 10

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Table 4.2. DC Electrical Specifications (VDD = 1.8 V ±5%)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

1.8 V Operating Voltage

VDD core

1.8 V ±5%

1.71

1.8

1.89

V

Supply voltage for differential Low

Power outputs

Output Supply Voltage

1.8 V Input High Voltage

1.8 V Input Mid Voltage

1.8 V Input Low Voltage

VDDIO

V_IH

0.9975

0.75 V_DD

0.4 V_DD

-0.3

1.05–1.8

—

1.9

V

Control input pins, except SDATA,

SCLK

VDD+0.3

0.6 VDD

0.25 VDD

Tri-level control input pins, except

SDATA, SCLK

V_IM

0.5 V_DD

—

Control input pins, except SDA-

TA,SCLK

V_IL

V_IHI2C

V_ILI2C

Input High Voltage

SDATA, SCLK

At VOL

1.11

—

3.3

0.6

V

Input Low Voltage

I_PULLUP

SDATA, SCLK Sink Current

4

mA

Single-ended inputs, VIN = GND,

VIN = VDD

I_IN

–5

—

5

uA

Single-ended inputs, VIN = 0V, in-

puts with internal pull-up resistors

VIN = VDD, inputs with internal

pull-down resistors

Input current

I_INP

–200

—

200

uA

C_IN

C_OUT

L_IN

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

1.5

—

5

6

7

pF

nH

—

Si52212 Current Consumption (VDD = 1.8 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.4

0.5

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 3 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.5

mA

Wake-on LAN Current

PWRGD/PWRDNb = "0"

Byte 2, bit 3 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.7

0.5

mA

VDD_IO, all differential outputs

off, REF running

I_{DD_IOWOL}

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 11

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.8V_Total}

—

84

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at

100 MHz

I_{DD_OP}

—

19

mA

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs

active at 100 MHz

I_{DD_IOOP}

58

Si52208 Current Consumption (VDD = 1.8 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.4

0.5

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = ''0"

Byte 2, bit 3 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.5

mA

Wake-on LAN Current

PWRGD/PWRDNb = "0"

Byte 2, bit 3 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.7

0.5

mA

VDD_IO, all differential outputs

off, REF running

I_{DD_IOWOL}

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.8V_Total}

—

65

19

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at

100 MHz

I_{DD_OP}

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs

active at 100 MHz

I_{DD_IOOP}

39

Si52204 Current Consumption (VDD = 1.8 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.4

0.5

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 3 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.5

mA

Wake-on LAN Current

PWRGD/PWRDNb = ''0"

Byte 2, bit 3 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.7

0.5

mA

VDD_IO, all differential outputs

off, REF running

I_{DD_IOWOL}

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 12

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.8V_Total}

—

46

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at

100 MHz

I_{DD_OP}

—

19

mA

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs

active at 100 MHz

I_{DD_IOOP}

20

Si52202 Current Consumption (VDD = 1.8 V ±5%)

I_{DD_PD_total}

All outputs off

—

1.4

0.5

mA

VDD, except VDDA and VDD_IO,

all outputs off

Power Down Current

PWRGD/PWRDNb = "0"

Byte 2, bit 3 = 0

I_{DD_PD}

I_{DD_APD}

I_{DD_IOPD}

VDDA, all outputs off

—

0.6

0.3

mA

VDD_IO, all outputs off

VDD, except VDDA and VDD_IO,

all differential outputs off, REF

running

I_{DD_WOL}

—

4.5

mA

Wake-on LAN Current

PWRGD/PWRDNb = ''0"

Byte 2, bit 2 = 1

VDDA, all differential outputs off,

REF running

I_{DD_AWOL}

—

0.7

0.5

mA

VDD_IO, all differential outputs

off, REF running

I_{DD_IOWOL}

All outputs enabled. Differential

clocks with 5” traces and 2 pF

load.

I_{DD_1.8V_Total}

—

36

19

mA

VDD, except VDDA and VDD_IO,

all differential outputs active at

100 MHz

I_{DD_OP}

Dynamic Supply Current

VDDA, all differential outputs ac-

tive at 100 MHz

I_{DD_AOP}

—

7

mA

VDD_IO, all differential outputs

active at 100 MHz

I_{DD_IOOP}

10

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 13

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Table 4.3. AC Electrical Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Clock Input

CLKIN Frequency

CLKIN Duty Cycle

—

25

—

MHz

%

T_DC

Measured at VDD/2

45

55

4

CLKIN Rising and Falling

Slew Rate

Measured between 0.2 VDD and

0.8 VDD

T_R/T_F

0.5

—

V/ns

V_IH

V_IL

0.75 V_DD

—

Input High Voltage

Input Low Voltage

Input Common Mode

Input Amplitude

XIN/CLKIN pin

—

V

0.25 VDD

1000

V_COM

V_SWING

Common mode input voltage

Peak to Peak value

300

mV

300

1450

Control Input Pins

Rise time of single-ended control

inputs

T_r

T_f

Trise

—

5

ns

Fall time of single-ended control

inputs

Tfall

(Max VIL – 0.15) to

(Min VIH + 0.15)

T_rI2C

SDATA, SCLK Rise Time

SDATA, SCLK Fall Time

1000

300

400

ns

(Min VIH + 0.15) to

(Max VIL – 0.15)

T_fI2C

ns

SMBus Operating

Frequency

Maximum SMBus operating

frequency

2

F_{maxI C}

kHz

LVCMOS – REF (VDD = 1.5 V ±5%)

Variation from reference

frequency

Long Accuracy

Clock Period

ppm

T_PERIOD

T_rf

0

ppm

ns

25 MHz output

—

40

0.5

Byte 2[1:0] = 48 (Slowest), 20% to

80% of VDDREF

V/ns

Byte 2[1:0] = 49 (Slow), 20% to

80% of VDDREF

—

0.7

0.9

V/ns

Slew Rate

Byte 2[1:0] = 4A (Fast), 20% to

80% of VDDREF

Byte 2[1:0] = 4B (Fastest), 20% to

80% of VDDREF

Duty Cycle¹

T_{DC_REF}

T_{CCJ_REF}

RMS_REF

VT = VDD/2 V

45

—

50

45

55

%

ps

Cycle-to-Cycle Jitter

Phase Jitter

12 kHz to 5MHz

1 kHz offset

0.35

–132

–143

ps

T_{J1kHz_REF}

T_{J10kHz_REF}

REF Noise Floor

dBc

10 kHz offset to Nyquist

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 14

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Unit

LVCMOS – REF (VDD = 1.8 V ±5%)

Variation from reference

frequency

Long Accuracy

Clock Period

ppm

T_PERIOD

T_rf

0

ppm

ns

25 MHz output

—

40

0.7

Byte 2[1:0] = 48 (Slowest), 20% to

80% of VDDREF

V/ns

Byte 2[1:0] = 49 (Slow), 20% to

80% of VDDREF

—

1.0

1.2

1.3

V/ns

Slew Rate

Byte 2[1:0] = 4A (Fast), 20% to

80% of VDDREF

Byte 2[1:0] = 4B (Fastest), 20% to

80% of VDDREF

Duty Cycle¹

T_{DC_REF}

T_{CCJ_REF}

RMS_REF

VT = VDD/2 V

45

—

50

30

55

%

ps

Cycle-to-Cycle Jitter

Phase Jitter

12 kHz to 5 MHz

1 kHz offset

0.32

–132

–145

ps

TJ_{1kHz_REF}

TJ_{10kHz_REF}

REF Noise Floor

DIFF HCSL

dBc

10 kHz offset to Nyquist

T_DC

Duty Cycle

Measured at 0 V differential

45

—

50

10

55

%

T_SKEW

Output-to-Output Skew

ps

Measured differentially from

±150 mV (fast setting)

—

2.3

V/ns

T_R/T_F

Slew Rate

Measured differentially from

±150 mV (slow setting)

—

1.8

2

V/ns

%

Delta T_R/T_F

Slew Rate Matching

T_max-freqmod-

Max modulation frequency

df/dt

—

1250

ppm/usec

slew

V_HIGH

V_LOW

V_MAX

V_MIN

Voltage High

Voltage Low

Max Voltage

Min Voltage

600

–150

—

850

150

mV

750

0

1150

–300

Absolute crossing point voltage at

0.7 V Swing

V_OX

Crossing Point Voltage

250

—

550

33

mV

Variation of VOX over all rising

clock edges

V_{OX_DELTA}

F_MOD

Crossing Point Voltage (var)

—

35

mV

Modulation Frequency

30

31.5

kHz

Enable/Disable and Setup

Clock Stabilization from

Power-up

T_STABLE

—

1

ms

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 15

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Differential outputs start after

OE_b assertion Differential out-

puts stop after OE_b deassertion

T_OEBLAT

OE_b Latency

—

2

clocks

PD_b Latency to differential

outputs enable

Differential outputs enable after

PD_b de-assertion

T_PDb

—

490

µs

Note:

1. This is for XTAL mode only. For CLKIN mode, there would be a duty cycle distortion spec of ±0.5 ns.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 16

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Table 4.4. PCIe and Intel QPI Jitter Specifications

Jitter

Limit

Parameter

DIFF HCSL

Symbol

Condition

Min

Typ

Max

Unit

ps

(pk-pk)

J_CCJ

Cycle to Cycle Jitter

Measured at 0 V differential

PCIe Gen 1

—

0

23

21

ps

(pk-pk)

J_Pk-Pk

PCIe Gen 1 Pk-Pk Jitter

86

3

ps

(RMS)

10 kHz < F < 1.5 MHz

1.5 MHz < F < Nyquist

0

0.9

1.4

0.3

0.39

0.3

0.41

J_RMSGEN2

PCIe Gen 2 Phase Jitter

PCIe Gen 3 Phase Jitter

ps

(RMS)

0

3.1

1.0

0.7

0.5

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

ps

(RMS)

J_RMSGEN3

J_{RMSGen3_SRIS}

J_RMSGen4

—

0.4

0.5

0.4

0.5

PCIe Gen 3 SRIS¹

Phase Jitter

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

ps

(RMS)

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

ps

(RMS)

PCIe Gen 4 Phase Jitter

PCIe Gen 4 SRIS¹

Phase Jitter

Includes PLL BW 2–4 MHz,

CDR = 10 MHz

ps

(RMS)

J_{RMSGen4_SRIS}

Intel QPI Specifications for 100 MHz and 133 MHz

Intel QPI and SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

8 Gb/s, 100 MHz, 12UI

9.6 Gb/s, 100 MHz, 12UI

—

0.13

0.11

0.4

accummulated jitter^{2, 3, 4}

Intel QPI and SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

accummulated jitter^{2, 3, 4}

Intel QPI and SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

4.8 Gb/s, 133 MHz, 12UI, 17.04M

4.8 Gb/s, 133 MHz, 12UI, 7.8M

6.4 Gb/s, 133 MHz, 12UI, 17.04M

6.4 Gb/s, 133 MHz, 12UI, 7.8M

accummulated jitter^{2, 3, 4}

Intel QPI and SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

0.2

accummulated jitter^{2, 3, 4}

Intel QPI and SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

0.3

accummulated jitter^{2, 3, 4}

Intel QPI & SMI REFCLK

J_{RMSQPI_SMI}

ps

(RMS)

0.15

accummulated jitter^{2, 3, 4}

Note:

1. The SRIS jitter limit is the system RefClk simulation budget divided by sqrt (2) for equal allocation of uncorrelated jitter between

two clocks.

2. Post processed evaluation through Intel supplied Matlab scripts

3. Measuring on 100 MHz output using the template file in the PCIe Jitter Tool

4. Measuring on 100 MHz, 133 MHz outputs using the template file in the PCIe Jitter Tool. Visit www.pcisig.com for complete PCIe

specifications.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 17

Si52212/Si52208/Si52204/Si52202 Data Sheet

Electrical Specifications

Table 4.5. Absolute Maximum Conditions

Parameter

Symbol

VDD_1.8V

VIN

Test Condition

Functional

Min

—

Typ

—

Max

2.5

Unit

V

Main Supply Voltage

Input Voltage

Relative to VSS

SDATA and SCLK

–0.5

—

VDD + 0.5

3.6

V

Input High Voltage I²C

VIH_I2C

V

Temperature, Storage

TS

T_A

Non-functional

Functional

–65

–40

—

150

85

Celsius

Temperature, Operating Ambient

Temperature, Junction

T_J

Functional

150

22

Celsius

Dissipation, Junction to Case

θ_JC

JEDEC

—

Celsius/W

(JESD 51)

Dissipation, Junction to Ambient

θ_JA

JEDEC

(JESD 51)

—

30

Celsius/W

V

ESD Protection

ESDHBM

JEDEC

–2000

2000

(Human Body Model)

(JESD 22-A114)

Flammability Rating

UL-94

UL (Class)

V–0

Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power

supply sequencing is not required.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 18

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Description

5. Functional Description

5.1 Crystal Recommendations

The clock device requires a parallel resonance crystal.

Table 5.1. Crystal Recommendations

Frequency

(Fund)

Cut

Loading

Load Cap

Shunt Cap

(max)

Motional

(max)

Tolerance

(max)

Stability

(max)

Aging (max)

25 MHz

AT

Parallel

8–15 pF

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

5.2 Crystal Loading

Crystal loading is critical in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees

to calculate the appropriate capacitive loading (CL).

The figure below shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series

with the crystal.

Figure 5.1. Crystal Capacitive Clarification

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 19

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Description

5.3 Calculating Load Capacitors

In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading

correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both sides is twice the specified

crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides.

Figure 5.2. Crystal Loading Example

Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2:

Load Capacitance (each side)

Ce = 2 × CL − (Cs + Ci)

Total Capacitance (as seen by the crystal)

1

CLe =

1

+

(

)

Ce + Cs1 + Ci1 Ce2 + Cs2 + Ci2

• CL: Crystal load capacitance

• CLe: Actual loading seen by crystal using standard value trim capacitors

• Ce: External trim capacitors

• Cs: Stray capacitance (terraced)

• Ci : Internal capacitance (lead frame, bond wires, etc.)

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 20

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Description

5.4 PWRGD/PWRDNb (Power Down) Pin

The PWRGD/PWRDNb pin is a dual-function pin. During initial power up, the pin functions as the PWRGD pin. Upon the first power up,

if the PWRGD pin is low, the outputs will be disabled, but the crystal oscillator and I²C logics will be active. Once the PWRGD pin has

been sampled high by the clock chip, the pin assumes a PWRDNb functionality. When the pin has assumed a PWRDNb functionality

and is pulled low, the device will be placed in power down mode. The PWRGD/PWRDNb pin is required to be driven at all times. The

assertion and dessertion of PWRDNb is asynchronous.

Tstable

<1.8 ms

PWRDWN

DIF

Tdrive_Pwrdn#

<300 µs; > 200 mV

Figure 5.3. Differential (CLOCK–CLOCK) Measurement Points (Tperiod, Duty Cycle, Jitter)

5.5 PWRDNb (Power Down) Assertion

The PDB pin is an asynchronous active low input used to disable all output clocks in a glitch-free manner. All outputs will be driven low

in power down mode. In power down mode, all outputs, the crystal oscillator, and the I₂C logic are disabled.

PWRDWN

DIF

Figure 5.4. PWRDNb Assertion

5.6 PWRDNb (Power Down) Deassertion

When a valid rising edge on PWRGD/PWRDNb pin is applied, all outputs are enabled in a glitch-free manner within two to six output

clock cycles.

5.7 OEb Pin

The OEb pin is an active low input used to enable and disable the output clock. To enable the output clock, the OEb pin needs to be

logic low, and I²C OE bit needs to be logic high. By default, the OEb pin is set to logic low, and I²C OE bit is set to logic high.There are

two methods to disable the output clock: the OEb pin is pulled to a logic high, or the I²C OEb bit is set to a logic low. The OEb pin is

required to be driven at all times.

5.8 OEb Assertion

The OEb pin is an active low input used for synchronous stopping and starting the respective output clock while the rest of the clock

generator continues to function. The assertion of the OEb function is achieved by pulling the OEb pin low while the I²C OE bit is high,

which causes the respective stopped output to resume normal operation. No short or stretched clock pulses are produced when the

clocks resume. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles.

5.9 OEb Deassertion

The OEb function is deasserted by pulling high or writing the I²C OE bit to a logic low. The corresponding output is stopped cleanly and

the final output state is driven low.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 21

Si52212/Si52208/Si52204/Si52202 Data Sheet

Functional Description

5.10 FS Pin

The FS pin will select 0 = 100 MHz, mid = 200 MHz, 1 = 133 MHz. This is a tri-state pin, and this pin has a weak internal pull-down of

approximately 100 kΩ.

The default output frequency is 100 MHz.

The following figure shows the recommended configurations for tri-state.

VDD

R1

1 k

R1

1 k

MCU

With Tri-State Outputs

MCU

With Tri-State Outputs

FS Pin

Outputs

0, High Z and VDD

0, VDD/2 and VDD

R2

1 k

R2

Static Option

Tri-State Dynamic Option

The user can use an MCU with

strong Tri-State outputs to drive

the FS pin. 1 k-ohm resistors

should be adequate for most MCU

drivers; however, the resistance

can be increased to compensate

for a weaker driver. Increasing the

resistors will increase noise levels

on the FS pin line.

3-Level Dynamic Option

An MCU with a 3-level output

capability can be directly

connected to the FS Pin.

The user can NP either R1, R2, or

neither to constantly maintain low,

high, or mid levels, respectively.

Figure 5.5. Si522xx FS Tri-State Pin Circuit Configuration Suggestions

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 22

Si52212/Si52208/Si52204/Si52202 Data Sheet

Test and Measurement Setup

6. Test and Measurement Setup

The following diagrams show the test load configuration for the differential clock signals.

Measurement

L1

Point

OUT+

50

2 pF

L1 = 5"

Measurement

Point

L1

OUT-

50

2 pF

Figure 6.1. 0.7 V Differential Load Configuration

Figure 6.2. Differential Output Signals (for AC Parameters Measurement)

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 23

Si52212/Si52208/Si52204/Si52202 Data Sheet

Test and Measurement Setup

Figure 6.3. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 24

Si52212/Si52208/Si52204/Si52202 Data Sheet

PCIe Clock Jitter Tool

7. PCIe Clock Jitter Tool

The PCIe Clock Jitter Tool is designed to enable users to quickly and easily take jitter measurements for PCIe Gen1/2/3/4 and SRNS/

SRIS. This software removes all the guesswork for PCIe Gen1/2/3/4 and SRNS/SRIS jitter measurements and margins in board de-

signs. This software tool will provide accurate results in just a few clicks, and is provided in an executable format to support various

common input waveform files, such as .csv, .wfm, and .bin. The easy-to-use GUI and helpful tips guide users through each step. Re-

lease notes and other documentation are also included in the software package.

Download it for free at http://www.silabs.com/pcie-learningcenter.

Figure 7.1. PCIe Clock Jitter Tool

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 25

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8. Control Registers

8.1 I²C Interface

To enhance the flexibility and function of the clock synthesizer, an I²C interface is provided. Through the I²C interface, various device

functions, such as individual clock output buffers, are individually enabled or disabled. The registers associated with the I²C interface

initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at

system initialization, if any are required.

8.2 Block Read/Write

The clock driver I²C protocol accepts block write and block read operations from the controller. For block write/read operation, access

the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transfer-

red. The block write and block read protocol is outlined in Table 8.2 Block Read and Block Write Protocol on page 29.

8.3 Block Read

After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The slave acknowledges the

register index in the command byte. The master sends a repeat start function. After the slave acknowledges this, the slave sends the

number of bytes it wants to transfer (>0 and <33). The master acknowledges each byte except the last and sends a stop function.

1

7

1 1

8

1 1

A

7

1 1

r

Rd

Wr

A

T Slave

Command Code

Slave

Register # to

read

MSB = 0

repeat starT

Acknowledge

Command

starT

Condition

Master to

Slave to

8

1

8

1

8

1 1

Data Byte

Data Byte 0

A Data Byte 1 N P

A

Not acknowledge

stoP Condition

Block Read Protocol

Figure 8.1. Block Read Protocol

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 26

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.4 Block Write

After the slave address is sent with the R/W condition bit not set, the command byte is sent with the MSB = 0. The lower seven bits

indicate the register at which to start the transfer. If the command byte is 00h, the slave device will be compatible with existing block

mode slave devices. The next byte of a write must be the count of bytes that the master will transfer to the slave device. The byte count

must be greater than zero and less than 33. Following this byte are the data bytes to be transferred to the slave device. The slave

device always acknowledges each byte received. The transfer is terminated after the slave sends the Ack and the master sends a stop

function.

1

7

1 1

8

1

A

Master to

Slave to

Wr

Command

A

T Slave Address

Register # to

write

Command bit

starT

Acknowledge

MSB = 0

Condition

1

8

1

8

1 1

8

A Data Byte 1 A P

Byte Count = 2

Data Byte 0

A

stoP Condition

Block Write Protocol

Figure 8.2. Block Write Protocol

8.5 Byte Read/Write

Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register number. Refer to Table

8.3 Byte Read and Byte Write Protocol on page 30 for byte read and byte write protocol.

8.6 Byte Read

The standard byte read is as shown in the figure below. It is an extension of the byte write. The write start condition is repeated; then,

the slave device starts sending data, and the master acknowledges it until the last byte is sent. The master terminates the transfer with

a NAK, then a stop condition. For byte operation, the MSB bit of the command byte must be set. For block operations, the MSB bit must

be reset. If the bit is not set, the next byte must be the byte transfer count.

1

7

1 1

8

1 1

A

7

1 1

8

1 1

r

Rd

Data Byte 0

Wr

A

N

T Slave

Command

P

Slave

Register # to

read

MSB bit = 1

Not ack

Command

starT

Condition

repeat starT

Acknowledge

stoP

Condition

Master to

Slave to

Byte Read Protocol

Figure 8.3. Byte Read Protocol

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 27

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.7 Byte Write

The figure below illustrates a simple, typical byte write. For byte operation, the MSB bit of the command byte must be set. For block

operations, the MSB bit must be reset. If the bit is not set, the next byte must be the byte transfer count. The count can be between 1

and 32. It is not allowed to be zero or to exceed 32.

1

7

1 1

8

1

A

8

1 1

A

P

Wr

A

T Slave

Command

Data Byte 0

Register # to

write

MSB bit = 1

Command

starT Condition

stoP Condition

Acknowledge

Master to

Slave to

Byte Write Protocol

Figure 8.4. Byte Write Protocol

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 28

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.8 Data Protocol

The clock driver I²C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/

read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any

complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The

block write and block read protocol is outlined in Table 8.2 Block Read and Block Write Protocol on page 29 while Table 8.3 Byte

Read and Byte Write Protocol on page 30 outlines byte write and byte read protocol.

Table 8.1. SA State on First Application of PWRGD/PWRDNb

Description

SA

0

Address

1101001

1101010

State of SA on first application of PWRGD/PWRDNb¹

1

Note:

1. Si52202 default address is 0x6A

Table 8.2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

1

Description

Start

Bit

1

Description

Start

8:2

Slave address—7 bits

Write

8:2

9

Slave address–7 bits

Write

9

10

Acknowledge from slave

Command Code—8 bits

Acknowledge from slave

Byte Count—8 bits

Acknowledge from slave

Data byte 1–8 bits

Acknowledge from slave

Data byte 2–8 bits

Acknowledge from slave

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

28

20

27:21

28

Slave address–7 bits

Read = 1

36:29

37

29

Acknowledge from slave

Byte Count from slave–8 bits

Acknowledge

45:38

46

37:30

38

....

Data Byte/Slave Acknowledges

Data Byte N–8 bits

Acknowledge from slave

Stop

46:39

47

Data byte 1 from slave–8 bits

Acknowledge

55:48

56

Data byte 2 from slave–8 bits

Acknowledge

....

Data bytes from slave/Acknowl-

edge

....

Data Byte N from slave–8 bits

NOT Acknowledge

Stop

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 29

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.3. Byte Read and Byte Write Protocol

Byte Read Protocol

Byte Write Protocol

Bit

1

Description

Start

Bit

1

Description

Start

8:2

9

Slave address–7 bits

Write

8:2

9

Slave address–7 bits

Write

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Data byte–8 bits

10

Acknowledge from slave

Command Code–8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

Acknowledge from slave

Stop

27:21

28

Slave address–7 bits

Read

29

Acknowledge from slave

Data from slave–8 bits

NOT Acknowledge

Stop

37:30

38

39

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 30

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.9 Register Tables

8.9.1 Si52212 Registers

Table 8.4. Control Register 0. Byte 0

Bit

7

Name

If Bit = 0

Disabled

If Bit = 1

Enabled

Type

RW

Default

Function

DIFF7_OE

DIFF6_OE

DIFF5_OE

DIFF4_OE

DIFF3_OE

DIFF2_OE

DIFF1_OE

DIFF0_OE

1

Output enable for DIFF[7]

Output enable for DIFF[6]

Output enable for DIFF[5]

Output enable for DIFF[4]

Output enable for DIFF[3]

Output enable for DIFF[2]

Output enable for DIFF[1]

Output enable for DIFF[0]

6

5

4

3

2

1

0

Table 8.5. Control Register 1. Byte 1

Bit

7

Name

If Bit = 0

Disabled

If Bit = 1

Enabled

Type

RW

Default

Function

DIFF11_OE

DIFF10_OE

DIFF9_OE

DIFF8_OE

1

0

Output enable for DIFF[11]

Output enable for DIFF[10]

Output enable for DIFF[9]

Output enable for DIFF[8]

6

5

4

3

Reserved

2

1

SS_EN_READ1

SS_EN_READ0

R

Spread Enable software readback

00 = –0.25%; 01 = –0.5%; 10 =

OFF; 11 = –0.5%

0

Table 8.6. Control Register 2. Byte 2

Bit

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Read back Byte

1[1:0]

SS control by

Byte 2 [6:5]

7

SS_EN_SW_HW_CTRL

RW

0

Enable software control of spread

6

5

SS_EN_SW1

SS_EN_SW0

RW

0

1

Software control of spread 00 = –

0.25%; 01 = OFF; 10 = OFF; 11 = –

0.5%

4

3

Reserved

Disabled

0

1

Reserved

REF_OE

Enabled

RW

Output Enable for REF

Wake-on LAN for REF. To have REF

output enabled in Power Down,

REF_OE needs to be enabled at the

same time.

REF output is

disabled in Pow- enabled in Pow-

er Down. er Down

REF output is

2

REF PWRDN

0

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 31

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Bit

Name

If Bit = 0

If Bit = 1

Type

Default

Function

1

RW

0

1

REF Output Slew Rate Control 00 =

Slowest; 01 = Slow; 10 = Fast; 11 =

Fastest

REF_SLR

0

RW

Table 8.7. Control Register 3. Byte 3

Bit

Name

If Bit = 0

If Bit = 1

Type

RW

Default

Function

7

6

5

4

3

2

1

0

SR_SEL_DIFF7

SR_SEL_DIFF6

SR_SEL_DIFF5

SR_SEL_DIFF4

SR_SEL_DIFF3

SR_SEL_DIFF2

SR_SEL_DIFF1

SR_SEL_DIFF0

Slow setting

Fast setting

1

Slew rate control for DIFF7

Slew rate control for DIFF6

Slew rate control for DIFF5

Slew rate control for DIFF4

Slew rate control for DIFF3

Slew rate control for DIFF2

Slew rate control for DIFF1

Slew rate control for DIFF0

Table 8.8. Control Register 4. Byte 4

Bit

7

Name

SR_SEL_DIFF11

SR_SEL_DIFF10

SR_SEL_DIFF9

SR_SEL_DIFF8

AMP

If Bit = 0

If Bit = 1

Type

RW

Default

Function

Slow setting

Fast setting

1

0

Slew rate control for DIFF11

Slew rate control for DIFF10

Slew rate control for DIFF9

Slew rate control for DIFF8

6

5

4

3

2

AMP

Controls Output Amplitude

1

AMP

0

AMP

Table 8.9. Control Register 5. Byte 5

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

7

6

5

4

3

2

1

0

1

0

R

Rev Code [7:4]

Vendor ID[3:0]

Revision Code

R

Vendor Identification Code

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 32

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.10. Control Register 6. Byte 6

Bit

7

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

0

6

R

5

R

4

R

Programming ID [7:0]

Programming ID (Internal Only)

3

R

2

R

1

R

0

R

Table 8.11. Control Register 7. Byte 7

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

Byte Count

7

6

5

4

3

2

1

0

BC

0

1

0

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 33

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.9.2 Si52208 Registers

Table 8.12. Control Register 0. Byte 0

Bit

7

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Reserved

0

1

0

1

Reserved

6

DIFF4_OE

DIFF3_OE

Disabled

Enabled

RW

Output enable for DIFF_4

Output enable for DIFF_3

Reserved

5

4

Reserved

Disabled

3

Reserved

2

DIFF2_OE

DIFF1_OE

DIFF0_OE

Enabled

RW

Output enable for DIFF_2

Output enable for DIFF_1

Output enable for DIFF_0

1

Disabled

0

Table 8.13. Control Register 1. Byte 1

Bit

7

Name

If Bit = 0

Disabled

If Bit = 1

Enabled

Type

RW

Default

Function

DIFF7_OE

DIFF6_OE

1

0

1

0

Output enable for DIFF_7

Output enable for DIFF_6

Reserved

6

RW

5

Reserved

Disabled

4

DIFF5_OE

Enabled

RW

Output enable for DIFF_5

3

Reserved

2

1

SS_EN_READ1

SS_EN_READ0

R

Spread Enable software readback

00 = –0.25%; 01 = –0.5%; 10 =

OFF; 11 = –0.5%

0

Table 8.14. Control Register 2. Byte 2

Bit

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Read back Byte

1[1:0]

SS control by

Byte 2 [6:5]

7

SS_EN_SW_HW_CTRL

RW

0

Enable software control of spread

6

5

SS_EN_SW1

SS_EN_SW0

RW

0

1

Software control of spread 00 = –

0.25%; 01 = OFF; 10 = OFF; 11 = –

0.5%

4

3

Reserved

Disabled

0

1

Reserved

REF_OE

Enabled

RW

Output Enable for REF

Wake-on LAN for REF. To have REF

output enabled in Power Down,

REF_OE needs to be enabled at the

same time.

REF output is

disabled in Pow- enabled in Pow-

er Down. er Down

REF output is

2

REF PWRDN

0

1

0

RW

0

1

REF Output Slew Rate Control 00 =

Slowest; 01 = Slow; 10 = Fast; 11 =

Fastest

REF_SLR

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 34

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.15. Control Register 3. Byte 3

Bit

7

Name

If Bit = 0

Reserved

If Bit = 1

Type

RW

Default

Function

1

Reserved

6

SR_SEL_DIFF_4

SR_SEL_DIFF_3

Slow setting

Reserved

Fast setting

Slew rate control for DIFF_4

Slew rate control for DIFF_3

Reserved

5

4

3

Reserved

2

SR_SEL_DIFF_2

SR_SEL_DIFF_1

SR_SEL_DIFF_0

Slow setting

Fast setting

Slew rate control for DIFF_2

Slew rate control for DIFF_1

Slew rate control for DIFF_0

1

0

Table 8.16. Control Register 4. Byte 4

Bit

7

Name

If Bit = 0

Slow setting

Reserved

If Bit = 1

Fast setting

Type

RW

Default

Function

SR_SEL_DIFF_7

SR_SEL_DIFF_6

1

0

Slew rate control for DIFF_7

Slew rate control for DIFF_6

Reserved

6

5

4

SR_SEL_DIFF_5

Slow setting

Fast setting

Slew rate control for DIFF_5

3

AMP

2

Controls Output Amplitude

1

0

Table 8.17. Control Register 5. Byte 5

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

7

6

5

4

3

2

1

0

1

0

R

Rev Code [7:4]

Vendor ID[3:0]

Revision Code

R

Vendor Identification Code

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 35

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.18. Control Register 6. Byte 6

Bit

7

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

0

6

R

5

R

4

R

Programming ID [7:0]

Programming ID (Internal Only)

3

R

2

R

1

R

0

R

Table 8.19. Control Register 7. Byte 7

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

Byte Count

7

6

5

4

3

2

1

0

BC

0

1

0

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 36

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.9.3 Si52204 Registers

Table 8.20. Control Register 0. Byte 0

Bit

7

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Reserved

0

1

0

1

0

6

DIFF2_OE

DIFF1_OE

Disabled

Enabled

RW

Output enable for DIFF_2

Output enable for DIFF_1

Reserved

5

4

Reserved

Disabled Enabled

3

Reserved

2

DIFF0_OE

RW

Output enable for DIFF_0

Reserved

1

Reserved

0

Reserved

Table 8.21. Control Register 1. Byte 1

Bit

7

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Reserved

0

1

0

6

Reserved

5

Reserved

4

DIFF3_OE

Disabled

Enabled

RW

Output enable for DIFF_3

3

Reserved

2

1

SS_EN_READ1

SS_EN_READ0

R

Spread Enable software readback

00 = –0.25%; 01 = –0.5%; 10 =

OFF; 11 = –0.5%

0

Table 8.22. Control Register 2. Byte 2

Bit

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Read back

Byte 1[1:0]

SS control by

Byte 2 [6:5]

7

SS_EN_SW_HW_CTRL

RW

0

Enable software control of spread

6

5

SS_EN_SW1

SS_EN_SW0

RW

0

1

Software control of spread 00 = –

0.25%; 01 = OFF; 10 = OFF; 11 = –

0.5%

4

3

Reserved

0

1

Reserved

REF_OE

Disabled

Enabled

RW

Output Enable for REF

Wake-on LAN for REF. To have REF

output enabled in Power Down,

REF_OE needs to be enabled at the

same time.

REF output is

disabled in

Power Down.

REF output is

enabled in

Power Down

2

REF PWRDN

0

1

0

RW

0

1

REF Output Slew Rate Control 00 =

Slowest; 01 = Slow; 10 = Fast; 11 =

Fastest

REF_SLR

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 37

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.23. Control Register 3. Byte 3

Bit

7

Name

If Bit = 0

Reserved

Slow setting

Reserved

Slow setting

Reserved

If Bit = 1

Type

RW

Default

Function

Reserved

1

6

SR_SEL_DIFF_2

SR_SEL_DIFF_1

Fast setting

Slew rate control for DIFF_2

Slew rate control for DIFF_1

Reserved

5

4

3

Reserved

2

SR_SEL_DIFF_0

Fast setting

Slew rate control for DIFF_0

Reserved

1

0

Reserved

Table 8.24. Control Register 4. Byte 4

Bit

7

Name

If Bit = 0

Reserved

Slow setting

If Bit = 1

Type

RW

Default

Function

Reserved

1

0

6

Reserved

5

Reserved

4

SR_SEL_DIFF_3

Fast setting

Slew rate control for DIFF_3

3

AMP

2

Controls Output Amplitude

1

0

Table 8.25. Control Register 5. Byte 5

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

7

6

5

4

3

2

1

0

1

0

R

Rev Code [7:4]

Vendor ID[3:0]

Revision Code

R

Vendor Identification Code

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 38

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.26. Control Register 6. Byte 6

Bit

7

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

0

6

R

5

R

4

R

Programming ID [7:0]

Programming ID (Internal Only)

3

R

2

R

1

R

0

R

Table 8.27. Control Register 7. Byte 7

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

Byte Count

7

6

5

4

3

2

1

0

BC

0

1

0

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 39

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

8.9.4 Si52202 Registers

Table 8.28. Control Register 0. Byte 0

Bit

7

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Reserved

0

1

0

6

DIFF0_OE

Disabled

Enabled

RW

Output enable for DIFF_0

Reserved

5

Reserved

4

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Reserved

Table 8.29. Control Register 1. Byte 1

Bit

7

Name

If Bit = 0

Reserved

Disabled

If Bit = 1

Type

Default

Function

Reserved

0

1

0

6

Reserved

5

DIFF1_OE

Enabled

RW

Output enable for DIFF_1

Reserved

4

Reserved

3

Reserved

2

1

SS_EN_READ1

SS_EN_READ0

R

Spread Enable software readback

00 = –0.25%; 01 = –0.5%; 10 =

OFF; 11 = –0.5%

0

Table 8.30. Control Register 2. Byte 2

Bit

Name

If Bit = 0

If Bit = 1

Type

Default

Function

Read back

Byte 1[1:0]

SS control by

Byte 2 [6:5]

7

SS_EN_SW_HW_CTRL

RW

0

Enable software control of spread

6

5

SS_EN_SW1

SS_EN_SW0

RW

0

1

Software control of spread 00 = –

0.25%; 01 = OFF; 10 = OFF; 11 = –

0.5%

4

3

2

1

0

Reserved

0

1

Reserved

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 40

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.31. Control Register 3. Byte 3

Bit

7

Name

If Bit = 0

Reserved

Slow setting

Reserved

If Bit = 1

Type

Default

Function

Reserved

1

6

SR_SEL_DIFF_0

Fast setting

RW

Slew rate control for DIFF_2

Reserved

5

4

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Reserved

Table 8.32. Control Register 4. Byte 4

Bit

7

Name

If Bit = 0

Reserved

Slow setting

Reserved

If Bit = 1

Type

Default

Function

Reserved

1

0

6

Reserved

5

SR_SEL_DIFF_1

Fast setting

RW

Slew rate control for DIFF_1

Reserved

4

3

AMP

RW

2

Controls Output Amplitude

1

0

Table 8.33. Control Register 5. Byte 5

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

7

6

5

4

3

2

1

0

1

0

R

Rev Code [7:4]

Vendor ID[3:0]

Revision Code

R

Vendor Identification Code

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 41

Si52212/Si52208/Si52204/Si52202 Data Sheet

Control Registers

Table 8.34. Control Register 6. Byte 6

Bit

7

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

0

6

R

5

R

4

R

Programming ID [7:0]

Programming ID (Internal Only)

3

R

2

R

1

R

0

R

Table 8.35. Control Register 7. Byte 7

Bit

Name

If Bit = 0

If Bit = 1

Type

R

Default

Function

Byte Count

7

6

5

4

3

2

1

0

BC

0

1

0

R

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 42

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

9. Pin Descriptions

9.1 Si52212 Pin Descriptions

1

2

3

4

VDDA

GNDA

48 GND

47

DIFF_7b

NC

46 DIFF_7

45

GND

OE_7b

SS_EN

OE_6b

5

6

44

43

PWRGD/PWRDNb

GND

DIFF_6b

DIFF_6

7

8

42

41

XIN/CLKIN

GND

Si52212

9

40

39

38

37

36

XOUT

VDDX

VDDR

VDD

10

11

DIFF_5b

DIFF_5

OE_5b

12

13

REF / SA

VSSR

SDA

SCLK

FS

OE_4b

DIFF_4b

DIFF_4

GND

14

15

35

34

16

33

Figure 9.1. 64-Pin QFN

Table 9.1. Si52212 64-Pin QFN Descriptions

Pin #

Name

VDDA

GNDA

NC

Type

PWR

Description

1

2

3

4

Analog Power Supply

Analog Ground

No connect

GND

I

Ground

Spread spectrum enable pin. 0 = –0.25% spread, mid= Off, 1= –0.5% spread (This

pin has an internal pull-up)

5

6

SS_EN

Active low input pin asserts power down (PDb) and disables all outputs, except

REF (This pin has an internal pull-up). Refer also to settings of Byte 2, Bit2 and

Bit3 for REF. Settings for Bit3 (REF_OE) will take precedence for REF.

PWRGD/

PWRDNb

I, PU

7

8

GND

XIN/CLKIN

XOUT

GND

I

Ground

25.00 MHz crystal input or 25 MHz Clock Input.

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

Power supply for crystal

9

O

10

11

VDDX

PWR

VDDR

Power supply for REF output

REF = 25MHz LVCMOS output. SA = Address select for I2C. When part is pow-

ered up, SA will be latched to select SM bus address. Refer to Table 8.1 SA State

on First Application of PWRGD/PWRDNb on page 29.

12

13

REF /SA

VSSR

O/I

GND

Ground

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 43

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

Pin #

14

Name

SDA

Type

I/O

I

Description

I²C compatible SDATA

I²C compatible SCLOCK

15

SCLK

Frequency select pin. 0 = 100 MHz, mid = 200 MHz, 1 = 133 MHz (This pin has an

internal pull-down)

16

FS

I

17

18

DIFF_0

O, DIF

0.7 V, 100 MHz differential clock

DIFF_0b

Output enable for DIFF_0 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

19

20

OE_0b

OE_1b

I, PD

Output enable for DIFF_1 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

21

22

23

24

25

26

27

DIFF_1

DIFF_1b

GND

O, DIF

GND

0.7 V, 100 MHz differential clock

Ground

VDD

PWR

Power supply

VDD_IO

DIFF_2

DIFF_2b

PWR

Output power supply

O, DIF

0.7 V, 100 MHz differential clock

Output enable for DIFF_2 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

28

29

OE_2b

OE_3b

I, PD

Output enable for DIFF_3 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

30

31

32

33

34

35

DIFF_3

DIFF_3b

VDD_IO

GND

O, DIF

PWR

0.7 V, 100 MHz differential clock

Output power supply

GND

Ground

DIFF_4

DIFF_4b

O, DIF

0.7 V, 100 MHz differential clock

Output enable for DIFF_4 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

36

37

OE_4b

OE_5b

I, PD

Output enable for DIFF_5 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

38

39

40

41

42

43

DIFF_5

DIFF_5b

VDD

O, DIF

PWR

0.7 V, 100 MHz differential clock

Power supply

GND

Ground

DIFF_6

DIFF_6b

O, DIF

0.7 V, 100 MHz differential clock

Output enable for DIFF_6 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

44

45

OE_6b

OE_7b

I, PD

Output enable for DIFF_7 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 44

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

Pin #

46

Name

DIFF_7

DIFF_7b

GND

Type

O, DIF

GND

Description

0.7 V, 100 MHz differential clock

Ground

47

48

49

VDD_IO

DIFF_8

DIFF_8b

PWR

Output power supply

50

O, DIF

0.7 V, 100 MHz differential clock

51

Output enable for DIFF_8 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

52

53

OE_8b

OE_9b

I, PD

Output enable for DIFF_9 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

54

55

56

57

58

59

60

DIFF_9

DIFF_9b

VDD_IO

VDD

O, DIF

PWR

0.7 V, 100 MHz differential clock

Output power supply

PWR

Power supply

GND

Ground

DIFF_10

DIFF_10b

O, DIF

0.7 V, 100 MHz differential clock

Output enable for DIFF_10 pair (This pin has an internal pull-down). 0 = Enable

outputs; 1 = Disable outputs

61

62

OE_10b

OE_11b

I, PD

Output enable for DIFF_11 pair (This pin has an internal pull-down). 0 = Enable

outputs; 1 = Disable outputs

63

64

DIFF_11

DIFF_11b

GND PAD

O, DIF

GND

0.7 V, 100 MHz differential clock

Ground pad. This pad provides an electrical and thermal connection to ground and

must be connected for proper operation. Use as many vias as practical, and keep

the via length to an internal ground plane as short as possible.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 45

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

9.2 Si52208 Pin Descriptions

VDDA

GNDA

SS_EN

1

2

3

4

VDD_IO

NC

36

35

OE_4b

34

33

PWRGD/PWRDNb

DIFF_4b

DIFF_4

5

6

32

XIN/CLKIN

XOUT

31 VDD

Si52208

VDDX

7

8

30 DIFF_3b

VDDR

29

DIFF_3

28

27

26

25

9

OE_3b

NC

REF / SA

VSSR

10

SDA 11

SCLK

VDD_IO

OE_2b

12

Figure 9.2. 48-pin QFN

1

Name

VDDA

GNDA

SS_EN

Type

Description

PWR

I

Analog Power Supply

Analog Ground

2

3

Spread spectrum enable pin. 0 = -0.25% spread, mid= Off, 1= -0.5%

spread (This pin has an internal pull-up)

4

PWRGD/PWRDNb

I, PU

Active low input pin asserts power down (PDb) and disables all outputs,

except REF (This pin has an internal pull-up). Refer also to settings of

Byte 2, Bit2 and Bit3 for REF. Settings for Bit3 (REF_OE) will take prece-

dence for REF.

5

6

7

8

9

XIN/CLKIN

XOUT

I

25.00 MHz crystal input or 25 MHz Clock Input.

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

Power supply for crystal

O

VDDX

PWR

O/I

VDDR

Power supply for REF output

REF = 25 MHz LVCMOS output. SA = Address select for I²C. When part

is powered up, SA will be latched to select SM bus address. Refer to Ta-

ble 6.1

REF /SA

10

11

VSSR

SDA

GND

I/O

Power supply for crystal

I²C compatible SDATA

I²C compatible SCLOCK

12

13

SCLK

FS

I

Frequency select pin. 0 = 100 MHz, mid = 200 MHz, 1 = 133 MHz (This

pin has an internal pull-down)

14

NC

No connect

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 46

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

15

16

17

Name

DIFF_0

DIFF_0b

OE_0b

Type

O, DIF

I, PD

Description

0.7 V, 100 MHz differential clock

Output enable for DIFF_0 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

18

OE_1b

I, PD

Output enable for DIFF_1 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

19

20

21

22

23

24

25

DIFF_1

DIFF_1b

VDD

O, DIF

PWR

0.7 V, 100 MHz differential clock

Power supply

VDD_IO

DIFF_2

DIFF_2b

OE_2b

PWR

Output power supply

O, DIF

I, PD

0.7 V, 100 MHz differential clock

Output enable for DIFF_2 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

26

27

28

VDD_IO

NC

PWR

NC

Output power supply

No connect

OE_3b

I, PD

Output enable for DIFF_3 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

29

30

31

32

33

34

DIFF_3

DIFF_3b

VDD

O, DIF

PWR

0.7 V, 100 MHz differential clock

Power supply

DIFF_4

DIFF_4b

OE_4b

O, DIF

I, PD

0.7 V, 100 MHz differential clock

Output enable for DIFF_4 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

35

36

37

38

39

NC

No connect

VDD_IO

DIFF_5

DIFF_5b

OE_5b

PWR

O, DIF

I, PD

Output power supply

0.7 V, 100 MHz differential clock

Output enable for DIFF_5 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

40

41

42

43

44

45

NC

No connect

VDD_IO

VDD

PWR

O, DIF

I, PD

Output power supply

Power supply

DIFF_6

DIFF_6b

OE_6b

0.7 V, 100 MHz differential clock

Output enable for DIFF_6 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

46

OE_7b

I, PD

Output enable for DIFF_7 pair (This pin has an internal pull-down). 0 =

Enable outputs; 1 = Disable outputs

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 47

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

47

Name

DIFF_7

Type

O, DIF

GND

Description

0.7 V, 100 MHz differential clock

48

DIFF_7b

GND PAD

0.7 V, 100 MHz differential clock

Ground pad. This pad provides an electrical and thermal connection to

ground and must be connected for proper operation. Use as many vias as

practical, and keep the via length to an internal ground plane as short as

possible.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 48

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

9.3 Si52204 Pin Descriptions

1

2

3

4

SS_EN

PWRGD/PWRDNb

XIN/CLKIN

XOUT

24 VDD_IO

23

OE_2b

22 DIFF_2b

21

DIFF_2

Si52204

VDDX

NC

5

6

20

19

VDDR

VDD

REF / SA

7

8

18

17

DIFF_1b

DIFF_1

VSSR

Figure 9.3. 32-pin QFN

Table 9.2. Si52204 32-pin QFN Descriptions

Pin #

Name

Type

Description

Spread spectrum enable pin. 0 = –0.25% spread; mid = Off; 1 = –0.5% spread (this

pin has an internal pull-up).

1

SS_EN

I

Active low input pin asserts power down (PDb) and disables all outputs, except

REF (This pin has an internal pull-up). Refer also to settings of Byte 2, Bit2 and

Bit3 for REF. Settings for Bit3 (REF_OE) will take precedence for REF.

PWRGD/

PWRDNb

2

I, PU

3

4

5

6

XIN/CLKIN

XOUT

I

25.00 MHz crystal input or 25 MHz Clock Input.

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

Power supply for crystal

O

VDDX

PWR

VDDR

Power supply for REF output

REF = 25 MHz LVCMOS output. SA = Address select for I²C. When part is pow-

ered up, SA will be latched to select SM bus address. Refer to Table 8.1 SA State

on First Application of PWRGD/PWRDNb on page 29.

7

REF /SA

O/I

8

9

VSSR

SDA

GND

I/O

I

Ground

I²C compatible SDATA

I²C compatible SCLOCK

10

SCLK

Frequency select pin. 0 = 100 MHz; mid = 200 MHz; 1 = 133 MHz (this pin has a

internal pull-down)

11

FS

I

12

13

DIFF_0

O, DIF

0.7 V, 100 MHz differential clock

DIFF_0b

Output enable for DIFF_0 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

14

15

16

17

OE_0b

VDD_IO

OE_1b

DIFF_1

I, PD

PWR

I, PD

Output power supply

Output enable for DIFF_1 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

O, DIF

0.7 V, 100 MHz differential clock

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 49

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

Pin #

18

Name

DIFF_1b

VDD

Type

O, DIF

PWR

NC

Description

0.7 V, 100 MHz differential clock

Power supply

19

20

NC

No connect

21

DIFF_2

DIFF_2b

O, DIF

0.7 V, 100 MHz differential clock

22

Output enable for DIFF_2 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

23

OE_2b

I, PD

24

25

26

VDD_IO

DIFF_3

PWR

O, DIF

Output power supply

0.7 V, 100 MHz differential clock

DIFF_3b

Output enable for DIFF_3 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

27

OE_3b

I, PD

28

29

30

31

32

NC

VDD

NC

No connect

PWR

NC

Power supply

No connect

NC

VDDA

GNDA

GND PAD

PWR

GND

Analog Power Supply

Analog Ground

Ground pad. This pad provides an electrical and thermal connection to ground and

must be connected for proper operation. Use as many vias as practical, and keep

the via length to an internal ground plane as short as possible.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 50

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

9.4 Si52202 Pin Descriptions

1

2

3

4

5

15 VDD_IO

PWRGD/PWRDNb

XIN/CLKIN

XOUT

14

OE_0b

13

12

DIFF_0b

DIFF_0

GND

Si52202

VDDX

11

VSSR

Figure 9.4. 20-pin QFN

Table 9.3. Si52202 20-pin QFN Descriptions¹

Pin #

Name

Type

Description

1

PWRGD/

PWRDNb

I, PU

Active low input pin asserts power down (PDb) and disables all outputs (This pin

has an internal pull-up).

2

3

4

5

6

XIN/CLKIN

XOUT

VDDX

VSSR

I

25.00 MHz crystal input or 25 MHz Clock Input.

25.00 MHz crystal output. Float XOUT if using only CLKIN (Clock input).

Power supply for crystal

O

PWR

GND

I/O

Ground

I²C compatible SDATA

I²C compatible SCLOCK

SDA

7

8

SCLK

I

SS_EN

Spread spectrum enable pin. 0 = –0.25% spread; mid = Off; 1 = –0.5% spread.

(this pin has an internal pull-up)

9

GND

VDD

GND

PWR

GND

Ground

10

11

12

13

14

Power supply

GND

Ground

DIFF_0

DIFF_0b

OE_0b

O, DIF

I, PD

0.7 V, 100 MHz differential clock

Output enable for DIFF_0 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

15

16

VDD_IO

OE_1b

PWR

I, PD

Output power supply

Output enable for DIFF_1 pair (This pin has an internal pull-down). 0 = Enable out-

puts; 1 = Disable outputs

17

18

19

DIFF_1

DIFF_1b

VDDA

O, DIF

PWR

0.7 V, 100 MHz differential clock

Analog Power Supply

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 51

Si52212/Si52208/Si52204/Si52202 Data Sheet

Pin Descriptions

Pin #

Name

GND

Type

GND

Description

20

Ground

GND PAD

Ground pad. This pad provides an electrical and thermal connection to ground and

must be connected for proper operation. Use as many vias as practical, and keep

the via length to an internal ground plane as short as possible.

Note:

1. Contact factory for 133/200M output frequencies.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 52

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10. Packaging

10.1 Si52212 Package

The figure below illustrates the package details for the Si52212 in a 64-Lead 9 x 9 mm QFN package. The table lists the values for the

dimensions shown in the illustration.

Figure 10.1. 64L 9 x 9 mm QFN Package Diagram

Table 10.1. Package Diagram Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

9.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

9.00 BSC

5.20

E

E2

L

5.10

0.30

5.30

0.50

0.40

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.08

0.10

0.05

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 53

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Dimension

Min

Nom

Max

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MO-220.

4. Recommended card reflow profile is per JEDEC/IPC J-STD-020D specification for Small Body Components.

10.2 Si52212 Land Pattern

The following figure illustrates the land pattern details for the Si52212 in a 64-Lead 9 x 9 mm QFN package. The table lists the values

for the dimensions shown in the illustration.

Figure 10.2. 64L 9 x 9 mm QFN Land Pattern

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 54

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Table 10.2. PCB Land Pattern Dimensions

Dimension

mm

8.90

0.50

0.30

0.85

5.30

C1

C2

E

X1

Y1

X2

Y2

Notes:

General

1. All dimensions shown are in millimeters (mm).

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all pads.

4. A 3x3 array of 1.25 mm square openings on a 1.80 mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 55

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.3 Si52208 Package

The figure below illustrates the package details for the Si52208 in a 48-Lead 6 x 6 mm QFN package. The table lists the values for the

dimensions shown in the illustration.

Figure 10.3. 48L 6 x 6 mm QFN Package Diagram

Table 10.3. Package Diagram Dimensions

Dimension

Min

0.80

0.00

0.15

Nom

0.85

Max

0.90

0.05

0.25

A

A1

b

0.02

0.20

D

6.00 BSC

3.6

D2

e

3.5

3.7

0.40 BSC

6.00 BSC

3.6

E

E2

L

3.5

3.7

0.30

0.40

0.50

aaa

bbb

ccc

ddd

eee

0.10

0.05

0.08

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 56

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Dimension

Min

Nom

Max

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Outline MO-220.

4. Recommended card reflow profile is per JEDEC/IPC J-STD-020 specification for Small Body Components.

10.4 Si52208 Land Pattern

The figure below illustrates the land pattern details for the Si52208 in a 48-Lead, 6 x 6 mm QFN package. The table lists the values for

the dimensions shown in the illustration.

Figure 10.4. 48L 6 x 6 mm QFN Land Pattern

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 57

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Table 10.4. PCB Land Pattern Dimensions

Dimension

mm

5.90

C1

C2

X1

X2

Y1

Y2

e

5.90

0.20

3.60

0.85

3.60

0.40 BSC

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 3x3 array of 0.90 mm square openings on 1.15mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 58

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.5 Si52204 Package

The figure below illustrates the package details for the Si52204 in a 32-Lead, 5 x 5 mm QFN package. The table lists the values for the

dimensions shown in the illustration.

Figure 10.5. 32L 5 x 5 mm QFN Package Diagram

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 59

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Table 10.5. Package Diagram Dimensions

Dimension

Min

0.80

0.00

Nom

0.85

Max

0.90

0.05

A

A1

A3

b

0.02

0.20 REF

0.25

0.18

4.90

3.40

0.30

5.10

3.60

D/E

D2/E2

E

5.00

3.50

0.50 BSC

—

K

0.20

0.30

0.09

—

L

0.40

0.50

0.14

R

—

aaa

bbb

ccc

ddd

eee

fff

0.15

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 60

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.6 Si52204 Land Pattern

The figure below illustrates the land pattern details for the Si52204 in a 32-Lead, 5 x 5 mm QFN package. The table lists the values for

the dimensions shown in the illustration.

Figure 10.6. 32L 5 x 5 mm QFN Land Pattern

Table 10.6. PCB Land Pattern Dimensions

Dimension

mm

4.01

3.50

0.50

0.26

0.86

S1

S

L1

W1

e

W

L

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on IPC-7351 guidelines.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125mm (5 mils).

3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.

4. A 3x3 array of 0.85 mm square openings on 1.00 mm pitch can be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 61

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.7 Si52202 Package

The figure below illustrates the package details for the Si52202 in a 20-Lead, 3 x 3 mm QFN package. The table lists the values for the

dimensions shown in the illustration.

Figure 10.7. 20L 3 x 3 mm QFN Package Diagram

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 62

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Table 10.7. Package Diagram Dimensions

Dimension

Min

0.80

0.00

—

Nom

0.85

Max

0.90

0.05

—

A

A1

A3

b

0.02

0.65

0.20 REF

0.20

0.15

1.8

0.25

2.0

D

3.00 BSC

1.9

D2

E

3.00 BSC

1.9

E2

e

1.8

2.0

0.40 BSC

—

K

0.20

—

L

0.30

0.40

0.125

R

0.075

—

aaa

bbb

ccc

ddd

eee

fff

0.10

0.07

0.10

0.05

0.08

0.10

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. The drawing complies with JEDEC MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 63

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.8 Si52202 Land Pattern

The figure below illustrates the land pattern details for the Si52202 in a 20-Lead, 3 x 3 mm QFN package. The table lists the values for

the dimensions shown in the illustration.

Figure 10.8. 20L 3 x 3 mm QFN Land Pattern

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 64

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

Table 10.8. PCB Land Pattern Dimensions

Dimension

mm

3.10

C1

C2

X1

X2

Y1

Y2

e

3.10

0.20

1.90

0.70

1.90

0.40 BSC

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 3x3 array of 0.90 mm square openings on 1.15 mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 65

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.9 Si52212 Top Markings

Figure 10.9. Si52212 Top Marking

Table 10.9. Si52212 Top Marking Explanation

Line

Characters

Description

1

2

3

52212

A01A

Device part number

YY = Assembly year

YYWWTTTTTT

WW = Assembly work week

TTTTTT = Manufacturing trace code

4

e# CC

e# = Lead-finish symbol. # is a number

CC = Country of origin (ISO abbreviation)

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 66

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.10 Si52208 Top Markings

Figure 10.10. Si52208 Top Marking

Table 10.10. Si52208 Top Marking Explanation

Line

Characters

Description

1

2

3

4

52208

A01A

Device part number

TTTTTT

YYWW

TTTTTT = Manufacturing trace code

YY = Assembly year

WW = Assembly work week

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 67

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.11 Si52204 Top Markings

Figure 10.11. Si52204 Top Marking

Table 10.11. Si52204 Top Marking Explanation

Line

Characters

Description

1

2

3

4

52204

A01A

Device part number

TTTTTT

YYWW

TTTTTT = Manufacturing trace code

YY = Assembly year

WW = Assembly work week

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 68

Si52212/Si52208/Si52204/Si52202 Data Sheet

Packaging

10.12 Si52202 Top Markings

Figure 10.12. Si52202 Top Marking

Table 10.12. Si52202 Top Marking Explanation

Line

Characters

Description

1

2

3

5220

TTTT

YWW

Device part number

Manufacturing trace code

Y = Assembly year

WW = Assembly work week

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 69

Si52212/Si52208/Si52204/Si52202 Data Sheet

Revision History

11. Revision History

11.1 Revision 0.7

September 20, 2017

• Initial Release.

silabs.com | Building a more connected world.

Preliminary Rev. 0.7 | 70

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of

Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass

destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,

EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,

Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri and others are trademarks or registered

trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other

products or brand names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com


型号：	Si52208-A02AGM
厂家：	SILICON
描述：	12/8/4/2-Output PCI-Express Gen 1/2/3/4 and SRIS Clock Generator PC
文件：	总71页 (文件大小：1122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si52208-A02AGM [SILICON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E