Si5342_技术文档

Si5345/44/42 Rev D Data Sheet

10-Channel, Any-Frequency, Any-Output Jitter Attenuator/

Clock Multiplier

KEY FEATURES

• Generates any combination of output

frequencies from any input frequency

These jitter attenuating clock multipliers combine fourth-generation DSPLL^™and

MultiSynth^™technologies to enable any-frequency clock generation and jitter attenu-

ation for applications requiring the highest level of jitter performance. These devices

are programmable via a serial interface with in-circuit programmable non-volatile

memory (NVM) so they always power up with a known frequency configuration. They

support free-run, synchronous, and holdover modes of operation, and offer both au-

tomatic and manual input clock switching. The loop filter is fully integrated on-chip,

eliminating the risk of noise coupling associated with discrete solutions. Furthermore,

the jitter attenuation bandwidth is digitally programmable, providing jitter perform-

ance optimization at the application level. Programming the Si5345/44/42 is easy

• Ultra-low jitter of 90 fs rms

• External Crystal: 25 to 54 MHz

• Input frequency range

• Differential: 8 kHz to 750 MHz

• LVCMOS: 8 kHz to 250 MHz

• Output frequency range

• Differential: 100 Hz to 1028 MHz

• LVCMOS: 100 Hz to 250 MHz

with Silicon Labs’ ClockBuilder Pro^™software. Factory preprogrammed devices are

also available.

• Meets G.8262 EEC Option 1, 2 (SyncE)

• Highly configurable outputs compatible with

LVDS, LVPECL, LVCMOS, CML, and HCSL

with programmable signal amplitude

Applications:

• Si5345: 4 input, 10 output, 64-QFN 9×9 mm

• Si5344: 4 input, 4 output, 44-QFN 7×7 mm

• Si5342: 4 input, 2 output, 44-QFN 7×7 mm

• OTN muxponders and transponders

• 10/40/100 G networking line cards

• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)

• Carrier Ethernet switches

• SONET/SDH line cards

• Broadcast video

• Test and measurement

• ITU-T G.8262 (SyncE) compliant

25-54 MHz XTAL

XA

XB

OSC

÷INT

MultiSynth

÷INT

OUT0

OUT1

OUT2

÷INT

IN0

IN1

IN2

÷INT

DSPLL

OUT3

4 Input

Clocks

Up to 10

Output Clocks

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

÷INT

IN3/FB_IN

Status Flags

I2C / SPI

Status Monitor

Control

NVM

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Si5345/44/42 Rev D Data Sheet

Features List

1. Features List

The Si5345/44/42 Rev D features are listed below:

• Generates any combination of output frequencies from any in-

put frequency

• Optional zero delay mode

• Fastlock feature for low nominal bandwidths

• Glitchless on the fly output frequency changes

• DCO mode: as low as 0.001 ppb step size

• Core voltage

• Ultra-low jitter of 90 fs rms

• Input frequency range

• Differential: 8 kHz–750 MHz

• LVCMOS: 8 kHz–250 MHz

• V_DD: 1.8 V ±5%

• Output frequency range

• V_DDA: 3.3 V ±5%

• Differential: 100 Hz to 1028 MHz

• LVCMOS: 100 Hz to 250 MHz

• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz

• Meets G.8262 EEC Option 1, 2 (SyncE)

• Independent output clock supply pins

• 3.3 V, 2.5 V, or 1.8 V

Serial interface: I²C or SPI

•

• In-circuit programmable with non-volatile OTP memory

• ClockBuilder Pro software simplifies device configuration

• Si5345: 4 input, 10 output, 64-QFN 9×9 mm

• Si5344: 4 input, 4 output, 44-QFN 7×7 mm

• Si5342: 4 input, 2 output, 44-QFN 7×7 mm

• Temperature range: –40 to +85 °C

• Highly configurable outputs compatible with LVDS, LVPECL,

LVCMOS, CML, and HCSL with programmable signal ampli-

tude

• Status monitoring (LOS, OOF, LOL)

• Hitless input clock switching: automatic or manual

• Locks to gapped clock inputs

• Pb-free, RoHS-6 compliant

• Free-run and holdover modes

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Si5345/44/42 Rev D Data Sheet

Ordering Guide

2. Ordering Guide

Ordering Part Number

(OPN)

Number of Input/ Output Clock Frequency Supported Frequency

Temperature

Package

Output Clocks

Range (MHz)

Synthesis Modes

Range

Si5345

Si5345A-D-GM^{1, 2}

Si5345B-D-GM^{1, 2}

Si5345C-D-GM^{1, 2}

Integer and

Fractional

0.001 to 1028 MHz

0.001 to 350 MHz

0.001 to 1028 MHz

0.001 to 350 MHz

64-QFN

–40 to 85 °C

9×9 mm

4/10

Integer Only

Si5345D-D-GM^{1, 2}

Si5344

Si5344A-D-GM^{1, 2}

Si5344B-D-GM^{1, 2}

Si5344C-D-GM^{1, 2}

Integer and

Fractional

0.001 to 1028 MHz

0.001 to 350 MHz

0.001 to 1028 MHz

0.001 to 350 MHz

44-QFN

–40 to 85 °C

7×7 mm

4/4

Integer Only

Si5344D-D-GM^{1, 2}

Si5342

Si5342A-D-GM^{1, 2}

Si5342B-D-GM^{1, 2}

Si5342C-D-GM^{1, 2}

Integer and

Fractional

0.001 to 1028 MHz

0.001 to 350 MHz

0.001 to 1028 MHz

0.001 to 350 MHz

44-QFN

–40 to 85 °C

7×7 mm

4/2

Integer Only

Si5342D-D-GM^{1, 2}

Si5345/44/42-D-EVB

Si5345-D-EVB

Si5344-D-EVB

Si5342-D-EVB

Notes:

Evaluation

—

Board

1. Add an R at the end of the OPN to denote tape and reel ordering options.

2. Custom, factory preprogrammed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuilder

Pro software utility. Custom part number format is “Si5345A-Dxxxxx-GM” where “xxxxx” is a unique numerical sequence repre-

senting the preprogrammed configuration.

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Si5345/44/42 Rev D Data Sheet

Ordering Guide

Figure 2.1. Ordering Part Number Fields

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Si5345/44/42 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional in-

put dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is

controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which

determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth

dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the

MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency.

3.1 Frequency Configuration

The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory.

The combination of fractional input dividers (P_n/P_d), fractional frequency multiplication (M_n/M_d), fractional output MultiSynth division

(N_n/N_d), and integer output division (R_n) allows the generation of virtually any output frequency on any of the outputs. All divider values

for a specific frequency plan are easily determined using the ClockBuilder Pro utility.

3.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

tings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always

remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.

3.3 Fastlock Feature

Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting

a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-

ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The

DSPLL will revert to its normal loop bandwidth once lock acquisition has completed.

3.4 Modes of Operation

Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or

Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 5. The follow-

ing sections describe each of these modes in greater detail.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.4.1 Initialization and Reset

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard

reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the

serial interface will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit.

A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Power-Up

Reset and

Initialization

No valid

input clocks

selected

Free-run

Valid input clock

selected

Lock Acquisition

(Fast Lock)

Phase lock on

selected input

clock is achieved

An input is

qualified and

available for

selection

Locked

Mode

No valid input

clocks available

for selection

Holdover

Mode

Input Clock

Switch

Selected input

clock fails

Yes

No

Other Valid

Clock Inputs

Available?

Yes

Holdover

History

Valid?

No

Figure 3.1. Modes of Operation

3.4.2 Freerun Mode

The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency ac-

curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or refer-

ence clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their

configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A

TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes.

3.4.3 Lock Acquisition Mode

The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically

start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth

setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs

will generate a clock that follows the VCO frequency change as it pulls in to the input clock frequency.

3.4.4 Locked Mode

Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this

point, any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is ach-

ieved. See 3.8.4 LOL Detection for more details on the operation of the loss-of-lock circuit.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.4.5 Holdover Mode

The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are

available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance

of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 sec-

onds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a

programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in

the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency

data that may be corrupt just before the input clock failure.

Clock Failure and Entry

into Holdover

Historical Frequency Data Collected

time

Programmable historical data window used to

determine the final holdover value

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

120s

0s

1s,10s, 30s, 60s

Figure 3.2. Programmable Holdover Window

When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in hold-

over, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If

the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This

process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is

glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth.

The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference be-

tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-

ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40

values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit

from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on

ramped input switching, see 3.7.4 Ramped Input Switching.

Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable

holdover exit BW.

3.5 External Reference (XA/XB)

An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the

DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 3.3 Crystal

Resonator and External Reference Clock Connection Options on page 7. The device includes internal XTAL loading capacitors

which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to

Table 5.12 Crystal Specifications on page 36 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended

for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows

frequency adjustments of ±200 ppm. The Si5345/44/42 Family Reference Manual provides additional information on PCB layout recom-

mendations for the crystal to ensure optimum jitter performance.

To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE line

card PLL applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to pro-

vide a stable holdover reference. See the Si5345/44/42 Family Reference Manual for more information. Selection between the external

XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode.

Refer to Table 5.3 Input Clock Specifications on page 25 for REFCLK requirements when using this mode. A PREF divider is availa-

ble to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to 54 MHz will achieve the

best output jitter performance.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.6 Digitally Controlled Oscillator (DCO) Mode

The output MultiSynths support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency

step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increment

(FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it.

Any number of MultiSynths can be updated at once or independently controlled. The DCO mode is available when the DSPLL is operat-

ing in either free-run or locked mode.

25-54MHz

XO

25-54MHz

XO

25-54MHz

XTAL

100

XA

XB

XA

XB

XA

XB

2xC_L

2xCL

2xC_L

OSC

P_REF

÷

P_REF

÷

Si5345/44/42

Crystal Resonator

Connection

Differential XO

Connection

Single-Ended XO

Connection

Figure 3.3. Crystal Resonator and External Reference Clock Connection Options

3.7 Inputs (IN0, IN1, IN2, IN3)

There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-ended clocks. Input

selection can be manual (pin or register controlled) or automatic with user definable priorities.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3)

Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection

as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the

device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input

(FB_IN) and is not available for selection as a clock input.

Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins

IN_SEL[1:0]

Selected Input

Zero Delay Mode Disabled

Zero Delay Mode Enabled

0

1

0

1

0

1

IN0

IN1

IN2

IN3

IN0

IN1

IN2

Reserved

3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3)

An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection

criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by

the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With

revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority be-

comes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain

selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated.

3.7.3 Hitless Input Switching

Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that

have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they

have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the

DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference

between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature

supports clock frequencies down to the minimum input frequency of 8 kHz.

3.7.4 Ramped Input Switching

When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input

switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients

and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off

when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp

rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover see 3.4.5 Holdover

Mode.

3.7.5 Glitchless Input Switching

The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the

new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will

assert while the DSPLL is pulling-in to the new clock frequency. There will be no abrupt phase change at the output during the transi-

tion.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.7.6 Input Configuration and Terminations

Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown

in Figure 14. Differential signals must be ac-coupled, while single-ended LVCMOS signals can be ac or dc-coupled. Unused inputs can

be disabled and left unconnected when not in use.

Standard AC Coupled Differential LVDS

Si5345/44/42

Standard

50

INx

100

INxb

3.3V, 2.5V

LVDS or

50

CML

Pulsed CMOS

Standard AC Coupled Differential LVPECL

Si5345/44/42

50

Standard

INx

100

INxb

50

3.3V, 2.5V

LVPECL

Pulsed CMOS

Standard AC Coupled Single Ended

Si5345/44/42

Standard

INx

50

3.3V, 2.5V, 1.8V

INxb

LVCMOS

Pulsed CMOS

Pulsed CMOS DC Coupled Single Ended

R1

Si5345/44/42

Standard

50

INx

3.3V, 2.5V, 1.8V

LVCMOS

R2

INxb

R1 (Ohm) R2 (Ohm)

VDD

1.8 V

2.5 V

3.3 V

324

511

634

665

475

365

Pulsed CMOS

Figure 3.4. Termination of Differential and LVCMOS Input Signals

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Functional Description

3.7.7 Synchronizing to Gapped Input Clocks

The DSPLL supports locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose of

gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely

increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic

clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For

example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock.

This is shown in the following figure. For more information on gapped clocks, see “AN561: Introduction to Gapped Clocks and PLLs”.

Gapped Input Clock

100 MHz clock

1 missing period every 10

Periodic Output Clock

90 MHz non-gapped clock

100 ns

DSPLL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

10

Period Removed

10 ns

11.11111... ns

Figure 3.5. Generating an Averaged Clock Output Frequency from a Gapped Clock Input

A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every eight. Lock-

ing to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the

hitless switching specification in Table 5.8 Performance Characteristics on page 31 when the switch occurs during a gap in either

input clock.

3.8 Fault Monitoring

All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-

ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is

also a Loss Of Lock (LOL) indicator which is asserted when the DSPLL loses synchronization.

XA XB

Si5345/44/42

OSC

IN0

Precision

Fast

LOS

OOF

÷P₀

÷P₁

÷P₂

÷P₃

IN0b

DSPLL

IN1

Precision

Fast

LOL

IN1b

PD

LPF

÷M

Precision

Fast

IN2

IN2b

IN3/FB_IN

Precision

Fast

IN3/FB_INb

Figure 3.6. Si5345/44/42 Fault Monitors

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Functional Description

3.8.1 Input LOS Detection

The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of

the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal

sensitivity is configurable using the ClockBuilder Pro utility.

The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current

LOS state and a sticky register always stays asserted until cleared. An option to disable any of the LOS monitors is also available.

Sticky

Monitor

LOS

en

Live

Figure 3.7. LOS Status Indicators

3.8.2 XA/XB LOS Detection

A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when

XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is

detected.

3.8.3 OOF Detection

Each input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0_ppm” reference. This

OOF reference can be selected as either:

• XA/XB pins

• Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure

below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state, and its sticky

register bit stays asserted until cleared.

Sticky

Monitor

Precision

Fast

en

LOS

OOF

Live

en

Figure 3.8. OOF Status Indicator

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Functional Description

3.8.3.1 Precision OOF Monitor

The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected

OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configura-

ble up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling

at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency

range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of

the XA/XB pins is available. This option is register configurable.

OOF Declared

OOF Cleared

f_IN

Hysteresis

-4 ppm

(Clear)

-6 ppm

(Set)

+4 ppm

(Clear)

+6 ppm

(Set)

0 ppm

OOF Reference

Figure 3.9. Example of Precise OOF Monitor Assertion and Deassertion Triggers

3.8.3.2 Fast OOF Monitor

Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored

input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in

frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-

ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than

±4000 ppm.

3.8.4 LOL Detection

The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock.

There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency

difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL

indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator

to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from

toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The

live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects

the current state of the LOL monitor.

LOL Monitor

Sticky

LOL

Clear

Timer

LOS

LOL

Set

Live

LOLb

DSPLL

f_IN

PD LPF

Feedback

Clock

÷M

Si5345/44/42

Figure 3.10. LOL Status Indicators

The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two sep-

arate frequency monitors allows for hysteresis to help prevent chattering of LOL status.

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Si5345/44/42 Rev D Data Sheet

Functional Description

An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase

detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

Lost Lock

LOL

Hysteresis

LOCKED

0

0.1

1

10,000

Phase Detector Frequency Difference (ppm)

Figure 3.11. LOL Set and Clear Thresholds

Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards.

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using

the ClockBuilder Pro utility.

3.8.5 Interrupt Pin (INTRb)

An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are

maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the

interrupt.

3.9 Outputs

Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addi-

tion to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing

up to 20 single-ended outputs, or any combination of differential and single-ended outputs.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.9.1 Output Crosspoint

A crosspoint allows any of the output drivers to connect with any of the MultiSynths as shown in the figure below. The crosspoint config-

uration is programmable and can be stored in NVM so that the desired output configuration is ready at power up.

VDDO0

OUT0

OUT0b

Multi

Synth

N_0n

N_0d

÷

t₀

t₁

t₂

t₃

t₄

÷R₀

VDDO1

OUT1

OUT1b

Multi

Synth

N_1n

N_1d

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

÷R₉

VDDO2

OUT2

OUT2b

Multi

Synth

N_2n

N_2d

Multi

Synth

N_3n

N_3d

VDDO3

OUT3

OUT3b

Multi

Synth

N_4n

N_4d

VDDO4

OUT4

OUT4b

VDDO5

OUT5

OUT5b

VDDO6

OUT6

OUT6b

VDDO7

OUT7

OUT7b

VDDO8

OUT8

OUT8b

VDDO9

OUT9

OUT9b

Figure 3.12. MultiSynth to Output Driver Crosspoint

3.9.2 Output Signal Format

The differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including

LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3 V, 2.5 V, or 1.8

V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs.

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Rev. 1.0 | 14

Si5345/44/42 Rev D Data Sheet

Functional Description

3.9.3 Differential Output Terminations

The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.

Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards.

DC Coupled LVDS/LVPECL

V

_DDO= 3.3V, 2.5V, 1.8V

50

OUTx

100

OUTxb

AC Coupled LVPECL

VDD – 1.3V

Si5345/44/42

V

_DDO= 3.3V, 2.5V

50

OUTx

OUTxb

AC Coupled LVDS/LVPECL

50

V

_DDO= 3.3V, 2.5V, 1.8V

Si5345/44/42

50

OUTx

100

OUTxb

Internally

self-biased

Si5345/44/42

Figure 3.13. Supported Differential Output Terminations

3.9.4 LVCMOS Output Terminations

LVCMOS outputs are dc-coupled, as shown in the following figure.

DC Coupled LVCMOS

3.3V, 2.5V, 1.8V

LVCMOS

V

_DDO= 3.3V, 2.5V, 1.8V

50

Rs

OUTx

OUTxb

50

Si5345/44/42

Rs

Figure 3.14. LVCMOS Output Terminations

3.9.5 Programmable Common Mode Voltage For Differential Outputs

The common mode voltage (V_CM) for the differential modes are programmable so that LVDS specifications can be met and for the best

signal integrity with different supply voltages. When dc coupling the output driver, it is essential that the receiver have a relatively high

common mode impedance so that the common mode current from the output driver is very small.

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Rev. 1.0 | 15

Si5345/44/42 Rev D Data Sheet

Functional Description

3.9.6 LVCMOS Output Impedance Selection

Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source termination resistor

is recommended to help match the selected output impedance to the trace impedance, where Rs = Transmission line impedance – Z_O.

There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each VDDO option as shown in the follow-

ing table.

Table 3.2. Typical Output Impedance (Z_S)

VDDO

CMOS Drive Selections

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

3.3 V

2.5 V

1.8 V

38 Ω

43 Ω

—

30 Ω

35 Ω

46 Ω

22 Ω

24 Ω

31 Ω

3.9.7 LVCMOS Output Signal Swing

The signal swing (V_OL/V_OH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

3.9.8 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock

on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configura-

ble, enabling complementary clock generation and/or inverted polarity with respect to other output drivers.

3.9.9 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high, all outputs are

disabled. When held low, the outputs are enabled. Outputs in the enabled state can be individually disabled through register control.

3.9.10 Output Driver State When Disabled

The disabled state of an output driver is configurable as disable low or disable high.

3.9.11 Synchronous Output Disable Feature

The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock

period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When

this feature is turned off, the output clock will disable immediately without waiting for the period to complete.

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Si5345/44/42 Rev D Data Sheet

Functional Description

3.9.12 Output Skew Control (Δt₀– Δt₄)

The Si5345/44/42 uses independent MultiSynth dividers (N₀– N₄) to generate up to five unique frequencies to its ten outputs through a

crosspoint switch. By default, all clocks are phase-aligned. A delay path (Δt₀– Δt₄) associated with each of these dividers is available

for applications that need a specific output skew configuration. This is useful for PCB trace length mismatch compensation. The resolu-

tion of the phase adjustment is approximately 0.28 ps per step, definable in a range of ±9.14 ns. Phase adjustments are register-config-

urable. An example of generating two frequencies with unique configurable path delays is shown in the following figure.

VDDO0

OUT0

OUT0b

÷R₀

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

VDDO1

OUT1

OUT1b

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

VDDO2

OUT2

OUT2b

VDDO3

OUT3

OUT3b

VDDO4

OUT4

OUT4b

VDDO5

OUT5

OUT5b

VDDO6

OUT6

OUT6b

VDDO7

OUT7

OUT7b

VDDO8

OUT8

OUT8b

VDDO9

OUT9

OUT9b

÷R₉

Figure 3.15. Example of Independently-Configurable Path Delays

All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RSTb pin. Phase delay de-

fault values can be written to NVM, allowing a custom phase offset configuration at power-up or after power-on reset, or after a hard-

ware reset using the RSTb pin.

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Rev. 1.0 | 17

Si5345/44/42 Rev D Data Sheet

Functional Description

3.9.13 Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.

The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally

as shown in the figure below.

This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the

outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize

the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection. The FB_IN input pins

must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for

best performance. Note that the hitless switching feature is not available when zero delay mode is enabled.

IN0

Si5345/44/42

÷P₀

IN0b

IN1

DSPLL

÷P₁

IN1b

PD LPF

IN2

÷P₂

IN2b

÷M

IN3/FB_IN

÷P₃

VDDO0

OUT0

OUT0b

IN3/FB_INb

÷R₀

VDDO1

OUT1

OUT1b

t₀

t₁

t₂

t₃

t₄

÷N₀

÷N₁

÷N₂

÷N₃

÷N₄

÷R₁

÷R₂

VDDO2

OUT2

OUT2b

VDDO7

OUT7

OUT7b

÷R₇

÷R₈

÷R₉

VDDO8

OUT8

OUT8b

VDDO9

OUT9

OUT9b

External Feedback Path

Figure 3.16. Si5345 Zero Delay Mode Setup

3.9.14 Output Divider (R) Synchronization

All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same

result. Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.

3.10 Power Management

Unused inputs and output drivers can be powered down when unused. Consult the Family Reference Manual and ClockBuilder Pro

configuration utility for details.

3.11 In-Circuit Programming

The Si5345/44/42 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its default register val-

ues from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to

generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power

supply voltages applied to its V_DDand V_DDApins. The NVM is two time writable. Once a new configuration has been written to NVM,

the old configuration is no longer accessible. Refer to the Family Reference Manual for a detailed procedure for writing registers to

NVM.

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Rev. 1.0 | 18

Si5345/44/42 Rev D Data Sheet

Functional Description

3.12 Serial Interface

Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I²C or SPI interface. The

I2C_SEL pin selects I²C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in

either 4-wire or 3-wire. See the Family Reference Manual for details.

3.13 Custom Factory Preprogrammed Parts

For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered

with a specific configuration written into NVM. A factory preprogrammed part will generate clocks at power-up. Custom, factory-preprog-

rammed devices are available. The ClockBuilder Pro custom part number wizard can be used to quickly and easily generate a custom

part number for your configuration.

In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your

design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local

Silicon Labs sales representative. Samples of your preprogrammed device will typically ship in about two weeks.

3.14 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Preprogrammed Devices

As with essentially all modern software utilities, ClockBuilder Pro is continually being updated and enhanced. By registering at www.si-

labs.com, you will be notified about changes and their impact. This update process will ultimately enable ClockBuilder Pro users to ac-

cess all features and register setting values documented in this data sheet and the Family Reference Manual.

However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register

setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-

tance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock

outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro

project file with your specific features and register settings enabled using what's referred to as the manual "settings override" feature of

CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro

design report are shown in the following table.

Table 3.3. Setting Overrides

Location

0x04535[0]

0x0B48[0:4]

Name

Type

No NVM

User

Target

N/A

Dec Value

Hex Value

0x1

FORCE_HOLD

OOF_DIV_CLK_DIS

1

0

OPN&EVB

0x00

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Rev. 1.0 | 19

Si5345/44/42 Rev D Data Sheet

Functional Description

Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the

NVM file. The flowchart for this process is shown in the following figure.

End: Place

sample order

Start

Do I need a

pre-programmed device with

a feature or setting which is

unavailable in ClockBuilder

Pro?

Generate

Custom OPN

in CBPro

Configure device

using CBPro

No

Yes

Contact Silicon Labs

Technical Support

to submit & review

your

Yes

non-standard

configuration

request & CBPro

project file

Receive

updated CBPro

project file

from

Silicon Labs

with “Settings

Override”

Does the updated

CBPro Project file

match your

Load project file

into CBPro and test

requirements?

Figure 3.17. Process for Requesting Non-Standard CBPro Features

Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.

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Rev. 1.0 | 20

Si5345/44/42 Rev D Data Sheet

Register Map

4. Register Map

The register map is divided into multiple pages where each page has 256 addressable registers. Page 0 contains frequently accessible

registers, such as alarm status, resets, device identification, etc. Other pages contain registers that need less frequent access such as

frequency configuration, and general device settings. A high level map of the registers is shown in “6.2. High-Level Register Map” .

Refer to the Family Reference Manual for a complete list of register descriptions and settings. Silicon Labs strongly recommends using

ClockBuilder Pro to create and manage register settings.

4.1 Addressing Scheme

The device registers are accessible using a 16-bit address that consists of an 8-bit page address plus an 8-bit register address. By

default, the page address is set to 0x00. Changing to another page is accomplished by writing to the "Set Page Address" byte located

at address 0x01 of each page.

4.2 High-Level Register Map

Table 4.1. High-Level Register Map

16-Bit Address

Content

8-bit Page Address

8-bit Register Address Range

00

01

Revision IDs

Set Page Address

02–0A

0B–15

17–1B

1C

Device IDs

Alarm Status

INTR Masks

00

Reset controls

1D

FINC, FDEC Control Bits

SPI (3-Wire vs 4-Wire)

Alarm Configuration

NVM Controls

2B

2C–E1

E2–E4

FE

Device Ready Status

Set Page Address

01

08–3A

41–42

FE

Output Driver Controls

Output Driver Disable Masks

Device Ready Status

Set Page Address

01

02–05

08–2F

30

XTAL Frequency Adjust

Input Divider (P) Settings

Input Divider (P) Update Bits

Output Divider (R) Settings

User Scratch Pad Memory

Device Ready Status

02

47–6A

6B–72

FE

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Rev. 1.0 | 21

Si5345/44/42 Rev D Data Sheet

Register Map

16-Bit Address

Content

8-bit Page Address

8-bit Register Address Range

01

02–37

0C

Set Page Address

MultiSynth Divider (N0–N4) Settings

MultiSynth Divider (N0) Update Bit

MultiSynth Divider (N1) Update Bit

MultiSynth Divider (N2) Update Bit

MultiSynth Divider (N3) Update Bit

MultiSynth Divider (N4) Update Bit

FINC/FDEC Settings N0–N4

Output Delay (Δt) Settings

Device Ready Status

17

22

03

2D

38

39–58

59–62

FE

04

05

87

Zero Delay Mode Set Up

Fast Lock Loop Bandwidth

Feedback Divider (M) Settings

Input Select Control

0E–14

15–1F

2A

2B

Fast Lock Control

2C–35

36

Holdover Settings

Input Clock Switching Mode Select

Input Priority Settings

38–39

3F

Holdover History Valid Data

Reserved

06–08

09

00–FF

01

Set Page Address

1C

Zero Delay Mode Settings

Control I/O Voltage Select

Input Settings

43

49

10–FF

00–FF

Reserved

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Rev. 1.0 | 22

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

5. Electrical Specifications

Table 5.1. Recommended Operating Conditions¹

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C

Parameter Symbol

Ambient Temperature

Min

–40

—

Typ

25

Max

85

Unit

°C

V

T_A

TJ_MAX

V_DD

Junction Temperature

—

125

1.89

3.47

2.62

1.89

3.47

1.89

1.71

3.14

2.37

1.71

3.14

1.71

1.80

3.30

2.50

1.80

3.30

1.80

Core Supply Voltage

V_DDA

V

V_DDO

Clock Output Driver Supply Voltage

V

V_DDS

Status Pin Supply Voltage

V

Note:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

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Rev. 1.0 | 23

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.2. DC Characteristics

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

I_DD

Test Condition

Min

—

Typ

135

120

Max

260

130

Unit

mA

Core Supply Current^{1, 2, 3}

I_DDA

—

LVPECL Output⁴

@ 156.25 MHz

LVDS Output⁴

—

22

15

22

18

12

26

18

30

23

16

mA

@ 156.25 MHz

3.3 V LVCMOS Output⁵

@ 156.25 MHz

2.5 V LVCMOS Output⁵

@ 156.25 MHz

1.8 V LVCMOS Output⁵

@ 156.25 MHz

Si5345¹

I_DDOx

Output Buffer Supply Current

—

900

730

670

1200

1000

950

mW

Total Power Dissipation⁶

Si5344²

P_d

Si5342³

Notes:

1. Si5345 test configuration: 7 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

2. Si5344 test configuration: 4 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

3. Si5342 test configuration: 2 x 2.5 V LVDS outputs enabled at 156.25 MHz. Excludes power in termination resistors.

4. Differential outputs terminated into an AC-coupled 100 Ω load.

5. LVCMOS outputs measured into a 6 inch 50 Ω PCB trace with 5 pF load. Measurements were made in CMOS3 mode.

Differential Output Test Configuration

LVCMOS Output Test Configuration

I_DDO

0.1 uF

I_DDO

6 inch

50

OUT

OUTa

100

50

OUTb

5 pF

0.1 uF

6. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is

not available. All EVBs support detailed current measurements for any configuration.

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Rev. 1.0 | 24

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.3. Input Clock Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Standard Input Buffer with Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)

Differential

0.008

—

750

250

MHz

f_IN

Input Frequency Range

All Single-ended signals

(including LVCMOS)

Differential AC-coupled

f_IN< 250 MHz

100

225

100

—

1800

3600

mVpp_se

Differential AC-coupled

250 MHz < f_IN< 750 MHz

Single-ended AC-coupled

f_IN< 250 MHz

Voltage Swing¹

V_IN

Slew Rate^{2, 3}

SR

DC

C_IN

R_IN

400

40

—

60

—

V/µs

%

Duty Cycle

Input Capacitance

Input Resistance

0.3

16

pF

—

kΩ

Pulsed CMOS Input Buffer—DC Coupled (IN0, IN1, IN2, IN4)³

f_{IN_PULSED_CM}

Input Frequency

0.008

—

250

MHz

OS

V_IL

–0.2

0.8

400

40

—

8

0.4

—

60

—

V

Input Voltage

V_IH

Slew Rate^{2, 3}

SR

DC

PW

R_IN

V/µs

%

Duty Cycle

Minimum Pulse Width

Input Resistance

Pulse Input

1.6

—

ns

kΩ

REFCLK (Applied to XA/XB)

Full operating range. Jit-

ter performance may be

reduced.

24.97

48

—

54.06

54

MHz

Range for best jitter.

f_{IN_REF}

REFCLK Frequency

TCXO frequency for

SyncE applications. Jitter

performance may be re-

duced.

—

40

—

MHz

Input Single-ended Voltage

Swing

V_{IN_SE}

V_{IN_DIFF}

SR

365

2000

mVpp_se

Input Differential Voltage Swing

Slew Rate^{2, 3}

365

400

2500

—

mVpp_diff

V/µs

—

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Rev. 1.0 | 25

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Parameter

Input Duty Cycle

Note:

Symbol

Test Condition

Min

Typ

Max

Unit

DC

40

—

60

%

1. Voltage swing is specified as single-ended mVpp.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

OUTxb

2. Imposed for jitter performance.

3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20= ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR. Pulsed

CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a

duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input

thresholds (V_IL, V_IH) of this buffer are non-standard (0.4 and 0.8 V, respectively) refer to the input attenuator circuit for dc-coupled

pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or

Single-Ended ac-coupled input mode.

Table 5.4. Control Input Pin Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5345 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)

0.3 ×

V_DDIO

V_IL

V_IH

—

V

1

Input Voltage

0.7 ×

V_DDIO

—

1

C_IN

R_IN

PW

T_UR

Input Capacitance

Input Resistance

Minimum Pulse Width

Update Rate

—

2

—

pF

kΩ

ns

µs

20

—

RSTb, FINC and FDEC

FINC and FDEC

100

1

Si5344/42 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)

0.3 ×

V_DDIO

V_IL

V_IH

—

V

1

Input Voltage

0.7 ×

V_DDIO

—

1

C_IN

R_IN

PW

Input Capacitance

Input Resistance

Minimum Pulse Width

Note:

—

2

—

pF

kΩ

ns

20

—

RSTb

100

1. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Family Reference Manual for more details

on the proper register settings.

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Rev. 1.0 | 26

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.5. Differential Clock Output Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Si5342/44/45

Symbol

Test Condition

Min

Typ

Max

Unit

0.0001

733.33

825

—

720

800.00

1028

720

MHz

%

MultiSynth not used

f_OUT

Output Frequency

Duty Cycle

MultiSynth used

f_OUT< 400 MHz

0.0001

48

52

DC

400 MHz < f_OUT< 1028

MHz

45

—

55

65

%

Outputs on same

MultiSynth

Output-Output Skew

T_SKS

ps

Using Same MultiSynth

(Measured at 712.5 MHz)

Outputs from different

MultiSynths

Output-Output Skew

Between MultiSynths

T_SKD

—

90

ps

(Measured at 712.5 MHz)

Measured from the positive

to negative output pins

OUT-OUTb Skew

TSK_OUT

—

0

50

ps

V_DDO= 3.3 V,

2.5 V, 1.8 V

LVDS

350

640

430

750

510

900

mVpp_se

Output Voltage Swing¹

VOUT

V_DDO= 3.3 V,

2.5 V

LVPECL

LVDS

LVPECL

LVDS

1.10

1.90

1.2

2.0

1.3

2.1

V

V_DDO= 3.3 V

Common Mode Voltage^{1, 2}

(100 Ω load line-to-line)

VCM

V_DDO= 2.5 V

V_DDO= 1.8 V

1.1

0.8

—

1.2

0.9

1.3

1.0

V

sub-LVDS

Rise and Fall Times

(20% to 80%)

tR/tF

ZO

100

150

ps

Differential Output Impedance

—

100

–101

–96

–99

–97

–72

–88

—

Ω

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

Si5345

dBc

Power Supply Noise Rejec-

tion²

PSRR

Output-output Crosstalk³

XTALK

Si5342/44

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Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-

put driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher

than the TIA/EIA-644 maximum. Refer to the Si5345/44/42 Family Reference Manual for more suggested output settings. Not all

combinations of voltage amplitude and common mode voltages settings are possible.

OUTx

Vcm

Vpp_se

Vpp_diff = 2*Vpp_se

OUTxb

2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-

ured.

3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25

MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on

crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk.

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Rev. 1.0 | 28

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.6. LVCMOS Clock Output Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDO= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

0.0001

48

Typ

—

Max

250

52

Unit

MHz

%

f_OUT

Output Frequency

f_OUT<100 MHz

100 MHz < f_OUT< 250 MHz

When outputs are on same MultSynth.

F_OUT= 156.25 MHz

—

Duty Cycle

DC

45

—

55

%

T_SK

Output-to-Output Skew

—

30

140

ps

V_DDO= 3.3 V

I_OH= –10 mA V_DDOx 0.85

I_OH= –12 mA V_DDOx 0.85

I_OH= –17 mA V_DDOx 0.85

V_DDO= 2.5 V

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

Output Voltage High^{1, 2, 3}

V_OH

I_OH= –6 mA

I_OH= –8 mA

V_DDOx 0.85

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

I_OH= –11 mA V_DDOx 0.85

V_DDO= 1.8 V

I_OH= –4 mA

I_OH= –5 mA

V_DDOx 0.85

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

V_DDOx 0.85

V_DDO= 3.3 V

I_OL= 10 mA

I_OL= 12 mA

I_OL= 17 mA

V_DDOx 0.15

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

—

V_DDO= 2.5 V

Output Voltage Low^{1, 2, 3}

V_OL

I_OL= 6 mA

I_OL= 8 mA

I_OL= 11 mA

V_DDOx 0.15

OUTx_CMOS_DRV = 1

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

—

V

—

V_DDO= 1.8 V

I_OL= 4 mA

I_OL= 5 mA

V_DDOx 0.15

600

OUTx_CMOS_DRV = 2

OUTx_CMOS_DRV = 3

V_DDO= 3.3V

—

V

400

450

550

ps

LVCMOS Rise and Fall

Times³

V_DDO= 2.5 V

tr/tf

600

(20% to 80%)

V_DDO= 1.8 V

750

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Rev. 1.0 | 29

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Note:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the

Family Reference Manual for more details on register settings.

2. I_OL/I_OHis measured at V_OL/V_OHas shown in the dc test configuration.

3. A series termination resistor (Rs) is recommended to help match the source impedance to a 50 Ω PCB trace. A 5 pF capacitive

load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, at 156.25 MHz.

AC Test Configuration

Trace length 5 inches

499

DC Block

56

I_DDO

I_OL/I_OH

50

50 probe, scope

OUT

4.7 pF

Zs

OUTb

V_OL/V_OH

499

DC Block

56

50

4.7 pF

Table 5.7. Output Status Pin Specifications

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, V_DDS= 3.3 V ±5%, 1.8 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Si5345 Status Output Pins (LOLb, INTRb, SDA/SDIO¹, SDO)

V_DDIO²x

0.85

V_OH

I_OH= –2 mA

—

V

Output Voltage

V_DDIO²x

0.15

V_OL

Si5344/42 Status Output Pins (INTRb, SDA/SDIO1¹, SDO)

V_OHI_OH= –2 mA

I_OL= 2 mA

—

V_DDIO²x

0.85

—

V

Output Voltage

V_DDIO²x

0.15

V_OL

I_OL= 2 mA

—

Si5344 Status Output Pins (LOLb, LOS_XAXBb)

Si5342 Status Output Pins (LOLb, LOS_XAXBb, LOS0b, LOS1b, LOS2b, LOS3b)

V_OH

V_OL

I_OH= –2 mA

I_OL= 2 mA

V_DDSx 0.85

—

V

Output Voltage

V_DDSx 0.15

Notes:

1. The V_OHspecification does not apply to the open-drain SDA/SDIO output when the serial interface is in I²C mode or is unused

with I2C_SEL pulled high. VOL remains valid in all cases.

2. V_DDIOis determined by the IO_VDD_SEL bit. It is selectable as V_DDAor V_DD. See the Family Reference Manual for more details

on the proper register settings.

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Rev. 1.0 | 30

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.8. Performance Characteristics

V_DD= 1.8 V ±5%, V_DDA= 3.3 V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

VCO Frequency Range

F_VCO

13.5

—

14.4

GHz

PLL Loop Bandwidth Program-

ming Range¹

f_BW

0.1

—

4000

45

Hz

ms

Time from power-up to

when the device gener-

ates free-running clocks

t_START

Initial Start-Up Time

PLL Lock Time²

30

t_ACQ

t_{DELAY_frac}

t_{DELAY_int}

t_RANGE

f_IN= 19.44 MHz

—

280

0.28

71.4

±9.14

—

300

—

ms

ps

f

_VCO= 14 GHz

Output Delay Adjustment

—

ps

—

ns

POR to Serial Interface Ready³

Jitter Peaking

t_RDY

15

ms

Measured with a frequen-

cy plan running a 25 MHz

input, 25 MHz output, and

a Loop Bandwidth of 4 Hz

J_PK

—

0.1

—

dB

Compliant with G.8262

Options 1 and 2 Carrier

Frequency = 10.3125

GHz

J_TOL

Jitter Tolerance

—

3180

UI pk-pk

Jitter Modulation

Frequency = 10 Hz

Only valid for a single au-

tomatic switch between

two input clocks at same

frequency.

—

2.0

1.3

ns

Maximum Phase Transient

During a Hitless Switch

t_SWITCH

Only valid for a single

manual switch between

two input clocks at same

frequency.

ω_P

Pull-in Range

—

500

—

ppm

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Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

—

Typ

—

Max

1.8

Unit

ns

Measured between a

common 2 MHz input and

2 MHz output with differ-

ent MultiSynths on the

same unit.

DSPLL BW = 4 kHz

t_IODELAY

Measured between a

common 2 MHz input and

2 MHz output with differ-

ent MultiSynths between

units.

—

2.0

ns

Input-to-Output Delay Variation

DSPLL bandwidth = 4

kHz

Delay between reference

and feedback input with

both clocks at 10 MHz

and same slew rate. Ref

clock rise time must be

<200 ps.

t_ZDELAY

—

110

—

ps

Integer Mode

12 kHz to 20 MHz

Fractional Mode

12 kHz to 20 MHz

—

90

145

170

fs rms

RMS Phase Jitter⁴

J_GEN

120

Note:

1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL tresholds, etc. For this case, lock

time was measured with nominal and fastlock bandwidths set to 100 Hz, LOL set/clear thresholds of 6/0.6 ppm respectively, us-

ing IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising

edge of the clock reference and the LOL indicator deassertion.

3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.

4. Jitter generation test conditions: f_IN= 19.44 MHz, f_OUT= 156.25 MHz LVPECL, loop bandwidth = 100 Hz, F_XTAL= 48 MHz.

Table 5.9. I²C Timing Specifications (SCL,SDA)

Standard Mode

100 kbps

Fast Mode

400 kbps

Parameter

Symbol

Test Condition

Unit

Min

Max

Min

Max

f_SCL

—

SCL Clock Frequency

SMBus Timeout

—

100

—

400

kHz

ms

When Timeout is

Enabled

25

35

25

35

Hold time (Repeated)

START condition

t_HD:STA

t_LOW

4.0

4.7

4.0

—

0.6

1.3

0.6

—

µs

Low Period of the SCL Clock

HIGH Period of the SCL

Clock

t_HIGH

Setup Time for a Repeated

START Condition

t_SU:STA

4.7

—

0.6

—

µs

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Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Standard Mode

100 kbps

Fast Mode

Parameter

Symbol

Test Condition

400 kbps

Unit

Min

100

250

Max

—

Min

Max

—

t_HD:DAT

t_SU:DAT

Data Hold Time

100

ns

Data Setup Time

—

Rise Time of both SDA and

SCL Signals

t_r

t_f

—

1000

300

—

20

—

300

—

ns

µs

Fall Time of both SDA and

SCL Signals

Setup Time for STOP Condi-

tion

t_SU:STO

4.0

0.6

Bus Free Time between a

STOP and START Condition

t_BUF

4.7

—

1.3

—

µs

t_VD:DAT

t_VD:ACK

Data Valid Time

3.45

0.9

Data Valid Acknowledge

Time

—

Figure 5.1. I²C Serial Port Timing Standard and Fast Modes

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Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.10. SPI Timing Specifications (4-Wire)

V_DD= 1.8 V ±5%, V_DDA= 3.3V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

T_C

—

ns

T_D1

Delay Time, SCLK Fall to SDO Active

Delay Time, SCLK Fall to SDO

Delay Time, CSb Rise to SDO Tri-State

Setup Time, CSb to SCLK

12.5

10

—

18

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, SCLK Fall to CSb

5

—

ns

Setup Time, SDI to SCLK Rise

Hold Time, SDI to SCLK Rise

5

—

ns

5

—

ns

T_CS

T_C

Delay Time Between Chip Selects (CSb)

2

—

T_D1

T_C

T_SU1

SCLK

CSb

T_H1

T_SU2

T_H2

T_CS

SDI

T_D2

T_D3

SDO

Figure 5.2. 4-Wire SPI Serial Interface Timing

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Rev. 1.0 | 34

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.11. SPI Timing Specifications (3-Wire)

V_DD= 1.8 V ±5%, V_DDA= 3.3V ±5%, T_A= –40 to 85 °C

Parameter

Symbol

f_SPI

Min

—

40

50

—

5

Typ

—

Max

20

60

—

Unit

MHz

%

SCLK Frequency

SCLK Duty Cycle

SCLK Period

T_DC

T_C

—

ns

Delay Time, SCLK Fall to SDIO Turn-on

Delay Time, SCLK Fall to SDIO Next-bit

Delay Time, CSb Rise to SDIO Tri-State

Setup Time, CSb to SCLK

T_D1

12.5

10

—

20

15

—

ns

T_D2

ns

T_D3

ns

T_SU1

T_H1

T_SU2

T_H2

ns

Hold Time, CSb to SCLK Fall

5

—

ns

Setup Time, SDI to SCLK Rise

5

—

ns

Hold Time, SDI to SCLK Rise

5

—

ns

Delay Time Between Chip Selects (CSb)

T_CS

2

—

T_C

T_SU1

T_C

SCLK

T_H1

T_D1

T_D2

CSb

T_SU2

T_H2

T_CS

SDIO

T_D3

Figure 5.3. 3-Wire SPI Serial Interface Timing

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Rev. 1.0 | 35

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.12. Crystal Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Crystal Frequency Range

f_XTAL

Full operating range. Jit-

ter performance may be

reduced.

24.97

—

54.06

MHz

Range for best jitter.

48

—

8

54

—

MHz

pF

Load Capacitance

C_L

d_L

Crystal Drive Level

—

200

µW

Equivalent Series Resistance

Shunt Capacitance

r_ESR

C_O

Refer to the Si5345/44/42 Reference Manual to determine ESR and shunt capac-

itance.

Note:

1. Refer to the Si5345/44/42 Reference Manual for recommended 48 to 54 MHz crystals. The Si5345/44/42 are designed to work

with crystals that meet these specifications.

Table 5.13. Thermal Characteristics

Test Condition ¹

Parameter

Symbol

Value

Unit

Si5345-64QFN

Still Air

22

°C/W

Thermal Resistance

Junction to Ambient

θ_JA

Air Flow 1 m/s

Air Flow 2 m/s

19.4

18.3

Thermal Resistance

Junction to Case

θ_JC

9.5

°C/W

θ_JB

9.4

9.3

°C/W

Thermal Resistance

Junction to Board

Ψ_JB

Thermal Resistance

Junction to Top Center

Si5344, Si5342-44QFN

Ψ_JT

0.2

°C/W

Still Air

22.3

19.4

18.4

°C/W

Thermal Resistance

Junction to Ambient

θ_JA

Air Flow 1 m/s

Air Flow 2 m/s

Thermal Resistance

Junction to Case

Thermal Resistance

Junction to Board

Thermal Resistance

Junction to Top Center

Note:

θ_JC

10.9

°C/W

θ_JB

9.3

9.2

°C/W

Ψ_JB

Ψ_JT

0.23

°C/W

1. Based on PCB Dimension: 3" x 4.5" PCB Thickness: 1.6 mm, PCB Land/Via: 36, Number of Cu Layers: 4

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Rev. 1.0 | 36

Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Table 5.14. Absolute Maximum Ratings ^{1, 2, 3}

Parameter

Symbol

V_DD

Test Condition

Value

Unit

V

–0.5 to 3.8

–0.85 to 3.8

V_DDA

V_DDO

V_DDS

V

DC Supply Voltage

V

4

V_I1

IN0–IN3/FB_IN

V

IN_SEL1, IN_SEL0, RSTb,

OEb, I2C_SEL, FINC, FDEC,

SDI, SCLK, A0/CSb, A1,

SDA/SDIO

Input Voltage Range

V_I2

–0.5 to 3.8

–0.5 to 2.7

V

V_I3

LU

XA/XB

Latch-up Tolerance

JESD78 Compliant

ESD Tolerance

HBM

T_STG

T_JCT

100 pF, 1.5 kΩ

2.0

–55 to 150

125

kV

°C

Storage Temperature Range

Maximum Junction Temperature in Operation

Soldering Temperature

T_PEAK

260

°C

s

(Pb-free profile)⁵

Soldering Temperature Time at T_PEAK

T_P

20–40

(Pb-free profile)⁵

Note:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

2. 64-QFN and 44-QFN packages are RoHS-6 compliant.

3. Moisture sensitivity level is MSL2. For more packaging information, go to the Silicon Labs RoHS information page.

4. The minimum voltage at these pins can be as low as –1.0 V when an ac input signal of 8 kHz or greater is applied. See Table

5.3 Input Clock Specifications on page 25 for single-ended ac-coupled f_IN< 250 MHz.

5. The device is compliant with JEDEC J-STD-020.

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Rev. 1.0 | 37

Si5345/44/42 Rev D Data Sheet

Typical Application Schematic

6. Typical Application Schematic

100 MHz (HCSL)

PCIe 3.0

133.333 MHz (CMOS)

CPU/NPU

Si5345

83.333 MHZ (CMOS)

50 MHz (CMOS)

DSPLL

100 MHz

125 MHz

FPGA/ASIC/

SWITCH

156.25 MHz (LVDS)

MultiSynth

19.44 MHz

2.048 MHz

156.525 MHz (LVDS)

155.52 MHz (LVDS)

10G PHY

125 MHz (LVPECL)

1G PHY

Figure 6.1. 10G Ethernet Data Center Switch and Compute Blade Schematic

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Rev. 1.0 | 38

Si5345/44/42 Rev D Data Sheet

Detailed Block Diagrams

7. Detailed Block Diagrams

48-54MHz XTAL or

REFCLK

3

XA

XB

Si5345

OSC

IN_SEL[1:0]

P_REF

÷

IN0

IN0b

IN1

P_0n

÷

P_0d

P_1n

÷

DSPLL

IN1b

P_1d

PD

LPF

P_2n

÷

IN2

P_2d

IN2b

IN3/FB_IN

M_n

M_d

P_3n

÷

Optional

External

Feedback

IN3/FB_INb

P_3d

VDDO0

OUT0

OUT0b

Multi

Synth

N_0n

÷

t₀

÷R₀

N_0d

VDDO1

OUT1

Multi

Synth

N_1n

÷

t₁

t₂

t₃

t₄

N_1d

÷R₁

÷R₂

÷R₃

÷R₄

÷R₅

÷R₆

÷R₇

÷R₈

÷R₉

OUT1b

VDDO2

OUT2

OUT2b

Multi

Synth

N_2n

÷

N_2d

Multi

Synth

N_3n

÷

VDDO3

OUT3

OUT3b

N_3d

Multi

Synth

N_4n

÷

VDDO4

OUT4

OUT4b

N_4d

VDDO5

OUT5

OUT5b

I2C_SEL

VDDO6

OUT6

OUT6b

SDA/SDIO

A1/SDO

SCLK

SPI/

I²C

NVM

VDDO7

OUT7

OUT7b

A0/CSb

VDDO8

OUT8

OUT8b

INTRb

Status

Monitors

LOLb

VDDO9

OUT9

OUT9b

Figure 7.1. Si5345 Block Diagram

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Rev. 1.0 | 39

Si5345/44/42 Rev D Data Sheet

Detailed Block Diagrams

48-54MHz XTAL or

REFCLK

2

4

XA

XB

Si5344

OSC

IN_SEL[1:0]

P_REF

÷

IN0

IN0b

IN1

P_0n

÷

P_0d

P_1n

÷

DSPLL

IN1b

P_1d

PD

LPF

P_2n

÷

IN2

P_2d

IN2b

IN3/FB_IN

M_n

M_d

P_3n

÷

Optional

External

Feedback

IN3/FB_INb

P_3d

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

VDDO0

OUT0

OUT0b

SPI/

I²C

Multi

Synth

N_0n

N_0d

÷

t₀

÷R₀

A0/CSb

VDDO1

OUT1

OUT1b

Multi

Synth

N_1n

N_1d

t₁

t₂

t₃

÷R₁

÷R₂

÷R₃

NVM

VDDO2

OUT2

OUT2b

Multi

Synth

N_2n

N_2d

Multi

Synth

N_3n

N_3d

VDDO3

OUT3

OUT3b

Status

Monitors

Figure 7.2. Si5344 Block Diagram

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Si5345/44/42 Rev D Data Sheet

Detailed Block Diagrams

48-54MHz XTAL or

REFCLK

2

4

3

XA

XB

Si5342

OSC

IN_SEL[1:0]

P_REF

÷

IN0

IN0b

IN1

P_0n

÷

P_0d

P_1n

÷

DSPLL

IN1b

P_1d

PD

LPF

P_2n

÷

IN2

P_2d

IN2b

IN3/FB_IN

M_n

M_d

P_3n

÷

Optional

External

Feedback

IN3/FB_INb

P_3d

I2C_SEL

VDDO0

OUT0

OUT0b

Multi

Synth

N_0n

N_0d

SDA/SDIO

A1/SDO

SCLK

÷

t₀

t₁

SPI/

I²C

÷R₀

÷R₁

VDDO1

OUT1

OUT1b

Multi

Synth

N_1n

N_1d

A0/CSb

NVM

Status

Monitors

Figure 7.3. Si5342 Block Diagram

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Si5345/44/42 Rev D Data Sheet

Typical Operating Characteristics

8. Typical Operating Characteristics

The phase noise plots below were taken under the following conditions: V_DD= 1.8 V; V_DDA= 3.3 V; V_DDS= 3.3 V, 1.8 V; T_A= 25 °C.

Figure 8.1. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS

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Rev. 1.0 | 42

Si5345/44/42 Rev D Data Sheet

Typical Operating Characteristics

Figure 8.2. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS

Figure 8.3. Input = 25 MHz; Output = 155.52 MHz, 2.5 V LVDS

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

9. Pin Descriptions

Si5345

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

IN1

IN1b

IN_SEL0

IN_SEL1

RSVD

RSTb

X1

FINC

LOLb

3

VDD

4

OUT6

5

OUT6b

VDDO6

OUT5

6

7

XA

8

OUT5b

VDDO5

I2C_SEL

OUT4

GND

Pad

9

XB

10

11

X2

OEb

INTRb 12

OUT4b

VDDO4

OUT3

13

14

15

VDDA

IN2

IN2b

OUT3b

VDDO3

SCLK 16

Si5344 44QFN

Top View

Si5342 44QFN

Top View

1

2

33

32

31

30

29

28

27

26

25

24

23

1

2

33

IN1

IN1b

IN1

IN1b

INTRb

VDD

OUT2

INTRb

32

VDD

3

31

30

29

28

27

26

25

24

23

LOS1b

LOS0b

VDDS

IN_SEL0

4

OUT2b

VDDO2

LOS_XAXBb

LOLb

X1

XA

X1

XA

5

GND

Pad

GND

Pad

6

LOS_XAXBb

LOLb

XB

7

X2

VDDS

8

VDDA

OUT1

9

VDDA

IN2

VDDA

IN2

10

11

10

11

OUT1b

VDDO1

OUT1b

VDDO1

IN2b

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

Table 9.1. Si5345/44/42 Pin Descriptions

Pin Number

Si5344

Pin Type¹

Si5342

Pin Name

Function

Si5345

Inputs

XA

8

9

7

5

6

4

5

6

4

I

Crystal Input. Input pins for external crystal (XTAL). Alternatively

these pins can be driven with an external reference clock

(REFCLK). An internal register bit selects XTAL or REFCLK

mode. Default is XTAL mode.

XB

X1

XTAL Shield. Connect these pins directly to the XTAL ground

pins. X1, X2 and the XTAL ground pins should be separated from

the PCB ground plane. Refer to the Si5345/44/42 Family Refer-

ence Manual for layout guidelines. These pins should be left dis-

connected when connecting XA/XB pins to an external reference

clock (REFCLK).

X2

10

7

I

IN0

IN0b

63

64

1

43

44

1

43

44

1

I

Clock Inputs. These pins accept an input clock for synchronizing

the device. They support both differential and single-ended clock

signals. Refer to 3.7.6 Input Configuration and Terminations for

input termination options. These pins are high-impedance and

must be terminated externally. The negative side of the differen-

tial input must be grounded through a capacitor when accepting a

single-ended clock.

IN1

IN1b

2

IN2

14

15

61

10

11

41

10

11

41

IN2b

IN3/FB_IN

Clock Input 3/External Feedback Input. By default these pins

are used as the fourth clock input (IN3/IN3b). They can also be

used as the external feedback input (FB_IN/FB_INb) for the op-

tional zero delay mode. See 3.9.13 Zero Delay Mode for details

on the optional zero delay mode.

IN3b/FB_INb

62

42

I

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

Table 9.2. Si5345/44/42 Pin Descriptions

Pin Number

Si5344

Pin Type¹

Si5342

Pin Name

Function

Si5345

Outputs

OUT0

24

23

28

27

31

30

35

34

38

37

42

41

45

44

51

50

54

53

59

58

20

19

25

24

31

30

36

35

—

20

19

25

24

—

O

OUT0b

OUT1

OUT1b

OUT2

OUT2b

OUT3

OUT3b

OUT4

Output Clocks. These output clocks support a programmable

signal swing and common mode voltage. Desired output signal

format is configurable using register control. Termination recom-

mendations are provided in 3.9.3 Differential Output Terminations

and 3.9.4 LVCMOS Output Terminations. Unused outputs should

be left unconnected.

OUT4b

OUT5

OUT5b

OUT6

OUT6b

OUT7

OUT7b

OUT8

OUT8b

OUT9

OUT9b

Serial Interface

I²C Select². This pin selects the serial interface mode as I²C

(I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is internally pulled

up by a ~ 20 kΩ resistor to the voltage selected by the

IO_VDD_SEL register bit.

I2C_SEL

39

18

38

13

38

13

I

Serial Data Interface²

This is the bidirectional data pin (SDA) for the I²C mode, or the

bidirectional data pin (SDIO) in the 3-wire SPI mode, or the input

data pin (SDI) in 4-wire SPI mode. When in I²C mode, this pin

must be pulled-up using an external resistor of at least 1 kΩ. No

pull-up resistor is needed when is SPI mode. Tie low when un-

used.

SDA/SDIO

I/O

Address Select 1/Serial Data Output²

In I²C mode, this pin functions as the A1 address input pin and

does not have an internal pull-up or pull-down resistor. In 4-wire

SPI mode this is the serial data output (SDO) pin and drives high

to the voltage selected by the IO_VDD_SEL bit. Leave discon-

nected when unused.

A1/SDO

17

15

I/O

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

Pin Number

Si5344

Pin Type¹

Pin Name

Function

Si5345

Si5342

Serial Clock Input²

This pin functions as the serial clock input for both I²C and SPI

SCLK

16

14

16

14

I

modes. When in I²C mode, this pin must be pulled-up using an

external resistor of at least 1 kΩ. No pull-up resistor is needed

when in SPI mode. Tie high or low when unused.

Address Select 0/Chip Select²

This pin functions as the hardware controlled address A0 in I²C

mode. In SPI mode, this pin functions as the chip select input (ac-

tive low). This pin is internally pulled-up by a ~20 kΩ resistor and

can be left unconnected when not in use.

A0/CSb

19

16

I

Control/Status

Interrupt²

INTRb

12

33

17

33

17

O

This pin is asserted low when a change in device status has oc-

curred. It should be left unconnected when not in use.

Device Reset²

Active low input that performs power-on reset (POR) of the de-

vice. Resets all internal logic to a known state and forces the de-

vice registers to their default values. Clock outputs are disabled

during reset. This pin is internally pulled-up and can be left un-

connected when not in use.

RSTb

OEb

6

I

Output Enable²

11

47

—

12

—

27

12

—

27

I

This pin disables all outputs when held high. This pin is internally

pulled low and can be left unconnected when not in use.

Loss Of Lock (Si5345)²

O

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). It can be left unconnected when not in use.

LOLb

Loss Of Lock (Si5344/42)³

This output pin indicates when the DSPLL is locked (high) or out-

of-lock (low). It can be left unconnected when not in use.

Loss Of Signal for IN0³

LOS0b

LOS1b

—

28

30

31

35

36

28

O

This pin indicate a loss of clock at the IN0 pin when low.

Loss Of Signal for IN1³

This pin indicate a loss of clock at the IN1 pin when low.

Loss Of Signal for IN2³

LOS2b

This pin indicate a loss of clock at the IN2 pin when low.

Loss Of Signal for IN3³

LOS3b

This pin indicate a loss of clock at the IN3 pin when low.

Loss Of Signal on XA/XB Pins³

LOS_XAXBb

This pin indicates a loss of signal at the XA/XB pins when low.

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

Pin Number

Si5344

Pin Type¹

Pin Name

Function

Si5345

Si5342

Frequency Increment Pin²

This pin is used to step-up the output frequency of a selected out-

put. The affected output and its frequency change step size is

register configurable. This pin is internally pulled low and can be

left unconnected when not in use.

FINC

48

—

I

Frequency Decrement Pin²

This pin is used to step-down the output frequency of a selected

output. The affected output driver and its frequency change step

size is register configurable. This pin is internally pulled low and

can be left unconnected when not in use.

FDEC

25

—

I

Input Reference Select²

IN_SEL0

IN_SEL1

3

4

3

I

The IN_SEL[1:0] pins are used in manual pin controlled mode to

select the active clock input as shown in Table 3.1 Manual Input

Selection Using IN_SEL[1:0] Pins on page 8. These pins are in-

ternally pulled low.

37

5

—

20

21

55

56

Reserved

RSVD

These pins are connected to the die. Leave disconnected.

No Connect

NC

—

22

These pins are not connected to the die. Leave disconnected.

Power

32

46

60

—

13

21

32

39

40

8

21

32

39

40

8

P

Core Supply Voltage

The device operates from a 1.8 V supply. A 1.0 µF bypass capac-

itor should be placed very close to this pin. See the Si5345/44/42

Family Reference Manual for power supply filtering recommenda-

tions.

VDD

Core Supply Voltage 3.3 V

This core supply pin requires a 3.3 V power source. A 1 µF by-

pass capacitor should be placed very close to this pin. See the

Si5345/44/42 Family Reference Manual for power supply filtering

recommendations.

VDDA

VDDS

—

9

P

—

26

—

26

29

P

Status Output Voltage

The voltage on this pin determines VOL/VOH on the Si5342/44

LOL_A and LOL_B outputs. Connect to either 3.3 V or 1.8 V. A

1.0 µF bypass capacitor should be placed very close to this pin.

—

34

P

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Si5345/44/42 Rev D Data Sheet

Pin Descriptions

Pin Number

Pin Type¹

Pin Name

Function

Si5345

22

Si5344

18

Si5342

18

23

—

VDDO0

VDDO1

VDDO2

VDDO3

VDDO4

VDDO5

VDDO6

VDDO7

VDDO8

VDDO9

P

26

23

29

33

34

—

Output Clock Supply Voltage

36

—

Supply voltage (3.3 V, 2.5 V, 1.8 V) for OUTn, OUTn outputs. For

unused outputs, leave VDDO pins unconnected. An alternative

option is to connect the VDDO pin to a power supply and disable

the output driver to minimize current consumption.

40

—

43

—

49

—

52

—

57

—

Ground Pad

This pad provides connection to ground and must be connected

for proper operation. Use as many vias as practical, and keep the

via length to an internal ground plane as short as possible.

GND PAD

—

P

Note:

1. I = Input, O = Output, P = Power.

2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.

3. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.

4. Refer to the Family Reference Manual for more information on register setting names.

5. All status pins except I2C and SPI are push-pull.

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Si5345/44/42 Rev D Data Sheet

Package Outlines

10. Package Outlines

10.1 Si5345 9x9 mm 64-QFN Package Diagram

The following figure illustrates the package details for the Si5345. The table lists the values for the dimensions shown in the illustration.

Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)

Table 10.1. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

9.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

9.00 BSC

5.20

E

E2

L

5.10

0.30

—

5.30

0.50

0.10

0.08

0.10

0.40

aaa

bbb

ccc

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Si5345/44/42 Rev D Data Sheet

Package Outlines

10.2 Si5344 and Si5342 7x7 mm 44-QFN Package Diagram

The following figure illustrates the package details for the Si5344 and Si5342. The table lists the values for the dimensions shown in the

illustration.

Figure 10.2. 44-Pin Quad Flat No-Lead (QFN)

Table 10.2. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

7.00 BSC

5.20

D2

e

5.10

5.30

0.50 BSC

7.00 BSC

5.20

E

E2

L

5.10

0.30

—

5.30

0.50

0.10

0.08

0.10

0.40

aaa

bbb

ccc

ddd

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Si5345/44/42 Rev D Data Sheet

PCB Land Pattern

11. PCB Land Pattern

The following figure illustrates the PCB land pattern details for the devices. The table lists the values for the dimensions shown in the

illustration.

Si5345

Si5344 and Si5342

Figure 11.1. PCB Land Pattern

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Si5345/44/42 Rev D Data Sheet

PCB Land Pattern

Table 11.1. PCB Land Pattern Dimensions

Dimension

Si5345 (Max)

8.90

Si5344/42 (Max)

C1

C2

E

6.90

0.50

0.30

0.85

5.30

8.90

0.50

X1

Y1

X2

Y2

0.30

0.85

5.30

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication

Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.

4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Si5345/44/42 Rev D Data Sheet

Top Marking

12. Top Marking

Figure 12.1. Si5345/44/42 Top Marking

Table 12.1. Top Marking Explanation

Line

Characters

Description

Base part number and Device Grade for Any-frequency, Any-output, Jitter

Cleaning Clock (single PLL):

f = 5: 10-output Si5345: 64-QFN

f = 4: 4-output Si5344: 44-QFN

f = 2: 2-output Si5342: 44-QFN

1

Si534fg-

g = Device Grade (A, B, C, D). See 2. Ordering Guide for more information.

– = Dash character.

R = Product revision. (Refer to 2. Ordering Guide for latest revision).

xxxxx = Customer specific NVM sequence number. Optional NVM code as-

signed for custom, factory pre-programmed devices.

2

3

Rxxxxx-GM

Characters are not included for standard, factory default configured devices.

See 2. Ordering Guide for more information.

-GM = Package (QFN) and temperature range (–40 to +85 °C)

YYWW = Characters correspond to the year (YY) and work week (WW) of

package assembly.

YYWWTTTTTT

TTTTTT = Manufacturing trace code.

Pin 1 indicator; left-justified

Circle w/ 1.6 mm (64-QFN) or 1.4

mm (44-QFN) diameter

4

e4

Pb-free symbol; Center-Justified

TW

TW = Taiwan; Country of Origin (ISO Abbreviation)

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Si5345/44/42 Rev D Data Sheet

Device Errata

13. Device Errata

Log in or register at www.silabs.com to access the device errata document.

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Si5345/44/42 Rev D Data Sheet

Document Change List

14. Document Change List

14.1 Revision 1.0

July 15, 2016

• Initial release.

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Rev. 1.0 | 56

Table of Contents

1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1 Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 DSPLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.3 Fastlock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.4.1 Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.4.2 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.4.3 Lock Acquisition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.4.4 Locked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.4.5 Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.5 External Reference (XA/XB) . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.6 Digitally Controlled Oscillator (DCO) Mode . . . . . . . . . . . . . . . . . . . . 7

3.7 Inputs (IN0, IN1, IN2, IN3). . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . . 8

3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3) . . . . . . . . . . . . . . . . . . 8

3.7.3 Hitless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.7.4 Ramped Input Switching. . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.7.5 Glitchless Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.7.6 Input Configuration and Terminations . . . . . . . . . . . . . . . . . . . . . 9

3.7.7 Synchronizing to Gapped Input Clocks . . . . . . . . . . . . . . . . . . . . .10

3.8 Fault Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.8.1 Input LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.2 XA/XB LOS Detection . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.3 OOF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.8.3.1 Precision OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8.3.2 Fast OOF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8.4 LOL Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8.5 Interrupt Pin (INTRb) . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.9 Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.9.1 Output Crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.2 Output Signal Format. . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.9.3 Differential Output Terminations . . . . . . . . . . . . . . . . . . . . . . .15

3.9.4 LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . .15

3.9.5 Programmable Common Mode Voltage For Differential Outputs . . . . . . . . . . . .15

3.9.6 LVCMOS Output Impedance Selection . . . . . . . . . . . . . . . . . . . . .16

3.9.7 LVCMOS Output Signal Swing . . . . . . . . . . . . . . . . . . . . . . .16

3.9.8 LVCMOS Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . .16

3.9.9 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.9.10 Output Driver State When Disabled . . . . . . . . . . . . . . . . . . . . .16

3.9.11 Synchronous Output Disable Feature . . . . . . . . . . . . . . . . . . . . .16

3.9.12 Output Skew Control (Δt – Δt ). . . . . . . . . . . . . . . . . . . . . . .17

0

4

Table of Contents 57

3.9.13 Zero Delay Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.9.14 Output Divider (R) Synchronization. . . . . . . . . . . . . . . . . . . . . .18

3.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.11 In-Circuit Programming . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.12 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.13 Custom Factory Preprogrammed Parts . . . . . . . . . . . . . . . . . . . . .19

3.14 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory Pre-

programmed Devices

. . . . . . . . . . . . . . . . . . . . . . . . . . 19.

4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.2 High-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . .21

5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . 38

7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8. Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . 42

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.1 Si5345 9x9 mm 64-QFN Package Diagram . . . . . . . . . . . . . . . . . . .50

10.2 Si5344 and Si5342 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . .51

11. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table of Contents 58

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,

ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-

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names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

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型号：	Si5342
厂家：	SILICON
描述：	10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
文件：	总60页 (文件大小：1092K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si5342 [SILICON]

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