Si8244CB-C-IS1 [SILICON]
CLASS D AUDIO DRIVER WITH PRECISION DEAD-TIME GENERATOR; 精确死区发生器D类音频驱动
| 型号： | Si8244CB-C-IS1 |
| 厂家： | 
SILICON |
| 描述： | CLASS D AUDIO DRIVER WITH PRECISION DEAD-TIME GENERATOR |
| 文件： | 总30页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si824x
CLASS D AUDIO DRIVER WITH PRECISION DEAD-TIME GENERATOR
Features
Input to output isolation for low noise
(up to 2500 V)
Up to 8 MHz operation
Wide operating range
–40 to +125 °C
Transient immunity >45 kV/µs
RoHS-compliant
SOIC-16 narrow body
0.5 A peak output (Si8241)
4.0 A peak output (Si8244)
PWM input
High-precision linear programmable
dead-time generator
0.4 ns to 1 µs
High latchup immunity >100 V/ns
Up to 1500 Vrms output-output
isolation, supply voltage of ±750 V
Applications
Ordering Information:
Class D audio amplifiers
See page 25.
Description
Pin Assignments
The Si824x isolated driver family combines two isolated drivers in a single
package. The Si8241/44 are high-side/low-side drivers specifically targeted at
high-power (>30 W) audio applications. Versions with peak output currents of
0.5 A (Si8241) and 4.0 A (Si8244) are available. All drivers operate with a
maximum supply voltage of 24 V.
SOIC-16 (Narrow)
1
16
15
14
13
PWM
NC
VDDA
VOA
GNDA
NC
Based on Silicon Labs' proprietary isolation technology, the Si824x audio drivers
incorporate input-to-output and output-to-output isolation, which enables level-
translation of signals without additional external circuits as well as use of bipolar
supply voltage up to ±750 V. The Si824x audio drivers feature an integrated dead-
time generator that provides highly precise control for achieving optimal THD.
These products also have overlap protection that safeguards against shoot-
through current damage. The CMOS-based design also provides robust immunity
from latch-up and high-voltage transients. The extremely low propagation delays
enable faster modulation frequencies for an enhanced audio experience. The TTL
level compatible inputs with >400 mV hysteresis are available in PWM input
configuration; other options include UVLO levels of 8 V or 10 V. These products
are available in narrow body SOIC packages.
2
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
Si8241/44
12
11
10
9
NC
VDDB
VOB
GNDB
NC
VDDI
Functional Block Diagram
Patents Pending
PWM
VDDA
VOA
DT
GNDA
Programmable Dead
Time, Control Gating
VDDI
UVLO
VDDB
DISABLE
GNDI
VOB
GNDB
Si8241/44
Rev. 0.2 2/11
Copyright © 2011 by Silicon Laboratories
Si824x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si824x
2
Rev. 0.2
Si824x
TABLE OF CONTENTS
Section
Page
1. Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. Typical Performance Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Typical Performance Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . .17
3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . .22
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1. Class D Digital Audio Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Rev. 0.2
3
Si824x
1. Top-Level Block Diagram
VDDI
VDDA
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8241/44
Figure 1. Si8241/44 Single-Input High-Side/Low-Side Isolated Drivers
4
Rev. 0.2
Si824x
2. Electrical Specifications
Table 1. Electrical Characteristics1
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
DC Specifications
Input-Side Power Supply
Voltage
VDDI
4.5
6.5
—
—
5.5
24
V
V
Voltage between VDDA and
VDDA, VDDB GNDA, and VDDB and GNDB
(See “6. Ordering Guide” )
Driver Supply Voltage
Input Supply Quiescent
Current
IDDI(Q)
Si8241/44
—
—
2
3
mA
mA
IDDA(Q),
IDDB(Q)
Output Supply Quiescent
Current
Current per channel
—
3.0
IDDI
IDDO
IPWM
IDISABLE
VIH
PWM freq = 500 kHz
PWM freq = 500 kHz
—
—
2.5
3.6
—
—
—
mA
mA
µA dc
µA dc
V
Input Supply Active Current
Output Supply Active Current
Input Pin Leakage Current
Input Pin Leakage Current
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
–10
–10
2.0
—
+10
+10
—
—
—
VIL
—
0.8
—
V
VIHYST
400
450
mV
(VDDA
/VDDB)
— 0.04
VOAH,
VOBH
IOA, IOB = –1 mA
—
—
V
Logic High Output Voltage
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
Si8241, Figure 2
Si8244, Figure 2
Si8241, Figure 3
Si8244, Figure 3
Si8241
—
—
—
—
—
—
—
—
—
—
0.5
4.0
0.25
2.0
5.0
1.0
15
0.04
—
V
A
A
A
A
IOA(SCL),
IOB(SCL)
Output Short-Circuit Pulsed
Sink Current
—
—
IOA(SCH),
IOB(SCH)
Output Short-Circuit Pulsed
Source Current
—
—
RON(SINK)
Output Sink Resistance
Si8244
—
Si8241
—
RON(SOURCE)
Output Source Resistance
Si8244
2.7
—
Notes:
1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices.
2. The largest RDT resistor that can be used is 220 k.
Rev. 0.2
5
Si824x
Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
VDDIUV+
VDDIUV–
VDDIHYS
VDDAUV+
Test Conditions
VDDI rising
Min
3.60
3.30
—
Typ
4.0
Max
4.45
4.15
—
Units
V
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
VDDI falling
3.70
250
V
mV
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB rising
VDDBUV+
See Figure 34 on page 21.
See Figure 35 on page 21.
7.50
9.60
8.60
11.1
9.40
12.2
V
V
8 V Threshold
10 V Threshold
VDDAUV–
VDDBUV–
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB falling
See Figure 34 on page 21.
See Figure 35 on page 21.
7.20
9.40
8.10
10.1
8.70
10.9
V
V
8 V Threshold
10 V Threshold
VDDAHYS
VDDBHYS
,
VDDA, VDDB
Lockout Hysteresis
UVLO voltage = 8 V
UVLO voltage = 10 V
—
—
600
—
—
mV
mV
VDDAHYS
VDDBHYS
,
VDDA, VDDB
Lockout Hysteresis
1000
AC Specifications
Minimum Pulse Width
—
—
—
10
25
—
60
ns
ns
ns
tPHL, tPLH
PWD
CL = 1 nF
Propagation Delay
Pulse Width Distortion
1.0
5.60
|t
- t
|
PLH PHL
Programmed Dead Time2
DT
See Figures 36 and 37
CL = 1 nF (Si8241)
CL = 1 nF (Si8244)
0.4
—
—
—
—
1000
20
ns
ns
ns
tR,tF
Output Rise and Fall Time
—
12
Shutdown Time from
Disable True
tSD
—
—
—
25
—
—
5
60
60
7
ns
ns
µs
Restart Time from
Disable False
tRESTART
tSTART
CMTI
Time from VDD_ = VDD_UV+
to VOA, VOB = VIA, VIB
Device Start-up Time
Common Mode
Transient Immunity
VIA, VIB, PWM = VDDI or 0 V
45
—
kV/µs
Notes:
1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices.
2. The largest RDT resistor that can be used is 220 k.
6
Rev. 0.2
Si824x
2.1. Test Circuits
Figures 2 and 3 depict sink current and source current test circuits.
VDDA = VDDB = 15 V
VDDI
(5 V)
VDD
OUT_
10
IN_
Si824x
INPUT
SCHOTTKY
+
5 V
VSS
100 µF
_
1 µF
1 µF
CER
10 µF
EL
Measure
50 ns
RSNS
0.1
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 2. Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
(5 V)
VDD
OUT_
10
IN_
Si824x
INPUT
SCHOTTKY
1 µF
+
VSS
100 µF
5 V
_
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 3. Source Current Test Circuit
Rev. 0.2
7
Si824x
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.6
–0.6
–0.5
—
Typ
—
—
—
—
—
—
—
—
—
—
Max
+150
+125
6.0
Units
°C
2
Storage Temperature
T
STG
Ambient Temperature under Bias
Input-side Supply Voltage
T
°C
A
VDDI
VDDA, VDDB
VIN
V
Driver-side Supply Voltage
30
V
Voltage on any Pin with respect to Ground
Output Drive Current per Channel
Lead Solder Temperature (10 sec)
VDD + 0.5
10
V
I
mA
°C
O
—
260
3
Latchup Immunity
—
100
V/ns
Maximum Isolation (Input to Output)
Maximum Isolation (Output to Output)
Notes:
—
2500
1500
V
V
RMS
RMS
—
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
3. Latchup immunity specification is for slew rate applied across GNDI and GNDA or GNDB.
Table 3. Regulatory Information*
CSA
The Si824x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 V
60950-1: Up to 300 V
VDE
reinforced insulation working voltage; up to 600 V
reinforced insulation working voltage; up to 600 V
basic insulation working voltage.
basic insulation working voltage.
RMS
RMS
RMS
RMS
The Si824x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 V
for basic insulation working voltage.
peak
UL
The Si824x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 V isolation voltage for basic protection.
RMS
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "6.Ordering Guide" on page 25.
8
Rev. 0.2
Si824x
Table 4. Insulation and Safety-Related Specifications
Value
Parameter
Symbol
Test Condition
Unit
NBSOIC-16
2.5 kV
RMS
Nominal Air Gap
(Clearance)
L(1O1)
L(1O2)
4.01
4.01
mm
mm
mm
1
1
Nominal External Tracking (Creepage)
Minimum Internal Gap
(Internal Clearance)
0.011
Tracking Resistance
(Proof Tracking Index)
PTI
ED
IEC60112
f = 1 MHz
600
V
mm
0.019
Erosion Depth
Resistance
12
R
10
IO
2
(Input-Output)
Capacitance
(Input-Output)
C
1.4
4.0
pF
pF
IO
2
3
C
Input Capacitance
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Package Outline:
16-Pin Narrow Body SOIC” . VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16.
UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance
and creepage limits as 3.9 mm minimum for the NB SOIC 16.
2. To determine resistance and capacitance, the Si824x is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 5. IEC 60664-1 (VDE 0884 Part 2) Ratings
Specification
Parameter
Test Conditions
NB SOIC-16
Basic Isolation Group
Material Group
I
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
I-IV
I-III
I-II
I-II
RMS
RMS
RMS
RMS
Installation Classification
Rev. 0.2
9
Si824x
Table 6. IEC 60747-5-2 Insulation Characteristics*
Characteristic
NB SOIC-16
560
Parameter
Symbol
Test Condition
Unit
V
V peak
Maximum Working Insulation Voltage
IORM
Method b1
(V
x 1.875 = V
100%
,
PR
IORM
V
1050
V peak
V peak
Input to Output Test Voltage
PR
Production Test, t = 1 sec,
Partial Discharge < 5 pC)
m
V
t = 60 sec
4000
2
Transient Overvoltage
IOTM
Pollution Degree
(DIN VDE 0110, Table 1)
Insulation Resistance at T ,
9
S
R
>10
S
V
= 500 V
IO
*Note: Maintenance of the safety data is ensured by protective circuits. The Si824x provides a climate classification of
40/125/21.
Table 7. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
NB SOIC-16
Unit
TS
150
°C
Case Temperature
JA = 105 °C/W (NB SOIC-16),
VDDI = 5.5 V,
IS
50
mA
W
Safety Input Current
VDDA = VDDB= 24 V,
TJ = 150 °C, TA = 25 °C
Device Power Dissipation2
PD
1.2
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 4.
2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle
square wave.
10
Rev. 0.2
Si824x
Table 8. Thermal Characteristics
Parameter
NB
SOIC-16
Symbol
Unit
IC Junction-to-Air
Thermal Resistance
105
°C/W
JA
60
50
40
30
20
10
VDDI = 5.5 V
VDDA, VDDB = 24 V
0
0
50
100
150
200
Case Temperature (ºC)
Figure 4. NB SOIC-16, Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per DIN EN 60747-5-2
Rev. 0.2
11
Si824x
3. Functional Description
The operation of an Si824x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si824x channel is shown in
Figure 5.
Transmitter
Receiver
Driver
VDD
RF Oscillator
Modulator
Semiconductor-
Based Isolation
Barrier
Dead
Time
Generator
B
Demodulator
A
0.5 to 4 A
peak
Gnd
Figure 5. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 6 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 6. Modulation Scheme
12
Rev. 0.2
Si824x
3.1. Typical Performance Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figures 7 through 18 are for information purposes only. Refer
to Table 1 on page 5 for actual specification limits.
10
7
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
8
6
4
2
0
1MHz
6
5
4
3
2
1
0
Tfall
500kHz
100kHz
Trise
50 kHz
VDD=12V, 25°C
CL = 100 pF
9
14
19
24
VDDA Supply Voltage (V)
9
12
15
18
21
24
VDDA Supply (V)
Figure 10. Supply Current vs. Supply Voltage
Figure 7. Rise/Fall Time vs. Supply Voltage
30
25
5
4
H-L
3
20
VDDA = 15V,
f = 250kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
2
1
L-H
15
VDD=12V, 25°C
CL = 100 pF
-50
0
50
Temperature (°C)
100
10
9
12
15
18
21
24
VDDA Supply (V)
Figure 11. Supply Current vs. Temperature
Figure 8. Propagation Delay vs. Supply Voltage
40
35
4
Trise
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
30
3.5
3
25
1MHz
20
15
10
5
Tfall
500kHz
100kHz
2.5
2
1.5
1
50 kHz
VDD=12V, 25°C
0
0.0
0.5
1.0
Load (nF)
1.5
2.0
9
14
19
24
VDDA Supply Voltage (V)
Figure 12. Rise/Fall Time vs. Load
Figure 9. Supply Current vs. Supply Voltage
Rev. 0.2
13
Si824x
4
3.75
3.5
3.25
3
50
45
40
35
30
25
20
15
L-H
H-L
2.75
2.5
2.25
2
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
0.0
0.5
1.0
Load (nF)
1.5
2.0
10
15
20
25
Supply Voltage (V)
Figure 13. Propagation Delay vs. Load
Figure 16. Output Source Current vs. Supply
Voltage
30
7
6.75
6.5
25
20
15
10
L-H
6.25
6
5.75
5.5
H-L
5.25
5
4.75
4.5
VDD=12V, Load = 200pF
4.25
4
VDD=12V, Vout=5V
-10 20
-40
-20
0
20
40
60
80
100
120
-40
50
80
110
Temperature (°C)
Temperature (°C)
Figure 14. Propagation Delay vs. Temperature
Figure 17. Output Sink Current vs. Temperature
9
8
7
6
5
3.5
3.25
3
2.75
2.5
VDD=12V, Vout=5V
2.25
4
VDD=12V, Vout=VDD-5V
10
12
14
16
18
20
22
24
2
-40
-10
20
50
80
110
Supply Voltage (V)
Temperature (°C)
Figure 15. Output Sink Current vs. Supply
Voltage
Figure 18. Output Source Current vs.
Temperature
14
Rev. 0.2
Si824x
3.2. Typical Performance Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figures 19 through 30 are for information purposes only. Refer
to Table 1 on page 5 for actual specification limits.
10
14
12
10
8
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
1MHz
8
6
4
2
0
Tfall
500kHz
6
Trise
100kHz
50 kHz
4
2
0
9
14
19
24
VDD=12V, 25°C
CL = 100 pF
VDDA Supply Voltage (V)
Figure 22. Supply Current vs. Supply Voltage
9
12
15
18
21
24
VDDA Supply (V)
10
8
Figure 19. Rise/Fall Time vs. Supply Voltage
30
6
VDDA = 15V,
f = 250kHz, CL = 0 pF
4
25
Duty Cycle = 50%
2 Channels Switching
2
L-H
0
20
-50
0
50
100
Temperature (°C)
H-L
15
Figure 23. Supply Current vs. Temperature
VDD=12V, 25°C
CL = 100 pF
10
40
35
9
12
15
18
21
24
VDDA Supply (V)
Trise
30
Figure 20. Propagation Delay vs. Supply
Voltage
25
20
15
10
5
Tfall
14
12
10
8
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
1MHz
VDD=12V, 25°C
0
500kHz
0
1
2
3
4
5
6
7
8
9
10
6
Load (nF)
4
100kHz
50 kHz
2
Figure 24. Rise/Fall Time vs. Load
0
9
14
19
24
VDDA Supply Voltage (V)
Figure 21. Supply Current vs. Supply Voltage
Rev. 0.2
15
Si824x
4
3.75
3.5
3.25
3
50
45
40
35
30
25
20
15
10
H-L
L-H
2.75
2.5
2.25
2
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
15
20
25
0
1
2
3
4
5
6
7
8
9
10
Supply Voltage (V)
Load (nF)
Figure 28. Output Source Current vs. Supply
Voltage
Figure 25. Propagation Delay vs. Load
30
7
6.75
6.5
H-L
25
20
15
10
6.25
6
L-H
5.75
5.5
5.25
5
4.75
4.5
4.25
VDD=12V, Load = 200pF
VDD=12V, Vout=5V
4
-40
-20
0
20
40
60
80
100
120
-40
-10
20
50
80
110
Temperature (°C)
Temperature (°C)
Figure 29. Output Sink Current vs. Temperature
Figure 26. Propagation Delay vs. Temperature
3.5
3.25
3
9
8
7
6
5
2.75
2.5
2.25
VDD=12V, Vout=5V
VDD=12V, Vout=VDD-5V
4
2
10
12
14
16
18
20
22
24
-40
-10
20
50
80
110
Supply Voltage (V)
Temperature (°C)
Figure 27. Output Sink Current vs. Supply
Voltage
Figure 30. Output Source Current vs.
Temperature
16
Rev. 0.2
Si824x
3.3. Family Overview and Logic Operation During Startup
The Si824x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
3.3.1. Products
Table 9 shows the configuration and functional overview for each product in this family.
Table 9. Si824x Family Overview
Part Number
Configuration
UVLO Voltage
Programmable
Dead Time
Inputs
Peak Output
Current (A)
Si8241
Si8244
High-Side/Low-Side
High-Side/Low-Side
8 V/10 V
8 V/10 V
PWM
PWM
0.5
4.0
3.3.2. Device Behavior
Table 10 contains truth tables for the Si8241/4 families.
Table 10. Si824x Family Truth Table*
Si8241/4 (PWM Input High-Side/Low-Side) Truth Table
Output
PWM Input
VDDI State Disable
Notes
VOA
VOB
Output transition occurs after internal dead time
expires.
H
L
Powered
Powered
L
L
H
L
Output transition occurs after internal dead time
expires.
L
H
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
Unpowered
Powered
X
H
L
L
L
L
Device is disabled.
*Note: This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see
"3.7.2.Undervoltage Lockout" on page 20 for more information.
Rev. 0.2
17
Si824x
3.4. Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these
supplies must be placed as close to the VDD and GND pins of the Si824x as possible. The optimum values for
these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low
effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
3.5. Power Dissipation Considerations
Proper system design must assure that the Si824x operates within safe thermal limits across the entire load range.
The Si824x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load. Equation 1 shows total Si824x power dissipation. In a non-overlapping
system, such as a high-side/low-side driver, n = 1.
PD = V
I
DDI DDI + 2V I
DDO QOUT + CintVDDO2F + 2nCLVDDO2F
where:
PD is the total Si824x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IQOUT is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (4.5 to 5.5 V)
VDDO is the driver-side supply voltage (10 to 24 V)
F is the switching frequency (Hz)
n is the overlap constant (max value = 2)
Equation 1.
The maximum power dissipation allowable for the Si824x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2:
T
jmax – TA
---------------------------
PDmax
where:
ja
PDmax = Maximum Si824x power dissipation (W)
Tjmax = Si824x maximum junction temperature (150 °C)
TA = Ambient temperature (°C)
ja = Si824x junction-to-air thermal resistance (105 °C/W)
F = Si824x switching frequency (Hz)
Equation 2.
Substituting values for P
T
, T , and into Equation 2 results in a maximum allowable total power
Dmax jmax A ja
dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 5 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and
Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
1.4 10–3
–11
--------------------------
CL(MAX)
=
– 7.5 10
F
Equation 3.
1.4 10–3
–10
--------------------------
CL(MAX)
=
– 3.7 10
F
Equation 4.
18
Rev. 0.2
Si824x
Equation 1 and Equation 2 are graphed in Figure 31 where the points along the load line represent the package
dissipation-limited value of CL for the corresponding switching frequency.
1 6 ,0 0 0
0 .5 A D rive r (p F )
1 4 ,0 0 0
4 A D rive r (p F )
1 2 ,0 0 0
1 0 ,0 0 0
8 ,0 0 0
T = 25 °C
a
6 ,0 0 0
4 ,0 0 0
2 ,0 0 0
0
F re q u e n c y (K h z)
Figure 31. Max Load vs. Switching Frequency
20
15
10
5
CL = 1000pF
CL = 500pF
CL = 200pF
VDD=15V, 25°C
0
0
200
400
600
800
1000
Switching Frequency (kHz)
Figure 32. Switching Frequency vs. Load Current
Rev. 0.2
19
Si824x
3.6. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si824x VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si824x as close to the device it is driving as possible.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
3.7. Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 33, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low
when input side power supply (VDDI) is not present.
3.7.1. Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period
tSTART. Following this, the outputs follow the states of inputs VIA and VIB.
3.7.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have
their own undervoltage lockout monitors.
The Si824x input side enters UVLO when VDDI < VDDI
, and exits UVLO when VDDI > VDDI
. The driver
UV+
UV–
outputs, VOA and VOB, remain low when the input side of the Si824x is in UVLO and their respective VDD supply
(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA
unconditionally enters UVLO when VDDA falls below VDDA
and exits UVLO when VDDA rises above
UV–
VDDA
.
UV+
UVLO+
VDDHYS
UVLO-
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
PWM
DISABLE
tSD
tRESTART
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
VOA
Figure 33. Device Behavior during Normal Operation and Shutdown
20
Rev. 0.2
Si824x
3.7.3. Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 34
and 35, upon power up, the Si824x is maintained in UVLO until VDD rises above VDD . During power down, the
UV+
Si824x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD
– VDD
).
UV+
HYS
VDDUV+ (Typ)
VDDUV+ (Typ)
8.5
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5
6.0
6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Supply Voltage (VDD - VSS) (V)
Supply Voltage (VDD - VSS) (V)
Figure 35. Si824x UVLO Response (10 V)
Figure 34. Si824x UVLO Response (8 V)
3.7.4. Control Inputs
PWM inputs are high-true, TTL level-compatible logic inputs. VOA is high and VOB is low when the PWM input is
high, and VOA is low and VOB is high when the PWM input is low.
3.7.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of input.
Device operation terminates within tSD after DISABLE = V and resumes within tRESTART after DISABLE = V .
IH
IL
The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). The DISABLE input
is typically connected to external protection circuitry to unconditionally halt driver operation in the event of a fault.
Rev. 0.2
21
Si824x
3.8. Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8241/4) include programmable overlap protection to prevent outputs VOA and
VOB from being high at the same time. These devices also include programmable dead time, which adds a user-
programmable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions,
even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT)
connected from the DT input to ground per Equation 5. Minimum dead time (approximately 400 ps) can be
achieved by connecting the DT pin to VDDI. Note that dead time accuracy is limited by the resistor’s (R
)
DT
tolerance and temperature coefficient. See Figures 36 and 37 for additional information about dead time operation.
DT 10 RDT
where:
DT= dead time (ns)
and
RDT= dead time programming resistor (k
Equation 5.
1000
900
800
700
600
500
400
300
200
100
0
0
20
40
60
80
100
Dead-time Resistance (kꢀ)
Figure 36. Dead Time vs.Resistance (RDT)
100
90
80
70
60
50
40
30
20
10
0
RDT = 10k
RDT = 6k
RDT = 5k
RDT = 4k
RDT = 3k
RDT = 2k
RDT = 1k
RDT = 0
-40
-20
0
20
40
60
80
100 120
Temperature (°C)
Figure 37. Dead Time vs.Temperature
22
Rev. 0.2
Si824x
4. Applications
The following examples illustrate typical circuit configurations using the Si824x.
4.1. Class D Digital Audio Driver
Figures 38 and 39 show the Si8241/4 controlled by a single PWM signal. Supply can be unipolar (0 to 1500 V) or
bipolar (± 750 V).
D1
VDD2
C2
VDDI
1 µF
VDDI
C1
1uF
1500 V max
VDDA
GNDI
PWM
CB
Q1
PWMOUT
CONTROLLER
I/O
VOA
GNDA
DT
RDT
Si8241/4
VDDB
VDDB
C3
10uF
DISABLE
GNDB
VOB
Q2
Figure 38. Si824x in Half-Bridge Audio Application
D1
VDD2
C2
VDDI
1 µF
VDDI
C1
1uF
+750 V max
VDDA
GNDI
PWM
CB
Q1
PWMOUT
CONTROLLER
I/O
VOA
GNDA
DT
RDT
Si8241/4
VDDB
VDDB
C3
10uF
DISABLE
GNDB
VOB
Q2
-750 V max
Figure 39. Si824x in Half-Bridge Audio Application
D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has
a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of
the Si824x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side supplies must be
between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will depend on the CB
cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the Si824x should be
located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors be
used to reduce high frequency noise and maximize performance. The D1 diode should be a fast-recovery diode; it
should be able to withstand the maximum high voltage (e.g. 1500 V) and be low-loss. See “AN486: High-Side
Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems” for more details in selecting the bootstrap
cap (CB) and diode (D1).
Rev. 0.2
23
Si824x
5. Pin Descriptions
SOIC-16 (Narrow)
1
16
15
14
13
PWM
NC
VDDA
VOA
GNDA
NC
2
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
Si8241/44
12
11
10
9
NC
VDDB
VOB
GNDB
NC
VDDI
Table 11. Si8241/44 PWM Input HS/LS Isolated Driver (SOIC-16)
Description
Pin
1
Name
PWM PWM input.
NC No connection.
2
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when con-
nected to VDDI or left open (see "3.8.Programmable Dead Time and Overlap Protection" on
page 22).
7
NC
No connection.
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for Driver B.
9
10
11
12
13
14
15
16
VOB Driver B output (low-side driver).
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output (high-side driver).
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
24
Rev. 0.2
Si824x
6. Ordering Guide
The currently available OPNs are listed in Table 12.
Table 12. Ordering Part Numbers
Isolation
Ordering Part
Number (OPN)
Drive
Strength
UVLO
Rating
Voltage (Input to
Output)
Input Type
Package
Output
Si8241BB-B-IS1
Si8241CB-B-IS1
Si8244BB-C-IS1
Si8244CB-C-IS1
PWM
PWM
PWM
PWM
NB SOIC-16
NB SOIC-16
NB SOIC-16
NB SOIC-16
8 V
0.5 A
4 A
10 V
2.5 kVrms
8 V
High-Side/Low-Side
10 V
Note: All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for narrow-body SOIC-16 packages with peak reflow temperatures of 260 °C
according to the JEDEC industry standard classifications and peak solder temperatures. Tape and reel options are
specified by adding an “R” suffix to the ordering part number.
Rev. 0.2
25
Si824x
7. Package Outline: 16-Pin Narrow Body SOIC
Figure 40 illustrates the package details for the Si824x in a 16-pin narrow-body SOIC (SO-16). Table 13 lists the
values for the dimensions shown in the illustration.
Figure 40. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 13. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
Dimension
Min
Max
A
L
0.40
1.27
A1
0.10
1.25
0.31
0.17
L2
0.25 BSC
A2
h
0.25
0°
0.50
8°
b
0.51
0.25
θ
c
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
D
E
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E1
e
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
26
Rev. 0.2
Si824x
8. Land Pattern: 16-Pin Narrow Body SOIC
Figure 41 illustrates the recommended land pattern details for the Si824x in a 16-pin narrow-body SOIC. Table 14
lists the values for the dimensions shown in the illustration.
Figure 41. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 14. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 0.2
27
Si824x
9. Top Marking: 16-Pin Narrow Body SOIC
Si824YUV
YYWWTTTTTT
e4
Figure 42. 16-Pin Narrow Body SOIC Top Marking
Table 15. 16-Pin Narrow Body SOIC Top Marking Explanations
Si824 = ISOdriver product series
Y = Peak output current
1 = 0.5 A
Base Part Number
Ordering Options
4 = 4.0 A
Line 1 Marking:
Line 2 Marking:
U = UVLO level
B = 8 V; C = 10 V
V = Isolation rating
B = 2.5 kV
See Ordering Guide for more
information.
YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the
year and workweek of the mold date.
Manufacturing Code from Assembly Purchase Order
form.
TTTTTT = Mfg Code
28
Rev. 0.2
Si824x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Deleted Table 3.
Added Tables 3 through 8.
Added Figure 4.
Updated common-mode transient immunity
specification throughout.
Rev. 0.2
29
Si824x
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
The sale of this product contains no licenses to Power-One’s intellectual property. Contact Power-One, Inc. for appropriate licenses.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
30
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