Si8274GB1-IM_技术文档

Si827x Data Sheet

4 Amp ISOdriver with High Transient (dV/dt) Immunity

KEY FEATURES

The Si827x isolators are ideal for driving power switches used in a wide variety of power

supply, inverter, and motor control applications. The Si827x isolated gate drivers utilize

Silicon Laboratories' proprietary silicon isolation technology, supporting up to 2.5

kVRMS withstand voltage per UL1577 and VDE0884. This technology enables industry

leading common-mode transient immunity (CMTI), tight timing specifications, reduced

variation with temperature and age, better part-to-part matching, and extremely high reli-

ability. It also offers unique features such as separate pull-up/down outputs, driver shut-

down on UVLO fault, and precise dead time programmability. The Si827x series offers

longer service life and dramatically higher reliability compared to opto-coupled gate driv-

ers.

• Single, dual, or high-side/low-side drivers

• Single PWM or dual digital inputs

• High dV/dt immunity:

• 200 kV/µs CMTI

• 400 kV/µs Latch-up

• Separate pull-up/down outputs for slew rate

control

• Wide supply range:

• Input supply: 2.5–5.5 V

• Driver supply: 4.2–30 V

• Very low jitter of 200 ps p-p

• 60 ns propagation delay (max)

• Dedicated enable pin

The Si827x drivers utilize Silicon Labs' proprietary silicon isolation technology, which

provides up to 2.5 kVRMS withstand voltage per UL1577 and fast 60 ns propagation

times. Driver outputs can be grounded to the same or separate grounds or connected to

a positive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis

are available in individual control input (Si8271/2/3/5) or PWM input (Si8274) configura-

tions. High integration, low propagation delay, small installed size, flexibility, and cost-

effectiveness make the Si827x family ideal for a wide range of isolated MOSFET/IGBT

and SiC or GaN FET gate drive applications.

• Silicon Labs’ high performance isolation

technology:

• Industry leading noise immunity

• High speed, low latency and skew

• Best reliability available

Applications:

• Compact packages:

• 8-pin SOIC

• Switch-mode Power Supplies

• Solar Power Inverters

• 16-pin SOIC

• 5 x 5 mm LGA-14

• Motor control and drives

• Uninterruptible Power Supplies

• High-Power Class D Amplifiers

• Industrial temperature range:

• –40 to 125 °C

• AEC-Q100 Qualified

Safety Regulatory Approvals (Pending):

• UL 1577 recognized

• Up to 2500 Vrms for 1 minute

• CSA component notice 5A approval

• IEC 60950-1 (reinforced insulation)

• VDE certification conformity

• VDE 0884 Part 10

• CQC certification approval

• GB4943.1

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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Preliminary Rev. 0.5

Si827x Data Sheet

Ordering Guide

1. Ordering Guide

Table 1.1. Si827x Ordering Guide

Ordering

Inputs

Driver

Output

UVLO

Integrated

Deglitcher

Dead Time

Adjustable

Range

Low

Jitter

Package

Isolation

Rating

Part Number

Configuration

Products Available Now

Si8271AB-IS

Si8271BB-IS

Si8271DB-IS

Si8271GB-IS

Si8273AB-IS1

Si8273ABD-IS1

Si8273AB-IM

VI

Single

HS/LS

5

8

N

Y

N

N/A

Y

N

Y

SOIC-8 NB

SOIC-16 NB

2.5 kVrms

VI

12

3

VI

VIA/VIB

5

5x5mm

LGA-14

Si8273ABD-IM

VIA/VIB

HS/LS

5

Y

N/A

N

5x5mm

LGA-14

2.5 kVrms

Si8273DB-IS1

Si8273DBD-IS1

Si8273GB-IS1

Si8273GBD-IS1

Si8273BB-IS1

Si8273BBD-IS1

Si8274AB1-IS1

Si8274AB4D-IS1

Si8274AB1-IM

VIA/VIB

PWM

HS/LS

12

3

N

Y

N

Y

N

Y

N

Y

N

N/A

Y

N

Y

N

Y

N

Y

N

Y

SOIC-16 NB

2.5 kVrms

N/A

3

N/A

8

N/A

8

N/A

5

10-200

20-700

10-200

PWM

5

PWM

5

5x5mm

LGA-14

Si8274AB4D-IM

PWM

HS/LS

5

Y

20-700

N

5x5mm

LGA-14

2.5 kVrms

Si8274BB1-IS1

Si8274DB1-IS1

Si8274GB1-IS1

Si8274GB4D-IS1

Si8274GB1-IM

PWM

HS/LS

8

12

3

N

Y

N

10-200

20-700

10-200

Y

N

Y

SOIC-16 NB

2.5 kVrms

3

5x5mm

LGA-14

Si8274GB4D-IM

PWM

HS/LS

3

Y

20-700

N

5x5mm

LGA-14

2.5 kVrms

Si8275GB-IS1

Si8275GBD-IS1

Si8275AB-IM

VIA/VIB

Dual

3

5

N

Y

N

N/A

Y

N

Y

SOIC-16 NB

2.5 kVrms

5x5mm

LGA-14

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Preliminary Rev. 0.5 | 1

Si827x Data Sheet

Ordering Guide

Ordering

Inputs

Driver

Output

UVLO

Integrated

Deglitcher

Dead Time

Adjustable

Range

Low

Jitter

Package

Isolation

Rating

Part Number

Configuration

Si8275ABD-IM

VIA/VIB

Dual

5

Y

N/A

N

5x5mm

LGA-14

2.5 kVrms

Contact Silicon Labs Sales for These Options

Si8271ABD-IS

Si8271BBD-IS

Si8271DBD-IS

Si8271GBD-IS

Si8273BB-IS1

Si8273BBD-IS1

Si8274BB4D-IS1

Si8274DB4D-IS1

Si8275AB-IS1

Si8275ABD-IS1

Si8275BB-IS1

Si8275BBD-IS1

Si8275DB-IS1

Si8275DBD-IS1

Si8275BB-IM

VI

Single

HS/LS

Dual

5

8

Y

N

Y

N

Y

N

Y

N

Y

N

N/A

N

Y

N

Y

N

Y

N

Y

N

Y

SOIC-8 NB

SOIC-16 NB

2.5 kVrms

VI

12

3

N/A

VI

N/A

VIA/VIB

PWM

8

N/A

8

N/A

8

20-700

N/A

PWM

12

5

VIA/VIB

Dual

5

N/A

Dual

8

N/A

Dual

8

N/A

Dual

12

8

N/A

Dual

N/A

Dual

N/A

5x5mm

LGA-14

Si8275BBD-IM

Si8275DB-IM

Si8275DBD-IM

Si8275GB-IM

Si8275GBD-IM

Si8275DA-IM

Si8275DAD-IM

VIA/VIB

Dual

8

12

3

Y

N

Y

N

Y

N

Y

N/A

N

Y

N

Y

N

Y

N

5x5mm

LGA-14

2.5 kVrms

1 kVrms

5x5mm

LGA-14

5x5mm

LGA-14

5x5mm

LGA-14

3

5x5mm

LGA-14

12

5x5mm

LGA-14

5x5mm

LGA-14

1 kVrms

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Preliminary Rev. 0.5 | 2

Si827x Data Sheet

System Overview

2. System Overview

VDD

VI

VDDI

VO+

VO-

VDDI

UVLO

EN

GNDI

GNDA

Si8271

Figure 2.1. Si8271 Block Diagram

VDDI

VDDA

VIA

VOA

UVLO

GNDA

OVERLAP

PROTECTION

VDDI

VDDB

VDDI

UVLO

VOB

UVLO

EN

GNDB

VIB

GNDI

Si8273

Figure 2.2. Si8273 Block Diagram

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Preliminary Rev. 0.5 | 3

Si827x Data Sheet

System Overview

VDDI

VDDA

PWM

LPWM

VOA

UVLO

GNDA

DT CONTROL

&

OVERLAP

PROTECTION

DT

VDDI

VDDB

VDDI

UVLO

VOB

UVLO

EN

GNDB

LPWM

GNDI

Si8274

Figure 2.3. Si8274 Block Diagram

VDDI

VDDA

VIA

VOA

UVLO

GNDA

VDDI

UVLO

VDDI

VDDB

EN

VOB

UVLO

GNDB

VIB

GNDI

Si8275

Figure 2.4. Si8275 Block Diagram

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Preliminary Rev. 0.5 | 4

Si827x Data Sheet

System Overview

The operation of an Si827x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of

light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A

simplified block diagram for a single Si827x channel is shown in the figure below.

Transmitter

Receiver

Driver

V_DD

RF

OSCILLATOR

Semiconductor-

Based Isolation

Barrier

Dead

time

control

B

MODULATOR

DEMODULATOR

A

4 A peak

Gnd

Figure 2.5. Simplified Channel Diagram

A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the

Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that

decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying

scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to

magnetic fields. See Figure 2.6 Modulation Scheme on page 5 for more details.

Input Signal

Modulation Signal

Output Signal

Figure 2.6. Modulation Scheme

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Preliminary Rev. 0.5 | 5

Si827x Data Sheet

System Overview

2.1 Typical Operating Characteristics

The typical performance characteristics depicted in the figures below are for information purposes only. Refer to Table 4.1 Electrical

Characteristics on page 16 for actual specification limits.

Figure 2.7. Rise/Fall Time vs. Supply Voltage

Figure 2.8. Propagation Delay vs. Supply Voltage

Figure 2.9. Supply Current vs. Supply Voltage

Figure 2.10. Supply Current vs. Supply Voltage

Figure 2.11. Supply Current vs. Temperature

Figure 2.12. Rise/Fall Time vs. Load

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Preliminary Rev. 0.5 | 6

Si827x Data Sheet

System Overview

Figure 2.13. Propagation Delay vs. Load

Figure 2.14. Propagation Delay vs. Temperature

Figure 2.15. Output Sink Current vs. Temperature

Figure 2.16. Output Source Current vs. Temperature

2.2 Family Overview and Logic Operation During Startup

The Si827x family of isolated drivers consists of single, high-side/low-side, and dual driver configurations.

2.2.1 Products

The table below shows the configuration and functional overview for each product in this family.

Table 2.1. Si827x Family Overview

Part Number

Configuration

Overlap

Programmable

Inputs

Peak Output

Protection

Dead Time

Current (A)

Si8271

Si8273

Si8274

Si8275

Single Driver

High-Side/Low-Side

PWM

—

Y

—

Y

VI

4.0

VIA, VIB

PWM

Y

Dual Driver

—

VIA, VIB

2.2.2 Device Behavior

The table below consists of truth tables for the Si8273, Si8274, and Si8275 families.

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Preliminary Rev. 0.5 | 7

Si827x Data Sheet

System Overview

Table 2.2. Si827x Family Truth Table¹

Si8271 (Single Driver) Truth Table

Inputs

VDDI State

Enable

Output

Notes

VI

L

VO+

Hi–Z

H

VO–

L

Powered

H

X

H

Hi–Z

L

X²

X

Unpowered

Hi–Z

Powered

L

Hi–Z

L

Si8273 (High-Side/Low-Side) Truth Table

Inputs

VDDI State

Enable

Output

Notes

VIA

L

VIB

L

VOA

VOB

Powered

Unpowered

H

X

L

H

L

H

L

H

L

H

Invalid state.

X²

Output returns to input state within 7

µs of VDDI power restoration.

X

Powered

L

Device is disabled.

Si8274 (PWM Input High-Side/Low-Side) Truth Table

PWM Input

VDDI State

Enable

Output

Notes

VOA

VOB

H

L

Powered

H

X

H

L

H

L

X²

Unpowered

Output returns to input state within 7

µs of VDDI power restoration.

X

Powered

L

Device is disabled.

Si8275 (Dual Driver) Truth Table

Enable Output

Inputs

VDDI State

Notes

VIA

VIB

VOA

VOB

L

Powered

Unpowered

H

X

L

H

L

H

L

H

L

H

L

X²

Output returns to input state within 7

µs of VDDI power restoration.

X

Powered

L

Device is disabled.

1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see 2.6.2 Undervoltage Lockout

for more information.

2. An input can power the input die through an internal diode if its source has adequate current.

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Preliminary Rev. 0.5 | 8

Si827x Data Sheet

System Overview

2.3 Power Supply Connections

Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be

placed as close to the VDD and GND pins of the Si827x as possible. The optimum values for these capacitors depend on load current

and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,

are recommended.

2.4 Power Dissipation Considerations

Proper system design must assure that the Si827x operates within safe thermal limits across the entire load range.The Si827x total

power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by

the series gate resistor and load. The equation below shows total Si827x power dissipation.

R

n

p

2

P

= V

I

+ 2 I

V

+ ( f ) Q

V

+ f

Q

V

+ 2 fCintV

DD2

(

)(

)

(

)(

)

(

)

(

D

DDI DDI

DD2

G

DD2

G

DD2

)

( )(

)(

)

R + R

p

g

n g

where:

P_Dis the total Si827x device power dissipation (W)

I_DDIis the input-side maximum bias current (10 mA)

I_DD2is the driver die maximum bias current (4 mA)

C_intis the internal parasitic capacitance (370 pF)

V_DDIis the input-side V_DDsupply voltage (2.5 to 5.5 V)

V_DD2is the driver-side supply voltage (4.2 to 30 V)

f is the switching frequency (Hz)

Q_Gis the gate charge of external FET

R_Gis the external gate resistor

R_Pis the R_DS(ON)of the driver pull-up switch: 2.7 Ω

R_nis the R_DS(ON)of the driver pull-down switch: 1 Ω

Equation 1

Power dissipation example for driver using Equation 1 with the following givens:

V_DDI= 5.0 V

V_DD2= 12 V

f = 350 kHz

R_G= 22 Ω

Q_G= 25 nC

Pd = 199 mW

From which the driver junction temperature is calculated using Equation 2, where:

Pd is the total Si827x device power dissipation (W)

θ_jais the thermal resistance from junction to air (105 °C/W in this example)

T_Ais the ambient temperature

T = P × θ + T = (0.199)(105) + 20 = 41.0 ° C

j

d

ja

A

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Preliminary Rev. 0.5 | 9

Si827x Data Sheet

System Overview

The maximum power dissipation allowable for the Si827x is a function of the package thermal resistance, ambient temperature, and

maximum allowable junction temperature, as shown in Equation 2:

T

− T

A

jmax

P

≤

Dmax

θ

ja

where:

P_Dmax= Maximum Si827x power dissipation (W)

T_jmax= Si827x maximum junction temperature (150 °C)

T_A= Ambient temperature (20 °C)

θ_ja= Si827x junction-to-air thermal resistance (105 °C/W)

Equation 2

Substituting values for P_DmaxT_jmax, T_A, and θ_jainto Equation 2 results in a maximum allowable total power dissipation of 1.19 W. Maxi-

mum allowable load is found by substituting this limit and the appropriate data sheet values from Table 4.1 Electrical Characteristics on

page 16 into Equation 1 and simplifying. The result is Equation 3, both of which assume VDDI = 5 V and VDDA = VDDB = 12 V.

−2

1.24 × 10

−9

C

=

− 1.21 × 10

L (MAX )

f

Equation 3

Figure 2.17. Max Load vs. Switching Frequency

2.5 Layout Considerations

It is most important to minimize ringing in the drive path and noise on the Si827x VDD lines. Care must be taken to minimize parasitic

inductance in these paths by locating the Si827x as close to the device it is driving as possible. In addition, the VDD supply and ground

trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane sys-

tem having separate ground and VDD planes for power devices and small signal components provides the best overall noise perform-

ance.

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Preliminary Rev. 0.5 | 10

Si827x Data Sheet

System Overview

2.6 Undervoltage Lockout Operation

Device behavior during start-up, normal operation and shutdown is shown in the figure below, where UVLO+ and UVLO- are the posi-

tive-going and negative-going thresholds respectively.

Note: Outputs VOA and VOB default low when input side power supply (VDDI) is not present.

2.6.1 Device Startup

Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,

the outputs follow the states of inputs VIA and VIB.

2.6.2 Undervoltage Lockout

Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its

specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.

The Si827x input side enters UVLO when VDDI < VDDI_UV–, and exits UVLO when VDDI > VDDI_UV+. The driver outputs, VOA and VOB,

remain low when the input side of the Si827x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each

driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDA_UV–

and exits UVLO when VDDA rises above VDDA_UV+

.

The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Upon power up, the Si827x is maintained in

UVLO until VDD rises above VDD_UV+. During power down, the Si827x enters UVLO when VDD falls below the UVLO threshold plus

hysteresis (i.e., VDD < VDD_UV+– VDD_HYS). Please refer to spec tables for UVLO values.

UVLO+

VDD_HYS

UVLO-

VDDI

UVLO+

VDD_HYS

UVLO-

VDDA

VIA

ENABLE

tSD

tRESTART

tPHL

tPLH

tSD

tSTART

VOA

Figure 2.18. Device Behavior during Normal Operation and Shutdown

2.6.3 Control Inputs

VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding

output to go high. For PWM input versions (Si8274), VOA is high and VOB is low when the PWM input is high, and VOA is low and

VOB is high when the PWM input is low.

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Preliminary Rev. 0.5 | 11

Si827x Data Sheet

System Overview

2.6.4 Enable Input

When brought low, the ENABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device opera-

tion terminates within tSD after ENABLE = V_ILand resumes within tRESTART after ENABLE = V_IH. The ENABLE input has no effect if

VDDI is below its UVLO level (i.e., VOA, VOB remain low).

2.7 Programmable Dead Time and Overlap Protection

All PWM drivers (Si8274x) include programmable dead time, which adds a user-programmable delay between transitions of VOA and

VOB. When enabled, dead time is present on all transitions. The amount of dead time delay (DT) is programmed by a single resistor

(RDT) connected from the DT input to ground per the equation below.

DT = 2.02 × RDT + 7.77 (for 10-200 ns range)

DT = 6.06 × RDT + 3.84 (for 20-700 ns range)

where:

DT = dead time (ns)

and

RDT = dead time programming resistor (kΩ)

Equation 4

Input/output timing waveforms for the Si8273 two-input drivers are shown in the figure below, and dead time waveforms for the Si8274

are shown in Figure 2.20 Dead Time Waveforms for Si8274 Drivers on page 13.

VIA

VIB

VOA

VOB

A

B

C

D

E

F

G

H

I

Figure 2.19. Input / Output Waveforms for Si8273 Drivers

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Preliminary Rev. 0.5 | 12

Si827x Data Sheet

System Overview

Table 2.3. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers

Ref

A

B

C

D

E

Description

Normal operation: VIA high, VIB low.

Normal operation: VIB high, VIA low.

Contention: VIA = VIB = high.

Recovery from contention: VIA transitions low.

Normal operation: VIA = VIB = low.

F

Normal operation: VIA high, VIB low.

Contention: VIA = VIB = high.

G

H

I

Recovery from contention: VIB transitions low.

Normal operation: VIB transitions high.

VOB

PWM

50%

LPWM

(internal)

DT

90%

VOA

10%

DT

90%

VOB

10%

Typical Dead Time Operation

Figure 2.20. Dead Time Waveforms for Si8274 Drivers

2.8 De-glitch Feature

A de-glitch feature is provided on some options, as defined in the 1. Ordering Guide. The internal de-glitch circuit provides an internal

time delay of 15 ns typical, during which any noise is ignored and will not pass through the IC. For these product options, the propaga-

tion delay will be extended by 15 ns, as specified in the spec table.

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Preliminary Rev. 0.5 | 13

Si827x Data Sheet

Applications

3. Applications

The following examples illustrate typical circuit configurations using the Si827x.

3.1 High-Side/Low-Side Driver

In the figure below, side A shows the Si8273 controlled using the VIA and VIB input signals, and side B shows the Si8274 controlled by

a single PWM signal.

VDD2

C3

VDD2

C3

D1

VDDI

1 µF

VDDI

GNDI

VDDI

C2

0.1 µF

C2

0.1 µF

C1

1500 V max

1 µF

VDDA

GNDI

PWM

CB

Q1

OUT1

OUT2

VIA

VIB

PWMOUT

CONTROLLER

I/O

VOA

GNDA

DT

RDT

VDD2

C4

VDD2

C4

CONTROLLER

Si8273

Si8274

VDDB

C5

10 µF

C5

0.1 µF

10 µF

I/O

ENABLE

GNDB

VOB

GNDB

VOB

Q2

A

B

Figure 3.1. Si827x in Half-Bridge Application

For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a

maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si827x requires

VDD in the range of 2.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 4.2 and 30 V with respect to their

respective grounds. The boot-strap start up time will depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that

the bypass capacitors on the Si827x should be located as close to the chip as possible. Moreover, it is recommended that bypass ca-

pacitors be used (as shown in the figures above for input and driver side) to reduce high frequency noise and maximize performance.

The outputs VOA and VOB can be used interchangeably as high side or low side drivers.

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Preliminary Rev. 0.5 | 14

Si827x Data Sheet

Applications

3.2 Dual Driver

The figure below shows the Si827x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a com-

mon ground or to different grounds with as much as 1500 V dc between them.

VDDI

Q1

C2

0.1 µF

C1

1 µF

VOA

GNDI

VDDA

C3

VDDA

GNDA

VIA

VIB

OUT1

OUT2

C4

10 µF

0.1 µF

CONTROLLER

Si8275

VDDB

C5

VDDB

GNDB

VOB

C6

10 µF

I/O

ENABLE

0.1 µF

Q2

Figure 3.2. Si827x in a Dual Driver Application

Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the

driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual

driver in a high-side/low-side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can operate

as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes.

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Preliminary Rev. 0.5 | 15

Si827x Data Sheet

Electrical Specifications

4. Electrical Specifications

Table 4.1. Electrical Characteristics

V_DDI= 5 V, GNDI = 0 V, VDDA/B-GNDA/B = 30 V, T_A= –40 to +125 °C; typical specs at 25 °C

Parameter

DC Parameters

Symbol

Test Condition

Min

Typ

Max

Units

Input Supply Voltage

VDDI

(VDDA/B – GNDA/B)

IDDI(Q)

2.5

4.2

—

5.5

30

V

Driver Supply Voltage

V

Input Supply Quiescent Current

Input Supply Active Current

Output Supply Quiescent Current

Output Supply Active Current

Gate Driver

7.9

8.0

2.5

10.0

4.0

mA

IDDI

f = 500 kHz

—

IDDx(Q)

—

IDDx

—

11.0

High Output Transistor RDS (ON)

Low Output Transistor RDS (ΟΝ)

High Level Peak Output Current

R_OH

R_OL

I_OH

—

2.7

1.0

1.8

—

Ω

A

V_DDA/B= 15 V,

See Figure 4.2 IOH

Source Current Test

Circuit on page 19

for Si827xG,

V

_DD= 4.2 V,

T < 250 ns

Low Level Peak Output Current

I_OL

V_DDA/B= 15 V,

—

4.0

—

A

See Figure 4.1 IOL

Sink Current Test Cir-

cuit on page 19

for Si827xG,

V_DD= 4.2 V,

T_{PW_IOL}< 250 ns

UVLO

VDDI UVLO Threshold +

VDDI UVLO Threshold –

VDDI Hysteresis

VDDI_UV+

VDDI_UV–

VDDI_HYS

1.85

1.75

—

2.2

2.1

100

2.45

2.35

—

V

mV

UVLO Threshold + (Driver Side)

3 V Threshold

VDDX_UV+

2.7

4.9

7.2

11

3.5

5.5

4.0

6.3

V

5 V Threshold

8 V Threshold

8.3

9.5

12 V Threshold

12.2

13.5

UVLO Threshold - (Driver Side)

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Preliminary Rev. 0.5 | 16

Si827x Data Sheet

Electrical Specifications

Parameter

3 V Threshold

Symbol

Test Condition

Min

2.5

4.6

6.7

9.6

Typ

3.2

Max

3.8

Units

VDDX_UV-

V

5 V Threshold

5.2

5.9

8 V Threshold

7.8

8.9

12 V Threshold

10.8

12.1

UVLO Lockout Hysteresis

3 V Threshold

VDD_HYS

—

300

—

mV

5 V Threshold

8 V Threshold

500

12 V Threshold

1400

Digital

Logic High Input Threshold

Logic Low Input Threshold

Input Hysteresis

VIH

VIL

2.0

—

0.8

—

V

VIHYST

VOH

350

400

—

mV

V

Logic High Output Voltage

IO = –1 mA

IO = 1 mA

VDDA/B –

0.04

—

Logic Low Output Voltage

AC Switching Parameters

Propagation Delay

VOL

—

20

30

20

30

65

—

30

45

30

45

85

3.6

14

38

200

0.04

60

75

60

75

105

8

V

t_PLH, t_PHL

C_L= 200 pF

|tPLH – tPHL|

ns

ps

Si8271/3/5 with low jitter

Propagation Delay

t_{PLH, PHL}

t

Si8271/3/5 with de-glitch option

Propagation Delay

t_PHL

Si8274 with low jitter

Propagation Delay

t_PHL

Si8274 with de-glitch option

Propagation Delay

t_PLH

Si8274 with low jitter

Propagation Delay

t_PLH

Si8274 with de-glitch option

Pulse Width Distortion

Si8271/3/5 all options

Pulse Width Distortion

Si8274 with low jitter

Pulse Width Distortion

Si8274 with de-glitch option

Peak to Peak Jitter

PWD

19

47

—

Si827x with low jitter

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Preliminary Rev. 0.5 | 17

Si827x Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

RDT = 6 kΩ

Min

10

Typ

20

Max

30

Units

Programmed dead-time (DT) for

products with 10–200 ns DT range

DT

ns

RDT = 15 kΩ

RDT = 100 kΩ

RDT = 6 kΩ

26

38

50

150

23

210

40

260

57

Programmed dead-time (DT) for

products with 20–700 ns DT range

DT

ns

RDT = 15 kΩ

RDT = 100 kΩ

CL = 200 pF

60

95

130

770

16

450

4

610

10.5

13.3

16

Rise time

t_R

t_F

ns

Fall time

5.5

—

18

Device Startup Time

t_START

30

µs

Common Mode Transient

Immunity

See Figure 4.3 Com-

mon Mode Transient

Immunity Test Circuit

on page 20.

200

350

400

kV/µs

Si827x with de-glitch option

VCM = 1500 V

Common Mode Transient

Immunity

See Figure 4.3 Com-

mon Mode Transient

Immunity Test Circuit

on page 20.

150

300

400

kV/µs

Si827x with low jitter option

VCM = 1500 V

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Preliminary Rev. 0.5 | 18

Si827x Data Sheet

Electrical Specifications

4.1 Test Circuits

The figures below depict sink current, source current, and common-mode transient immunity test circuits.

VDDA = VDDB = 15 V

VDDI

VDD

10

IN

OUT

Si827x

INPUT

SCHOTTKY

+

_

8 V

GND

100 µF

1 µF

CER

10 µF

EL

Measure

50 ns

RSNS

0.1

VDDI

GND

200 ns

INPUT WAVEFORM

Figure 4.1. IOL Sink Current Test Circuit

VDDA = VDDB = 15 V

VDDI

VDD

10

IN

OUT

Si827x

INPUT

SCHOTTKY

1 µF

+

_

5.5 V

GND

100 µF

1 µF

CER

10 µF

EL

Measure

RSNS

0.1

50 ns

VDDI

GND

200 ns

INPUT WAVEFORM

Figure 4.2. IOH Source Current Test Circuit

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Preliminary Rev. 0.5 | 19

Si827x Data Sheet

Electrical Specifications

12 V

Supply

Si827x

VDDI

VDDA

Input Signal

Switch

INPUT

EN

VOA

GNDA

VDDB

VOB

5V

Isolated

Supply

DT

Oscilloscope

100k

GNDI

GNDB

Isolated

Ground

High Voltage

Differential

Probe

Output

Input

Vcm Surge

Output

High Voltage

Surge Generator

Figure 4.3. Common Mode Transient Immunity Test Circuit

4.2 Regulatory Information (Pending)

Table 4.2. Regulatory Information^1,2

CSA

The Si827x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.

60950-1: Up to 125 V_RMSreinforced insulation working voltage; up to 600 V_RMSbasic insulation working voltage.

VDE

The Si827x is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.

VDE 0884-10: Up to 630 V_peakfor basic insulation working voltage.

UL

The Si827x is certified under UL1577 component recognition program. For more details, see File E257455.

Rated up to 2500 V_RMSisolation voltage for basic protection.

CQC

The Si827x is certified under GB4943.1-2011.

Rated up to 125 V_RMSreinforced insulation working voltage; up to 600 V_RMSbasic insulation working voltage.

1. Regulatory Certifications apply to 2.5 kV_RMSrated devices which are production tested to 3.0 kV_RMSfor 1 sec.

2. For more information, see 1. Ordering Guide.

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Preliminary Rev. 0.5 | 20

Si827x Data Sheet

Electrical Specifications

Table 4.3. Insulation and Safety-Related Specifications

Parameter

Symbol

L(1O1)

L(1O2)

Test Condition

Value

NB SOIC-16

4.7

Unit

SOIC-8

14 LD LGA

Nominal Air Gap

4.7

3.5

mm

V

(Clearance)

Nominal External Tracking

(Creepage)

3.9

0.008

600

3.9

0.008

600

3.5

Minimum Internal Gap

(Internal Clearance)

Tracking Resistance

(Proof Tracking Index)

Erosion Depth

0.008

600

PTI

IEC60112

ED

0.019

10¹²

0.019

10¹²

0.021

10¹²

mm

Ω

Resistance

R_IO

(Input-Output)¹

Capacitance

C_IO

f = 1 MHz

0.5

3.0

0.5

3.0

0.5

3.0

pF

(Input-Output)¹

Input Capacitance²

C_I

Notes:

1. To determine resistance and capacitance, the Si827x is converted into a 2-terminal device. All pins on side 1 are shorted to cre-

ate terminal 1, and all pins on side 2 are shorted to create terminal 2. The parameters are then measured between these two

terminals.

2. Measured from input pin to ground.

Table 4.4. IEC 60664-1 Ratings

Parameter

Test Condition

Specification

SOIC-8

I

NB SOIC-16

14 LD LGA

Basic Isolation Group

Material Group

I

Installation Classification

Rated Mains Voltages < 150 V_RMS

Rated Mains Voltages < 300 V_RMS

Rated Mains Voltages < 400 V_RMS

Rated Mains Voltages < 600 V_RMS

I-IV

I-III

I-II

I-IV

I-III

I-II

I-IV

I-III

I-II

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Preliminary Rev. 0.5 | 21

Si827x Data Sheet

Electrical Specifications

Table 4.5. VDE 0884 Insulation Characteristics¹

Parameter

Symbol

V_IORM

V_PR

Test Condition

Characteristic

Unit

Maximum Working Insulation Voltage

Input to Output Test Voltage

630

V peak

Method b1

1181

(V_IORMx 1.875 = V_PR, 100%

Production Test, t_m= 1 sec,

Partial Discharge < 5 pC)

Transient Overvoltage

Pollution Degree

(DIN VDE 0110, Table 1)

Insulation Resistance at

T_S, V_IO= 500 V

V_IOTM

t = 60 sec

4000

2

V peak

>10⁹

R_S

Ω

Note:

1. Maintenance of the safety data is ensured by protective circuits. The Si827x provides a climate classification of 40/125/21.

Table 4.6. IEC Safety Limiting Values¹

Parameter

Symbol

Test Condition

SOIC-8

NB SOIC-16

14 LD LGA

Unit

Case

T_S

140

150

°C

Temperature

Safety Input Current

Ι_S

θ

_JA= 110 °C/W

35

40

mA

(SOIC-8),

105 °C/W

(NB SOIC-16, 14 LD

LGA),

VDDI = 5.5 V,

V_DDA= V_DDB= 30 V,

T_J= 150 °C,

T_A= 25 °C

Device Power Dissipation

P_D

1

1.2

Ω

Note:

1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in the two figures below.

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Preliminary Rev. 0.5 | 22

Si827x Data Sheet

Electrical Specifications

Table 4.7. Thermal Characteristics

Parameter

Symbol

SOIC-8

NB

14 LD LGA

Unit

SOIC-16

IC Junction-to-Air

Thermal Resistance

θ_JA

110

105

°C/W

60

50

40

30

20

10

0

VDDI = 5.5 V

VDDA, VDDB = 30 V

0

50

100

150

200

Case Temperature (ºC)

Figure 4.4. NB SOIC-16, LGA-14 Thermal Derating Curve, Dependence of Safety Limiting Values Limiting Values with Case

Temperature per VDE 0884

60

50

VDDI = 5.5 V

VDDA, VDDB = 30 V

40

30

20

10

0

60

100

140

200

Case Temperature (ºC)

Figure 4.5. NB SOIC-8 Thermal Derating Curve, Dependence of Safety Limiting Values

Limiting Values with Case Temperature per VDE 0884

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Preliminary Rev. 0.5 | 23

Si827x Data Sheet

Electrical Specifications

Table 4.8. Absolute Maximum Ratings¹

Parameter

Symbol

Min

–65

–40

—

Max

+150

+125

+150

6.0

Units

°C

V

Storage Temperature

Operating Temperature

Junction Temperature

T_STG

T_A

T_J

Input-side supply voltage

VDDI

–0.6

–0.5

—

Driver-side supply voltage

VDDA, VDDB

V_IO

36

V

Voltage on any pin with respect to ground

VDD + 0.5

4.0

V

Peak Output Current (t_PW= 10 µs, duty cycle = 0.2%)

I_OPK

A

Lead Solder Temperature (10 s)

—

260

°C

kV

V

HBM Rating ESD

—

3.5

CDM

—

2000

3000

Maximum Isolation Voltage (Input to Output) (1 sec)

—

V_RMS

NB SOIC-16 and SOIC-8

Maximum Isolation Voltage (Input to Output) (1 sec)

—

3000

1500

650

V_RMS

kV/μs

5x5 LGA-14

Maximum Isolation Voltage (Output to Output) (1 sec)

NB SOIC-16

Maximum Isolation Voltage (Output to Output) (1 sec)

5x5 LGA-14

Latch-up Immunity

Note:

400

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to

the conditions specified in the operational sections of this data sheet.

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Preliminary Rev. 0.5 | 24

Si827x Data Sheet

Pin Descriptions

5. Pin Descriptions

5.1 Si8271 Pin Descriptions

VDD

VO+

VO-

VI

1

2

3

4

8

7

6

5

VDDI

Si8271

GNDI

EN

GND

Figure 5.1. Pin Assignments Si8271

Table 5.1. Si8271 Pin Descriptions

1

Name

VI

Description

Digital driver control signal

Input side power supply

Input side ground

2

VDDI

GNDI

EN

3

4

Enable

5

GND

VO–

VO+

VDD

Driver side ground

Gate drive pull low

Gate drive pull high

Driver side power supply

6

7

8

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Preliminary Rev. 0.5 | 25

Si827x Data Sheet

Pin Descriptions

5.2 Si8273/75 Pin Descriptions

VDDA

VOA

GNDA

NC

VIA

1

2

3

4

5

16

15

14

13

12

VIB

VDDA

VOA

GNDA

NC

1

2

3

4

5

14

13

12

VDDI

VIA

VIB

GNDI

EN

Si8273

Si8275

Si8273

Si8275

11 NC

GNDI

EN

10 VDDB

NC

6

7

9

8

VOB

GNDB

NC

6

7

8

11

10

9

VDDB

VOB

VDDI

GNDB

VDDI

Figure 5.2. Pin Assignments Si8273/5

Table 5.2. Si8273/5 Pin Descriptions

NB SOIC-16 Pin #

5x5 mm LGA-14 Pin #

Name

VIA

Description

1

2

Digital driver control signal for “A” driver

Digital driver control signal for “B” driver

Input side power supply

2

3

VIB

3,8

7

VDDI

GNDI

EN

4

Input side ground

5

1, 6, 11

8

Enable

6, 7, 12, 13

NC

No Connect

9

GNDB

VOB

VDDB

GNDA

VOA

VDDA

Driver side power supply for “B” driver

Gate drive output for “B” driver

Driver side power supply for “B” driver

Driver side power supply for “A” driver

Gate drive output for “A” driver

Driver side power supply for “A” driver

10

11

14

15

16

9

10

12

13

14

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Preliminary Rev. 0.5 | 26

Si827x Data Sheet

Pin Descriptions

5.3 Si8274 Pin Descriptions

VDDA

VOA

GNDA

NC

PWM

1

2

3

4

5

16

15

14

13

12

NC

VDDA

VOA

GNDA

NC

1

2

3

4

5

14

13

12

VDDI

PWM

NC

GNDI

EN

11 NC

GNDI

EN

Si8274

10 VDDB

NC

DT

6

7

9

8

VOB

GNDB

DT

NC

6

7

8

11

10

9

VDDB

VOB

VDDI

GNDB

VDDI

Figure 5.3. Pin Assignments Si8274

Table 5.3. Si8274 Pin Descriptions

NB SOIC-16 Pin #

5x5 mm LGA-14 Pin #

Name

PWM

NC

Description

1

2

Pulse width modulated driver control signal

No Connect

2, 7, 12, 13

1, 3, 11

3, 8

4

7

4

VDDI

GNDI

EN

Input side power supply

Input side ground

5

Enable

6

DT

Dead time control

9

8

GNDB

VOB

VDDB

GNDA

VOA

VDDA

Driver side power supply for “B” driver

Gate drive output for “B” driver

Driver side power supply for “B” driver

Driver side power supply for “A” driver

Gate drive output for “A” driver

Driver side power supply for “A” driver

10

11

14

15

16

9

10

12

13

14

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Preliminary Rev. 0.5 | 27

Si827x Data Sheet

Package Outlines

6. Package Outlines

6.1 Package Outline: 16-Pin Narrow-Body SOIC

The figure below illustrates the package details for the Si827x in a 16-pin narrow-body SOIC (SO-16). The table below lists the values

for the dimensions shown in the illustration.

Figure 6.1. 16-pin Small Outline Integrated Circuit (SOIC) Package

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Preliminary Rev. 0.5 | 28

Si827x Data Sheet

Package Outlines

Table 6.1. Package Diagram Dimensions

Dimension

Min

—

Max

1.75

0.25

—

Dimension

Min

Max

A

A1

A2

b

L

0.40

1.27

0.10

1.25

0.31

0.17

L2

0.25 BSC

h

0.25

0°

0.50

8°

0.51

0.25

θ

c

aaa

bbb

ccc

ddd

0.10

0.20

0.10

0.25

D

9.90 BSC

6.00 BSC

3.90 BSC

1.27 BSC

E

E1

e

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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Preliminary Rev. 0.5 | 29

Si827x Data Sheet

Package Outlines

6.2 Package Outline: 8-Pin Narrow Body SOIC

The figure below illustrates the package details for the Si827x in an 8-pin narrow-body SOIC package. The table below lists the values

for the dimensions shown in the illustration.

Figure 6.2. 8-Pin Narrow Body SOIC Package

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Preliminary Rev. 0.5 | 30

Si827x Data Sheet

Package Outlines

Table 6.2. 8-Pin Narrow Body SOIC Package Diagram Dimensions

Symbol

Millimeters

Min

1.35

Max

1.75

0.25

A

A1

A2

B

0.10

1.40 REF

0.33

1.55 REF

0.51

C

D

E

0.19

0.25

4.80

5.00

3.80

4.00

e

1.27 BSC

H

h

5.80

6.20

0.50

1.27

8°

0.25

L

0.40

0°

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Preliminary Rev. 0.5 | 31

Si827x Data Sheet

Package Outlines

6.3 Package Outline: 14 LD LGA (5 x 5 mm)

The figure below illustrates the package details for the Si827x in an LGA outline. The table below lists the values for the dimensions

shown in the illustration.

Figure 6.3. Si827x LGA Outline

Table 6.3. Package Diagram Dimensions

Dimension

MIN

0.74

0.25

NOM

0.84

MAX

0.94

0.35

A

b

0.30

D

5.00 BSC

4.15 BSC

0.65 BSC

5.00 BSC

3.90 BSC

0.75

D1

e

E

E1

L

0.70

0.05

—

0.80

0.15

0.10

0.08

0.15

0.08

L1

aaa

bbb

ccc

ddd

eee

0.10

—

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

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Preliminary Rev. 0.5 | 32

Si827x Data Sheet

Land Patterns

7. Land Patterns

7.1 Land Pattern: 16-Pin Narrow Body SOIC

The figure below illustrates the recommended land pattern details for the Si827x in a 16-pin narrow-body SOIC. The table below lists

the values for the dimensions shown in the illustration.

Figure 7.1. 16-Pin Narrow Body SOIC PCB Land Pattern

Table 7.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions

Dimension

Feature

Pad Column Spacing

Pad Row Pitch

Pad Width

(mm)

5.40

1.27

0.60

1.55

C1

E

X1

Y1

Pad Length

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.

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Preliminary Rev. 0.5 | 33

Si827x Data Sheet

Land Patterns

7.2 Land Pattern: 8-Pin Narrow Body SOIC

The figure below illustrates the recommended land pattern details for the Si827x in an 8-pin narrow-body SOIC. The table below lists

the values for the dimensions shown in the illustration.

Figure 7.2. 8-Pin Narrow Body SOIC Land Pattern

Table 7.2. 8-Pin Narrow Body SOIC Land Pattern Dimensions

Dimension

Feature

(mm)

5.40

1.27

0.60

1.55

C1

Pad Column Spacing

Pad Row Pitch

Pad Width

E

X1

Y1

Pad Length

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.

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Preliminary Rev. 0.5 | 34

Si827x Data Sheet

Land Patterns

7.3 Land Pattern: 14 LD LGA

The figure below illustrates the recommended land pattern details for the Si827x in a 14-pin LGA. The table below lists the values for

the dimensions shown in the illustration.

Figure 7.3. 14-Pin LGA Land Pattern

Table 7.3. 14-Pin LGA Land Pattern Dimensions

Dimension

(mm)

4.20

0.65

0.80

0.40

C1

E

X1

Y1

Notes:

1. All dimensions shown are in millimeters (mm).

2. This Land Pattern Design is based on the IPC-7351 guidelines.

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-

cation Allowance of 0.05 mm.

4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm

minimum, all the way around the pad.

5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

6. The stencil thickness should be 0.125 mm (5 mils).

7. The ratio of stencil aperture to land pad size should be 1:1.

8. A No-Clean, Type-3 solder paste is recommended.

9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

silabs.com | Smart. Connected. Energy-friendly.

Preliminary Rev. 0.5 | 35

Si827x Data Sheet

Top Markings

8. Top Markings

8.1 Si827x Top Marking (16-Pin Narrow Body SOIC)

Table 8.1. Top Marking Explanation (16-Pin Narrow Body SOIC)

Line 1 Marking:

Base Part Number

Ordering Options

Si827 = ISOdriver product series

Y = Configuration

3 = High-side/Low-side (HS/LS)

4 = PWM HS/LS

5 = Dual driver

See 1. Ordering Guide for

more information.

U = UVLO level

G = 3 V

A = 5 V

B = 8 V

D = 12 V

V = Isolation rating

B = 2.5 kV

W = Dead-time setting range

1= 10-200 ns

4 = 20-700 ns

X = Integrated de-glitch circuit

D = integrated

none = not included

Line 2 Marking:

YY = Year

Assigned by the Assembly House. Corresponds to the year and workweek

of the mold date.

WW = Workweek

TTTTTT = Mfg Code

Manufacturing Code from Assembly Purchase Order form.

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Preliminary Rev. 0.5 | 36

Si827x Data Sheet

Top Markings

8.2 Si8271 Top Marking (8-Pin Narrow Body SOIC)

Table 8.2. Top Marking Explanation (Narrow Body SOIC)

Line 1 Marking:

Customer Part Number

Si827 = ISOdriver product series

Y = Configuration

1 = Single driver

U = UVLO level

G = 3 V

A = 5 V

B = 8 V

D = 12 V

V = Isolation rating

B = 2.5 kV

Line 2 Marking:

WX = Ordering options

W = Dead-time setting range

1= 10-200 ns

4 = 20-700 ns

X = Integrated de-glitch circuit

D = integrated

none = not included

YY = Year

Assigned by the Assembly House. Corresponds to the year and workweek

of the mold date.

WW = Work week

TTTTTT = Mfg code

Line 3 Marking:

Manufacturing Code from Assembly Purchase Order form.

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Preliminary Rev. 0.5 | 37

Si827x Data Sheet

Top Markings

8.3 Si827x Top Marking (14 LD LGA)

Table 8.3. Top Marking Explanation (14 LD LGA)

Line 1 Marking:

Base Part Number

Ordering Options

Si827 = ISOdriver product series

Y = configuration

1 = single driver

3 = High-side/Low-side (HS/LS)

4 = PWM HS/LS

5 = Dual driver

See 1. Ordering Guide for

more information.

Line 2 Marking:

Ordering Options

U = UVLO level

G = 3 V

A = 5 V

B = 8 V

D = 12 V

V = Isolation rating

B = 2.5 kV

W = Dead-time setting range

1= 10-200 ns

4 = 20-700 ns

X = Integrated de-glitch circuit

D = integrated

none = not included

Manufacturing Code from Assembly.

Pin 1 identifier.

Line 3 Marking:

Line 4 Marking:

TTTTTT = Mfg code

Circle = 1.5 mm diameter

YYWW

Manufacturing date code.

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Preliminary Rev. 0.5 | 38

Si827x Data Sheet

Revision History

9. Revision History

9.1 Revision 0.1

February 26, 2016

• Initial release.

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Preliminary Rev. 0.5 | 39

Table of Contents

1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . 7

2.2.1 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.2 Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . 9

2.5 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .10

2.6 Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . .11

2.6.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.6.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.6.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.6.4 Enable Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.7 Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . .12

2.8 De-glitch Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . .14

3.2 Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2 Regulatory Information (Pending) . . . . . . . . . . . . . . . . . . . . . . .20

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 Si8271 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.2 Si8273/75 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .26

5.3 Si8274 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .27

6. Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 Package Outline: 16-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . .28

6.2 Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . .30

6.3 Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .32

7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1 Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . .33

7.2 Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . .34

7.3 Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . .35

8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1 Si827x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .36

8.2 Si8271 Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .37

Table of Contents 40

8.3 Si827x Top Marking (14 LD LGA) . . . . . . . . . . . . . . . . . . . . . . .38

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.1 Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table of Contents 41

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Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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型号：	Si8274GB1-IM
厂家：	SILICON
描述：	Single PWM or dual digital inputs
文件：	总43页 (文件大小：763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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