TS1108-200IQT1633 [SILICON]
Portable/Battery-Powered Systems;
| 型号： | TS1108-200IQT1633 |
| 厂家： | 
SILICON |
| 描述： | Portable/Battery-Powered Systems 电池 |
| 文件： | 总23页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS1108 Data Sheet
TS1108 Coulomb Counter: Bidirectional Current Sense Amplifier
with Integrator + Comparator
KEY FEATURES
• Coulomb Counting plus Charge Polarity
• Adjustable Charge Count Frequency
• External Crystal Oscillator Not Required
The TS1108 coulomb counter accurately measures battery depletion while also indicat-
ing the battery charging polarity. The battery discharge current is monitored by a current-
sense amplifier through an external sense resistor. Utilizing an Integrator and a Compa-
rator plus a Monoshot, the TS1108 voltage-to-frequency converter provides a series of
90 µs output pulses at COUT which represents an accumulation of coulombs flowing out
of the battery. The charge count frequency is adjustable by the integration resistor and
capacitor.
• Low Supply Current
• Current Sense Amplifier: 0.68 µA
• I
: 1.93 µA
VDD
• High Side Bidirectional Current Sense
Amplifier
Applications
• Wide CSA Input Common Mode Range: +2
V to +27 V
• Power Management Systems
• Portable/Battery-Powered Systems
• Smart Chargers
• Low CSA Input Offset Voltage: 150
µV(max)
• Low Gain Error: 1%(max)
• Two Gain Options Available:
• Gain = 20 V/V : TS1108-20
• Gain = 200 V/V : TS1108-200
• 16-Pin TQFN Packaging (3 mm x 3 mm)
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TS1108 Data Sheet
Ordering Information
1. Ordering Information
Table 1.1. Ordering Part Numbers
Description
Ordering Part Number
TS1108-20IQT163
Gain V/V
Coulomb counter: Bidirectional current sense amplifier with integrator and comparator
Coulomb counter: Bidirectional current sense amplifier with integrator and comparator
20
TS1108-200 IQT1633
200
Note: Adding the suffix “T” to the part number (e.g. TS1108-200IQT1633T) denotes tape and reel.
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TS1108 Data Sheet
System Overview
2. System Overview
2.1 Functional Block Diagram
Figure 2.1. TS1108 Coulomb Counter Block Diagram
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TS1108 Data Sheet
System Overview
2.2 Current Sense Amplifier + Output Buffer
The internal configuration of the TS1108 bidirectional current-sense amplifier is a variation of the TS1101 bidirectional current-sense
amplifier. The TS1108 current-sense amplifier is configured for fully differential input/output operation.
Referring to the block diagram, the inputs of the TS1108’s differential input/output amplifier are connected to RS+ and RS– across an
external RSENSE resistor that is used to measure current. At the non-inverting input of the current-sense amplifier, the applied voltage
difference in voltage between RS+ and RS– is ILOAD x RSENSE. Since the RS– terminal is the non-inverting input of the internal op-amp,
the current-sense op-amp action drives PMOS[1/2] to drive current across RGAIN[A/B] to equalize voltage at its inputs.
Thus, since the M1 PMOS source is connected to the inverting input of the internal op-amp and since the voltage drop across RGAINA is
the same as the external VSENSE, the M1 PMOS drain-source current is equal to:
V
SENSE
I
I
=
=
DS(M 1)
R
GAINA
I
× R
LOAD
SENSE
GAINA
DS(M 1)
R
The drain terminal of the M1 PMOS is connected to the transimpedance amplifier’s gain resistor, ROUT, via the inverting terminal. The
non-inverting terminal of the transimpedance amplifier is internally connected to VBIAS, therefore the output voltage of the TS1108 at
the OUT terminal is:
R
OUT
V
= V
− I
× R
×
OUT
BIAS
LOAD
SENSE
R
GAINA
When the voltage at the RS– terminal is greater than the voltage at the RS+ terminal, the external VSENSE voltage drop is impressed
upon RGAINB. The voltage drop across RGAINB is then converted into a current by the M2 PMOS. The M2 PMOS’ drain-source current
is the input current for the NMOS current mirror which is matched with a 1-to-1 ratio. The transimpedance amplifier sources the M2
PMOS drain-source current for the NMOS current mirror. Therefore the output voltage of the TS1108 at the OUT terminal is:
R
OUT
V
= V
+ I
× R
×
OUT
BIAS
LOAD
SENSE
R
GAINB
When M1 is conducting current (VRS+ > VRS–), the TS1108’s internal amplifier holds M2 OFF. When M2 is conducting current (VRS–
VRS+), the internal amplifier holds M1 OFF. In either case, the disabled PMOS does not contribute to the resultant output voltage.
>
The current-sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN[A/B]. For each of the two gain options availa-
ble, The following table lists the values for RGAIN[A/B]
.
Table 2.1. Internal Gain Setting Resistors (Typical Values)
GAIN (V/V)
RGAIN[A/B] (Ω)
ROUT (Ω)
40 k
Part Number
TS1108-20
20
2 k
200
200
40 k
TS1108-200
The TS1108 allows access to the inverting terminal of the transimpedance amplifier by the FILT pin, whereby a series RC filter may be
connected to reduce noise at the OUT terminal. The recommended RC filter is 4 kΩ and 0.47 µF connected in series from FILT to GND
to suppress the noise. Any capacitance at the OUT terminal should be minimized for stable operation of the buffer.
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TS1108 Data Sheet
System Overview
2.3 Sign Output
The TS1108 SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current (VRS+
> VRS–). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (VRS– > VRS+). The SIGN comparator’s transfer
characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the TS1108
exhibits no “dead zone” at ILOAD switchover.
Figure 2.2. TS1108 Sign Output Transfer Characteristic
2.4 Integrator + Comparator
The TS1108 Coulomb Counter function utilizes an Integrator and a Comparator plus a 90 µs Monoshot. The CSA’s buffered output is
applied to the integrator’s input. This signal is integrated by the comparator until it reaches a level that trips the comparator. The compa-
rator’s trip level is determined by the voltage applied to the comparator’s non-inverting terminal, CIN+. The Monoshot produces a 90 µs
output pulse at COUT and the integrator is reset. Therefore, each COUT 90 µs pulse represents an accumulation of coulombs (Please
refer to the equations in 2.6 Coulomb Counter). The TS1108 Integrator works best when the 90 μs Monoshot represents less than 2%
of the total integration period. Therefore, the minimum integration time for a full-scale VSENSE should be limited to 4.7 ms. To guarantee
stable operation of the OUT buffer, an integration capacitance of 0.1 µF should be used for integration capacitor, CINT . The maximum
integration period can be very long, limited by the leakage current and offset.
A reset switch is configured internally to discharge the external integration capacitor, CINT. To enable the Coulomb Counting feature,
SW_RST should be tied to either GND or COUT, allowing the 90 µs Monoshot Pulse to control the discharge of CINT. To close the reset
switch and short out CINT, SW_RST may be tied high.
TS1108’s Coulomb Counting interrupt is provided by the internal comparator with a push-pull output configuration. As shown in the
block diagram, the integrator’s output is applied internally to the non-inverting terminal of the comparator, CIN+. Therefore the compara-
tor’s output will latch high for 90 µs once the integrator’s output is charged to the voltage supplied to the comparator’s inverting terminal,
CIN–. The inverting terminal of the comparator, CIN–, must be at a higher potential than the voltage supplied to VBIAS for proper oper-
ation. The capacitive load at COUT should be minimized for minimal output delays.
2.5 VREF Divider
The TS1108 provides an internal voltage divider network to set VBIAS and CIN–, eliminating the need for externally setting the required
voltages. The VREF Divider is activated once the voltage applied to VREF is 0.9 V or greater. The VREF divider connects to VBIAS
and CIN–, where the VBIAS voltage is equal to 50% of VREF while the CIN– voltage is equal to 90% of VREF . The VREF Divider
exhibits a typical total series resistance of 4.6 MΩ from VREF to GND when activated.
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TS1108 Data Sheet
System Overview
2.6 Coulomb Counter
The amount of charge, or coulombs, over time is measured by the integration of current. The TS1108 Coulomb Counter measures the
charge consumed by the load by integrating the voltage output of the Current Sense Amplifier, thereby converting the sensed current at
the CSA’s applied input into a measurement of coulombs. The comparator’s output represents a measurement of coulombs per output
pulse. The period of the comparator’s output pulses is defined by:
R
C
V
− V
VBIAS
(
)
INT INT CIN −
GAIN × V
t
=
COUT
SENSE
Since a coulomb is defined as the multiplication of current and time, the quantity of coulombs per comparator output pulse can be de-
fined as:
R
C
V
− V
VBIAS
(
)
Coulombs
INT INT CIN −
GAIN × R
OneComparatorOutputPulse =
SENSE
The comparator’s output pulse can also quantify the ampere-hours (Ah) of battery charge, as most battery manufacturers specify a bat-
tery’s capacity in ampere-hours.
R
C
V
− V
(
)
Ah
INT INT CIN − VBIAS
OneComparatorOutputPulse =
3600 × GAIN × R
SENSE
It should be noted that the sense resistor value, RSENSE, should not be used to adjust the relationship between coulombs and the ap-
plied sense current to the CSA’s input. The integration resistor, RINT, and the comparator’s upper limit voltage, VCIN–, should be used to
adjust the integration time, and therefore the comparator’s output period.
2.7 Selecting a Sense Resistor
Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows:
1. RSENSE Voltage Loss
2. VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD
3. Total ILOAD Accuracy
4. Circuit Efficiency and Power Dissipation
5. RSENSE Kelvin Connections
2.7.1 RSENSE Voltage Loss
For lowest IR power dissipation in RSENSE, the smallest usable resistor value for RSENSE should be selected.
2.7.2 VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD
Although the Current Sense Amplifier draws its power from the voltage at its RS+ and RS– terminals, the signal voltage at the OUT
terminal is provided by a buffer, and is therefore bounded by the buffer’s output range. As shown in the Electrical Characteristics table,
the CSA Buffer has a maximum and minimum output voltage of:
V
V
= VDD
= 0.2V
− 0.2V
(min )
OUT (max )
OUT (min )
Therefore, the full-scale sense voltage should be chosen so that the OUT voltage is neither greater nor less than the maximum and
minimum output voltage defined above. To satisfy this requirement, the positive full-scale sense voltage, VSENSE(pos_max), should be
chosen so that:
VBIAS − V
OUT (min )
V
<
SENSE(pos_max )
GAIN
Likewise, the negative full-scale sense voltage, VSENSE(neg_min), should be chosen so that:
V
− VBIAS
OUT (max )
V
<
SENSE(neg_min )
GAIN
For best performance, RSENSE should be chosen so that the full-scale VSENSE is less than ±75 mV.
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TS1108 Data Sheet
System Overview
2.7.3 Total Load Current Accuracy
In the TS1108’s linear region where VOUT(min) < VOUT < VOUT(max), there are two specifications related to the circuit’s accuracy: a) the
TS1108 CSA’s input offset voltage (VOS(max) = 150 µV), b) the TS1108 CSA’s gain error (GE(max) = 1%). An expression for the
TS1108’s total error is given by:
V
= VBIAS − GAIN × 1 ± GE × V
± GAIN × V
SENSE OS
(
)
(
)
OUT
A large value for RSENSE permits the use of smaller load currents to be measured more accurately because the effects of offset voltag-
es are less significant when compared to larger VSENSE voltages. Due care though should be exercised as previously mentioned with
large values of RSENSE
.
2.7.4 Circuit Efficiency and Power Dissipation
IR loses in RSENSE can be large especially at high load currents. It is important to select the smallest, usable RSENSE value to minimize
power dissipation and to keep the physical size of RSENSE small. If the external RSENSE is allowed to dissipate significant power, then
its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Precisely
because the TS1108 CSA’s input stage was designed to exhibit a very low input offset voltage, small RSENSE values can be used to
reduce power dissipation and minimize local hot spots on the pcb.
2.7.5 RSENSE Kelvin Connections
For optimal VSENSE accuracy in the presence of large load currents, parasitic pcb track resistance should be minimized. Kelvin-sense
pcb connections between RSENSE and the TS1108’s RS+ and RS– terminals are strongly recommended. The drawing below illustrates
the connections between the current-sense amplifier and the current-sense resistor. The pcb layout should be balanced and symmetri-
cal to minimize wiring-induced errors. In addition, the pcb layout for RSENSE should include good thermal management techniques for
optimal RSENSE power dissipation.
Figure 2.3. Making PCB Connections to RSENSE
2.7.6 RSENSE Composition
Current-shunt resistors are available in metal film, metal strip, and wire-wound constructions. Wire-wound current-shunt resistors are
constructed with wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self-inductance. In
applications where the load current contains high-frequency transients, metal film or metal strip current sense resistors are recommen-
ded.
2.7.7 Internal Noise Filter
In power management and motor control applications, current-sense amplifiers are required to measure load currents accurately in the
presence of both externally-generated differential and common-mode noise. An example of differential-mode noise that can appear at
the inputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple (whether injected into the circuit inductively or ca-
pacitively) can produce a differential-mode voltage drop across the external current-shunt resistor, RSENSE. An example of externally-
generated, common-mode noise is the high-frequency output ripple of a switching regulator that can result in common-mode noise in-
jection into both inputs of a current-sense amplifier.
Even though the load current signal bandwidth is dc, the input stage of any current-sense amplifier can rectify unwanted out-of-band
noise that can result in an apparent error voltage at its output. Against common-mode injection noise, the current-sense amplifier’s in-
ternal common-mode rejection ratio is 130 dB (typ).
To counter the effects of externally-injected noise, the TS1108 incorporates a 50 kHz (typ), 2nd-order differential low-pass filter as
shown in the TS1108’s block diagram, thereby eliminating the need for an external low-pass filter, which can generate errors in the
offset voltage and the gain error.
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TS1108 Data Sheet
System Overview
2.7.8 PC Board Layout and Power-Supply Bypassing
For optimal circuit performance, the TS1108 should be in very close proximity to the external current-sense resistor and the pcb tracks
from RSENSE to the RS+ and the RS– input terminals of the TS1108 should be short and symmetric. Also recommended are surface
mount resistors and capacitors, as well as a ground plane.
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TS1108 Data Sheet
Electrical Charaviscteristics
3. Electrical Charaviscteristics
Table 3.1. Recommended Operating Conditions1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
System Specifications
Operating Voltage Range
Common-Mode Input Range
Note:
VDD
VCM
1.7
2
—
—
5.25
27
V
V
VRS+, Guaranteed by CMRR
1. All devices 100% production tested at TA = +25 °C. Limits over Temperature are guaranteed by design and characterization.
Table 3.2. DC Characteristics1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
System Specifications
No Load Input Supply Current
IRS+ + IRS–
IVDD
See Note 2
—
—
0.68
1.93
1.2
μA
μA
2.88
Current Sense Amplifier
Common Mode Rejection Ra-
tio
CMRR
VOS
2 V < VRS+ < 27 V
120
130
—
dB
Input Offset Voltage3
TA = +25 °C
–40 °C < TA < +85 °C
TA = +25 °C
—
—
—
±100
—
±150
±200
—
μV
μV
μV
VOS Hysteresis4
Gain
VHYS
G
10
TS1108-20
TS1108-200
—
—
—
—
—
—
—
—
28
20
200
±0.1
—
—
—
V/V
V/V
%
Positive Gain Error5
Negative Gain Error5
Gain Match5
GE+
GE–
GM
TA = +25 °C
±0.6
±1
–40 °C < TA < +85 °C
TA = +25 °C
%
±0.6
—
±1
%
–40 °C < TA < +85 °C
TA = +25 °C
±1.4
±1
%
±0.6
—
%
–40 °C < TA < +85 °C
From FILT to OUT
±1.4
52
%
Transfer Resistance
CSA Buffer
ROUT
40
kΩ
Input Bias Current
Input referred DC Offset
Offset Drift
IBuffer_BIAS
VBuffer_OS
TCVBuffer_OS
VBuffer_CM
—
—
—
—
0.5
±2.5
nA
mV
–40 °C < TA < +85 °C
—
0.6
—
—
μV/°C
V
Input Common Mode Range
CSA Sign Comparator
0.2
VDD – 0.2
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TS1108 Data Sheet
Electrical Charaviscteristics
Parameter
Symbol
VSIGN_OL
VSIGN_OH
Conditions
Min
Typ
—
Max
0.2
—
Units
Output Low Voltage
Output High Voltage
Comparator
VDD = 1.7 V, ISINK = 35 μA
—
V
V
V
DD = 1.7 V, ISOURCE = 35 μA VDD – 0.2
—
Input Bias Current
Input Bias Current
Input referred DC offse
Input Common Mode Range
COUT Output Range
Output Range
ICIN–_BIAS
ICIN+_BIAS
VC_OS
CIN–
CIN+
—
—
—
0.3
—
—
—
—
0.5
—
nA
nA
mV
V
—
±4
VC_CM
0.4
0.4
0.2
VDD – 0.4
VDD – 0.4
VDD – 0.2
VCOUT(min,max) ICOUT = ±500 μA; VDD = 1.7 V
V
VOUT(min,max)
IOUT = ±150 μA; VDD = 1.7 V
V
Integrator
Input Referred DC Offset
Offset Drift
VINT_OS
TCVINT_OS
VINT_CM
IINT_OL
—
—
—
0.6
—
±2.5
—
mV
µV/C
V
–40 C < TA < +85 C
Input Common-Mode Range
Output Low Voltage
0.2
—
VDD – 0.2
0.2
ICIN+(SINK) = 150 μA; VDD = 1.7
V
—
V
Output High Voltage
IINT_OH
ICIN+(SOURCE) = 150 μA; VDD = VDD – 0.2
1.7 V
—
—
V
VREF Divider
VREF Activation voltage
Resistor on VREF
VBIAS
VREF(min)
RVREF
VVBIAS
VCIN–
VREF Rising edge
—
—
0.9
—
V
MΩ
V
—
4.6
0.5
0.9
VREF = 1 V
VREF = 1 V
0.495
0.895
0.505
0.505
CIN–
V
Note:
1. RS+ = RS– = 3.6 V; VSENSE =(VRS+ – VRS–) = 0 V; VDD = 3 V; VBIAS = 1.5 V; CIN+ = 0.75 V; VREF = GND; CLATCH = GND;
RFET = 1 MΩ; FILT connected to 4 kΩ and 470 nF in series to GND. TA = TJ = –40 °C to +85 °C unless otherwise noted. Typical
values are at TA=+25 °C.
2. Extrapolated to VOUT = VFILT; IRS+ + IRS– is the total current into the RS+ and the RS– pins.
3. Input offset voltage VOS is extrapolated from a VOUT(+) measurement with VSENSE set to +1 mV and a VOUT(–) measurement with
VSENSE set to –1 mV; average VOS = (VOUT(–) – VOUT(+))/(2 x GAIN).
4. Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states.
5. Gain error is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer
characteristic. For GAIN = 20 V/V, the applied VSENSE for GE± is ±25 mV and ±60 mV. For GAIN = 200 V/V, the applied VSENSE
for GE± is ±2.5 mV and ±6 mV
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TS1108 Data Sheet
Electrical Charaviscteristics
Table 3.3. AC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
CSA Buffer
Output Settling time
tOUT_s
1% Final value, VOUT
1.3 V
=
—
1.35
—
msec
Sign Comparator Parameters
Propagation Delay
tSIGN_PD
VSENSE = ±1 mV
VSENSE = ±10 mV
—
—
3
—
—
msec
msec
0.4
Reset Switch
Capacitor Discharge Time
tRESET
CINT = 0.1 µF;
—
—
60
µsec
After comparator trigger
Comparator
Rising Propagation Delay
tC_PDR
Overdrive = +10 mV,
CCOUT = 15 pF
—
—
9
—
—
µsec
mV
Comparator Hysteresis
Monoshot
VC_HYS
CIN+ Rising
20
Monoshot Time
tMONO
1.7 ≤ VDD ≤ 5.25
75.5
90
126
µsec
Table 3.4. Thermal Conditions
Parameter
Symbol
TOP
Conditions
Min
Typ
Max
Units
Operating Temperature Range
-40
—
+85
°C
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TS1108 Data Sheet
Electrical Charaviscteristics
Table 3.5. Absolute Maximum Limits
Parameter
Symbol
VRS+
Conditions
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
Units
V
RS+ Voltage
27
RS– Voltage
VRS–
27
V
Supply Voltage
VDD
6
V
OUT Voltage
VOUT
6
V
SIGN Voltage
VSIGN
6
V
FILT Voltage
VFILT
6
V
SW_RST Voltage
COUT Voltage
VSW_RST
VCOUT
VVREF
VCIN+
6
6
V
V
VREF Voltage
6
V
CIN+ Voltage
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
27
V
CIN– Voltage
VCIN–
V
INT– Voltage
VINT–
V
VBIAS Voltage
VVBIAS
VRS+ – VRS–
V
RS+ to RS– Voltage
Short Circuit Duration: OUT to GND
Continuous Input Current (Any Pin)
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
Soldering Temperature (Reflow)
ESD Tolerance
V
—
Continuous
20
–20
—
mA
°C
°C
°C
°C
150
–65
—
150
300
—
260
Human Body Model
Machine Model
—
—
—
—
2000
200
V
V
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TS1108 Data Sheet
Electrical Charaviscteristics
For the following graphs, VRS+ = VRS– = 3.6 V; VDD = 3 V; VREF = GND; VBIAS = 1.5 V, CIN– = 2.5 V, SW_RST = COUT; RINT = 47
kΩ; CINT = 0.1 µF, and TA = +25 C unless otherwise noted.
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TS1108 Data Sheet
Electrical Charaviscteristics
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TS1108 Data Sheet
Electrical Charaviscteristics
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TS1108 Data Sheet
Electrical Charaviscteristics
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TS1108 Data Sheet
Electrical Charaviscteristics
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TS1108 Data Sheet
Typical Application Circuit
4. Typical Application Circuit
Figure 4.1. TS1108 Typical Application Circuit
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TS1108 Data Sheet
Pin Descriptions
5. Pin Descriptions
TS1108
Table 5.1. Pin Descriptions
Pin
1
Label
SIGN
VDD
Function
Sign output. SIGN is HIGH for VRS+ > VRS– and LOW for VRS– > VRS+
External power supply pin. Connect this to the system’s VDD supply.
.
2
3
VBIAS Bias voltage for CSA output. When VREF is activated, leave open.
4
GND
CIN–
Ground. Connect to analog ground.
5
Inverting terminal of Comparator. Supply a reference voltage for integration limit. CIN- voltage must be
greater than VBIAS. If VREF is activated, leave open.
6
7
8
CIN+
INT–
Integrator Output and Non-inverting terminal of Comparator. Connect CINT in series from INT–.
Inverting Terminal of Integrator. Connect RINT in series from OUT. Connect CINT in series to CIN+.
VREF
Voltage reference. To activate, a minimum voltage of 0.9 V is required. To disable voltage divider, connect
to analog ground, GND.
9
OUT
FILT
RS+
RS–
NC
CSA buffered output. Connect RINT in series to INT–.
10
11
12
13
14
Inverting terminal of CSA Buffer. Connect a series RC Filter of 4 kΩ and 0.47 µF, otherwise leave open.
External Sense Resistor Power-Side Connection
External Sense Resistor Load-Side Connection. Connect external PFET’s source.
No connection. Leave open.
SW_RST Integrator Reset Switch control. To enable coulomb counting, connect SW_RST to GND or COUT. Hold
SW_RST HIGH to short CIN+ and INT–.
15
16
NC
No connection. Leave open.
COUT
EPAD
Coulomb Comparator Counter Output.
Exposed Pad
Exposed backside paddle. For best electrical and thermal performance, solder to analog ground.
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Rev. 1.0 | 18
TS1108 Data Sheet
Packaging
6. Packaging
Figure 6.1. TS1108 3x3 mm 16-QFN Package Diagram
Table 6.1. Package Dimensions
Dimension
Min
0.70
0.00
0.20
Nom
0.75
Max
A
A1
b
0.80
0.05
0.30
0.02
0.25
C1
C2
D
1.50 REF
0.25 REF
3.00 BSC
2.00
D2
e
1.90
2.10
0.50 BSC
3.00 BSC
2.00
E
E2
L
1.90
0.20
—
2.10
0.30
0.05
0.05
0.05
0.10
0.25
aaa
bbb
ccc
ddd
—
—
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 1.0 | 19
TS1108 Data Sheet
Top Marking
7. Top Marking
Figure 7.1. Top Marking
Table 7.1. Top Marking Explanation
Mark Method
Laser
Circle = 0.50 mm Diameter (lower left corner)
0.50 mm (20 mils)
Pin 1 Mark:
Font Size:
Line 1 Mark Format:
Line 2 Mark Format:
Line 3 Mark Format:
Product ID
Note: A = 20 gain, B = 200 gain
Manufacturing code
TTTT – Mfg Code
YY = Year; WW = Work Week
Year and week of assembly
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Rev. 1.0 | 20
Table of Contents
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Current Sense Amplifier + Output Buffer . . . . . . . . . . . . . . . . . . . . . 3
2.3 Sign Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Integrator + Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5 VREF Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.6 Coulomb Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7 Selecting a Sense Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7.1 RSENSE Voltage Loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7.2 VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD. . . . . . . . . . 5
2.7.3 Total Load Current Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7.4 Circuit Efficiency and Power Dissipation . . . . . . . . . . . . . . . . . . . . 6
2.7.5 RSENSE Kelvin Connections . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7.6 RSENSE Composition . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7.7 Internal Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7.8 PC Board Layout and Power-Supply Bypassing . . . . . . . . . . . . . . . . . . 7
3. Electrical Charaviscteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Top Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table of Contents 21
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
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