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STK25CA8-D45 [SIMTEK]

Non-Volatile SRAM Module, 128KX8, 45ns, CMOS, PDIP32, 0.600 INCH, MODULE, DIP-32;
STK25CA8-D45
型号： STK25CA8-D45
厂家： SIMTEK CORPORATION    SIMTEK CORPORATION
描述：

Non-Volatile SRAM Module, 128KX8, 45ns, CMOS, PDIP32, 0.600 INCH, MODULE, DIP-32

静态存储器 光电二极管 内存集成电路
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STK25CA8  
128K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM Module  
FEATURES  
DESCRIPTION  
• Nonvolatile Storage without Battery Problems  
• Directly Replaces 128K x 8 Static RAM, Battery-  
Backed RAM or EEPROM  
• 35ns and 45ns Access Times  
• STORE to EEPROM Initiated by AutoStore™  
on Power Down  
• RECALL to SRAM on Power Restore  
• 22mA ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to EEPROM  
• 100-Year Data Retention Over Full Commercial  
Temperature Range  
The Simtek STK25CA8 is a fast static RAM with a  
nonvolatile, electrically erasable PROM element  
incorporated in each static memory cell. The SRAM  
can be read and written an unlimited number of  
times, while independent nonvolatile data resides in  
the EEPROM. Data transfers from the SRAM to the  
EEPROM (the STORE operation) can take place auto-  
matically on power down using charge stored in sys-  
tem capacitance. Transfers from the EEPROM to the  
SRAM (the RECALL operation) take place automati-  
cally on restoration of power.  
• Commercial and Industrial Temperatures  
• 32-Pin 600 mil Dual In-Line Module  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
1
V
NC  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CC  
A15  
A16  
MODULE  
DECODER  
2
A
A
A
A
A
A
A
A
A
A
A
A
NC  
W
A
A
A
A
G
A
E
DQ  
16  
14  
12  
15  
3
EEPROM ARRAY  
512 x 512  
4
5
V
CC  
7
6
5
4
3
13  
6
8
A5  
A6  
A7  
7
9
STORE  
8
11  
STORE/  
RECALL  
CONTROL  
9
POWER  
CONTROL  
10  
11  
12  
13  
14  
15  
16  
A8  
A9  
2
10  
STATIC RAM  
ARRAY  
RECALL  
1
0
7
6
5
512 x 512  
A11  
A12  
A13  
A14  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
0
32 - 600 mil  
Dual In-Line  
Module  
1
2
4
3
V
SS  
PIN NAMES  
DQ  
0
1
2
COLUMN I/O  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+ 5V)  
Ground  
0
16  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
COLUMN DEC  
W
3
4
DQ - DQ  
0
7
E
5
6
7
A
A
A
A
10  
4
A
A
0
1
2
3
G
G
V
V
CC  
E
SS  
W
August 1999  
6-1  
STK25CA8  
a
ABSOLUTE MAXIMUM RATINGS  
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)  
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)  
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W  
DC Output Current (1 output at a time, 1s duration) . . . . . . . .15mA  
Note a: Stresses greater than those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device. This is a  
stress rating only, and functional operation of the device at condi-  
tions above those indicated in the operational sections of this  
specification is not implied. Exposure to absolute maximum rat-  
ing conditions for extended periods may affect reliability.  
DC CHARACTERISTICS  
(V = 5.0V ± 10%)  
CC  
COMMERCIAL  
INDUSTRIAL  
SYMBOL  
PARAMETER  
UNITS  
NOTES  
MIN  
MAX  
MIN  
MAX  
b
1
I
Average V Current  
CC  
140  
125  
150  
133  
mA  
mA  
t
t
= 35ns  
= 45ns  
CC  
AVAV  
AVAV  
c
I
I
Average V Current During STORE  
CC  
20  
22  
25  
25  
mA  
mA  
All Inputs Don’t Care, V = max  
CC  
CC  
CC  
2
b
3
Average V  
Current at t  
= 200ns  
W ≥ (V – 0.2V)  
CC  
AVAV  
CC  
All Others Cycling, CMOS Levels  
c
I
I
I
I
Average V Current During AutoStore™  
CC  
Cycle  
All Inputs Don’t Care  
CC  
4
18  
9
20  
9
mA  
mA  
µA  
d
V
Standby Current  
E ≥ (V – 0.2V)  
CC  
All Others V ≤ 0.2V or ≥ (V  
IN  
SB  
CC  
(Standby, Stable CMOS Input Levels)  
– 0.2V)  
CC  
Input Leakage Current  
V = max  
CC  
ILK  
±2  
±10  
±2  
±10  
V
= V to V  
IN  
SS  
CC  
Off-State Output Leakage Current  
V = max  
CC  
OLK  
µA  
V
= V to V , E or G ≥ V  
IN  
SS CC  
IH  
V
V
Input Logic “1” Voltage  
Input Logic “0” Voltage  
Output Logic “1” Voltage  
Output Logic “0” Voltage  
Operating Temperature  
2.2  
V
+ .5  
2.2  
V
+ .5  
V
V
All Inputs  
All Inputs  
IH  
CC  
CC  
V
– .5  
0.8  
V
– .5  
SS  
0.8  
IL  
SS  
V
2.4  
2.4  
V
I
I
=– 4mA  
= 8mA  
OH  
OUT  
V
0.4  
70  
0.4  
85  
V
OL  
OUT  
T
0
–40  
°C  
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.  
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).  
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.  
AC TEST CONDITIONS  
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V  
5.0V  
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns  
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V  
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1  
480 Ohms  
e
OUTPUT  
CAPACITANCE  
(TA = 25°C, f = 1.0MHz)  
30 pF  
INCLUDING  
SCOPE  
255 Ohms  
SYMBOL  
PARAMETER  
MAX  
UNITS  
CONDITIONS  
∆V = 0 to 3V  
∆V = 0 to 3V  
AND FIXTURE  
C
Input Capacitance  
Output Capacitance  
20  
pF  
IN  
C
28  
pF  
OUT  
Note e: These parameters are guaranteed but not tested.  
Figure 1: AC Output Loading  
August 1999  
6-2  
 
 
 
STK25CA8  
SRAM READ CYCLES #1 & #2  
(V = 5.0V ± 10%)  
CC  
SYMBOLS  
NO.  
STK25CA8-35 STK25CA8-45  
UNITS  
PARAMETER  
#1, #2  
Alt.  
MIN  
MAX  
MIN  
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
f
35  
45  
AVAV  
RC  
AA  
g
3
Address Access Time  
Output Enable to Data Valid  
35  
15  
45  
20  
AVQV  
4
GLQV  
OE  
OH  
LZ  
g
5
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
5
5
5
5
AXQX  
6
ELQX  
h
7
13  
13  
35  
15  
15  
45  
EHQZ  
HZ  
8
0
0
0
0
GLQX  
OLZ  
OHZ  
PA  
h
9
GHQZ  
e
10  
11  
ELICCH  
EHICCL  
d, e  
PS  
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.  
Note g: I/O state assumes E, G, < VIL and W > VIH; device is continuously selected.  
Note h: Measured + 200mV from steady state output voltage.  
f, g  
SRAM READ CYCLE #1: Address Controlled  
2
t
AVAV  
ADDRESS  
3
t
AVQV  
5
t
AXQX  
DQ (DATA OUT)  
DATA VALID  
f
SRAM READ CYCLE #2: E Controlled  
2
t
AVAV  
ADDRESS  
1
11  
t
ELQV  
t
EHICCL  
6
ELQX  
E
t
7
t
EHQZ  
G
9
t
4
GHQZ  
t
GLQV  
8
t
GLQX  
DATA VALID  
DQ (DATA OUT)  
10  
ELICCH  
t
ACTIVE  
STANDBY  
I
CC  
August 1999  
6-3  
 
 
 
 
STK25CA8  
SRAM WRITE CYCLES #1 & #2  
(V = 5.0V ± 10%)  
CC  
SYMBOLS  
NO.  
STK25CA8-35  
STK25CA8-45  
PARAMETER  
UNITS  
#1  
#2  
Alt.  
MIN  
35  
25  
25  
12  
0
MAX  
MIN  
45  
30  
30  
15  
0
MAX  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
t
t
t
WC  
Write Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVAV  
AVAV  
t
t
t
Write Pulse Width  
WLWH  
WLEH  
WP  
CW  
t
t
t
Chip Enable to End of Write  
Data Set-up to End of Write  
Data Hold after End of Write  
ELWH  
DVWH  
WHDX  
ELEH  
DVEH  
EHDX  
t
t
t
DW  
t
t
t
DH  
AW  
t
t
t
Address Set-up to End of Write  
Address Set-up to Start of Write  
Address Hold after End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
25  
0
30  
0
AVWH  
AVEH  
t
t
t
AS  
AVWL  
AVEL  
t
t
t
0
0
WHAX  
EHAX  
WR  
h, i  
WLQZ  
t
t
13  
15  
WZ  
OW  
t
t
5
5
WHQX  
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.  
Note j: E or W must be ≥ VIH during address transitions.  
j
SRAM WRITE CYCLE #1: W Controlled  
12  
AVAV  
t
ADDRESS  
19  
WHAX  
14  
ELWH  
t
t
E
17  
AVWH  
t
18  
AVWL  
t
13  
WLWH  
t
W
15  
DVWH  
16  
WHDX  
t
t
DATA IN  
DATA VALID  
20  
WLQZ  
t
21  
WHQX  
t
HIGH IMPEDANCE  
DATA OUT  
PREVIOUS DATA  
SRAM WRITE CYCLE #2: E Controlledj  
12  
AVAV  
t
ADDRESS  
14  
ELEH  
18  
AVEL  
19  
t
EHAX  
t
t
E
17  
AVEH  
t
13  
WLEH  
t
W
15  
DVEH  
16  
t
EHDX  
t
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
August 1999  
6-4  
 
STK25CA8  
AutoStore™/POWER-UP RECALL  
(V = 5.0V 10%)  
CC  
SYMBOLS  
STK25CA8  
NO.  
PARAMETER  
UNITS NOTES  
Standard  
MIN  
MAX  
550  
10  
22  
23  
24  
25  
26  
t
t
t
Power-up RECALL Duration  
STORE Cycle Duration  
µs  
ms  
µs  
V
k
g
g
RESTORE  
STORE  
Time Allowed to Complete SRAM Cycle  
Low Voltage Trigger Level  
1
DELAY  
V
4.0  
4.5  
3.9  
SWITCH  
RESET  
V
Low Voltage Reset Level  
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH  
.
AutoStore™/POWER-UP RECALL  
V
CC  
5V  
25  
V
SWITCH  
26  
RESET  
V
AutoStore™  
23  
STORE  
t
POWER-UP RECALL  
24  
DELAY  
22  
RESTORE  
t
t
W
DQ (DATA OUT)  
POWER-UP  
RECALL  
BROWN OUT  
NO STORE DUE TO  
NO SRAM WRITES  
BROWN OUT  
AutoStore™  
BROWN OUT  
AutoStore™  
NO RECALL  
NO RECALL  
RECALL WHEN  
(VCC DID NOT GO  
(VCC DID NOT GO  
V
CC RETURNS  
BELOW VRESET  
)
BELOW VRESET)  
ABOVE VSWITCH  
August 1999  
6-5  
 
 
STK25CA8  
DEVICE OPERATION  
The STK25CA8 is a versatile memory module that  
provides two modes of operation. The STK25CA8  
can operate as a standard 128K x 8 SRAM. It has a  
128K x 8 EEPROM shadow to which the SRAM infor-  
mation can be copied, or from which the SRAM can  
be updated in nonvolatile mode.  
AutoStore™ OPERATION  
The STK25CA8 uses the intrinsic system capaci-  
tance to perform an automatic store on power down.  
As long as the system power supply takes at least  
tSTORE to decay from VSWITCH down to 3.6V the  
STK25CA8 will safely and automatically store the  
SRAM data in EEPROM on power down.  
NOISE CONSIDERATIONS  
In order to prevent unneeded STORE operations,  
automatic STOREs will be ignored unless at least  
one WRITE operation has taken place since the most  
recent STORE or RECALL cycle.  
Note that the STK25CA8 is a high-speed memory  
and so must have a high frequency bypass capaci-  
tor of approximately 0.1µF connected between VCC  
and VSS, using leads and traces that are as short as  
possible. As with all high-speed CMOS ICs, normal  
careful routing of power, ground and signals will help  
prevent noise problems.  
POWER-UP RECALL  
During power up, or after any low-power condition  
(VCC < VRESET), an internal RECALL request will be  
latched. When VCC once again exceeds the sense  
voltage of VSWITCH, a RECALL cycle will automatically  
be initiated and will take tRESTORE to complete.  
SRAM READ  
The STK25CA8 performs a READ cycle whenever E  
and G are low and W is high. The address specified  
on pins A0-16 determines which of the 131,072 data  
bytes will be accessed. When the READ is initiated  
by an address transition, the outputs will be valid  
after a delay of tAVQV (READ cycle #1). If the READ is  
initiated by E or G, the outputs will be valid at tELQV or  
at tGLQV, whichever is later (READ cycle #2). The data  
outputs will repeatedly respond to address changes  
within the tAVQV access time without the need for tran-  
sitions on any control input pins, and will remain valid  
until another address change or until E or G is  
brought high.  
If the STK25CA8 is in a WRITE state at the end of  
power-up RECALL, the SRAM data will be corrupted.  
To help avoid this situation, a 10K Ohm resistor  
should be connected either between W and system  
VCC or between E and system VCC.  
HARDWARE PROTECT  
The STK25CA8 offers hardware protection against  
inadvertent STORE operation and SRAM WRITEs dur-  
ing low-voltage conditions. When VCAP < VSWITCH, all  
externally initiated STORE operations and SRAM  
WRITEs are inhibited.  
SRAM WRITE  
LOW AVERAGE ACTIVE POWER  
A WRITE cycle is performed whenever E and W are  
low. The address inputs must be stable prior to  
entering the WRITE cycle and must remain stable  
until either E or W goes high at the end of the cycle.  
The data on the common I/O pins DQ0-7 will be writ-  
ten into the memory if it is valid tDVWH before the end  
of a W controlled WRITE or tDVEH before the end of an  
E controlled WRITE.  
The STK25CA8 draws significantly less current  
when it is cycled at times longer than 50ns. If the  
chip enable duty cycle is less than 100%, only  
standby current is drawn when the chip is disabled.  
The overall average current drawn by the  
STK25CA8 depends on the following items:  
1) CMOS vs. TTL input levels; 2) the duty cycle of  
chip enable; 3) the overall cycle rate for accesses;  
4) the ratio of READs to WRITEs; 5) the operating  
temperature; 6) the VCC level; and 7) I/O loading.  
It is recommended that G be kept high during the  
entire WRITE cycle to avoid data bus contention on  
the common I/O lines. If G is left low, internal circuitry  
will turn off the output buffers tWLQZ after W goes low.  
August 1999  
6-6  
STK25CA8  
ORDERING INFORMATION  
- D 45 I  
STK25CA8  
Temperature Range  
Blank = Commercial (0 to 70˚C)  
I = Industrial (–40 to 85˚C)  
Access Time  
35 = 35ns  
45 = 45ns  
Package  
D = 32-pin 600 mil Dual In-Line Module  
August 1999  
6-7  

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