U621708DC07G1 [SIMTEK]

128KX8 STANDARD SRAM, 70ns, PDIP32, 0.600 INCH, LEAD FREE, PLASTIC, DIP-32;


型号：	U621708DC07G1
厂家：	SIMTEK CORPORATION
描述：	128KX8 STANDARD SRAM, 70ns, PDIP32, 0.600 INCH, LEAD FREE, PLASTIC, DIP-32 静态存储器光电二极管内存集成电路
文件：	总10页 (文件大小：165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

U621708

128K x 8 SRAM

Features

Description

The U621708 is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

S 131072 x 8 bit static CMOS RAM

S 70 ns Access Time

S Common data inputs and

data outputs

available at the outputs DQ0-DQ7.

After the address change, the data

outputs go High-Z until the new

information is available. The data

outputs have no preferred state. If

the memory is driven by CMOS

levels in the active state, and if

there is no change of the address,

data input and control signals W or

G, the operating current (I_O= 0 mA)

drops to the value of the operating

current in the Standby mode. The

Read cycle is finished by the falling

edge of E2 or W, or by the rising

edge of E1, respectively.

- Read

- Write

- Standby

S Three-state outputs

S Typ. operating supply current

70 ns: 15 mA

- Data Retention

The memory array is based on a

6-Transistor cell.

S Standby current < 1 mA at 85°C

S TTL/CMOS-compatible

S Power supply voltage 5 V

S Operating temperature range

0 °C to 70 °C

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active.

During the active state (E1 = L and

E2 = H) each address change

leads to a new Read cycle. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word will be

-40 °C to 85 °C

S QS 9000 Quality Standard

S ESD protection > 750 V

(MIL STD 883C M3015.7)

S Latch-up immunity >100 mA

S Package: PDIP32 (600 mil)

SOP32 (450 mil)

Data retention is guaranteed down

to 2 V. With the exception of E1

and E2, all inputs consist of NOR

gates, so that no pull-up/pull-down

resistors are required.

TSOP I 32

sTSOP I 32

Pin Configuration

Pin Description

VCC

A15

n.c.

A16

A14

A12

A11

A10

A13

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name Signal Description

A13

A0 - A16

DQ0 - DQ7

Address Inputs

Data In/Out

A15

VCC

n.c.

A16

A14

A12

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

Power Supply Voltage

Ground

TSOP

PDIP

SOP

A11

sTSOP

A10

VSS

DQ2

DQ7

DQ1

DQ0

VCC

VSS

n.c.

DQ0

DQ1

DQ2

VSS

DQ6

DQ5

DQ4

DQ3

not connected

Top View

September 1, 2004

U621708

Block Diagram

A16

Memory Cell

Array

1024 Rows x

128 x 8 Columns

A10

A11

A12

DQ0

DQ1

DQ2

Sense Amplifier/

A13

A14

Write Control Logic

DQ3

DQ4

DQ5

A15

Address

Change

Detector

Clock

DQ6

DQ7

Generator

V_CC

V_SS

E1 E2

Truth Table

Operating Mode

DQ0 - DQ7

High-Z

Standby/not selected

Internal Read

Read

High-Z

Data Outputs Low-Z

Data Inputs High-Z

Write

H or L

September 1, 2004

U621708

Characteristics

All voltages are referenced to V_SS= 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V_I, as well as

input levels of V_IL= 0 V and V_IH= 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the t_dis-times and t_en-times, in which cases transition is measured ±200 mV from steady-state voltage.

Absolute Maximum Ratings

Symbol

Min.

Max.

Unit

Power Supply Voltage

Input Voltage

V_CC

V_I

-0.5

V_CC+ 0.5

Output Voltage

V_O

P_D

T_a

Power Dissipation

Operating Temperature

°C

C-Type

K-Type

-40

Storage Temperature

T_stg

-65

150

°C

Output Short-Circuit Current

| I_OS

200

at V_CC= 5 V and V_O= 0 V

Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating

only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

Maximum voltage is 7 V

Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Recommended

Symbol

V_CC

Conditions

Min.

4.5

Max.

5.5

Unit

Operating Conditions

Power Supply Voltage

Input Low Voltage

V_IL

-0.3

2.2

0.8

Input High Voltage

V_IH

V_CC+ 0.3

-2 V at Pulse Width 10 ns

September 1, 2004

U621708

Electrical Characteristics

Symbol

Conditions

Min.

Max.

Unit

Supply Current - Operating Mode

I_CC(OP)

V_CC

V_IL

= 5.5 V

= 0.8 V

= 2.2 V

V_IH

Supply Current - Standby Mode

(CMOS level)

I_CC(SB)

V_CC

= 5.5 V

= V

= V_CC- 0.2 V

V_CC

= V

Supply Current - Standby Mode

(TTL level)

I_CC(SB)1

= 5.5 V

= 2.2 V

Output High Voltage

Output Low Voltage

V_OH

V_OL

V_CC

I_OH

V_CC

I_OL

= 4.5 V

2.4

= -4.0 mA

= 4.5 V

0.4

= 8.0 mA

Input High Leakage Current

Input Low Leakage Current

I_IH

I_IL

V_CC

V_IH

V_CC

V_IL

= 5.5 V

µA

-2

0 V

Output High Current

Output Low Current

I_OH

I_OL

V_CC

V_OH

V_CC

V_OL

= 4.5 V

= 2.4 V

= 4.5 V

= 0.4 V

-4

Output Leakage Current

High at Three-State Outputs

I_OHZ

I_OLZ

V_CC

V_OH

V_CC

V_OL

= 5.5 V

µA

Low at Three-State Outputs

-2

0 V

September 1, 2004

U621708

Symbol

Alt.

t_RC

t_AA

t_ACE

t_OE

Switching Characteristics

Read Cycle

Unit

Min.

Max.

IEC

t_cR

Read Cycle Time

Address Access Time to Data Valid

Chip Enable Access Time to Data Valid

G LOW to Data Valid

t_a(A)

t_a(E)

t_a(G)

t_dis(E)

t_dis(G)

t_en(E)

t_en(G)

t_v(A)

E1 HIGH or E2 LOW to Output in High-Z

G HIGH to Output in High-Z

t_HZCE

t_HZOE

t_LZCE

t_LZOE

t_OH

E1 LOW or E2 HIGH to Output in Low-Z

G LOW to Output in Low-Z

Output Hold Time from Address Change

E1 LOW or E2 HIGH to Power-Up Time

E1 HIGH or E2 LOW to Power-Down Time

t_PU

t_PD

Symbol

Switching Characteristics

Write Cycle

Unit

Alt.

t_WC

IEC

t_cW

Min.

Max.

Write Cycle Time

Write Pulse Width

t_WP

t_w(W)

t_su(W)

t_su(A)

Write Setup Time

t_WP

Address Setup Time

t_AS

Address Valid to End of Write

Chip Enable Setup Time

Pulse Width Chip Enable to End of Write

Data Setup Time

t_AW

su(A-WH)

t_CW

t_su(E)

t_CW

t_w(E)

t_su(D)

t_h(D)

t_DS

Data Hold Time

t_DH

Address Hold from End of Write

W LOW to Output in High-Z

G HIGH to Output in High-Z

W HIGH to Output in Low-Z

G LOW to Output in Low-Z

W to Chip Enable Setup Time

t_AH

t_h(A)

t_HZWE

t_HZOE

t_LZWE

t_LZOE

t_dis(W)

t_dis(G)

t_en(W)

t_en(G)

su(W-E)

September 1, 2004

U621708

Data Retention Mode

Data Retention

Characteristics

Symbol

Conditions

Min. Typ. Max.

Unit

Alt.

IEC

V_CC(DR)

Data Retention Supply Voltage

Data Retention Supply Current

5.5

0.6

= 3 V

= V

I_CC(DR)

CC(DR)

- 0.2 V

CC(DR)

Data Retention Setup Time

Operating Recovery Time

t_CDR

t_R

t_su(DR)See Data Retention

Waveforms (below)

t_rec

t_cR

Data Retention Mode E1 - controlled

V_CC

4.5 V

_CC(DR)≥ 2 V

2.2 V

t_su(DR)

Data Retention

t_rec

0 V

≥ V

- 0.2 V or V

E1(DR)

≤ 0.2 V

E2(DR)

CC(DR)

E2(DR)

+ 0.3 V

CC(DR)

- 0.2 V ≤ V

≤ V

Data Retention Mode E2 - controlled

V_CC

4.5 V

0 V

_CC(DR)≥ 2 V

t_DR

Data Retention

t_rec

0.8 V

≥ V

- 0.2 V or V

≤ 0.2 V

E1(DR)

E2(DR)

CC(DR)

E1(DR)

≤ 0.2 V

September 1, 2004

U621708

Test Configuration for Functional Check

5 V

V_CC

DQ0

DQ1

481

V_IH

V_IL

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A10

A11

A12

A13

A14

A15

A16

V_O

30 pF ^e

255

V_SS

In measurement of t

, t

the capacitance is 5 pF.

dis(E) dis(W) en(E) en(W) en(G)

Capacitance

Conditions

Symbol

Min.

Max.

Unit

Input Capacitance

V_CC

V_I

= 5.0 V

= V_SS

C_I

= 1 MHz

= 25 °C

Output Capacitance

C_o

All pins not under test must be connected with ground by capacitors.

Ordering Code

Example

U621708

Type

Leadfree Option

blank= Standard Package

Package

G1 = Leadfree Green Package ^f

D = PDIP32 (600 mil)

S = SOP32 (450 mil)

T = TSOP I 32

T1 = sTSOP I 32

Access Time

07 = 70 ns

Operating Temperature Range

C = 0 to 70 °C

K = -40 to 85 °C

^fon special request

Device Marking (example)

ZMD

Product specification

Date of manufacture

U621708SK

(The first 2 digits indicating

the year, and the last 2

digits the calendar week.)

C 0425

Assembly location and

trace code

1 ZZ

Internal Code

Leadfree Green Package

September 1, 2004

U621708

Read Cycle 1: A_i-controlled (during Read Cycle : E1 = G = V_IL, W = E2 = V_IH)

t_cR

Address Valid

t_a(A)

DQi

Output Data Valid

Previous Data Valid

t_v(A)

Output

Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = V_IH)

t_cR

Addresses Valid

t_a(E)

t_en(E)

t_su(A)

t_dis(E)

t_a(E)

t_su(A)

t_en(E)

t_a(G)

t_dis(G)

t_en(G)

High-Z

DQi

Output Data Valid

Output

t_PU

t_PD

I_CC(OP)

I_CC(SB)

50 %

* The same applies to E1

Write Cycle1: W-controlled

t_cW

Addresses Valid

t_su(E)

t_h(A)

t_su(E)

t_su(W-E)

t_su(A)

t_w(W)

t_su(D)

t_h(D)

DQi

Input Data Valid

t_dis(W)

Input

t_en(W)

High-Z

DQi

Output

September 1, 2004

U621708

Write Cycle 2: E1-controlled

t_cW

Addresses Valid

t_w(E)

t_su(A)

t_h(A)

t_su(E)

t_su(W)

t_h(D)

t_su(D)

DQi

Input

Input Data Valid

t_dis(W)

t_dis(G)

t_en(E)

DQi

Output

High-Z

Write Cycle 3 (E2-controlled)

t_cW

Addresses Valid

t_su(E)

t_h(A)

t_w(E)

t_su(A)

t_su(W)

t_su(D)

t_h(D)

Input Data Valid

t_dis(W)

DQi

t_en(E)

Input

High-Z

t_dis(G)

DQi

Output

undefined

L- to H-level

H- to L-level

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design reserved.

September 1, 2004

U621708

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The information in this document describes the type of component and shall not be considered as assured charac-

teristics.

ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.

September 1, 2004

Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de

U621708DC07G1 [SIMTEK]

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