UL62H256BSK55G1 [SIMTEK]
Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOP-28;型号: | UL62H256BSK55G1 |
厂家: | SIMTEK CORPORATION |
描述: | Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.300 INCH, SOP-28 静态存储器 光电二极管 内存集成电路 |
文件: | 总10页 (文件大小:87K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UL62H256B
Low Voltage Automotive Fast 32K x 8 SRAM
Features
Description
The UL62H256B is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
F 32768 x 8 bit static CMOS RAM
F 35 and 55 ns Access Time
F Common data inputs and
data outputs
address change, the data outputs
go High-Z until the new information
is available. The data outputs have
no preferred state. The Read cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 1.5 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
F Three-state outputs
F Typ. operating supply current
35 ns: 45 mA
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
55 ns: 30 mA
F Standby current < 30 µA at 125 °C The circuit is activated by the fal-
F Power supply voltage 2.5 V
F Operating temperature range
-40 °C to 85 °C
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
-40 °C to 125 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity >100 mA
F Package: SOP28 (300/330 mil)
Pin Description
Pin Configuration
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A12
A7
2
W
3
A13
A8
A6
4
Signal Name Signal Description
A5
5
A9
A0 - A14
Address Inputs
Data In/Out
A4
6
A11
DQ0 - DQ7
A3
7
G
Chip Enable
E
A2
8
A10
Output Enable
Write Enable
Power Supply Voltage
Ground
G
SOP
A1
9
E
W
A0
DQ7
10
11
12
13
14
VCC
VSS
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
Top View
November 26, 2002
1
UL62H256B
Block Diagram
A6
A7
A8
A9
Memory Cell
Array
A10
A11
A12
A13
A14
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
DQ0
DQ1
Sense Amplifier/
Write Control Logic
DQ2
DQ3
DQ4
A5
DQ5
DQ6
DQ7
Address
Change
Detector
Clock
Generator
VCC
VSS
E
W
G
Truth Table
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
Internal Read
Read
H
L
L
L
*
*
H
L
*
High-Z
High-Z
H
H
L
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
2
November 26, 2002
UL62H256B
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 2.2 V. The timing reference level of all input and output signals is 1.1 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
-
4
VCC + 0.3
VCC + 0.3
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
°C
K-Type
A-Type
-40
-40
85
125
Storage Temperature
Tstg
-65
150
100
°C
Output Short-Circuit Current
at VCC = 2.5 V and VO = 0 V c
| IOS
|
mA
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 4 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Operating Conditions
Symbol
VCC
Conditions
Min.
2.3
Max.
2.7
Unit
V
Power Supply Voltage
Input Low Voltage d
Input High Voltage
VIL
-0.2
2.0
0.4
V
VIH
VCC + 0.2
V
d -2 V at Pulse Width 10 ns
November 26, 2002
3
UL62H256B
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
tcW
tcW
= 2.7 V
= 0.6 V
= 2.0 V
= 35 ns
= 55 ns
90
70
mA
mA
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
VE
= 2.7 V
= VCC - 0.2 V
K-Type
A-Type
6
30
µA
µA
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
VE
= 2.7 V
= 2.2 V
K-Type
A-Type
10
20
mA
mA
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 2.3 V
= -0.5 mA
= 2.3 V
2.0
V
V
0.4
2
= 0.5 mA
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 2.7 V
= 2.7 V
= 2.7 V
µA
µA
-2
=
0 V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 2.3 V
= 2.0 V
= 2.3 V
= 0.4 V
-0.5
mA
mA
0.5
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 2.7 V
= 2.7 V
= 2.7 V
2
µA
µA
Low at Three-State Outputs
-2
=
0 V
4
November 26, 2002
UL62H256B
Symbol
Alt.
tRC
tAA
tACE
tOE
35
55
Switching Characteristics
Read Cycle
Unit
IEC
tcR
Min.
Max.
Min.
Max.
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
ta(A)
35
35
15
12
12
55
55
25
15
15
ta(E)
ta(G)
tdis(E)
tdis(G)
ten(E)
ten(G)
tv(A)
E HIGH to Output in High-Z
G HIGH to Output in High-Z
E LOW to Output in Low-Z
G LOW to Output in Low-Z
Output Hold Time from Address Change
E LOW to Power-Up Time
tHZCE
tHZOE
tLZCE
tLZOE
tOH
3
0
3
0
3
0
3
0
tPU
E HIGH to Power-Down Time
tPD
35
55
Symbol
35
55
Switching Characteristics
Write Cycle
Unit
Min.
35
20
20
0
Max.
Min.
55
35
35
0
Max.
Alt.
tWC
IEC
tcW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
tWP
tw(W)
tsu(W)
tsu(A)
Write Setup Time
tWP
Address Setup Time
tAS
t
Address Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable to End of Write
Data Setup Time
tAW
25
25
25
15
0
40
40
40
25
0
su(A-WH)
tCW
tsu(E)
tCW
tw(E)
tsu(D)
th(D)
tDS
Data Hold Time
tDH
Address Hold from End of Write
W LOW to Output in High-Z
G HIGH to Output in High-Z
W HIGH to Output in Low-Z
G LOW to Output in Low-Z
tAH
th(A)
0
0
tHZWE
tHZOE
tLZWE
tLZOE
tdis(W)
tdis(G)
ten(W)
ten(G)
15
12
20
15
0
0
0
0
November 26, 2002
5
UL62H256B
Data Retention Mode
E - controlled
VCC
2.3 V
VCC(DR) ≥ 1.5 V
2.0 V
2.0 V
tsu(DR)
trec
Data Retention
E
0 V
V
- 0.2 V ≤ V
≤ V
+ 0.3 V
CC(DR)
E(DR)
CC(DR)
Data Retention
Characteristics
Symbol
Alt. IEC
VCC(DR)
ICC(DR) VCC(DR) = 2V
Conditions
Min. Typ. Max.
Unit
Data Retention Supply Voltage
Data Retention Supply Current
1.5
V
VE
= VCC(DR) - 0.2 V
K-Type
A-Type
5
20
µA
µA
Data Retention Setup Time
Operating Recovery Time
tCDR
tR
tsu(DR) See Data Retention
0
ns
ns
Waveforms (above)
trec
tcR
Test Configuration for Functional Check
2.5 V
VCC
A0
A1
A2
A3
A4
DQ0
DQ1
DQ2
DQ3
3332
A5
A6
VIH
A7
A8
A9
DQ4
DQ5
DQ6
DQ7
A10
A11
A12
A13
A14
VIL
VO
30 pF e
E
W
G
3077
VSS
e
In measurement of t
,t
, t
, t
, t
the capacitance is 5 pF.
6
dis(E) dis(W) en(E) en(W) en(G)
November 26, 2002
UL62H256B
Capacitance
Conditions
Symbol
Min.
Max.
Unit
Input Capacitance
VCC = 2.5 V
CI
7
7
pF
VI
f
= VSS
= 1 MHz
= 25 °C
Output Capacitance
Co
pF
T
a
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
UL62H256B S
35
A
Internal Code
Type
Access Time
Package
S = SOP28 (300 mil)
S2 = SOP28 (330 mil) Type 2
35 = 35 ns
55 = 55 ns
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digits indicating the year,
and the last 2 digits the calendar week.
Assembly location and trace code are shown in line 4.
November 26, 2002
7
UL62H256B
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
tcR
Ai
Address Valid
ta(A)
DQi
Output
Previous Data Valid
tv(A)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH)
tcR
Ai
E
Address Valid
ta(E)
tdis(E)
tsu(A)
ten(E)
tdis(G)
ta(G)
G
ten(G)
DQi
Output
High-Z
tPU
Output Data Valid
tPD
ICC(OP)
ICC(SB)
50 %
50 %
8
November 26, 2002
UL62H256B
Write Cycle1: W-controlled
tcW
Ai
Address Valid
tsu(E)
th(A)
E
tsu(A-WH)
tw(W)
W
tsu(A)
tsu(D)
Input Data Valid
ten(W)
th(D)
DQi
Input
tdis(W)
DQi
High-Z
Output
G
Write Cycle 2: E-controlled
tcW
Ai
E
Address Valid
tw(E)
tsu(A)
th(A)
tsu(W)
W
tsu(D)
th(D)
DQi
Input
Input Data Valid
tdis(W)
ten(E
)
DQi
High-Z
Output
tdis(G)
G
undefined
L- to H-level
H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
November 26, 2002
9
UL62H256B
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
November 26, 2002
Zentrum Mikroelektronik Dresden AG
Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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