SP509CF-L [SIPEX]
Line Transceiver, 8 Func, 8 Driver, 8 Rcvr, BICMOS, PQFP100, LEAD FREE, MS-026BED, LQFP-100;
| 型号： | SP509CF-L |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Line Transceiver, 8 Func, 8 Driver, 8 Rcvr, BICMOS, PQFP100, LEAD FREE, MS-026BED, LQFP-100 驱动 信息通信管理 接口集成电路 驱动器 |
| 文件： | 总29页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
SP509
Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver
with Programmable DCE/DTE and Termination Resistors
FEATURES
■ Ultra Fast 40Mbps Differential Transmission Rates Available
■ Improved ESD Tolerance for Analog I/Os with 15kV HBM.
■ Internal Transceiver Termination Resistors for V.11 and V.35
■ Interface Modes:
Now Available in Lead Free Packaging
■ RS-232 (V.28)
■ X.21 (V.11)
■ RS-449/V.36
(V.10 & V.11)
■ EIA-530 (V.10 & V.11)
■ EIA-530A (V.10 & V.11)
■ V.35
Refer to page 7 for pinout
■ Protocols are Software Selectable with 3-Bit Word
■ Eight (8) Drivers and Eight (8) Receivers
APPLICATIONS
■ V.35 and V.11 Receiver Termination Network Disable Option
■ Internal Line or Digital Loopback for Diagnostic Testing
■ Adheres to NET1/NET2 and TBR-2 Compliancy Requirements
■ Easy Flow-Through Pinout
■ Router
■ Frame Relay
■ CSU
■ DSU
■ +5V Only Operation
■ PBX
■ Individual Driver and Receiver Enable/Disable Controls
■ Operates in either DTE or DCE Mode
■ Secure Communication Terminals
DESCRIPTION
The SP509 is a monolithic device that supports eight (8) popular serial interface standards for
Wide Area Network (WAN) connectivity. The SP509 is fabricated using a low power BiCMOS
process technology, and incorporates a Sipex regulated charge pump allowing +5V only
operation. Sipex's patented charge pump provides a regulated output of +5.8V, which will
provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8)
receiverscanbeconfiguredviasoftwareforanyoftheaboveinterfacemodesatanytime. The
SP509 requires no additional external components for compliant operation for all of the eight
(8) modes of operation other than four capacitors used for the internal charge pump. All
necessaryterminationisintegratedwithintheSP509andisswitchablewhenV.35driversand
V.35 receivers, or when V.11 receivers are used. The SP509 provides the controls and
transceiver availability for operating as either a DTE or DCE.
Additional features with the SP509 include internal loopback that can be initiated in any of the
operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are
internally connected to driver inputs creating an internal signal path bypassing the serial
communications controller for diagnostic testing. The SP509 also includes a latch enable pin
with the driver and receiver address decoder. The internal V.11 or V.35 receiver termination
can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8)
drivers and receivers in the SP509 include separate enable pins for added convenience. The
SP509 is ideal for WAN serial ports in networking equipment such as routers, concentrators,
network muxes, DSU/CSU's, networking test equipment, and other access devices.
Applicable U.S. Patents-5,306,954; and others patents pending
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
STORAGE CONSIDERATIONS
Duetotherelativelylargepackagesizeofthe100-pinquadflat-
pack, storage in a low humidity environment is preferred. Large
highdensityplasticpackagesaremoisturesensitiveandshould
be stored in Dry Vapor Barrier Bags. Prior to usage, the parts
should remain bagged and stored below 40°C and 60%RH. If
the parts are removed from the bag, they should be used within
48 hours or stored in an environment at or below 20%RH. If the
above conditions cannot be followed, the parts should be
bakedforfourhoursat125°Cinorderto remove moisture prior
to soldering. Sipex ships the 100-pin LQFP in Dry Vapor
Barrier Bags with a humidity indicator card and desiccant pack.
The humidity indicator should be below 30%RH.
These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated in the
operation sections of the specifications below is not implied.
Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
VCC ................................................................................................ +7V
Input Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ............................................. -0.3V to (VCC+0.5V)
Receivers ........................................................... ±15.5V
Output Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ................................................................... ±12V
Receivers ........................................ -0.3V to (VCC+0.5V)
Storage Temperature ................................................ -65°C to +150°C
Power Dissipation ................................................................. 1520mW
(derate 19.0mW/°C above +70°C)
Package Derating:
øJA ................................................................................................................. 52.7 °C/W
øJC .................................................................................................................... 6.5 °C/W
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
LOGIC INPUTS
VIL
VIH
0.8
Volts
Volts
2.0
LOGIC OUTPUTS
VOL
VOH
0.4
Volts
Volts
IOUT= –3.2mA
IOUT= 1.0mA
2.4
V.28 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
Loaded Voltage
Short-Circuit Current
Power-Off Impedance
AC Parameters
Outputs
±15
±15
±100
Volts
Volts
mA
per Figure 1
per Figure 2
per Figure 4, VOUT=0V
per Figure 5
VCC = +5V for AC parameters
±5.0
300
Ω
Transition Time
Instantaneous Slew Rate
Propagation Delay
tPHL
1.5
30
µs
V/µs
per Figure 6; +3V to -3V
per Figure 3
0.5
0.5
1
1
5
5
µs
µs
tPLH
Max.Transmission Rate
120
230
kbps
V.28 RECEIVER
DC Parameters
Inputs
Input Impedance
Open-Circuit Bias
HIGH Threshold
LOW Threshold
AC Parameters
Propagation Delay
tPHL
3
7
+2.0
3.0
kΩ
per Figure 7
per Figure 8
Volts
Volts
Volts
1.7
1.2
0.8
VCC = +5V for AC parameters
50
50
100
100
500
500
ns
ns
tPLH
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
V.28 RECEIVER (continued)
AC Parameters (cont.)
Max.Transmission Rate
120
235
kbps
V.10 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
±4.0
±6.0
Volts
Volts
mA
per Figure 9
per Figure 10
per Figure 11
per Figure 12
Test-Terminated Voltage 0.9VOC
Short-Circuit Current
Power-Off Current
AC Parameters
±150
±100
µA
VCC = +5V for AC parameters
Outputs
Transition Time
200
ns
per Figure 13; 10% to 90%
Propagation Delay
tPHL
tPLH
30
30
100
100
500
500
ns
ns
Max.Transmission Rate
120
kbps
V.10 RECEIVER
DC Parameters
Inputs
Input Current
Input Impedance
Sensitivity
–3.25
4
+3.25
mA
kΩ
Volts
per Figures 14 and 15
±0.3
AC Parameters
Propagation Delay
tPHL
VCC = +5V for AC parameters
50
50
ns
ns
tPLH
Max.Transmission Rate
120
kbps
V.11 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
Test Terminated Voltage
±6.0
Volts
Volts
Volts
Volts
Volts
mA
per Figure 16
per Figure 17
±2.0
0.5VOC
0.67VOC
±0.4
+3.0
±150
±100
Balance
Offset
Short-Circuit Current
Power-Off Current
AC Parameters
Outputs
per Figure 17
per Figure 17
per Figure 18
per Figure 19
µA
VCC = +5V for AC parameters
Transition Time
Propagation Delay
tPHL
10
ns
per Figures 21 and 36; 10% to 90%
Using CL = 50pF;
per Figures 33 and 36
per Figures 33 and 36
per Figures 33 and 36
30
30
2
50
50
5
ns
ns
ns
tPLH
Differential Skew
(|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
40
–7
Mbps
ns
2
V.11 RECEIVER
DC Parameters
Inputs
Common Mode Range
Sensitivity
+7
±0.2
Volts
Volts
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
3
ELECTRICAL SPECIFICATIONS
TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted.
MIN.
TYP.
MAX.
UNITS
CONDITIONS
V.11 RECEIVER (continued)
DC Parameters (cont.)
Input Current
–3.25
±3.25
mA
per Figure 20 and 22;
power on or off
Current w/100Ω Termination
Input Impedance
AC Parameters
Propagation Delay
tPHL
±60.75
mA
kΩ
per Figure 23 and 24
4
VCC = +5V for AC parameters
Using CL = 50pF;
per Figures 33 and 38
per Figures 33 and 38
per Figure 33
30
30
2
50
50
5
ns
ns
ns
Mbps
ns
tPLH
Skew (|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
40
2
V.35 DRIVER
DC Parameters
Outputs
Test Terminated Voltage
Offset
±0.44
±0.66
±0.6
+0.2VST
150
165
Volts
Volts
Volts
Ω
per Figure 25
per Figure 25
per Figure 25; VST = Steady state value
per Figure 27; ZS = V2/V1 x 50
per Figure 28
Output Overshoot
Source Impedance
Short-Circuit Impedance
AC Parameters
Outputs
-0.2VST
50
135
Ω
VCC = +5V for AC parameters
Transition Time
Propagation Delay
tPHL
7
20
ns
per Figure 29; 10% to 90%
30
30
2
50
50
5
ns
ns
ns
per Figures 33 and 36; CL = 20pF
per Figures 33 and 36; CL = 20pF
per Figures 33 and 36; CL = 20pF
tPLH
Differential Skew
(|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
40
Mbps
ns
2
V.35 RECEIVER
DC Parameters
Inputs
Sensitivity
±50
+100
110
165
mV
Ω
Ω
Source Impedance
Short-Circuit Impedance
AC Parameters
Propagation Delay
tPHL
90
135
per Figure 30; ZS = V2/V1 x 50Ω
per Figure 31
VCC = +5V for AC parameters
30
30
2
50
50
5
ns
ns
ns
Mbps
ns
per Figures 33 and 38; CL = 20pF
per Figures 33 and 38; CL = 20pF
per Figure 33; CL = 20pF
tPLH
Skew (|tPHL - tPLH|)
Max.Transmission Rate
Channel to Channel Skew
40
2
TRANSCEIVER LEAKAGE CURRENT
Driver Output 3-State Current
Rcvr Output 3-State Current
500
1
µA
µA
per Figure 32; Drivers disabled
TX & RX disabled, 0.4V - VO - 2.4V
10
POWER REQUIREMENTS
VCC
4.75
5.00
1
95
230
270
170
200
5.25
Volts
µA
mA
mA
mA
mA
mA
ICC (Shutdown Mode)
(V.28/RS-232)
(V.11/RS-422)
(EIA-530 & RS-449)
(V.35)
All ICC values are with VCC = +5V
fIN = 120kbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loaded
V.35 @ fIN = 10Mbps, V.28 @ 20kbps
fIN = 10Mbps; Drivers active & loaded
(EIA-530A)
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
4
OTHER AC CHARACTERISTICS
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
0.11
0.11
0.05
0.05
5.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
RS-423/V.10
tPZL; Tri-state to Output LOW
0.07
0.05
0.55
0.12
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
CL = 100pF, Fig. 34 & 40; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
RS-422/V.11
tPZL; Tri-state to Output LOW
0.04
0.05
0.03
0.11
10.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 37; S1
closed
CL = 100pF, Fig. 34 & 37; S2
closed
CL = 15pF, Fig. 34 & 37; S1
closed
CL = 15pF, Fig. 34 & 37; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
V.35
tPZL; Tri-state to Output LOW
0.85
0.36
0.06
0.05
10.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 37; S1
closed
CL = 100pF, Fig. 34 & 37; S2
closed
CL = 15pF, Fig. 34 & 37; S1
closed
CL = 15pF, Fig. 34 & 37; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
0.05
0.05
0.65
0.65
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 40; S1
closed
CL = 100pF, Fig. 35 & 40; S2
closed
CL = 100pF, Fig. 35 & 40; S1
closed
CL = 100pF, Fig. 35 & 40; S2
closed
RS-423/V.10
tPZL; Tri-state to Output LOW
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 40; S1
closed
CL = 100pF, Fig. 35 & 40; S2
closed
CL = 100pF, Fig. 35 & 40; S1
closed
CL = 100pF, Fig. 35 & 40; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
5
OTHER AC CHARACTERISTICS (Continued)
TA = +25°C and VCC = +5.0V unless otherwise noted.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
RS-422/V.11
tPZL; Tri-state to Output LOW
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 39; S1
closed
CL = 100pF, Fig. 35 & 39; S2
closed
CL = 15pF, Fig. 35 & 39; S1
closed
CL = 15pF, Fig. 35 & 39; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
V.35
tPZL; Tri-state to Output LOW
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 39; S1
closed
CL = 100pF, Fig. 35 & 39; S2
closed
CL = 15pF, Fig. 35 & 39; S1
closed
CL = 15pF, Fig. 35 & 39; S2
closed
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
TRANSCEIVER TO TRANSCEIVER SKEW
(per Figures 32, 33, 36, 38)
RS-232 Driver
100
100
20
20
2
ns
ns
ns
ns
ns
ns
[ (tphl
[ (tplh
[ (tphl
[ (tphl
[ (tphl
[ (tplh
)
Tx1 – (tphl
Tx1 – (tplh
)
)
]
Txn
Txn
)
]
RS-232 Receiver
RS-422 Driver
)
Rx1 – (tphl
Rx1 – (tphl
Tx1 – (tphl
Tx1 – (tplh
)
)
]
]
Rxn
)
Rxn
)
)
)
]
Txn
Txn
2
)
]
RS-422 Receiver
RS-423 Driver
2
3
5
ns
ns
ns
[ (tphl
[ (tphl
[ (tphl
)
)
– (tphl
)
)
]
]
Rxn
RRxx11 – (tphl
Rxn
]
)
Tx2 – (tphl
Tx2 – (tplh
)
Txn
Txn
5
5
5
2
2
ns
ns
ns
ns
ns
[ (tplh
[ (tphl
[ (tphl
[ (tphl
[ (tplh
)
)
]
RS-423 Receiver
V.35 Driver
)
Rx2 – (tphl
Rx2 – (tphl
)
)
]
]
Rxn
)
Rxn
)
Tx1 – (tphl
Tx1 – (tplh
)
)
]
Txn
Txn
)
]
V.35 Receiver
2
2
ns
ns
[ (tphl
[ (tphl
)
)
– (tphl
)
)
]
]
Rxn
Rxn
RRxx11 – (tphl
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
6
PINOUT 100 PIN LQFP
VCC
GND
1
2
3
4
5
6
7
8
9
75 TR(a)
74 GND
SDEN
TTEN
STEN
RSEN
TREN
RRCEN
RLEN
73 VDD
72 C1+
71 VCC
70 C2+
®
69 C1-
68 GND
67 C2-
LLEN 10
RDEN 11
RTEN 12
TXCEN 13
CSEN 14
DMEN 15
RRTEN 16
ICEN 17
66 VSS
65 RL(a)
64 VCC
63 LL(a)
62 TM(a)
61 IC(a)
60 RRT(a)
59 RRT(b)
58 V10GND
57 DM(a)
56 DM(b)
55 CS(a)
54 CS(b)
53 TXC(a)
52 GND
51 TXC(b)
SP509
TMEN 18
D0 19
D1 20
D2 21
TERM_OFF 22
D_LATCH 23
N/C 24
GND 25
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
7
PIN DESCRIPTION
Pin Number Pin Name Description
Pin Number Pin Name Description
1
VCC
GND
5V Power Supply Input
Signal Ground
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TxC(b)
GND
TxC Non-Inverting Input
Signal Ground
2
3
SDEN
TTEN
STEN
RSEN
TREN
RRCEN
RLEN
LLEN#
RDEN#
RTEN#
TxCEN#
CSEN#
DMEN#
RRTEN#
ICEN#
TMEN
D0
TxD Driver Enable Input
TxCE Driver Enable Input
ST Driver Enable Input
RTS Driver Enable Input
DTR Driver Enable Input
DCD Driver Enable Input
RL Driver Enable Input
LL Driver Enable Input
RxD Receiver Enable Input
RxC Receiver Enable Input
TxC Receiver Enable Input
CTS Receiver Enable Input
DSR Receiver Enable Input
DCDDTE Receiver Enable Input
RI Receiver Enable Input
TM Receiver Enable Input
Mode Select Input
TxC(a)
CS(b)
CS(a)
DM(b)
DM(a)
GNDV10
RRT(b)
RRT(a)
IC
TxC Inverting Input
4
CTS Non-Inverting Input
CTS Inverting Input
DSR Non-Inverting Input
DSR Inverting Input
V.10 Rx Reference Node
DCDDTE Non-Inverting Input
DCDDTE Inverting Input
RI Receiver Input
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TM(a)
LL(a)
VCC
TM Receiver Input
LL Driver Output
Power Supply Input
RL Driver Output
RL(a)
VSS1
C2N
-2xVCC Charge Pump Output
Charge Pump Capacitor
Signal Ground
GND
C1N
Charge Pump Capacitor
Charge Pump Capacitor
Power Supply Input
Charge Pump Capacitor
2xVCC Charge Pump Output
Signal Ground
D1
Mode Select Input
C2P
D2
Mode Select Input
VCC
TERM_OFF Termination Disable Input
D_LATCH# Decoder Latch Input
C1P
VDD
NC
No Connect
GND
GND
VCC
Signal Ground
TR(a)
NC
DTR Inverting Output
No Connect
5V Power Supply Input
LOOPBACK# Loopback Mode Enable Input
VCC
Power Supply Input
DTR Non-Inverting Output
DCD Non-Inverting Output
Power Supply Input
DCD Inverting Output
Signal Ground
TxD
TxCE
ST
TxD Driver TTL Input
TxCE Driver TTL Input
ST Driver TTL Input
RTS Driver TTL Input
DTR Driver TTL Input
TR(b)
RRC(b)
VCC
RTS
DTR
RRC(a)
GND
DCD_DCE DCDDCE Driver TTL Input
RS(a)
VCC
RTS Inverting Output
Power Supply Input
RTS Non-Inverting Output
Signal Ground
RL
LL
RL Driver TTL Input
LL Driver TTL Input
RS(b)
GND
RxD
RxC
TxC
CTS
DSR
RxD Receiver TTL Output
RxC Receiver TTLOutput
TxC Receiver TTL Output
CTS Receiver TTL Output
DSR Receiver TTL Output
ST(a)
VCC
ST Inverting Output
Power Supply Input
V35TGND3 ST Termination Referance
ST(b)
GND
TT(a)
VCC
ST Non-Inverting Output
Signal Ground
DCD_DTE DCDDTE Receiver TTL Output
RI
RI Receiver TTL Output
TM Receiver TTL Output
Signal Ground
TxCE Inverting Output
5V Power Supply Input
TM
GND
VCC
V35TGND2 ST Termination Referance
Power Supply Input
TT(b)
GND
SD(a)
VCC
TxCE Non-Inverting Output
Signal Ground
V35RGND Reciever Termination Refrence
RD(b)
RD(a)
RT(b)
RT(a)
RXD Non-Inverting Input
RXD Inverting Input
TxD Inverting Output
5V Power Supply Input
RxC Non-Inverting Input
RxC Inverting Input
V35TGND1 ST Termination Referance
SD(b)
TxD Non-Inverting Output
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
8
SP509 Driver Table
RS-232
Mode
(V.28)
RS-449
Mode
(V.36)
Driver Output
Pin
EIA-530
Mode
EIA-530A
Mode
X.21 Mode
(V.11)
Suggested
Signal
V.35 Mode
Shutdown
MODE (D0, D1, D2)
T1OUT(a)
T1OUT(b)
T2OUT(a)
T2OUT(b)
T3OUT(a)
T3OUT(b)
T4OUT(a)
T4OUT(b)
T5OUT(a)
T5OUT(b)
T6OUT(a)
T6OUT(b)
T7OUT(a)
T8OUT(a)
001
V.35
010
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
011
V.28
100
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
High-Z
V.11
V.11
V.10
V.10
101
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
110
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
High-Z
High-Z
111
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
TxD(a)
TxD(b)
V.35
High-Z
V.28
V.35
TxCE(a)
TxCE(b)
TxC_DCE(a)
TxC_DCE(b)
RTS(a)
V.35
High-Z
V.28
V.35
V.35
High-Z
V.28
V.28
High-Z
V.28
High-Z
V.28
RTS(b)
DTR(a)
High-Z
V.28
High-Z
V.28
DTR(b)
DCD_DCE(a)
DCD_DCE(b)
RL
High-Z
V.28
High-Z
V.28
V.28
V.28
LL
Table 1. Driver Mode Selection
SP509 Receiver Table
RS-232
Mode
(V.28)
RS-449
Mode
(V.36)
Receiver Input
V.35 Mode
Pin
EIA-530
Mode
EIA-530A
Mode
X.21 Mode
(V.11)
Suggested
Signal
Shutdown
MODE (D0, D1, D2)
R1IN(a)
R1IN(b)
R2IN(a)
R2IN(b)
R3IN(a)
R3IN(b)
R4IN(a)
R4IN(b)
R5IN(a)
R5IN(b)
R6IN(a)
R6IN(b)
R7IN(a)
R8IN(a)
001
V.35
010
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
011
V.28
100
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
High-Z
V.11
V.11
V.10
V.10
101
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.10
V.10
110
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
High-Z
High-Z
111
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
RxD(a)
RxD(b)
V.35
High-Z
V.28
V.35
RxC(a)
V.35
High-Z
V.28
RxC(b)
V.35
TxC_DTE(a)
TxC_DTE(b)
CTS(a)
V.35
High-Z
V.28
V.28
High-Z
V.28
High-Z
V.28
CTS(b)
DSR(a)
High-Z
V.28
High-Z
V.28
DSR(b)
DCD_DTE(a)
DCD_DTE(b)
RI
High-Z
V.28
High-Z
V.28
V.28
V.28
TM
Table 2. Receiver Mode Selection
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
9
TEST CIRCUITS
A
A
VOC
VT
3kΩ
C
C
Figure 1. V.28 Driver Output Open Circuit Voltage
Figure 2. V.28 Driver Output Loaded Voltage
A
A
Oscilloscope
VT
Isc
7kΩ
C
C
Scope used for slew rate
measurement.
Figure 3. V.28 Driver Output Slew Rate
Figure 4. V.28 Driver Output Short-Circuit Current
V
= 0V
CC
A
A
Ix
±2V
Oscilloscope
3kΩ
2500pF
C
C
Figure 6. V.28 Driver Output Rise/Fall Times
Figure 5. V.28 Driver Output Power-Off Impedance
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
10
A
A
Iia
±15V
voc
C
C
Figure 7. V.28 Receiver Input Impedance
Figure 8. V.28 Receiver Input Open Circuit Bias
A
A
VOC
Vt
3.9kΩ
450Ω
C
C
Figure 9. V.10 Driver Output Open-Circuit Voltage
Figure 10. V.10 Driver Output Test Terminated Voltage
V
= 0V
CC
A
A
Ix
±0.25V
Isc
C
C
Figure 11. V.10 Driver Output Short-Circuit Current
Figure 12. V.10 Driver Output Power-Off Current
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
11
A
A
Iia
±10V
Oscilloscope
450Ω
C
C
Figure 13. V.10 Driver Output Transition Time
Figure 14. V.10 Receiver Input Current
A
V.10 RECEIVER
VOCA
+3.25mA
+10V
VOC
3.9kΩ
VOCB
-10V
-3V
B
+3V
Maximum Input Current
vesus Voltage
C
-3.25mA
Figure 15. V.10 Receiver Input IV Graph
Figure 16. V.11 Driver Output Open-Circuit Voltage
A
A
Isa
50Ω
50Ω
VT
Isb
B
V
B
OS
C
C
Figure 17. V.11 Driver Output Test Terminated Voltage
Figure 18. V.11 Driver Output Short-Circuit Current
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
12
V
= 0V
CC
A
Iia
±10V
A
Ixa
±0.25V
B
B
C
C
V
= 0V
CC
A
A
±10V
±0.25V
Iib
Ixb
B
B
C
C
Figure 19. V.11 Driver Output Power-Off Current
Figure 20. V.11 Receiver Input Current
A
V.11 RECEIVER
+3.25mA
+10V
50Ω
Oscilloscope
50Ω
-10V
-3V
B
VE
50Ω
+3V
C
Maximum Input Current
vesus Voltage
-3.25mA
Figure 22. V.11 Receiver Input IV Graph
Figure 21. V.11 Driver Output Rise/Fall Time
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
13
V.11 RECEIVER
w/ Optional Cable Termination
(100Ω to 150Ω)
A
Iia
i [mA] = V [V] / 0.1
±6V
i [mA] = V [V] - 3) / 4.0
100Ω to
150Ω
-6V
-3V
+3V
+6V
B
i [mA] = V [V] - 3) / 4.0
C
Maximum Input Current
versus Voltage
i [mA] = V [V] / 0.1
Figure 24. V.11 Receiver Input Graph w/ Termination
A
A
±6V
50Ω
100Ω to
150Ω
VT
50Ω
Iib
VOS
B
B
C
C
Figure 23. V.11 Receiver Input Current w/ Termination
Figure 25. V.35 Driver Output Test Terminated Voltage
V1
A
A
50Ω
50Ω
VT
24kHz, 550mV
p-p
Sine Wave
V2
50Ω
VOS
B
B
C
C
Figure 26. V.35 Driver Output Offset Voltage
Figure 27. V.35 Driver Output Source Impedance
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
14
A
A
50Ω
50Ω
Oscilloscope
ISC
B
B
50Ω
±2V
C
C
Figure 29. V.35 Driver Output Rise/Fall Time
Figure 28. V.35 Driver Output Short-Circuit Impedance
V1
A
A
50Ω
24kHz, 550mV
p-p
Sine Wave
V2
Isc
B
B
±2V
C
C
Figure 30. V.35 Receiver Input Source Impedance
Figure 31. V.35 Receiver Input Short-Circuit Impedance
Any one of the three conditions for disabling the driver.
1
1
1
VCC = 0V
D1
D0
D2
C
C
L1
A
VCC
B
A
IZSC
±12V
B
A
TIN
ROUT
L2
15pF
Logic “1”
B
fIN (50% Duty Cycle, 2.5V
)
P-P
Figure 33. Driver/Receiver Timing Test Circuit
Figure 32. Driver Output Leakage Current Test
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
15
1KΩ
Test Point
Receiver
Output
V
CC
V
CC
S
S
1
S
S
1
500Ω
Output
Under
Test
C
RL
1KΩ
C
L
2
2
Figure 35. Receiver Timing Test Load Circuit
Figure 34. Driver Timing Test Load Circuit
f > 10MHz; t < 10ns; t < 10ns
R F
+3V
DRIVER
INPUT
1.5V
1.5V
0V
t
t
PHL
PLH
A
1/2V
1/2V
O
O
DRIVER
OUTPUT
V
O
B
+
t
t
DPHL
DPLH
DIFFERENTIAL
OUTPUT
V
V
O
0V
–
V – V
O
B
A
t
R
t
F
t
t t
| DPLH - DPHL |
SKEW =
Figure 36. Driver Propagation Delays
Mx or Tx_Enable
+3V
0V
1.5V
1.5V
tZL
2.3V
tLZ
5V
A, B
A, B
Output normally LOW
Output normally HIGH
0.5V
0.5V
VOL
VOH
2.3V
tZH
0V
tHZ
Figure 37. Driver Enable and Disable Times
f > 10MHz; t < 10ns; t < 10ns
R
F
+
–
V
V
0D2
0V
0V
A – B
INPUT
OUTPUT
0D2
V
OH
(VOH - VOL)/2
(VOH - VOL)/2
RECEIVER OUT
V
OL
t
t
PHL
PLH
tSKEW
tPHL tPLH
- |
= |
Figure 38. Receiver Propagation Delays
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
16
f = 1MHz; tR < 10ns; tF < 10ns
1.5V
DECx +3V
1.5V
0V
5V
RCVRENABLE
tZL
1.5V
tLZ
RECEIVER OUT
Output normally LOW
Output normally HIGH
0.5V
0.5V
VIL
VIH
RECEIVER OUT
1.5V
tZH
0V
tHZ
Figure 39. Receiver Enable and Disable Times
f = 60kHz; t < 10ns; t < 10ns
R
F
+3V
Tx_Enable
0V
1.5V
1.5V
t
LZ
t
ZL
0V
T
OUT
V
0.5V
-
OL
V
0.5V
-
OL
V
OL
Output LOW
f = 60kHz; t < 10ns; t < 10ns
R
F
+3V
1.5V
1.5V
t
Tx_Enable
0V
t
HZ
ZH
Output HIGH
V
OH
V
OH - 0.5V
T
OUT
0V
Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
17
Figure 42. Typical V.10 Driver Output Waveform
Figure 41. Typical V.28 Driver Output Waveform
Figure 43. Typical V.11 Driver Output Waveform
Figure 44. Typical V.35 Driver Output Waveform
Figure 45. Typical V.11 Driver Output Waveform at 20MHz
Figure 46. Typical V.35 Driver Output Waveform at 20 MHz
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
18
+5V (decoupling capacitor not shown)
1µF
1µF
1µF
V
C1+
C1-
C2+
C2-
CC
V
SS
V
DD
Regulated Charge Pump
1µF
V35RGND
TxD
RD(a)
SD(a)
V35TGND1
SD(b)
RxD
RDEN
SDEN
RD(b)
RT(a)
TxCE
TT(a)
V35TGND2
TT(b)
RxC
RTEN
RT(b)
TTEN
TxC(a)
ST
ST(a)
TxC
TxCEN
V35TGND3
ST(b)
TxC(b)
CS(a)
STEN
RTS
RS(a)
CTS
CSEN
RS(b)
RSEN
CS(b)
DM(a)
DTR
TR(a)
DSR
DMEN
TR(b)
TREN
DM(b)
RRT(a)
DCD_DCE
RRC(a)
DCD_DTE
RRTEN
RRC(b)
RRCEN
RRT(b)
IC
RL
RI
ICEN
RL(a)
RLEN
LL
TM
TM
TMEN
LL(a)
LLEN
D0
D1
D2
SP509
V.10-GND
D-LATCH
TERM-OFF
LOOPBACK
GND
RECEIVER TERMINATION NETWORK
V.35 DRIVER TERMINATION NETWORK
51ohms
V.35 MODE
V.11 MODE
51ohms
124ohms
124ohms
V.35 MODE
TX ENABLE
RX ENABLE
51ohms
51ohms
Figure 47. Functio nal Diagram
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
19
FEATURES
There are four basic types of driver circuits –
ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423),
ITU-T-V.11 (RS-422), and CCITT-V.35.
The SP509 contains highly integrated serial
transceivers that offer programmability between
interface modes through software control. The
SP509 offers the hardware interface modes for
RS-232 (V.28), RS-449/V.36 (V.11 and V.10),
EIA-530 (V.11 and V.10), EIA-530A (V.11 and
V.10), V.35 (V.35 and V.28) and X.21(V.11). The
interface mode selection is done via three control
pins, which can be latched via microprocessor
control.
The V.28 (RS-232) drivers output single-ended
signals with a minimum of +5V (with 3kΩ &
2500pF loading), and can operate over 120kbps.
Since the SP509 uses a charge pump to generate
the RS-232 output rails, the driver outputs will
never exceed +10V. The V.28 driver architecture
is similar to Sipex's standard line of RS-232
transceivers.
The SP509 has eight drivers, eight receivers, and
Sipex'spatentedon-boardchargepump(5,306,954)
that is ideally suited for wide area network
connectivityandothermulti-protocolapplications.
Other features include digital and line loopback
modes, individual enable/disable control lines for
each driver and receiver, fail-safe when inputs are
either open or shorted, individual termination
resistor ground paths, separate driver and receiver
groundoutputs,enhancedESDprotectionondriver
outputs and receiver inputs.
The RS-423 (V.10) drivers are also single-ended
signals which produce open circuit V and VOH
measurementsof+4.0Vto+6.0V.WhenOtLerminated
with a 450Ω load to ground, the driver output will
not deviate more than 10% of the open circuit
value. This is in compliance of the ITU V.10
specification. The V.10 (RS-423) drivers are used
in RS-449/V.36, EIA-530, and EIA-530A modes
as Category II signals from each of their
corresponding specifications. The V.10 drivers
are guaranteed to transmit over 120kbps, but can
operate at over 1Mbps if necessary.
THEORY OF OPERATION
The SP509 device is made up of 1) the drivers, 2)
the receivers, 3) a charge pump, 4) DTE/DCE
switching algorithm, and 5) control logic.
The third type of drivers are V.11 (RS-422)
differentialdrivers.Duetothenatureofdifferential
signaling, the drivers are more immune to noise as
opposed to single-ended transmission methods.
The advantage is evident over high speeds and
long transmission lines. The strength of the driver
outputs can produce differential signals that can
maintain +2V differential output levels with a load
of 100Ω. The signal levels and drive capability of
these drivers allow the drivers to also support
RS-485 requirements of +1.5V differential output
levels with a 54Ω load. The strength allows the
SP509 differential driver to drive over long cable
lengthswithminimalsignaldegradation.TheV.11
drivers are used in RS-449, EIA-530, EIA-530A
and V.36 modes as Category I signals which are
used for clock and data. Sipex's new driver design
over its predecessors allow the SP509 to operate
over 40Mbps for differential transmission.
Drivers
TheSP509haseightenhancedindependentdrivers.
Control for the mode selection is done via a three-
bit control word into D0, D1, and D2. The drivers
are prearranged such that for each mode of
operation, the relative position and functionality
of the drivers are set up to accommodate the
selectedinterfacemode.Asthemodeofthedrivers
ischanged,theelectricalcharacteristicswillchange
to support the required signal levels. The mode of
each driver in the different interface modes that
can be selected is shown in Table 1.
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
20
The fourth type of drivers are V.35 differential
drivers. There are only three available on the
SP509 for data and clock (TxD, TxCE, and TxC
in DCE mode). These drivers are current sources
that drive loop current through a differential pair
resulting in a 550mV differential voltage at the
receiver. These drivers also incorporate fixed
termination networks for each driver in order to
settheV andVOL dependingonloadconditions.
This terOmHination network is basically a “Y”
configuration consisting of two 51Ω resistors
connectedinseriesanda124Ωresistorconnected
between the two 50Ω resistors and a V35TGND
output.Eachofthethreedriversanditsassociated
termination will have its own V35TGND output
forgroundingconvenience.Filteringcanbedone
on these pins to reduce common mode noise
transmitted over the transmission line by
connecting a capacitor to ground.
protocols of the receivers. Table 1 shows
the mode of each receiver in the different
interface modes that can be selected. There are
twobasictypesofreceivercircuits—ITU-T-V.28
(RS-232) and ITU-T-V.11, (RS-422).
The RS-232 (V.28) receiver is single-ended and
accepts RS-232 signals from the RS-232 driver.
The RS-232 receiver has an operating input
voltage range of +15V and can receive signals
downs to +3V. The input sensitivity complies
with RS-232 and V .28 at +3V. The input
impedance is 3kΩ to 7kΩ in accordance to RS-
232 and V .28. The receiver output produces a
TTL/CMOS signal with a +2.4V minimum for
alogic“1”anda+0.4Vmaximumforalogic“0”.
TheRS-232(V.28)protocolusesthesereceivers
for all data, clock and control signals. They are
also used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The RS-232 receivers
can operate over 120kbps.
The drivers also have separate enable pins
which simplifies half-duplex configurations for
some applications, especially programmable
DTE/DCE. The enable pins will either enable or
disable the output of the drivers according to the
appropriateactivelogicillustratedonFigure47.
The enable pins have internal pull-up and pull-
down devices, depending on the active polarity
ofthereceiver,thatenablethedriveruponpower-
on if the enable lines are left floating. During
disabled conditions, the driver outputs will be at
a high impedance 3-state.
The second type of receiver is a differential type
that can be configured internally to support
ITU-T-V.10 and CCITT-V.35 depending on its
input conditions. This receiver has a typical
input impedance of 10kΩ and a differential
threshold of less than +200mV, which complies
with the ITU-T-V.11 (RS-422) specifications.
V.11 receivers are used in RS-449/V.36,
EIA-530, EIA-530A and X.21 as Category I
signalsforreceivingclock,data,andsomecontrol
line signals not covered by Category II V.10
circuits. The differential V.11 transceiver has
improved architecture that allows over 40Mbps
transmission rates.
The driver inputs are both TTL or CMOS
compatible. All driver inputs have an internal
pull-up resistor so that the output will be at a
defined state at logic LOW (“0”). Unused driver
inputs can be left floating. The internal pull-up
resistor value is approximately 500kΩ.
Receivers dedicated for data and clock (RxD,
RxC, TxC) incorporate internal termination for
V.11. The termination resistor is typically 120Ω
connected between the A and B inputs. The
termination is essential for minimizing crosstalk
and signal reflection over the transmission line .
The minimum value is guaranteed to exceed
100Ω,thuscomplyingwiththeV.11andRS-422
specifications. This resistor is invoked when the
receiverisoperatingasaV.11receiver,inmodes
EIA-530, EIA-530A, RS-449/V.36, and X.21.
Receivers
The SP509 has eight enhanced independent
receivers. Control for the mode selection is done
viaathree-bitcontrolwordthatisthesameasthe
driver control word. Therefore, the modes for
the drivers and receivers are identical in the
application.
Like the drivers, the receivers are prearranged
for the specific requirements of the synchronous
serial interface. As the operating mode of the
receiversischanged,theelectricalcharacteristics
willchangetosupporttherequiredserialinterface
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
21
Thesamereceiversalsoincorporateatermination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51Ω resistors
connectedinseriesanda124Ωresistorconnected
between the two 50Ω resistors and V35RGND
output.TheV35RGNDisusuallygrounded.The
receiver itself is identical to the V.11 receiver.
CHARGE PUMP
The charge pump is a Sipex-patented design
(5,306,954)andusesauniqueapproachcompared
to older less-efficient designs. The charge pump
still requires four external capacitors, but uses
four-phase voltage shifting technique to attain
symmetrical power supplies. The charge pump
V
and VSS outputs are regulated to +5.8V and
-5D.8DV, respectively. There is a free-running
oscillator that controls the four phases of the
voltage shifting. A description of each phase
follows.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
1Mbps and are used in RS-449/V.36, E1A-530,
E1A-530AandX.21modesasCategoryIIsignals
asindicatedbytheircorrespondingspecifications.
All receivers include an enable/disable line for
disablingthereceiveroutputallowingconvenient
half-duplex configurations. The enable pins will
eitherenableordisabletheoutputofthereceivers
according to the appropriate active logic
illustrated on Figure 47. The receiver’s enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of the
receiver,thatenablesthereceiveruponpowerup
iftheenablelinesareleftfloating.Duringdisabled
conditions, the receiver outputs will be at a high
impedance state. If the receiver is disabled any
associatedterminationisalsodisconnectedfrom
the inputs.
Phase 1
__VSS charge storage ——During this phase of
the clock cycle, the positive side of capacitors C1
and C2 are initially charged to VCC. C+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to VCC,
the voltage potential across capacitor C2 is now
2XVCC.
Phase 2
—VSS transfer—Phasetwooftheclockconnects
the negative terminal of C2 to the V storage
capacitor and the positive terminal SSof C2 to
ground, and transfers the negative generated
voltagetoC .Thisgeneratedvoltageisregulated
to –5.8V. S3imultaneously, the positive side of
the capacitor C1 is switched to VCC and the
negative side is connected to ground.
Phase 3
—VDD charge storage —The third phase of the
clock is identical to the first phase—the charge
transferred in C1 produces –VCC in the negative
terminal of C1 which is applied to the negative
side of the capacitor C2 . Since C2+ is at VCC, the
voltage potential across C2 is 2XVCC.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
areinternal5kΩpull-downresistorsontheinputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
Phase 4
—VDD transfer —The fourth phase of the clock
connects the negative terminal of C2 to ground,
and transfers the generated 5.8V across C2 to C4,
the VDD storage capacitor. This voltage is
regulated to +5.8V. At the regulated voltage, the
internaloscillatorisdisabledandsimultaneously
with this, the positive side of capacitor C1 is
switchedtoVCC andthenegativesideisconnected
toground,andthecyclebeginsagain.Thecharge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
22
Since both V+ and V- are separately generated
from VCC; in a no-load condition V+ and V- will
be symmetrical. Older charge pump approaches
that generate V- from V+ will show a decrease in
the magnitude of V- compared to V+ due to the
inherent inefficiencies in the design.
There are internal pull-up devices on D0, D1,
and D2, which allow the device to be in
SHUTDOWN mode (“111”) upon power up.
However , if the device is powered -up with the
D_LATCH at a logic HIGH, the decoder state of
the SP509 will be undefined.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 1µF with a 16V breakdown voltage
rating.
ESD TOLERANCE
TheSP509 deviceincorporatesruggedizedESD
cells on all driver output and receiver input
pins. The ESD structure is improved over our
previous family for more rugged applications
and environments sensitive to electrostatic
discharges and associated transients.
TERM_OFF FUNCTION
The SP509 contains a TERM_OFF pin that
disables all three receiver input termination
networks regardless of mode. This allows the
device to be used in monitor mode applications
typically found in networking test equipment.
The TERM_OFF pin internally contains a
pull-down device with an impedance of over
500kΩ, which will default in a “ON” condition
during power-up if V.35 receivers are used. The
individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Sipex’s previous multi-protocol
serial transceiver IC’s the drivers and receivers
have been designed to meet all the requirements
to NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy. The SP509 is also
tested in-house at Sipex and adheres to all the
NET1/2physicallayertestingandtheITUSeries
V specifications before shipment. Please note
thatalthoughtheSP509,aswithitspredecessors,
adhere to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for details.
LOOPBACK FUNCTION
The SP509 contains a LOOPBACK pin that
invokes a loopback path. This loopback path is
illustrated in Figure 48. LOOPBACK has an
internal pull-up resistor that defaults to normal
modeduringpoweruporifthepinisleftfloating.
During loopback, the driver output and receiver
input characteristics will still adhere to its
appropriate specifications.
DECODER AND D_LATCH FUNCTION
TheSP509containsaD_LATCHpinthatlatches
the data into the D0, D1, and D2 decoder inputs.
If tied to a logic LOW (“0”), the latch is
transparent, allowing the data at the decoder
inputs to propagate through and program
the SP509 accordingly. If tied to a logic
HIGH(“1”), the latch locks out the data and
prevents the mode from changing until this pin
is brought to a logic LOW.
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
23
SD(a)
SD(b)
RD(a)
TxD
RxD
RD(b)
TT(a)
TxCE
TT(b)
RT(a)
RxC
ST
RT(b)
ST(a)
ST(b)
TxC(a)
TxC(b)
RS(a)
TxC
RTS
CTS
DTR
RS(b)
CS(a)
CS(b)
TR(a)
TR(b)
DM(a)
DSR
DM(b)
RRC(a)
DCD_DCE
RRC(b)
RRT(a)
RRT(b)
DCD_DTE
RL
RI
RL(a)
IC
LL
LL(a)
TM
TM(a)
Figure 48. SP509 Loopback Path
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
24
1µF
1µF
1µF
Vcc
+
10µF
73
VDD
72
C1+
69
70
67
1µF
C1- C2+ C2-
66
VCC
VSS
CIRCUIT #
Serial Port Connector Pins
2
TxD_RXD_A
28
97 SD(a)
100 S(b)
92 TT(a)
#103
14
TxD_RXD_B
TxD
24
11
TxCE_TXC_A
TXCE_TXC_B
29
#113
#113
TxCE
95 TT(b)
87 ST(a)
30
ST
90 ST(b)
83 RS(a)
85 RS(b)
75 TR(a)
78 TR(b)
4
RTS_CTS_A
RTS_CTS_B
31
#105
#108
19
RTS
20
23
DTR_DSR_A
DTR_DSR_B
32
DTR
33
81 RRC(a)
79 RRC(b)
#109
#140
#141
DCD_DCE
34
21
18
RL_RI
LL_TM
RL
65 RL(a)
35
LL
63 LL(a)
SP509
3
RXD_TXD_A
RXD_TXD_B
36
48 RD(a)
#105
#115
#114
RxD
16
47 RD(b)
17
9
RXC_TXCE_A
RXC_TXCE_B
37
50 RT(a)
49 RT(b)
RxC
15
12
TXC_RXC_A
TXC_RXC_B
38
53 TxC(a)
51 TxC(b)
55 CS(a)
54 CS(b)
TxC
5
CTS_RTS_A
CTS_RTS_B
39
#106)
#107
13
CTS
6
DSR_DTR_A
DSR_DTR_B
40
57 DM(a)
56 DM(b)
22
DSR
8
DCD_DCD_A
DCD-DCD-B
41
60 RRT(a)
59 RRT(b)
#109
#125
10
DCD_DTE
42
22
25
RI_RL
LL_TM
RI
61 IC
43
#142
TM
62 TM
Logic Section
D0 19
3
4
5
SDEN
Vcc
TTEN
STEN
D1 20
D2 21
DCE/DTE
6
7
8
9
RSEN
TREN
RRCEN
RLEN
LOOPBACK 27
Vcc
LATCH 23
10 LLEN
TERM_OFF 22
11 RDEN
12 RTEN
13 TxCEN
* - Driver applies for DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
Driver applies for DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
V35TGND1 99
V35TGND2 94
14 CSEN
15 DMEN
35TGND3 89
V35RGND 46
16 RRTEN
17 ICEN
18 TMEN
Input Line
Output Line
Bi-directional Bus.
V10_GND 58
Figure 49. Configuring SP509 to Operate as either DCE or DTE
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
25
PACKAGE: 100 Pin LQFP
D
0.2 RAD MAX.
D1
c
0.08 RAD MIN.
PIN 1
11°-13°
0°MIN
E1
C
L
E
0°–7°
11°-13°
L
L1
C
L
A2
A
Seating
Plane
A1
b
e
DIMENSIONS
Minimum/Maximum
(mm)
100–PIN LQFP
JEDEC MS-026
(BED) Variation
COMMON DIMENSIONS
SYMBL MIN NOM MAX
c
L
0.09
0.20
SYMBOL
MIN
NOM MAX
1.60
0.45 0.60 0.75
1.00 REF
A
A1
A2
b
L1
0.05
1.35
0.17
0.15
1.40
0.22
1.45
0.27
D
16.00 BSC
14.00 BSC
0.50 BSC
16.00 BSC
14.00 BSC
100
D1
e
E
E1
N
100 PIN LQFP
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
26
DCE CONFIGURATION
SP508 Multiprotocol Configured as DCE
Interface to Port-
Connector
Recommended Signals and Port Pin Assignments
Interface to System Logic
Pin
RS-232 or V.24
EIA-530
RS-449
V.35
X.21
Pin
Pin Mnemonic Number
Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15
Number Pin Mnemonic
Circuit
Type
V.28
nic
BB
Pin(F) Type
nic
Pin(F) Type
nic
Pin(F) Type
nic
Pin(F) Type
nic
Pin(F)
4
11
7**
14**
6
13
5
12
28
3
29
4
30
5
31
6
32
7
33
8
34
9
35
10
36
11
37
12
38
13
39
14
40
15
41
16
42
17
43
18
TxD
SDEN
TxCE
TTEN
ST
STEN
RTS
RSEN
DTR
TREN
DCD_DCE
RRCEN
RL
Driver_1
SD(A)
SD(B)
TT(A)
97
100
92
95
87
90
83
85
75
78
81
79
65
3
V.11 BB(A)
V.11 BB(B)
V.11 DD(A)
V.11 DD(B)
V.11 DB(A)
V.11 DB(B)
V.11 CB(A)
V.11 CB(B)
V.11 CC(A)
V.11 CC(B)
V.11 CF(A)
V.11 CF(B)
3
V.11 RD(A)
V.11 RD(B)
V.11 RT(A)
V.11 RT(B)
6
24
8
26
5
23
9
V.35
V.35
V.35
V.35
V.35
V.35
V.28
104
104
115
115
114
114
106
R
T
V
X
Y
V.11
V.11
V.11
V.11
V.11
V.11
V.11
V.11
R(A)
R(B)
B(A)
B(B)
S(A)
S(B)
I(A)
16
17
9
Driver_2
Driver_3
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
DD
DB
CB
CC
CF
CE
TM
BA
DA
17
15
5
TT(B)
ST(A)
ST(B)
RS(A)
RS(B)
TR(A)
TR(B)
RRC(A)
RRC(B)
RL(A)
15
12
5
13
6
22
8
10
V.11
V.11
ST(A)
ST(B)
AA
D
Driver_4
V.11 CS(A)
V.11 CS(B)
V.11 DM(A)
V.11 DM(B)
V.11 RR(A)
V.11 RR(B)
27
11
29
13
31
I(B)
Driver_5
6
V.28
V.28
V.28
V.28
107
109
125
142
E
F
Driver_6
8
Driver_7
22
25
2
J
RLEN
LL
Driver_8
LL(A)
63
V.10
TM
25
V.10
TM
18
NN
LLEN#
RxD
RDEN#
RxC
RTEN#
TxC
TxCEN#
CTS
CSEN#
DSR
DMEN#
DCD_DTE
RRTEN#
RI
Receiver_1
Receiver_2
Receiver_3
Receiver_4
Receiver_5
Receiver_6
Receiver_7
Receiver_8
RD(A)
RD(B)
RT(A)
RT(B)
TxC(A)
TxC(B)
CS(A)
CS(B)
DM(A)
DM(B)
RRT(A)
RRT(B)
IC
48
47
50
49
53
51
55
54
57
56
60
59
61
V.11 BA(A)
V.11 BA(B)
V.11 DA(A)
V.11 DA(B)
2
V.11 SD(A)
V.11 SD(B)
V.11
V.11
4
V.35
V.35
V.35
V.35
103
103
113
113
P
S
U
V.11
V.11
V.11
V.11
T(A)
T(B)
X(A)
X(B)
2
9
7**
14**
12
24
11
22
17
35
24
TT(A)
TT(B)
W
V.28
V.28
CA
CD
4
V.11 CA(A)
V.11 CA(B)
V.11 CD(A)
V.11 CD(B)
4
V.11 RS(A)
V.11 RS(B)
V.11 TR(A)
V.11 TR(B)
7
V.28
V.28
105
108
C
H
V.11
V.11
C(A)
C(B)
3
10
19
20
23
25
12
30
20
V.28
V.28
RL
LL
21
18
V.10
V.10
RL
LL
21
18
V.10
V.10
RL
LL
14
10
V.28
V.28
140
141
N
L
ICEN#
TM
TM(A)
62
TMEN
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
Pin assignments and signal functions are subject to national or regional variation and
proprietary / non-standard implementations
** X.21 use either B() or
X(), not both
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
27
DTE CONFIGURATION
SP508 Multiprotocol Configured as DTE
Interface to Port-
Connector
Recommended Signals and Port Pin Assignments
Interface to System Logic
RS-232 or V.24
EIA-530
RS-449
V.35
X.21
AppleTalk™
Pin
Pin
Pin Mnemonic Number
Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34
Signal Mnemo DB-15 Signal Mnemo DIN-8
Number Pin Mnemonic
28
3
29
4
30
5
31
6
32
7
33
8
34
9
35
10
36
11
37
12
38
13
39
14
40
15
41
16
42
17
43
18
Circuit
Driver_1
Type
V.28
nic
BA
Pin(M) Type
nic
BA(A)
BA(B)
Pin(M)
2
14
24
11
Type
V.11 SD(A)
V.11 SD(B)
V.11
V.11
nic
Pin(M)
4
22
17
35
Type
V.35
V.35
V.35
V.35
nic
103
103
113
113
Pin(M) Type
P
S
U
W
nic
Pin(M)
2
9
7**
14**
Type
V.11
V.11
nic
TxD -
TxD +
Pin(F)
3
6
TxD
SDEN
TxCE
TTEN
ST
STEN
RTS
RSEN
DTR
TREN
DCD_DCE
RRCEN
RL
RLEN
LL
LLEN#
RxD
RDEN#
RxC
RTEN#
TxC
TxCEN#
CTS
CSEN#
DSR
DMEN#
DCD_DTE
RRTEN#
RI
SD(A)
SD(B)
TT(A)
97
100
92
95
87
90
83
85
75
78
81
79
65
2
V.11
V.11
V.11
V.11
V.11
V.11
T(A)
T(B)
X(A)
X(B)
Driver_2
Driver_3
V.28
DA
24
V.11 DA(A)
V.11 DA(B)
TT(A)
TT(B)
TT(B)
ST(A)
ST(B)
RS(A)
RS(B)
TR(A)
TR(B)
RRC(A)
RRC(B)
RL(A)
Driver_4
V.28
V.28
CA
CD
4
V.11 CA(A)
V.11 CA(B)
4
V.11 RS(A)
V.11 RS(B)
V.11 TR(A)
V.11 TR(B)
7
V.28
V.28
105
108
C
H
V.11
V.11
C(A)
C(B)
3
10
19
20
23
25
12
30
Driver_5
20 V.11/10 CD(A)
V.11/Z CD(B)
V.10
HSKo
1
Driver_6
Driver_7
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
V.28
RL
LL
21
18
3
V.10
V.10
RL
LL
21
18
V.10
V.10
RL
LL
14
10
V.28
V.28
140
141
N
L
Driver_8
LL(A)
63
Receiver_1
Receiver_2
Receiver_3
Receiver_4
Receiver_5
Receiver_6
Receiver_7
Receiver_8
RD(A)
RD(B)
RT(A)
RT(B)
TxC(A)
TxC(B)
CS(A)
CS(B)
DM(A)
DM(B)
RRT(A)
RRT(B)
IC
48
47
50
49
53
51
55
54
57
56
60
59
61
BB
DD
DB
CB
CC
CF
CE
TM
V.11
V.11
BB(A)
BB(B)
3
16
17
9
15
12
5
13
6
22 ‡
8
V.11 RD(A)
V.11 RD(B)
V.11 RT(A)
V.11 RT(B)
V.11 ST(A)
V.11 ST(B)
V.11 CS(A)
V.11 CS(B)
V.11 DM(A)
V.11 DM(B)
V.11 RR(A)
V.11 RR(B)
6
24
8
26
5
23
9
27
11
29
13
31
V.35
V.35
V.35
V.35
V.35
V.35
V.28
104
104
115
115
114
114
106
R
T
V
X
Y
V.11
V.11
R(A)
R(B)
4
11
V.11
V.11
RxD-
RxD+
5
8
17
15
5
V.11 DD(A)
V.11 DD(B)
V.11 DB(A)
V.11 DB(B)
V.11 CB(A)
V.11 CB(B)
V.11/10 CC(A)
V.11/Z CC(B)
V.11
V.11
V.11
V.11
V.11
V.11
S(A)
S(B)
I(A)
I(B)
B(A)
B(B)
6
13
5
12
7**
14**
AA
D
GND
HSKi
GPi
V.10*
V.10
2
7
6
V.28
V.28
V.28
V.28
107
109
125
142
E
F
8
V.11
V.11
V.10
CF(A)
CF(B)
RI
10
22 ‡
22
25
J
ICEN#
TM
TMEN
TM(A)
62
V.10
TM
25
V.10
TM
18
NN
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
Pin assignments and signal functions are subject to national or regional variation and proprietary
/ non-standard implementations
** X.21 use either B() or
X(), not both
‡ EIA-530 uses V.11 (differential) for DSR (CC) and DTR (CD) signals; EIA-530-A uses single-
ended V.10 for DSR and DTR and adds RI signal on pin 22
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
28
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP509CF ...............................................0°C to +70°C ............................................................ 100 Lead LQFP
Available in lead free packaging. To order add “-L” suffix to part number.
Example: SP509CF = standard; SP509CF-L = lead free
REVISION HISTORY
DATE
3/31/04
6/14/04
8/19/04
REVISION
DESCRIPTION
A
B
C
Implemented tracking revision.
Added tables to pages 27 and 28.
Corrected pin description table and figure 49. Updated DCE/DTE
tables.
8/19/04
D
Corrected reference to figure 48.
Corporation
ANALOGEXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 1/19/05
SP509 Enhanced WAN Multi–Protocol Serial Transceiver
© Copyright 2005 Sipex Corporation
29
相关型号：
SP509_05
Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors
SIPEX
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