SP6136ER1-L [SIPEX]
Switching Controller, Voltage-mode, 2A, 680kHz Switching Freq-Max, 3 X 3 MM, ROHS COMPLIANT, MO-220VEED-4, QFN-16;
| 型号： | SP6136ER1-L |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Switching Controller, Voltage-mode, 2A, 680kHz Switching Freq-Max, 3 X 3 MM, ROHS COMPLIANT, MO-220VEED-4, QFN-16 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 |
| 文件： | 总18页 (文件大小：826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP6136
Synchronous Buck Controller
FEATURES
■ 5V to 24V Input step down converter
■ Up to 7A output in a small form factor
■ Highly integrated design, minimal components
■ UVLO Detects Both VCC and VIN
■ Overcurrent circuit protection with auto-restart
■ Power Good Output, ENABLE Input
■ Maximum Controllable Duty Cycle Ratio up to 92%
■ Wide BW amp allows Type II or III compensation
■ Programmable Soft Start
13
16
15
14
1
2
3
4
12
11
10
9
GH
GL
PGND
GND
SP6136
SWN
ISP
16 Pin QFN
3mm x 3mm
V
ISN
FB
■ Fast Transient Response
■ Available in Lead Free, RoHS Compliant
ꢀ6-Pin QFN package
5
6
7
8
■ External Driver Enable/Disable
■ U.S. Patent #6,922,04ꢀ
DESCRIPTION
The SP6ꢀ36 is a synchronous step-down switching regulator controller optimized for high
efficiency. The part is designed to be especially attractive for single supply step down con-
version from 5V to 24V. The SP6ꢀ36 is designed to drive a pair of external NFETs using
a fixed 600 KHz frequency, PWM voltage mode architecture. Protection features include
UVLO, thermal shutdown, output short circuit protection, and overcurrent protection with
auto restart. The device also features a PWRGD output and an enable input. The SP6ꢀ36
is available in a space saving ꢀ6-pin QFN and offers excellent thermal performance.
TYPICAL APPLICATION CIRCUIT
VIN
C3
0.1uF
CIN
22uF
12V
DBST
CVCC
4.7uF
CBST
0.1uF
SD101AWS
MT, Si4354DY
18.5 mΩ, 30V
GND
VIN
BST
GH
VCC
Inter-Technical SC7232-2R2
2.2uH, 13A, 10.4mΩ
R5 10kΩ
VOUT
PWRGD
UVIN
SWN
POWERGOOD
MB, Si4886DY
13.5 mΩ, 30V
RS1
5.11KΩ
RS2
5.11KΩ
COUT
100uF
NC
SP6136
EN
3.3V
0-7A
ENABLE
GND
GL
RS3
10KΩ
ISP
GND
PGND
COMP
CSP
6.8nF
ISN
SS
CS
0.1uF
VFB
CSS
47nF
CP1
12 pF
R1
68.1kΩ, 1%
CZ3
270pF
RZ3
1kΩ
R2
21.5kΩ, 1%
CF1
22pF
CZ2
560pF
RZ2
30.9kΩ
Note: Die attach paddle is internally connected to GND.
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
Peak Output Current < 10µs
GH,GL ............................................................................................. 2A
VCC .................................................................................................. 6V
VIN .............................................................................................. 24.5V
BST................................................................................................ 30V
BST-SWN........................................................................................ 7V
SWN ....................................................................................-2V to 24V
GH ..........................................................................-0.3V to BST+0.3V
GH-SWN.......................................................................................... 6V
Storage Temperature................................................... -65°C to 150°C
Power Dissipation........................................................................... ꢀW
ESD Rating........................................................................... 2kV HBM
Thermal Resistance.............................................................. 41.9°C/W
All other pins............................................................-0.3V to VCC+0.3V
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC
= ꢀ0µF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = 10KΩ.
PARAMETER
MIN TYP MAX UNITS CONDITIONS
QUIESCENT CURRENT
VIN Supply Current
ꢀ.5
ꢀ.5
0.2
3.0
3.0
0.4
mA
mA
mA
VFB = ꢀV (no switching)
VFB = ꢀV (no switching)
VFB = ꢀV (no switching)
VCC Supply Current
BST Supply Current
PROTECTION: UVLO
VCC UVLO Start
Threshold
4.00
4.25
4.5
V
VCC UVLO Hysteresis
UVIN Start Threshold
UVIN Hysteresis
ꢀ50
2.35
200
9.0
200
2.50
300
9.5
250
2.65
400
mV
V
Apply voltage to UVIN pin
Apply voltage to UVIN pin
UVIN Floating
mV
V
VIN Start Threshold
VIN Hysteresis
ꢀ0.0
300
0.4
mV
µA
UVIN Floating
Enable Pullup Current
Apply voltage to EN pin
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference 0.792 0.800 0.808
V
V
2X Gain Config.
Error Amplifier Reference
Over Line and Tempera- 0.788 0.800 0.8ꢀ2
ture
COMP Sink Current
70
-230
ꢀ
ꢀ50
-ꢀ50
50
230
-70
µA
µA
nA
COMP Source Current
VFB Input Bias Current
ꢀ00
COMP Common Mode
Output Range
ꢀ.9
3.2
3.0
3.5
3.2
3.8
V
V
COMP Pin Clamp
Voltage
VFB = 0.7V
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0V, UVIN = 3.0V,
CVCC = 0.ꢀµF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN TYP MAX UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Offset
ꢀ.7
2.0
ꢀ.0
50
2.3
ꢀ.20
ꢀ00
V
V
TA = 25˚C
Ramp Amplitude
0.80
GH Minimum Pulse Width
ns
Maximum Controllable Duty
Ratio
92
%
Guaranteed by
design
Maximum Duty Ratio
ꢀ00
520
%
Internal Oscillator Frequency
TIMERS: SOFTSTART
SS Charge Current:
600
680
kHz
-ꢀ6
ꢀ.0
-ꢀ0
2.0
-4
µA
SS Discharge Current:
3.0
mA
Fault Present
VCC LINEAR REGULATOR
VIN = 6 to 23V,
ILOAD = 0mA to 30mA
VCC Output Voltage
4.6
5.0
5.4
V
Dropout Voltage
250
500
750
mV
IVCC = 30mA
POWER GOOD OUTPUT
Power Good Threshold
-ꢀ0
-7.5
2.0
-5
%
%
Power Good Hysteresis
Power Good Sink Current
4.0
VFB = 0.7V,
VPWRGD = 0.2V
ꢀ.0
ꢀ0
mA
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold
Voltage
Measured VREF
(0.8V) - VFB
0.2
0.25
0.3
V
Overcurrent Threshold
Voltage
54
60
66
mV
Measured ISP - ISN
ISP, ISN Common Mode
Range
0
3.3
ꢀ30
ꢀ55
3.3
V
Hiccup Timeout
90
ꢀꢀ0
ꢀ45
ꢀ0
ms
˚C
˚C
Thermal Shutdown
Temperature
ꢀ35
Thermal Hysteresis
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
3
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC
= 0.ꢀµF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN TYP MAX UNITS CONDITIONS
OUTPUT: NFET GATE DRIVERS
GH & GL Rise Times
GH & GL Fall Times
35
30
50
40
ns
ns
Measured ꢀ0% to 90%
Measured 90% to ꢀ0%
GH & GL Measured at
2.0V
GL to GH Non Overlap Time
45
25
50
70
40
85
ns
ns
SWN to GL Non Overlap
Time
Measured SWN =
ꢀ00mV to GL = 2.0V
GH & GL Pull Down
Resistance
ꢀ5
KΩ
Driver Pull Down Resistance
Driver Pull Up Resistance
ꢀ.5
2.5
ꢀ.9
3.9
Ω
Ω
BLOCꢀ DIAGRAM
VCC
NON SYNCH. STARTUP
COMPARATOR
5
COMP
SS
GL HOLD OFF
1.6 V
VFBINT
13 BST
PWM LOOP
4
VFB
VCC
GmERROR AMPLIFIER
RESET
DOMINANT
VCC
12 GH
FAULT
Gm
R
10 uA
VPOS
POS REF
QPWM
11 SWN
Q
SOFTSTART INPUT
0.1V
SYNCHRONOUS
SS
8
DRIVER
FAULT
S
1
GL
FAULT
600 kHZ
2
PGND
RAMP = 1V
1.3 V
CLK
CLOCK PULSE GENERATOR
2.8 V
0.8V
VCC
REFERENCE
CORE
VCC 16
REFOK
1 uA
ENABLE
COMPARATOR
EN
6
1.7V ON
1.0V OFF
POWER FAULT
FAULT
4.25 V ON
4.05 V OFF
VCC UVLO
THERMAL
SHUTDOWN
SET
DOMINANT
145ºC ON
135ºC OFF
S
5V
HICCUP FAULT
3
GND
LINEAR
Q
REGULATOR
0.25V
R
SHORTCIRCUIT
DETECTION
VPOS
VIN
14
VFBINT
CLK
100ms Delay
COUNTER
CLR
140KΩ
OVER CURRENT
DETECTION
UVIN
15
2.50 V ON
2.20 V OFF
REFOK
7
PWRGD
VIN UVLO
60 mV
Power Good
50KΩ
VFB
9
10
ISN
0.74 V ON
0.72 V OFF
ISP
UVLO COMPARATORS
THERMAL AND OVER CURRENT PROTECTION
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
4
PIN DESCRIPTION
PIN
#
PIN
NAME
DESCRIPTION
High current driver output for the low side NFET switch. It is always low if GH is high or
during a fault. Resistor pull down ensures low state at low voltage.
ꢀ
GL
Ground Pin. The power circuitry is referenced to this pin. Return separately from other
ground traces to the (-) terminal of Cout.
2
3
PGND
GND
Ground pin. The control circuitry of the IC is referenced to this pin.
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter. The
output voltage is sensed and can be adjusted through an external resistor divider.
Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected
and the IC enters hiccup mode.
4
5
VFB
Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM
comparator. An optimal filter combination is chosen and connected to this pin and either
ground or VFB to stabilize the voltage mode loop.
COMP
Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is
internally pulled to VCC with a ꢀµA current source.
6
7
EN
Power Good Output. This open drain output is pulled low when VOUT is outside of the
regulation. Connect an external resistor to pull high.
PWRGD
Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft
start rate based on the ꢀ0µA source current. The SS pin is held low via a ꢀmA (min) current
during all fault conditions.
8
9
SS
Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE
and NSENSE. Offset accuracy +ꢀ0%.
ISN
Positive Input for the Inductor Current Sense.
ꢀ0
ꢀꢀ
ꢀ2
ISP
SWN
GH
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at
the junction between the two external power MOSFET transistors.
H
igh current driver output for the high side NFET switch. It is always low if GL is high or during a fault.
High side driver supply pin. Connect BST to the external boost diode and capacitor as shown
in the Application Schematic of page ꢀ. High side driver is connected between BST pin and SWN pin.
ꢀ3
BST
S
upply Input -- supplies power to the internal LDO.
ꢀ4
ꢀ5
VIN
Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground.
Can be overridden with external resistors.
UVIN
Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an
external 5V supply.
ꢀ6
VCC
Note: Die attach paddle is internally connected to GND.
THEORY OF OPERATION
General Overview
tion schemes. A precision 0.8V reference
present on the positive terminal of the error
amplifier permits the programming of the
output voltage down to 0.8V via the VFB pin.
The output of the error amplifier, COMP,
compared to a ꢀV peak-to-peak ramp is
responsible for trailing edge PWM control.
This voltage ramp and PWM control logic
are governed by the internal oscillator that
accuratelysetsthePWMfrequencyto600kHz.
The SP6136 is a fixed frequency, voltage
mode, synchronous PWM controller opti-
mized for high efficiency. The part has been
designedtobeespeciallyattractiveforsingle
supply input voltages ranging between 5V
and 24V.
TheheartoftheSP6ꢀ36isawidebandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
5
THEORY OF OPERATION
The SP6136 contains two unique control
features that are very powerful in distributed
applications. First, non-synchronous driver
control is enabled during start up to prohibit
thelowsideNFETfrompullingdowntheout-
putuntilthehighsideNFEThasattemptedto
turn on. Second, a ꢀ00% duty cycle timeout
ensuresthatthelowsideNFETisperiodically
enhanced during extended periods at ꢀ00%
dutycycle.Thisguaranteesthesynchronized
refreshing of the BST capacitor during very
large duty ratios.
and the 0.8V reference voltage. Therefore,
the excess current source can be redefined
as:
ꢀ0µA
IVIN, X = COUT • ΔVOUT
•
(CSS X 0.8V)
Hiccup
Upon the detection of a power, thermal, or
short-circuit fault, the SP6ꢀ36 is forced into
an idle state for a minimum of 200ms. The
SS and COMP pins are immediately pulled
low, and the gate drivers are held off for the
duration of the timeout period. Power and
thermal faults have to be removed before a
restart may be attempted, whereas, a short-
circuit fault is internally cleared shortly after
the fault latch is set. Therefore, a restart at-
temptisguaranteedevery200ms(typical)as
long as the short-circuit condition persists.
TheSP6ꢀ36alsocontainsanumberofvalu-
able protection features. A programmable
input UVLO allows a user to set the exact
value at which the conversion voltage is
at a safe point to begin down conversion,
and an internal VCC UVLO ensures that
the controller itself has enough voltage to
properly operate. Other protection features
include thermal shutdown and short-circuit
detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP6ꢀ36isforcedintoanidlestatewherethe
output drivers are held off for a finite period
before a re-start is attempted.
A short-circuit detection comparator has
also been included in the SP6ꢀ36 to protect
against the accidental short or severe build
up of current at the output of the power con-
verter. This comparator constantly monitors
the inputs to the error amplifier, and if the
VFB pin ever falls more than 250mV (typical)
below the voltage reference, a short-circuit
faultisset.BecausetheSSpinoverridesthe
internal 0.8V reference during soft start, the
SP6ꢀ36 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Soft Start
“Soft Start” is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter,rampingupthenon-invertinginput
of the error amplifier controls soft start. As a
result,excesssourcecurrentcanbedefined
as the current required to charge the output
capacitor
Error Amplifier & Voltage Loop
As stated before, the heart of the SP6ꢀ36
voltage error loop is a high performance,
wide bandwidth transconductance ampli-
fier. Because of the amplifier’s current
limited (+ꢀ00µA) transconductance, there
are many ways to compensate the voltage
loop or to control the COMP pin externally.
Ifasimple, singlepole, singlezeroresponse
is required, then compensation can be as
simple as an RC circuit to ground. If a more
complex compensation is required, then the
amplifier has enough bandwidth (45° at 4
Cout • ΔVout
IVIN, X
=
ΔTSoft-start
The SP6ꢀ36 provides the user with the op-
tion to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
ꢀ0µA pull up current present at the SS pin
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
6
THEORY OF OPERATION
included to prevent the IC from malfunction-
ing at extreme temperatures.
MHz)andenoughgain(60dB)torunTypeIII
compensation schemes with adequate gain
andphasemarginsatcrossoverfrequencies
greater than 200 kHz.
Over-Current Protection
Thecommonmodeoutputoftheerrorampli-
fier (COMP) is 0.9V to 2.2V. Therefore, the
PWM voltage ramp has been set between
ꢀ.0V and 2.0V to ensure proper 0% to ꢀ00%
duty cycle capability. The voltage loop also
includes two other very important features.
One is a non-synchronous start up mode.
Basically,theGLdrivercannotturnonunless
the GH driver has attempted to turn on or
the SS pin has exceeded ꢀ.7V. This feature
preventsthecontrollerfrom“draggingdown”
the output voltage during startup or in fault
modes. The second feature is a ꢀ00% duty
cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the GH driver is
on for 20 continuous clock cycles, a reset is
given to the PWM flip flop half way through
the 20th cycle. This forces GL to rise for the
remainder of the cycle, in turn refreshing the
BST capacitor.
Over-current is detected by monitoring a
differential voltage across the output in-
ductor as shown in figure 1. Inputs to an
over-current detection comparator, set to
trigger at 60 mV nominal, are connected to
the inductor as shown.
Since the average voltage sensed by the
comparator is equal to the product of in-
ductor current and inductor DC resistance
(DCR) then Imax = 60mV / DCR. Solving
this equation for the specific inductor in cir-
cuit ꢀ, Imax = ꢀ4.6A. When Imax is reached,
a 220 ms time-out is initiated, during which
top and bottom drivers are turned off. Fol-
lowing the time-out, a restart is attempted.
If the fault condition persists, then the time-
out is repeated (referred to as hiccup).
SP613X
L = 2.7uH, DCR = 4.ꢀmOhm
Vout
SWN
Gate Drivers
RSꢀ
5.11K
RS2
5.ꢀꢀK
The SP6ꢀ36 contains a pair of powerful 2W
Pull-up and ꢀ.5W Pull-down drivers. These
state-of-the-artdriversaredesignedtodrive
an external NFET capable of handling up to
30A. Rise, fall, and non-overlap times have
all been minimized to achieve maximum
efficiency. All drive pins GH, GL, & SWN
are monitored continuously to ensure that
only one external NFET is ever on at any
given time.
ISP
ISN
CSP
6.8nF
CS
0.ꢀuF
Figure 1: Over-current detection circuit
Thermal & Short-Circuit Protection
Because the SP6ꢀ36 is designed to drive
large NFETs running at high current, there is
a chance that either the controller or power
converterwillbecometoohot.Therefore, an
internalthermalshutdown(145°C)hasbeen
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
7
APPLICATION INFORMATION
Increasing the Current Limi
t
RS3
=
If itisdesiredtosetImax >{60mV/DCR}(in
this case larger than ꢀ4.6A), then a resistor
RS3 should be added as shown in figure 2.
RS3 forms a resistor divider and reduces the
voltage seen by the comparator.
RS2
•
[Vout - 60mV + (IMAX•DCR)].........(2)
60mV - (IMAX • DCR)
Asanexample: forImaxofꢀ2AandVoutof3.3V,
calculated RS3 is ꢀ.5MW (232KW standard).
Since: 60mV
RS3
(Imax • DCR)
{RSꢀ + RS2 + RS3}
=
SP613X
L = 2.7uH, DCR = 4.ꢀmOhm
Vou
Solving for RS3 we get:
SWN
[60mV • (RSꢀ + RS2)]
.......(ꢀ)
RSꢀ
5.11K
RS2
5.ꢀꢀK
RS3
=
[(Imax • DCR) – 60mV]
ISP
ISN
As an example: if desired Imax is ꢀ7A, then
RS3 = 63.4KW.
CSP
6.8nF
CS
0.ꢀuF
RS3
ꢀ.5MOh
SP613X
L = 2.7uH, DCR = 4.ꢀmOhm
Vout
SWN
RSꢀ
5.ꢀꢀK
RS2
5.ꢀꢀK
Figure 3- Over-current detection circuit
for Imax < {60mV / DCR}
RS3
63.4K
ISP
ISN
CSP
6.8nF
CS
0.ꢀuF
Power MOSFET Selection
There are four main criterion in selecting
Power MOSFETs for buck conversion:
Figure 2- Over-current detection circuit
for Imax > 60mV / DCR
●
Voltage rating BVdss
On resistance Rds(on)
Gate-to-drain charge Qgd
Package type
●
Decreasing the Current Limi
t
●
If it is required to set Imax < {60mV / DCR}, a
resistor is added as shown in figure 3. RS3
increases the net voltage detected by the
current-sense comparator. Voltage at the
positive and negative terminal of compara-
tor is given by:
●
In order to better illustrate the MOSFET se-
lectionprocess,thefollowingbuckconverter
designexamplewillbeused:Vin =ꢀ2V,Vout
= 3.3V, Iout = 10A, f = 2000KHz, DCR =
4.5mW (inductor DC resistance), efficiency
= 94% and Ta = 40˚C.
VSP = Vout + (Imax • DCR)
VSN = Vout •
{
RS3 / (RS2 + RS3)
}
Selectthevoltageratingbasedonmaximum
input voltage of the converter. A commonly
used practice is to specify BVdss at least
twice the maximum converter input voltage.
This is done to safeguard against switching
transientsthatmaybreakdowntheMOSFET.
For converters with Vin of less than ꢀ0V, a
Since the comparator is triggered at 60mV:
VSP-VSN = 60 mV
Combining the above equations and solv-
ing for RS3:
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
8
APPLICATION INFORMATION
20VratedMOSFETissufficient.Forconvert-
ers with ꢀ0-ꢀ5Vin, as in the above example,
select a 30V MOSFET.
ThecalculationofRds(on) forTopandBottom
MOSFETs is interrelated and can be done
using the following procedure:
P
Rds(on) =
[I2out • (Vout/Vin) • ꢀ.5]
= ꢀ0.7W.
Gate-to-drain charge Qgd for the top MOS-
FET needs to be specified. A simplified
expression for switching losses is:
ꢀ)
Calculate the maximum permissible
power dissipation P(dissipation) based on
required efficiency. The converter in the
above example should deliver an output
power Pout = 3.3V•ꢀ0A = 33W. For a target
efficiency of 94%, input power Pin is given
by Pin = Pout/0.94 = 35.ꢀW. Maximum al-
lowable power dissipation is then:
Vin Iout
Iout • Vin •
f
•
...................(3)
Ps =
+
{
}
d
v/dt
di/dt
where dv/dt and di/dt are the rates at which
voltage and current transition across the top
MOSFETrespectively, and fis the switching
frequency. Voltageswitchingtime Vin
(
/
)
dv/dt
P(dissipation)
= Pin – Pout = 2.ꢀ W
is related to Qgd:
2) Calculate the total power dissipation in
top and bottom MOSFETs P( ) by sub-
mosFEt
(
Vin
= Qgd/Ig............................... (4)
/
)
dv/dt
tracting inductor losses from P(dissipation)
calculated in step ꢀ. To simplify, disregard
core losses; then PL = I2rms • DCR • ꢀ.4,
where ꢀ.4 accounts for the increase in DCR
at operating temperature. For the above
example PL = 0.63W. Then:
whereIg isCurrentchargingthegate-to-drain
capacitance. It can be calculated from:
Ig = (VdrivE-VgatE)/RdrivE......................(5)
where VdrivE is the drive voltage of the
SP6ꢀ36topdriverminusthedropacrossthe
boost diode (approximately 4.5V); VgatE is
thetopMOSFET’sgatevoltagecorrespond-
ing to Iout (assume 2.5V) and RdrivE is the
internal resistance of the SP6ꢀ36 top driver
(assume2Waverageforturn-onandturn-off).
Substituting these values in equation (5) we
get Ig = ꢀA. Substituting for Ig in equation
P( ) = 2.ꢀW – 0.63W = ꢀ.47W.
mosFEt
3) CalculateRds(on) ofthebottomMOSFET
by allocating 40% of calculated losses to it.
40% dissipation allocation reflects the fact
that the the top MOSFET has essentially no
switchingloss. ThenP(bottom) =0.4Xꢀ.47W
= 0.59W. Rds(on) = P/(I2rms • ꢀ.5) where Irms
= Iout • {ꢀ-(Vout/Vin)}0.5 and ꢀ.5 accounts
for the increase in Rds(on) at the operating
temperature. Then:
(4), we get Vin
= Qgd. Substituting
(
/
)
dv/dt
for Vin
in equation (3) we have:
(
/
)
dv/dt
P
Rds(on) =
{ } • ꢀ.5]
I2out • (ꢀ-Vout/Vin)
Ps = Iout • Vin •
f
•
{Qgd + (Iout / di/dt
)
}
[
= 5.4 W.
Solving for Qgd we get:
4) Allocate 60% of the calculated losses
to the top MOSFET, P(top) = 0.6Xꢀ.47 =
0.88W. Assume conduction losses equal
to switching losses, then P = 0.5X0.88W =
0.44W. Since it operates at the duty cycle
of D=Vin/Vout; then:
Ps
_ Iout
.............. (6)
Qgd =
{
}
Iout • Vin • f
di/dt
Di/dt is usually limited by parasitic DC-Loop
Inductance (Lp) according to di/dt = Vin/Lp.
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
9
APPLICATION INFORMATION
side regulation. The PWRGD pin can be
connected to VCC with an external 10KW
resistor. During startup, output regulates
whenSoftStart(SS)reaches0.8V(therefer-
encevoltage). PWRGDisenabledwhenSS
reaches ꢀ.6V. PWRGD output can be used
as a “Power on Reset”. The simplest way to
adjust delay of the “Power on Reset” signal
with respect to Vout in regulation is with the
Soft Start Capacitor (Css) and is given by:
Css = (Iss •Tdelay)/0.8 where Iss is the Soft
Start charge current (ꢀ0µA nominal).
LpisduetowiringandPCBtracesconnecting
input capacitors and switching MOSFETs.
For typical Lp of ꢀ2nH and Vin of ꢀ2V, di/dt
is 1A/ns. Substituting for di/dt in equation
(6) we get Qgd = 2 nC.
In selecting a package type, the main con-
siderations are cost, power/current handling
capability and space constraints. A larger
package in general offers higher power and
currenthandlingatincreasedcost. Package
selectioncanbenarroweddownbycalculat-
ingtherequiredjunction-to-ambientthermal
resistance θja:
Under Voltage Lock Out (UVLO)
The SP6ꢀ36 has two separate UVLO com-
parators to monitor the bias (Vcc) and Input
(Vin)voltagesindependently.TheVccUVLO
is internally set to 4.25V. The Vin UVLO is
programmable through UVin pin. When
UVIN pin is greater than 2.5V the SP6ꢀ36
is permitted to start up pending the removal
of all other faults. A pair of internal resistors
is connected to UVIN as shown in figure 4.
Therefore without external biasing the Vin
startthresholdis9.5V.Asmallcapacitormay
be required between UVIN and GND to filter
out noise. For applications with Vin of 5V or
3.3V, connect UVIN directly to Vin.
θja =
{
Tj(max) - Ta(max))
}
........... (7)
/
P(max)
Where: Tj(max) is the die maximum tem-
perature rating, Ta(max) is maximum ambient
temperature, and P(max) is maximum power
dissipated in the die.
It is common practice to add a guard-band
of 25˚C to the junction temperature rating.
Following this convention, a 150˚C rated
MOSFETwillbedesignedtooperateat125˚C
(i.e., Tj(max) = 125˚C). P(max) = 0.88W (from
section 4) and Ta(max) = 40˚C as specified in
the design example. Substituting in equation
(7) we get θja = 96.6 ˚C/W.
SP613X
VIN
For the top MOSFET, we now have deter-
mined the following requirements; BVdss
=
R4
R5
ꢀ40K
30V, Rds(on) = ꢀ0.7m , Qgd = 2 nC and θja
W
< 96.6˚C/W.An SO-8 MOSFETthat meets the
requirements is Vishay-Siliconix’s Si4394DY;
UVIN
GND
+
-
2.5V ON
2.2V OFF
BVdss =30V, Rds(on) =9.75m
W@Vgs =4.5V,
50K
Qgd = 2.ꢀnC and θja = 90 ˚C/W.
The bottom MOSFEThas the requirements of
. Vishay-
Siliconix’sSi4320DYmeetstherequirements;
BVdss = 30V and Rds(on) = 5.4m
W
Figure 4- Internal and external bias of UVIN
BVdss = 30V, Rds(on) = 4mW @ Vgs = 4.5V.
To program the Vin start threshold, use a
pairofexternalresistorsasshown.Ifexternal
resistors are an order of magnitude smaller
Power Good
Power Good (PWRGD) is an open drain
output that is pulled low when Vout is out-
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ0
APPLICATION INFORMATION
than internal resistors, then the Vin start
threshold is given by:
Oncetherequiredinductorvalueisselected,
theproperselectionofcorematerialisbased
on peak inductor current and efficiency re-
quirements. The core must be large enough
not to saturate at the peak inductor current
Vin(start) = 2.5 • (R4+R5)/R5................ (8)
For example, if it is required to have a Vin
start threshold of 7V, then let R5 = 5KW and
using equation (9) we get R4 = 9.09KW.
Ipp
IpEak = Iout(max) +
/
2
and provide low core loss at the high switch-
ingfrequency.Lowcostpowderedironcores
have a gradual saturation characteristic
but can introduce considerable AC core
loss, especially when the inductor value is
relatively low and the ripple current is high.
Ferritematerials,ontheotherhand,aremore
expensive and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is
exceeded. Nevertheless, they are preferred
at high switching frequencies because they
present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are the
better choice for all but the most cost sensi-
tive applications.
Inductor Selection
Therearemanyfactorstoconsiderinselect-
ing the inductor including cost, efficiency,
size and EMI. In a typical SP6ꢀ36 circuit,
the inductor is chosen primarily for value,
saturation current and DC resistance. In-
creasing the inductor value will decrease
output voltage ripple, but degrade transient
response. Low inductor values provide the
smallest size, but cause large ripple cur-
rents, poor efficiency and need more output
capacitance to smooth out the larger ripple
current. The inductor must also be able to
handle the peak current at the switching
frequencywithoutsaturating,andthecopper
resistance in the winding should be kept as
low as possible to minimize resistive power
loss.Agoodcompromisebetweensize, loss
and cost is to set the inductor ripple current
to be within 20% to 40% of the maximum
output current.
Thepowerdissipatedintheinductorisequal
to the sum of the core and copper losses.
To minimize copper losses, the winding
resistance needs to be minimized, but this
usually comes at the expense of a larger
inductor.Corelosseshaveamoresignificant
contribution at low output current where the
copper losses are at a minimum, and can
typically be neglected at higher output cur-
rents where the copper losses dominate.
Core loss information is usually available
from the magnetic vendor.
The switching frequency and the inductor
operatingpointdeterminetheinductorvalue
as follows:
Vout • (Vin(max) - Vout)
Vin(max) • Fs • Kr • Iout(max)
L =
where:
The copper loss in the inductor can be cal-
Fs = switching frequency
Kr = ratio of the ac inductor ripple current
to the maximum output current
culated using the following equation:
PL(cu) = I2
• Rwinding
L(rms)
The peak to peak inductor ripple current is:
whereIL(rms) istheRMSinductorcurrentthat
Vout • (Vin(max) - Vout)
Ipp =
can be calculated as follows:
Vin(max) • Fs • L
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀꢀ
APPLICATION INFORMATION
ΔVout = Peak to Peak Output Voltage Ripple
ipk-pk = Peak to Peak Inductor Ripple Current
IL(rms) =
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
2
Iout(max) X
ꢀ
3
Ipp
Iout(max)
ꢀ +
•
{
}
√
Output Capacitor Selection
ΔVout =
.
.
The required ESR (Equivalent Series Re-
sistance) and capacitance drive the selec-
tion of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the ad-
ditional current demanded by the load until
the SP6ꢀ36 adjusts the inductor current to
the new value.
2
{ Ipp • (1-d) }
Cout • Fs
(Ipp•REsr)2
+
√
where:
Fs = Switching Frequency
D = Duty Cycle
Cout = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for
ripplecurrentrating,capacitanceandvoltage
rating. The input capacitor must meet the
ripple current requirement imposed by the
switching current. In continuous conduction
mode, the source current of the high-side
MOSFET is approximately a square wave
of duty cycle Vout/VIN. Most of this current
is supplied by the input bypass capacitors.
The RMS value of input capacitor current is
determined at the maximum output current
and under the assumption that the peak to peak
inductor ripple current is low, it is given by:
.
Therefore, the capacitance must be large
enough so that the output voltage is held up
while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitorcausesastepintheoutputvoltage
equaltothecurrent. Becauseofthefasttran-
sient response and inherent ꢀ00% and 0%
dutycyclecapabilityprovidedbytheSP6ꢀ36
when exposed to output load transients, the
output capacitor is typically chosen for ESR,
not for capacitance value.
Icin(rms) = Iout(max) X D • (ꢀ-D)
The output capacitor’s ESR, combined with
the inductor ripple current, is typically the
main contributor to output voltage ripple.
The maximum allowable ESR required to
maintain a specified output voltage ripple
can be calculated by:
√
Schottky Diode Selection
When paralleled with the bottom MOSFET,
an optional Schottky diode can improve
efficiency and reduce noise. Without this
Schottky diode, the body diode of the bot-
tom MOSFET conducts the current during
the non-overlap time when both MOSFETs
are turned off. Unfortunately, the body di-
ΔVout
ipk-pk
RESR <
where:
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ2
APPLICATION INFORMATION
ode has high forward voltage and reverse
recovery problems. The reverse recovery of
the body diode causes additional switching
noisewhenthediodeturnsoff.TheSchottky
diode alleviates these sources of noise and
additionally improves efficiency thanks to its
low forward voltage. The reverse voltage
across the diode is equal to input voltage,
and the diode must be able to handle the
peak current equal to the maximum load
current.
Thegoalofloopcompensationistomanipu-
late loop frequency response such that its
gain crosses over 0db at a slope of -20db/
dec. The first step of compensation design
is to pick the loop crossover frequency. High
crossover frequency is desirable for fast
transient response, but often jeopardizes
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
The power dissipation of the Schottky diode
is determined by:
PDIODE = 2 • VF • Iout • TNOL • FS
ƒz(Esr) =
ꢀ
where:
2π • Cout • REsr
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
The next step is to calculate the complex
conjugatepolescontributedbytheLCoutput
filter,
Loop Compensation Design
The open loop gain of the whole system can
be divided into the gain of the error ampli-
fier, PWM modulator, buck converter output
stage, and feedback resistor divider. In or-
der to cross over at the selected frequency
FCO, the gain of the error amplifier has to
compensate for the attenuation caused by
the rest of the loop at this frequency.
ꢀ
ƒp(Lc)
=
2π • L • Cout
√
WhentheoutputcapacitorsareofaCeramic
Type,theSP6136EvaluationBoardrequires
aTypeIIIcompensationcircuittogiveaphase
boostof180°inordertocounteracttheeffects
ofanunderdampedresonanceoftheoutput
filter at the double pole frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
+
_
VREF
(Volts)
VOUT
(Volts)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S2LCOUT+S(RESR+RDC) COUT+1]
VRAMP_PP
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
(R1 R2
VREF
or
VOUT
)
+
VFBK
(Volts)
Figure 5: SP6136 Voltage Mode
Control Loop with Loop Dynamic
Definitions:
REsr = Output Capacitor Equivalent Series Resistance
Rdc = Output Inductor DC Resistance
Vramp _ pp = SP6ꢀ36 internal RAMP Amplitude Peak to Peak Voltage
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ3
APPLICATION INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Frequency
(Hz)
Figure 6: Bode Plot of Type III Error Amplifier Compensation
Note: Loop Compensation component calculations discussed in this Datasheet can
be quickly iterated with the Type III Loop Compensation Calculator on the web at:
www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
INDUCTORS - SURFACE MOUNT
Inductor Specification
Inductance
Manufacturer
Part No.
Series R
Isat
Size
Inductor Type
Manufacturer
Website
(uH)
m
(A)
LxW(mm) Ht.(mm)
Inter-
www.inter-technical.com
Shielded Ferrite Core
2.2
SC7232-2R2M
10.4
13.00
7.2x6.6
3.20
Technical
CAPACITORS - SURFACE MOUNT
Capacitor Specification
Capacitance
(uF)
Manufacturer
Part No.
ESR
Ripple Current
Size
Voltage
(V)
Capacitor
Type
Manufacturer
Website
(max)
(A) @ 45°C LxW(mm) Ht.(mm)
16.0 X5R Ceramic
www.TDK.com
www.TDK.com
22
0.005
4.00
4.00
3X2
3X2
2.00
2.00
TDK
TDK
C3225X5R1C226M
6.3
X5R Ceramic
100
C3225X5R0J107M 0.005
MOSFETS - SURFACE MOUNT
MOSFET Specification
MOSFET
Manufacturer
Part No.
RDS(on)
(max)
18.50
ID Current
(A)
Qg
Voltage
(V)
Foot Print
Manufacturer
Website
nC (Typ) nC (Max)
N-Ch
N-Ch
VISHAY
VISHAY
Si4354DY
Si4886DY
9.0
7.0
10.5
20.0
30.0
SO-8
SO-8
www.vishay.com
www.vishay.com
13.5
11.0
14.5
30.0
Table 1. Input and Output Stage Components Selection Charts
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ4
APPLICATION INFORMATION
Figure 7: SP6136 output ripple is 32mV at Iout=7A
Figure 8: SP6136 Step load response 0-5A, top trace is Vout (100mV/div), bottom
trace Iload (2A/div)
Figure 9: SP6136 startup at full load, Ch1: Vin, Ch2: Vout, Ch3:PWRGD, Ch4: SS
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ5
APPLICATION INFORMATION
SP6136 Efficiency versus Iout
@ Vin=12V, Vout=3.3V
96
94
92
90
88
ꢀ.0
2.0
3.0
4.0
5.0
6.0
7.0
Iout (A)
SP6136 Load Regulation
@ Vin=12V
3.350
3.348
3.346
3.344
3.342
3.340
ꢀ.0
2.0
3.0
4.0
5.0
6.0
7.0
Iout (A)
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ6
PACꢀAGE: 3MMX3MM 16 PIN QFN
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ7
ORDERING INFORMATION
Part Number
Temperature Range
Package
SP6ꢀ36ERꢀ...............................................-40°C to +85°C..................... 3mm X 3mm ꢀ6 Pin QFN
SP6ꢀ36ERꢀ/TR.........................................-40°C to +85°C..................... 3mm X 3mm ꢀ6 Pin QFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6ꢀ36ERꢀ/TR = standard; SP6ꢀ36ERꢀ-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 3000 for QFN.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Oct 3ꢀ-06 Rev L
SP6ꢀ36 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ8
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