SP6138ER1-L/TR [SIPEX]
Switching Controller, Voltage-mode, 2A, 2800kHz Switching Freq-Max, 3 X 3 MM, MO-220VEED-4, QFN-16;
| 型号： | SP6138ER1-L/TR |
| 厂家： | 
SIPEX CORPORATION |
| 描述： | Switching Controller, Voltage-mode, 2A, 2800kHz Switching Freq-Max, 3 X 3 MM, MO-220VEED-4, QFN-16 |
| 文件： | 总80页 (文件大小：4803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Solved by
SP6138
TM
Synchronous Buck Controller
FEATURES
13
14
16
15
■ 5V to 24V Input step down converter
■ Up to 3A output in a small form factor
■ Highly integrated design, minimal components
■ UVLO Detects Both VCC and VIN
■ Overcurrent circuit protection with auto-restart
■ Power Good Output, ENABLE Input
■ Maximum Controllable Duty Cycle Ratio up to 92%
■ Wide BW amp allows Type II or III compensation
■ Programmable Soft Start
1
2
3
4
12
GH
GL
PGND
GND
SP6138
11
10
9
SWN
ISP
ISN
16 Pin QFN
3mm x 3mm
V
FB
5
6
7
8
■ Fast Transient Response
■ Available in ꢀ6-Pin QFN package
■ External Driver Enable/Disable
■ U.S. Patent #6,922,04ꢀ
Now Available in Lead Free Packaging
DESCRIPTION
The SP6ꢀ38 is a synchronous step-down switching regulator controller optimized for small
footprint. The part is designed to be especially attractive for single supply step down con-
version from 5V to 24V. The SP6ꢀ38 is designed to drive a pair of external NFETs using a
fixed2.5MHzfrequency, PWMvoltagemodearchitecture. ProtectionfeaturesincludeUVLO,
thermalshutdown, outputshortcircuitprotection, andovercurrentprotectionwithautorestart.
The device also features a PWRGD output and an enable input. The SP6ꢀ38 is available in
a space saving ꢀ6-pin QFN and offers excellent thermal performance.
TYPICAL APPLICATION CIRCUIT
VIN
C5
12V
0.1uF
C1
4.7uF
DBST
CVCC
4.7uF
CBST
0.1uF
MT/MB, Si7214DN
47 mΩ, 30V
(Co-Packaged FETs)
SD101AWS
VCC
GND
VIN
BST
GH
SWN
COOPER, SD25-2R2
2.2uH, 2.8A, 31mΩ
R3 10KΩ
VOUT
PWRGD
POWERGOOD
UVIN
EN
3.3V
0-2A
NC
RS1
1KΩ
RS2
1KΩ
SP6138
C2
ENABLE
GL
GND
22uF
RS3
4.99KΩ
ISP
GND
PGND
COMP
CSP
ISN
6.8nF
CS
0.1uF
SS
VFB
CSS
CP1
6 pF
R1
68.1KΩ, 1%
47nF
CZ3
47pF
RZ3
1KΩ
R2
21.5KΩ, 1%
CF1
18pF
CZ2
100pF
RZ2
54.9KΩ
Note: Die-attach paddle is connected to GND
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.
Peak Output Current < 10µs
GH,GL ............................................................................................. 2A
VCC .................................................................................................. 6V
VIN .............................................................................................. 24.5V
BST................................................................................................ 30V
BST-SWN........................................................................................ 7V
SWN ....................................................................................-2V to 24V
GH ..........................................................................-0.3V to BST+0.3V
GH-SWN.......................................................................................... 6V
Storage Temperature................................................... -65°C to 150°C
Power Dissipation........................................................................... ꢀW
ESD Rating........................................................................... 2kV HBM
Thermal Resistance.............................................................. 41.9°C/W
All other pins............................................................-0.3V to VCC+0.3V
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC
= ꢀ0µF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = ꢀ0KΩ.
PARAMETER
MIN TYP MAX UNITS CONDITIONS
QUIESCENT CURRENT
VIN Supply Current
ꢀ.5
ꢀ.5
0.2
3.0
3.0
0.4
mA
mA
mA
VFB = ꢀV (no switching)
VFB = ꢀV (no switching)
VFB = ꢀV (no switching)
VCC Supply Current
BST Supply Current
PROTECTION: UVLO
VCC UVLO Start Thresh-
old
4.00
ꢀ50
4.25
200
4.5
250
2.65
V
mV
V
VCC UVLO Hysteresis
Apply voltage to UVIN
pin
UVIN Start Threshold
2.35
2.50
Apply voltage to UVIN
pin
UVIN Hysteresis
200
9.0
300
400
mV
VIN Start Threshold
VIN Hysteresis
9.5
300
0.4
ꢀ0.0
V
UVIN Floating
mV
µA
UVIN Floating
Enable Pullup Current
Apply voltage to EN pin
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
0.792 0.800 0.808
V
V
2X Gain Config.
Error Amplifier Reference
Over Line and Temperature
0.788 0.800 0.8ꢀ2
COMP Sink Current
70
-230
ꢀ
ꢀ50
-ꢀ50
50
230
-70
µA
µA
nA
COMP Source Current
VFB Input Bias Current
ꢀ00
COMP Common Mode
Output Range
ꢀ.9
3.2
3.0
3.5
3.2
3.8
V
V
COMP Pin Clamp Voltage
VFB = 0.7V
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0V, UVIN = 3.0V,
CVCC = 0.ꢀµF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN TYP MAX UNITS CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Offset
ꢀ.7
2.0
ꢀ.0
30
2.3
ꢀ.20
70
V
V
TA = 25˚C
Ramp Amplitude
0.80
GH Minimum Pulse Width
ns
Maximum Controllable Duty
Ratio
92
%
Maximum Duty Ratio
ꢀ00
%
Guaranteed by design
Fault Present
Internal Oscillator Frequency 2.2
2.5
2.8
MHZ
TIMERS: SOFTSTART
SS Charge Current
-ꢀ6
ꢀ.0
-ꢀ0
2.0
-4
µA
SS Discharge Current
3.0
mA
VCC LINEAR REGULATOR
VCC Output Voltage
VIN = 6 to 23V,
ILOAD = 0mA to 30mA
4.6
5.0
5.4
V
Dropout Voltage
250
500
750
mV
IVCC = 30mA
POWER GOOD OUTPUT
Power Good Threshold
Power Good Hysteresis
-ꢀ0
-7.5
2.0
-5
%
%
4.0
Power Good Sink Current
VFB = 0.7V, VPWRGD =
0.2V
ꢀ.0
ꢀ0
mA
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold
Voltage
Measured VREF (0.8V)
- VFB
0.2
54
0.25
60
0.3
66
V
Overcurrent Threshold
Voltage
Measured ISP - ISN
mV
ISP, ISN Common Mode
Range
0
3.3
40
V
Hiccup Timeout
20
30
ꢀ45
ꢀ0
ms
˚C
˚C
Thermal Shutdown
Temperature
ꢀ35
ꢀ55
3.3
Thermal Hysteresis
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
3
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC
= 0.ꢀµF, CCOMP = 0.ꢀµF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN TYP MAX UNITS CONDITIONS
OUTPUT: NFET GATE DRIVERS
GH & GL Rise Times
GH & GL Fall Times
35
30
50
40
ns
ns
Measured ꢀ0% to 90%
Measured 90% to ꢀ0%
GL to GH Non Overlap
Time
45
25
50
70
40
85
ns
ns
GH & GL Measured at 2.0V
SWN to GL Non Overlap
Time
Measured SWN = ꢀ00mV
to GL = 2.0V
GH & GL Pull Down Re-
sistance
ꢀ5
KΩ
Driver Pull Down Resistance
Driver Pull Up Resistance
ꢀ.5
2.5
ꢀ.9
3.9
Ω
Ω
BLOCꢀ DIAGRAM
NON SYNC. STARTUP
COMPARATOR
VCC
5
COMP
SS
GL HOLD OFF
1.6 V
VFBINT
13 BST
PWM LOOP
4
VFB
VCC
GmERROR AMPLIFIER
RESET
VCC
DOMINANT
12 GH
FAULT
Gm
R
10 uA
VPOS
POS REF
QPWM
SYNCHRONOUS
DRIVER
11 SWN
Q
SOFTSTART INPUT
SS
0.1V
8
FAULT
S
1
GL
FAULT
2.5 MHZ
2
PGND
RAMP =1V
CLK
CLOCK PULSE GENERATOR
1.3 V
2.8 V
0.8V
VCC
REFERENCE
CORE
VCC 16
REFOK
1 uA
ENABLE
COMPARATOR
EN
6
1.7V ON
1.0V OFF
POWER FAULT
FAULT
4.25 V ON
4.05 V OFF
VCC UVLO
THERMAL
SHUTDOWN
SET
DOMINANT
145ºC ON
135ºC OFF
S
5V
HICCUP FAULT
3
GND
LINEAR
REGULATOR
Q
0.25V
R
SHORTCIRCUIT
DETECTION
VPOS
VIN
14
VFBINT
CLK
100ms Delay
140KΩ
COUNTER
CLR
OVER CURRENT
DETECTION
UVIN
15
2.50 V ON
2.20 V OFF
REFOK
7
PWRGD
60 mV
VIN UVLO
Power Good
50KΩ
VFB
9
10
ISN
ISP
0.74 V ON
0.72 V OFF
UVLO COMPARATORS
THERMAL AND OVER CURRENT PROTECTION
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
4
PIN DESCRIPTION
PIN
#
PIN
NAME
DESCRIPTION
High current driver output for the low side NFET switch. It is always low if GH is high or
during a fault. Resistor pull down ensures low state at low voltage.
ꢀ
GL
Ground Pin. The power circuitry is referenced to this pin. Return separately from other
ground traces to the (-) terminal of Cout.
2
3
PGND
GND
Ground pin. The control circuitry of the IC is referenced to this pin.
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter. The output
voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB
drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters
hiccup mode.
4
5
VFB
Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM
comparator. An optimal filter combination is chosen and connected to this pin and either
ground or VFB to stabilize the voltage mode loop.
COMP
Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is
internally pulled to VCC with a ꢀµA current source.
6
7
EN
Power Good Output. This open drain output is pulled low when VOUT is outside of the
regulation. Connect an external resistor to pull high.
PWRGD
Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft
start rate based on the ꢀ0µA source current. The SS pin is held low via a ꢀmA (min) current
during all fault conditions.
8
SS
Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE
and NSENSE. Offset accuracy +ꢀ0%.
9
ISN
ISP
Positive Input for the Inductor Current Sense.
ꢀ0
ꢀꢀ
ꢀ2
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at
the junction between the two external power MOSFET transistors.
SWN
GH
H
igh current driver output for the high side NFET switch. It is always low if GL is high or during a fault.
High side driver supply pin. Connect BST to the external boost diode and capacitor as
shown in the Application Schematic of page ꢀ. High side driver is connected between BST pin and
SWN pin.
ꢀ3
BST
S
upply Input. Provides power to the internal LDO.
ꢀ4
ꢀ5
VIN
Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground.
Can be overridden with external resistors.
UVIN
Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an
external 5V supply.
ꢀ6
VCC
Note: Die-attach paddle is internally connected to GND
THEORY OF OPERATION
General Overview
tion schemes. A precision 0.8V reference
present on the positive terminal of the error
amplifier permits the programming of the
output voltage down to 0.8V via the VFB pin.
The output of the error amplifier, COMP,
compared to a ꢀV peak-to-peak ramp is
responsible for trailing edge PWM control.
ThisvoltagerampandPWMcontrollogicare
governed by the internal oscillator that ac-
curately sets the PWM frequency to 2.5 MHz.
The SP6138 is a fixed frequency, voltage
mode, synchronous PWM controller opti-
mized for high efficiency. The part has been
designedtobeespeciallyattractiveforsingle
supply input voltages ranging between 5V
and 24V.
TheheartoftheSP6ꢀ38isawidebandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
5
THEORY OF OPERATION
the excess current source can be redefined as:
ꢀ0µA
The SP6138 contains two unique control
features that are very powerful in distributed
applications. First, non-synchronous driver
control is enabled during start up to prohibit
thelowsideNFETfrompullingdowntheout-
putuntilthehighsideNFEThasattemptedto
turn on. Second, a ꢀ00% duty cycle timeout
ensuresthatthelowsideNFETisperiodically
enhanced during extended periods at ꢀ00%
dutycycle.Thisguaranteesthesynchronized
refreshing of the BST capacitor during very
large duty ratios.
IVIN, X = COUT • ∆VOUT
•
(CSS • 0.8V)
Hiccup
Upon the detection of a power, thermal, or
short-circuit fault, the SP6ꢀ38 is forced into
an idle state for a minimum of 30ms. The SS
and COMP pins are immediately pulled low,
and the gate drivers are held off for the dura-
tionofthetimeoutperiod.Powerandthermal
faults have to be removed before a restart
may be attempted, whereas, a short-circuit
faultisinternallyclearedshortlyafterthefault
latch is set. Therefore, a restart attempt is
guaranteed every 30ms (typical) as long as
the short-circuit condition persists.
TheSP6ꢀ38alsocontainsanumberofvalu-
able protection features. A programmable
input UVLO allows a user to set the exact
value at which the conversion voltage is at a
safe point to begin down conversion, and an
internalVCC UVLOensuresthatthecontroller
itselfhasenoughvoltagetoproperlyoperate.
Other protection features include thermal
shutdown and short-circuit detection. In the
event that either a
A short-circuit detection comparator has
also been included in the SP6ꢀ38 to protect
against the accidental short or severe build
up of current at the output of the power con-
verter. This comparator constantly monitors
the inputs to theerror amplifier, and if the
VFB pin ever falls more than 250mV (typical)
below the reference voltage, a short-circuit
faultisset.BecausetheSSpinoverridesthe
internal 0.8V reference during soft start, the
SP6ꢀ38 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
thermal, short-circuit, or UVLO fault is de-
tected,theSP6ꢀ38isforcedintoanidlestate
where the output drivers are held off for a
finite period before a re-start is attempted.
Soft Start
“Soft Start” is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter,rampingupthenon-invertinginput
of the error amplifier controls soft start. As a
result,excesssourcecurrentcanbedefined
as the current required to charge the output
capacitor
Error Amplifier & Voltage Loop
As stated before, the heart of the SP6ꢀ38
voltage error loop is a high performance,
wide bandwidth transconductance ampli-
fier. Because of the amplifier’s current
limited (+ꢀ00µA) transconductance, there
are many ways to compensate the voltage
loop or to control the COMP pin externally.
Ifasimple, singlepole, singlezeroresponse
is required, then compensation can be as
simple as an RC circuit to ground. If a more
complex compensation is required, then the
amplifierhasenoughbandwidthtorunTypeIII
compensation schemes with adequate gain
andphasemarginsatcrossoverfrequencies
greater than 200 kHz.
Cout • ∆Vout
IVIN, X
=
∆TSoft-start
The SP6ꢀ38 provides the user with the op-
tion to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
ꢀ0µA pull up current present at the SS pin
and the 0.8V reference voltage. Therefore,
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
6
THEORY OF OPERATION
Thecommonmodeoutputoftheerrorampli-
fier (COMP) is 0.9V to 2.2V. Therefore, the
PWM voltage ramp has been set between
ꢀ.0V and 2.0V to ensure proper 0% to ꢀ00%
duty cycle capability. The voltage loop also
includes two other very important features.
One is an non-synchronous start up mode.
Basically,theGLdrivercannotturnonunless
the GH driver has attempted to turn on or
the SS pin has exceeded ꢀ.7V. This feature
preventsthecontrollerfrom“draggingdown”
the output voltage during startup or in fault
modes. The second feature is a ꢀ00% duty
cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the GH driver is
on for 20 continuous clock cycles, a reset is
given to the PWM flip flop half way through
the 20th cycle. This forces GL to rise for the
remainder of the cycle, in turn refreshing the
BST capacitor.
Over-Current Protection
Over-current is detected by monitoring a
differential voltage across the output induc-
tor as shown in figure 1. Inputs to an over-
current detection comparator, set to trigger
at 60 mV nominal, are connected to the in-
ductor as shown.
Since the average voltage sensed by the
comparator is equal to the product of in-
ductor current and inductor DC resistance
(DCR) then Imax = 60mV / DCR. Solving
this equation for the specific inductor in cir-
cuit ꢀ, Imax = ꢀ4.6A. When Imax is reached,
a 220 ms time-out is initiated, during which
top and bottom drivers are turned off. Fol-
lowing the time-out, a restart is attempted.
If the fault condition persists, then the time-
out is repeated (referred to as hiccup).
SP613X
L = 2.7uH, DCR = 4.ꢀmOhm
Vout
Gate Drivers
SWN
TheSP6ꢀ38containsapairofpowerful2.5Ω
pull-up and ꢀ.5Ω pull-down drivers. These
state-of-the-artdriversaredesignedtodrive
an external NFET capable of handling up to
30A. Rise, fall, and non-overlap times have
all been minimized to achieve maximum
efficiency. All drive pins GH, GL, & SWN
are monitored continuously to ensure that
only one external NFET is ever on at any
given time.
RSꢀ
5.ꢀꢀK
RS2
5.ꢀꢀK
ISP
ISN
CSP
6.8nF
CS
0.ꢀuF
Thermal & Short-Circuit Protection
Figure 1: Over-current detection circuit
Because the SP6ꢀ38 is designed to drive
large NFETs running at high current, there is
a chance that either the controller or power
converterwillbecometoohot.Therefore, an
internalthermalshutdown(145°C)hasbeen
included to prevent the IC from malfunction-
ing at extreme temperatures.
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
7
APPLICATION INFORMATION
Increasing the Current Limi
t
Combining the above equations and solv-
ing for RS3:
If it is desired to set Imax > {60mV / DCR}
(in this case larger than ꢀ4.6A), then a resis-
tor RS3 should be added as shown in figure
2. RS3 forms a resistor divider and reduces
the voltage seen by the comparator.
RS3
=
RS2
•
[Vout - 60mV + (IMAX•DCR)].........(2b)
60mV - (IMAX • DCR)
Since: 60mV
( Imax • DCR )
Asanexample: forImaxofꢀ2AandVoutof3.3V,
calculated RS3 is ꢀ.5MΩ (232KΩ standard).
=
RS3
{RSꢀ + RS2 + RS3}
SP613X
Solving for RS3 we get:
L = 2.7uH, DCR = 4.ꢀmOhm
Vout
SWN
[60mV • (RSꢀ + RS2)]
RS3
.........(2a)
= [(Imax • DCR) – 60mV]
RSꢀ
5.ꢀꢀK
RS2
5.ꢀꢀK
As an example: if desired Imax is ꢀ7A, then
RS3 = 63.4KΩ.
ISP
ISN
CSP
6.8nF
CS
0.ꢀuF
RS3
ꢀ.5MOhm
SP613X
L = 2.7uH, DCR = 4.ꢀmOhm
Vout
SWN
RSꢀ
5.ꢀꢀK
RS2
5.ꢀꢀK
Figure 3- Over-current detection circuit
for Imax < {60mV / DCR}
RS3
63.4K
ISP
ISN
CSP
6.8nF
Power MOSFET Selection
CS
0.ꢀuF
There are four main criterion in selecting
Power MOSFETs for buck conversion:
●
Voltage rating BVdss
On resistance Rds(on)
Gate-to-drain charge Qgd
Package type
Figure 2- Over-current detection circuit
for Imax > 60mV / DCR
●
●
●
Decreasing the Current Limi
t
In order to better illustrate the MOSFET se-
lectionprocess,thefollowingbuckconverter
designexamplewillbeused:Vin =ꢀ2V,Vout
= 3.3V, Iout = ꢀ0A, f = 2000KHz, DCR =
4.5mΩ (inductor DC resistance), efficiency
= 94% and Ta = 40˚C.
If it is required to set Imax < {60mV / DCR}, a
resistor is added as shown in figure 3. RS3
increases the net voltage detected by the
current-sense comparator. Voltage at the
positive and negative terminal of compara-
tor is given by:
Selectthevoltageratingbasedonmaximum
input voltage of the converter. A commonly
used practice is to specify BVdss at least
twice the maximum converter input voltage.
This is done to safeguard against switching
transientsthatmaybreakdowntheMOSFET.
For converters with Vin of less than ꢀ0V, a
VSP = Vout + (Imax • DCR)
VSN = Vout x {RS3 / (RS2 +RS3)}
Since the comparator is triggered at 60mV:
VSP-VSN = 60 mV
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
8
APPLICATION INFORMATION
20VratedMOSFETissufficient.Forconvert-
ers with ꢀ0-ꢀ5Vin, as in the above example,
select a 30V MOSFET.
ThecalculationofRds(on) forTopandBottom
MOSFETs is interrelated and can be done
using the following procedure:
P
Rds(on) =
[I2out • (Vout/Vin) • ꢀ.5]
= ꢀ0.7 mΩ.
Gate-to-drain charge Qgd for the top MOS-
FET needs to be specified. A simplified
expression for switching losses is:
ꢀ)
Calculate the maximum permissible
power dissipation P(dissipation) based on
required efficiency. The converter in the
above example should deliver an output
power Pout = 3.3Vxꢀ0A= 33W. For a target
efficiency of 94%, input power Pin is given
by Pin = Pout/0.94 = 35.ꢀW. Maximum al-
lowable power dissipation is then:
Vin Iout
Iout • Vin •
f
•
...................(3)
Ps =
+
{
}
dv/dt
di/dt
where dv/dt and di/dt are the rates at which
voltage and current transition across the top
MOSFETrespectively, and fis the switching
frequency. Voltageswitchingtime Vin
(
/
)
P(dissipation) = Pin – Pout = 2.ꢀ W
dv/dt
is related to Qgd:
2) Calculate the total power dissipation
in top and bottom MOSFETs P(
) by
mosFEt
(
Vin
= Qgd/Ig............................... (4)
/
)
dv/dt
subtractinginductorlossesfromP(dissipation)
calculated in step ꢀ. To simplify, disregard
core losses; then PL = I2rms x DCR x ꢀ.4,
where ꢀ.4 accounts for the increase in DCR
at operating temperature. For the above
example PL = 0.63W. Then:
whereIg isCurrentchargingthegate-to-drain
capacitance. It can be calculated from:
Ig = (VdrivE-VgatE)/RdrivE......................(5)
where VdrivE is the drive voltage of the
SP6ꢀ38topdriverminusthedropacrossthe
boost diode (approximately 4.5V); VgatE is
thetopMOSFET’sgatevoltagecorrespond-
ing to Iout (assume 2.5V) and RdrivE is the
internal resistance of the SP6ꢀ38 top driver
(assume2Ωaverageforturn-onandturn-off).
Substituting these values in equation (5) we
get Ig = ꢀA. Substituting for Ig in equation
P(
) = 2.ꢀW – 0.63W = ꢀ.47W.
MOSFET
3) CalculateRds(on) ofthebottomMOSFET
by allocating 40% of calculated losses to it.
40% dissipation allocation reflects the fact
that the the top MOSFET has essentially no
switchingloss. ThenP(bottom) =0.4xꢀ.47W
= 0.59W. Rds(on) = P/(I2rms x ꢀ.5) where Irms
= Iout x {ꢀ-(Vout/Vin)}0.5 and ꢀ.5 accounts
for the increase in Rds(on) at the operating
temperature. Then:
(4), we get Vin
= Qgd. Substituting
(
/
)
dv/dt
for Vin
in equation (3) we have:
(
/
)
dv/dt
P
Ps = Iout • Vin • f • {Qgd + (Iout / di/dt)}
Rds(on) =
[{I2out • (ꢀ-Vout/Vin)} • ꢀ.5]
= 5.4 mΩ.
Solving for Qgd we get:
4) Allocate 60% of the calculated losses
to the top MOSFET, P(top) = 0.6xꢀ.47 =
0.88W. Assume conduction losses equal
to switching losses, then P = 0.5x0.88W =
0.44W. Since it operates at the duty cycle
of D=Vin/Vout; then:
Ps
_ Iout
.............. (6)
Qgd =
{
}
Iout • Vin • f
di/dt
Di/dt is usually limited by parasitic DC-Loop
Inductance (Lp) according to di/dt = Vin/Lp.
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
9
APPLICATION INFORMATION
Power Good
LpisduetowiringandPCBtracesconnecting
input capacitors and switching MOSFETs.
For typical Lp of ꢀ2nH and Vin of ꢀ2V, di/dt
is 1A/ns. Substituting for di/dt in equation (6)
we get Qgd = 2 nC.
Power Good (PWRGD) is an open drain
output that is pulled low when Vout is out-
side regulation. The PWRGD pin can be
connected to VCC with an external ꢀ0KΩ
resistor. During startup, output regulates
whenSoftStart(SS)reaches0.8V(therefer-
ence voltage). PWRGD is enabled when SS
reaches ꢀ.6V. PWRGD output can be used
as a “Power on Reset”. The simplest way to
adjust delay of the “Power on Reset” signal
with respect to Vout in regulation is with the
Soft Start Capacitor (Css) and is given by:
Css =(IssxTdelay)/0.8whereIssistheSoft
Start charge current (ꢀ0µA nominal).
In selecting a package type, the main con-
siderations are cost, power/current handling
capability and space constraints. A larger
package in general offers higher power and
currenthandlingatincreasedcost. Package
selectioncanbenarroweddownbycalculat-
ingtherequiredjunction-to-ambientthermal
resistance θja:
θja = {Tj(max) - Ta(max)} / P(max)........... (7)
Under Voltage Lock Out (UVLO)
Where: Tj(max) is the die maximum tem-
peraturerating,Ta(max) ismaximumambient
temperature, and P(max) is maximum power
dissipated in the die.
The SP6ꢀ38 has two separate UVLO com-
parators to monitor the bias (Vcc) and Input
(Vin)voltagesindependently.TheVccUVLO
is internally set to 4.25V. The Vin UVLO is
programmable through UVin pin. When
UVIN pin is greater than 2.5V the SP6ꢀ38
is permitted to start up pending the removal
of all other faults. A pair of internal resistors
is connected to UVIN as shown in figure 4.
Therefore without external biasing the Vin
startthresholdis9.5V.Asmallcapacitormay
be required between UVIN and GND to filter
out noise. For applications with Vin of 5V or
3.3V, connect UVIN directly to Vin.
It is common practice to add a guard-band
of 25˚C to the junction temperature rating.
Following this convention, a 150˚C rated
MOSFETwillbedesignedtooperateat125˚C
(i.e., Tj(max) = 125˚C). P(max) = 0.88W (from
section 4) and Ta(max) = 40˚C as specified in
the design example. Substituting in equation
(7) we get θja = 96.6 ˚C/W.
For the top MOSFET, we now have deter-
mined the following requirements; BVdss
=
SP613X
30V, Rds(on) = ꢀ0.7mΩ, Qgd = 2 nC and θja
< 96.6˚C/W.An SO-8 MOSFETthat meets the
requirements is Vishay-Siliconix’s Si4394DY;
BVdss = 30V, Rds(on) = 9.75mΩ @ Vgs = 4.5V,
VIN
R4
R5
ꢀ40K
UVIN
GND
Q
gd = 2.ꢀnC and θja = 90 ˚C/W.
+
-
2.5V ON
2.2V OFF
The bottom MOSFEThas the requirements of
BVdss = 30V and Rds(on) = 5.4mΩ. Vishay-
Siliconix’sSi4320DYmeetstherequirements;
BVdss = 30V, Rds(on) = 4mΩ @ Vgs = 4.5V.
50K
Figure 4- Internal and external bias of UVIN
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ0
APPLICATION INFORMATION
The peak to peak inductor ripple current is:
ToprogramtheVin startthreshold, useapair
of external resistors as shown. If external
resistors are an order of magnitude smaller
than internal resistors, then the Vin start
threshold is given by:
Vout • (Vin(max) - Vout)
Ipp =
Vin(max) • Fs • L
Oncetherequiredinductorvalueisselected,
theproperselectionofcorematerialisbased
on peak inductor current and efficiency re-
quirements. The core must be large enough
not to saturate at the peak inductor current
Vin(start) = 2.5 • (R4+R5)/R5................ (8)
For example, if it is required to have a Vin
start threshold of 7V, then let R5 = 5KΩ and
using equation (9) we get R4 = 9.09KΩ.
Ipp
IpEak = Iout(max) +
/
2
and provide low core loss at the high switch-
ingfrequency.Lowcostpowderedironcores
have a gradual saturation characteristic
but can introduce considerable AC core
loss, especially when the inductor value is
relatively low and the ripple current is high.
Ferritematerials,ontheotherhand,aremore
expensive and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is
exceeded. Nevertheless, they are preferred
at high switching frequencies because they
present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are the
better choice for all but the most cost sensi-
tive applications.
Inductor Selection
Therearemanyfactorstoconsiderinselect-
ing the inductor including cost, efficiency,
size and EMI. In a typical SP6ꢀ38 circuit,
the inductor is chosen primarily for value,
saturation current and DC resistance. In-
creasing the inductor value will decrease
output voltage ripple, but degrade transient
response. Low inductor values provide the
smallest size, but cause large ripple cur-
rents, poor efficiency and need more output
capacitance to smooth out the larger ripple
current. The inductor must also be able to
handle the peak current at the switching
frequencywithoutsaturating,andthecopper
resistance in the winding should be kept as
low as possible to minimize resistive power
loss.Agoodcompromisebetweensize, loss
and cost is to set the inductor ripple current
to be within 20% to 40% of the maximum
output current.
Thepowerdissipatedintheinductorisequal
to the sum of the core and copper losses.
To minimize copper losses, the winding
resistance needs to be minimized, but this
usually comes at the expense of a larger
inductor.Corelosseshaveamoresignificant
contribution at low output current where the
copper losses are at a minimum, and can
typically be neglected at higher output cur-
rents where the copper losses dominate.
Core loss information is usually available
from the magnetic vendor.
The switching frequency and the inductor
operatingpointdeterminetheinductorvalue
as follows:
Vout • (Vin(max) - Vout)
Vin(max) • Fs • Kr • Iout(max)
L =
where:
Fs = switching frequency
Kr = ratio of the ac inductor ripple current
to the maximum output current
The copper loss in the inductor can be cal-
culated using the following equation:
PL(cu) = I2
• Rwinding
L(rms)
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀꢀ
APPLICATION INFORMATION
whereIL(rms) istheRMSinductorcurrentthat
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
can be calculated as follows:
.
iL(rms)
=
.
∆Vout =
.
.
2
ꢀ
3
Ipp
Iout(max)
Iout(max) •
ꢀ +
•
}
{
√
2
{ Ipp • (1-d) }
Cout • Fs
(Ipp•REsr)2
+
Output Capacitor Selection
√
The required ESR (Equivalent Series Re-
sistance) and capacitance drive the selec-
tion of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the ad-
ditional current demanded by the load until
the SP6ꢀ38 adjusts the inductor current to
the new value.
where:
Fs = Switching Frequency
D = Duty Cycle
Cout = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for
ripplecurrentrating,capacitanceandvoltage
rating. The input capacitor must meet the
ripple current requirement imposed by the
switching current. In continuous conduction
mode, the source current of the high-side
MOSFET is approximately a square wave
of duty cycle Vout/VIN. Most of this current
is supplied by the input bypass capacitors.
The RMS value of input capacitor current is
determined at the maximum output current
and under the assumption that the peak to
peak inductor ripple current is low, it is given
Therefore, the capacitance must be large
enough so that the output voltage is held up
while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitor causes a step in the output volt-
age equal to the current. Because of the
fast transient response and inherent ꢀ00%
and 0% duty cycle capability provided by
the SP6ꢀ38 when exposed to output load
transients, the output capacitor is typically
chosen for ESR, not for capacitance value.
by:
.
Icin(rms) = Iout(max)
D (ꢀ-D)
*
*
√
Schottky Diode Selection
When paralleled with the bottom MOSFET,
an optional Schottky diode can improve
efficiency and reduce noise. Without this
Schottky diode, the body diode of the bot-
tom MOSFET conducts the current during
the non-overlap time when both MOSFETs
are turned off. Unfortunately, the body di-
ode has high forward voltage and reverse
recovery problems. The reverse recovery of
the body diode causes additional switching
noisewhenthediodeturnsoff.TheSchottky
diode alleviates these sources of noise and
additionally improves efficiency thanks to its
The output capacitor’s ESR, combined with
the inductor ripple current, is typically the
main contributor to output voltage ripple.
The maximum allowable ESR required to
maintain a specified output voltage ripple
can be calculated by:
∆Vout
ipk-pk
RESR <
where:
∆Vout = Peak to Peak Output Voltage Ripple
ipk-pk = Peak to Peak Inductor Ripple Current
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ2
APPLICATION INFORMATION
low forward voltage. The reverse voltage
across the diode is equal to input voltage,
and the diode must be able to handle the
peak current equal to the maximum load
current.
The first step of compensation design is
to pick the loop crossover frequency. High
crossover frequency is desirable for fast
transient response, but often jeopardizes
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
The power dissipation of the Schottky diode
is determined by:
PDIODE = 2 • VF • Iout • TNOL • FS
where:
ꢀ
ƒz(Esr) =
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
2π • Cout • REsr
The next step is to calculate the complex
conjugate poles contributed by the LC out-
Loop Compensation Design
put filter,
The open loop gain of the whole system can
be divided into the gain of the error ampli-
fier, PWM modulator, buck converter output
stage, and feedback resistor divider. In or-
der to cross over at the selected frequency
FCO, the gain of the error amplifier must
compensate for the attenuation caused by
the rest of the loop at this frequency. The
goal of loop compensation is to manipulate
loop frequency response such that its gain
crosses over 0db at a slope of -20db/dec.
ꢀ
ƒp(Lc)
=
.
.
2π • L • COUT
√
WhentheoutputcapacitorsareofaCeramic
Type,theSP6138EvaluationBoardrequires
aTypeIIIcompensationcircuittogiveaphase
boostof180°inordertocounteracttheeffects
ofanunderdampedresonanceoftheoutput
filter at the double pole frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
+
_
VREF
(Volts)
VOUT
(Volts)
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
(R1 R2
VREF
or
VOUT
)
+
VFBK
(Volts)
Figure 5: SP6138 Voltage Mode Control Loop with Loop Dynamic
Definitions:
REsr = Output Capacitor Equivalent Series Resistance
Rdc = Output Inductor DC Resistance
Vramp _ pp = SP6ꢀ38 internal RAMP Amplitude Peak to Peak Voltage
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ3
APPLICATION INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
Frequency
(Hz)
Figure 6: Bode Plot of Type III Error Amplifier Compensation
Note: Loop Compensation component calculations discussed in this
Datasheet can be quickly iterated with the Type III Loop Compensation
Calculator on the web at:
www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
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Table 1. Input and Output Stage Components Selection Charts
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ4
APPLICATION INFORMATION
SP6138 Efficiency versus load current
@ Vin=12V, Vout=3.3V
90
85
80
75
70
0.5
1.0
1.5
2.0
2.5
3.0
Load current (A)
SP6138 Load Regulation
@ Vin=12V
3.345
3.340
3.335
3.330
0.5
1.0
1.5
2.0
2.5
3.0
Load current (A)
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ5
PACꢀAGE: 16 PIN QFN
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ6
ORDERING INFORMATION
Part Number
Temperature Range
Package
SP6ꢀ38ERꢀ...............................................-40°C to +85°C.......................................... ꢀ6 Pin QFN
SP6ꢀ38ERꢀ/TR.........................................-40°C to +85°C...........................................ꢀ6 Pin QFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6138ER1/TR = standard; SP6138ER1-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 2500 for QFN.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Oct 24-06 Rev J
SP6ꢀ38 Synchronous Buck Controller
© 2006 Sipex Corporation
ꢀ7
Solved by
TM
Appendix and Web Link Information
For further assistance:
Email:
Sipexsupport@sipex.com
WWW Support page:
Sipex Application Notes:
Product Change Notices:
http://www.sipex.com/content.aspx?p=support
http://www.sipex.com/applicationNotes.aspx
http://www.sipex.com/content.aspx?p=pcn
Sipex Corporation
Solved by
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA95035
tel: (408) 934-7500
faX: (408) 935-7600
TM
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
The following sections contain information which is more
changeable in nature and is therefore generated as appendices.
1) Package Outline Drawings
2) Ordering Information
If Available:
3) Frequently Asked Questions
4) Evaluation Board Manuals
5) Reliability Reports
6) Product Characterization Reports
7) Application Notes for this product
8) Design Solutions for this product
Datasheet Appendix & Web Link Information
© 2007 Sipex Corporation
Solved by
APPLICATION NOTE ANP1
TM
Using Sipex PWM Controllers for Boost
Introduction:
Sipex PWM controllers can be configured in boost mode to provide efficient and
cost effective solutions. Circuit operation and design procedure are explained in
the following.
Circuit Operation:
A boost circuit using Sipex’s SP6136 controller is shown in figure 1. When
MOSFET M1 is on, inductor L1 gets charged while the output capacitor sustains
the load current. When M1 turns off, L1 replenishes the capacitor’s charge through
D1. Under light load conditions, the energy stored in the inductor is discharged
before the next switching cycle begins (i.e., inductor current reduces to zero). This
is referred to as Discontinuous Conduction Mode (DCM).
VIN
C1
0.1uF
L1, Vishay IHLP-2525CZ
1.5uH, 9A
Cin
10uF,25V
CVCC
4.7uF
GND
BST VIN
D1, Diodes Inc, B140
VOUT
VCC
R5 10K
PWRGD
Co1
Co2
M1, Siliconix
Si2318DS
100uF,50V
3.3uF, 50V
POWERGOOD
SP6136 GH
EN
ENABLE
Vin
R4
SWN
GL
R1
51.1K, 1%
GND
UVIN
ISP
NC
VFB
ISN
9.09K, 1%
CZ
RZ
COMP
SS
R2
1.5K, 1%
27nF
51.1K
R3
5.11K, 1%
CSS
47nF
PGND
GND
CP
CF1
100pF
56pF
Figure 1- Boost converter based on SP6136, VIN=7 to 18V, VOUT=28V, IOUT=0 to 0.5A,
converter operates at Discontinuous Current Mode under all line and load conditions
11/27/06
Using PWM Controllers for Boost Conversion
© 2006 Sipex Corporation
Design Strategy:
As far as Conduction Mode is concerned, there are basically two choices in
designing a boost converter:
1- Design for Discontinuous Conduction Mode (DCM) over full operating conditions:
This approach offers easy control of the boost converter. With DCM, the converter
transfer function has a single pole (second pole and Right Half Plane (RHP) zero
are insignificant). Peak current (and IRMS) however, will be high at low VIN and/or
high load conditions.
2- Design for Continuous Conduction Mode (CCM) for nominal operating conditions:
With this approach the converter will transition to DCM at light loads. An RHP zero
is present and hence, compensation is more difficult. The inductor current ripple,
however, is significantly reduced.
DCM Boost Design Procedure:
For cases where output current requirement is low, less than 2A, a DCM design
can be used as follows:
1- Controller selection
Sipex offers controllers with fixed operating frequency ranging from 300KHz to
2.5MHz. 600Khz controllers such as SP6136 and SP6134 offer a good
compromise. This intermediate switching frequency helps reduce inductor size
without incurring significant switching losses in the MOSFET M1. SP6134 is
recommended for battery operated applications. This controller requires external
VCC, which can be shut down -- removing VCC results in very low leakage current.
SP6136 is recommended for applications where external VCC is not available.
2- Inductor L1
Select an inductor based on required inductance (L1) and peak current (Ip). The
following calculations assume that in order to ensure DCM operation a dead-time
of 20% of full switching period is needed [1]. Hence, the combined conduction time
of the MOSFET and diode is 80% of the switching period. This is the reason for
K=0.8 used in following equations.
Calculate the required inductance from:
Vo
K ×
× Ton
……………………………………. (1)
Io
L 1 =
2
Vo
Vin , min
⎛
⎞
⎟
2 ×
⎜
⎝
⎠
Where:
K = 0.8 is ratio of MOSFET and diode conduction time to T (T=1/f)
Vo
is output impedance at full load Io
Io
Vo is output Voltage
Vin,min is minimum input Voltage
TON is maximum on time of MOSFET M1.
11/27/06
Using PWM Controllers for Boost Conversion
© 2006 Sipex Corporation
Calculate TON from:
1
0.8 ×
×
(
Vo − Vin , min
)
f
Ton =
………………………… (2)
Vo
Calculate peak inductor current Ip from:
Vin , min
Ip = Ton ×
……………………………………… (3)
L1
Where:
TON is the maximum on time of the MOSFET calculated above
L1 is the inductance calculated above
3- MOSFET M1
Choose M1 based on Voltage rating (BVdss), current rating (Ids), ON resistance
rating RDS(ON)) and gate charge (Qg). BVdss must be greater than Vo of the
converter. M1 must have the current capability to conduct Ip calculated in step 2.
RDS(ON)) can be up to twice the DCR of L1. Select a MOSFET with lowest Qg that
meets the above requirements.
4- Schottky diode D1
Select D1 based on the reverse blocking Voltage (VR) and forward current (IF). VR
must meet the output Voltage requirement of the converter and IF must meet the
peak current requirement Ip calculated in step 2.
5- Input capacitor CIN
Select CIN based on input Voltage requirement, RMS ripple current rating and
capacitance.
Calculate input rms current from equation for triangular current waveform:
0 .8
Irms = Ip
…………………………………………... (4)
3
Where 0.8 is combined conduction time of the MOSFET and diode as explained in
step 2 and Ip is peak inductor current also calculated in step 2. Since peak inductor
current is supplied by the input capacitor, it is used for calculating IRMS for CIN.
Calculate capacitance from:
T −Ton
0.2×V
Cin = Irms×
…………………………………..… (5)
Where T and TON are defined in step 2 of the procedure
6- Output capacitor COUT
For optimum performance use a combination of ceramic and electrolytic
capacitors. A ceramic capacitor with its low ESR helps reduce output Voltage ripple.
11/27/06
Using PWM Controllers for Boost Conversion
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A larger electrolytic capacitor is needed to keep a stiff output Voltage. The choice
of this capacitor is critical since it dictates the frequency of converter’s single pole
(see section 7). In addition, its ESR introduces a “Zero” that limits system
bandwidth. As a rule of thumb, select a 100uF low ESR capacitor and calculate the
uncompensated transfer function and adjust the capacitance value if necessary.
7- Feedback loop compensation
The Control-to-Output transfer function of the converter is shown in figure 2. This is
also referred to as an “uncompensated transfer function”. The converter has
essentially a single pole transfer function due to DCM. Pole frequency fp is
determined by COUT. VIN and IOUT influence fp (and therefore crossover frequency
fc) as shown in figure 2. There is a “Zero” due to ESR of Aluminum Electrolytic COUT.
Use the equations of appendix 1 to plot this transfer function. Then use a type II
compensator to increase the cross-over frequency and increase the low-frequency gain.
Co determines the
pole frequency, fp
Gain (dB)
Max. fc is at
maximum Vin
and load
ESR of Co creates
a "Zero" at
fz = 1 / 6.28 ESR Co
0 (dB)
Low fc at
minimum Vin
and light load
0 (deg)
-90 (deg)
Phase (deg)
Figure 2- Control-to-Output transfer function of DCM boost converter, Gain/phase
corresponding to low VIN and light load are shown in blue.
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Design example:
Design a boost converter that will meet the following requirements: VIN = 7V to 18V
with nominal value of 12V, VOUT = 28V, IOUT = 0.5A. An external VCC is not
available for this design.
Following the design procedure outlined in the previous page:
1- Use Sipex SP6136 for controller.
2- Calculate the required inductance for L1
First calculate the TON of M1 from (2)
1
0.8 ×
×
(
28V − 7V
)
600000 Hz
28V
Ton =
TON = 1us, then use (1) to calculate L1
28 V
0 .8 ×
× 1us
0 .5
28 V
7V
L1 =
2
⎞
⎛
⎜
2 ×
⎟
⎝
⎠
L1 = 1.4 uH (use a 1.5uH standard value)
Calculate peak inductor current from (3)
7V
Ip = 1us ×
1.5uH
Ip = 4.67A
Choose a 1.5uH inductor that meets this current rating. As an example Vishay’s
IHLP-2525CZ-1R5 can be used (l=1.5uH, DCR=15mOhm, I=9A, size=
6.47x6.86x3mm).
3- Select a 40V rated MOSFET that has a 4.67A peak current rating. For example
Siliconix’s Si2318DS can be used (BVdss = 40V, RDS(ON) = 58mOhm, Id=3.5A
(continuous), Qg=10nC).
4- Select a 40V rated Schottky that has a 4.67A peak current capability (ex. Diodes
Inc B140).
5- Use 25V ceramic input capacitor and calculate required IRMS and CIN from (4)
and (5) respectively:
0.8
Irms = 4.67 A ×
3
IRMS = 2.41
1.67 us − 1us
0.2V
Use a 10uF, 25V ceramic capacitor
Cin = 2.41 A ×
= 8.1uF
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6- Use a low ESR 100uF, 50V Aluminum electrolytic (ex., Sanyo 50MV1000WX).
The low ESR helps maximize the “Zero” frequency (see figure 3). Use a 3.3uF
ceramic in parallel to help reduce output ripple.
7- Feedback loop compensation
Using the procedure outlined in appendix 1, the control-to-output transfer function
is calculated and plotted in figure 3. Using an Error Amplifier (EA) with type II
compensation as shown in figure 4, it is desirable to increase the cross-over
frequency fc shown in figure 3 to a maximum of 1/5 of switching frequency fs. In
this example, however, fc cannot be increased due to the ESR zero. In order to
leave fc unchanged, compensation should have a gain of 0dB, hence
RZ=R1=51.1KΩ. Place compensator “Zero” at Max fp=108Hz. Since RZ is already
set at 51.1KΩ, then CZ=28nF (use 27nF). Set the compensator pole at a
sufficiently low frequency to obtain good noise attenuation at the given switching
frequency. For example, in order to obtain a 20dB attenuation at 600khz, set the
pole frequency to 60KHz. Solving for CP, we get CP=52pF (use 56pF).
Min. fp
is 6.6Hz
Max. fp
is 108Hz
40dB
Gain (dB)
0 (dB)
ESR Zero is
at 22KHz
Max. fc is
10.8KHz
Min. fc
is 660Hz
0 (deg)
-90 (deg)
Phase (deg)
Figure 3- Design example Control-to-output transfer function, gain/phase
corresponding to VIN=7V and Io=50mA are shown in blue.
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© 2006 Sipex Corporation
CP
56pF
fp=1/(6.28 CP RZ)
CZ
RZ
Gain=RZ/R1
27nF
51.1K
Gain (dB)
R1
VFB
-
+
COMP
51.1K
fz=1/(6.28 CZ RZ)
Vref =0.8V
CF1
100pF
frequency (Hz)
Figure 4- Error Amplifier (EA) and its transfer function for type II compensation,
components shown are redrawn from figure 1, Error Amplifier is internal to SP6136
controller.
8-Miscellaneous
Select Voltage divider resistors as follows:
Let R2=1.5KΩ then
⎡
⎢
⎣
⎤
⎛
⎞
Vout
Vref
⎜
⎜
⎟
⎟
R1 = R2×
−1
⎥
⎦
⎝
⎠
⎡ 28V
⎤
⎛
⎞
⎟
R1 = 1.5K ×
−1
⎜
⎝
⎢
⎥
0.8V
⎠
⎣
⎦
R1=51K (select 51.1KΩ standard)
Select Under Voltage Lock Out resistors for VIN(start)=7V according to the
procedure given in the data sheet. Choosing R3=5.11KΩ then R4=9.09KΩ.
Other small signal components, shown in figure 1, are standard components
required for the operation of the SP6136.
[1] Switching Power Supply Design, A. Pressman, pages 27, 30.
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© 2006 Sipex Corporation
SP6136 Boost Efficiency versus Iout
95
90
85
80
75
70
65
0
100
200
300
400
500
Iout (mA)
Figure 5- Efficiency at VIN=12V
SP6136 Boost load regulation
28
27.9
27.8
27.7
0
100
200
300
400
500
Iout (mA)
Figure 6- Load regulation at VIN=12V
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Figure 7- Step load response, I1=50mA, I2=500mA, f=1KHz, D=0.5, Ch1=VOUT,
Ch4=IOUT
Figure 8- Converter waveforms at VIN=7V, IOUt=500mA, Ch1=SWN, Ch4=IL
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© 2006 Sipex Corporation
Figure 9- Converter waveforms at VIn=18V, IOUT=500mA, Ch1=SWN, Ch4=IL
11/27/06
Using PWM Controllers for Boost Conversion
© 2006 Sipex Corporation
Appendix 1: Calculation of Boost converter Control-to-Output transfer
function
The following equations can be used to calculate the DC gain and corner
frequency of a boost converter’s Control-to-Output transfer function [2]
Calculate the pole’s corner frequency (fp) from:
(
2 × M
)
− 1
fp =
2 × π ×
(
M − 1
)
× R × C
where:
Vout
Vin
M =
Vout
Iout
R =
C = output capacitance
Calculate the DC gain from:
⎡
⎤
2 × Vout
M − 1
2 × M − 1
⎡
⎤
Gdc =
×
⎢
⎣
⎥
⎦
⎢
⎣
⎥
⎦
D
(
)
Where :
D is steady state duty cycle
Vout
M
=
Vin
Calculate D from:
2 × L
D =
Re × T
Where:
L is output inductance
T is switching period (1/f)
Re is the effective resistance of the small signal model of converter
Calculate Re from:
Vin 2
Re =
Iout ×
(
Vout − Vin
)
[2]- Fundamentals of Power Electronics, Robert Erickson, page 389
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© 2006 Sipex Corporation
Application Note ANP 15
Voltage Mode Control: The Modulator in
Continuous Current Mode (CCM) of operation
There are three main components in the control loop of a voltage mode DC to DC converter.
The three stages are the output stage consisting of the output filter, the modulator gain, and the
voltage loop compensation. The two topologies for generating a PWM signal are fixed ramp
voltage and feed forward voltage topology both of which will be discussed in this document. The
issue of how the modulator gain stage affects the stability of the voltage mode open loop system
and closed loop system in continuous current mode (CCM) will also be discussed.
1. Basics of operation and definitions
The actual PWM signal in a voltage mode regulator is generated by a comparator triggering on
a voltage ramp as shown in diagram 1. This ramp is generated from a clock signal and it can be
fixed to a particular peak voltage or it can be variable depending on Vin as in the feed forward
topology.
Diagram 1
When the error amplifier input (Vcomp) is 0 V the duty cycle is 0% meaning the part is off. When
the error amplifier voltage (Vcomp) is equal to peak of the ramp voltage (Vramp) the driver circuitry
is at 100% duty cycle.
The duty cycle of the controller is defined as D=ton/T where T is the Total time defined with
respect to the comp voltage and the ramp voltage.
ton
D =
(1)
T
ton time = Vcomp
toff time = Vramp-Vcomp
T= ton+toff
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This results in equation 2 by substituting ton and T into the duty cycle equation 1
Vcomp
Vcomp
D =
=
Vcomp +Vramp −Vcomp Vramp
(2)
It is important to note that these definitions could vary from controller to controller depending
on what the driver logic is but for the SP613X family and the PowerBlox family of products the
above definitions hold true.
The gain of the modulator is defined as
∂Vout
Gain =
(3)
∂Vcomp
In the feed forward topology another definition is needed. In a feed forward topology the ramp
voltage is no longer fixed but varies depending on what the input voltage is. The Vramp signal can
go full input voltage range or in many instances it is clamped to a maximum voltage. For
example the SP612X family of products has a K (gain) of 5 with a maximum ramp voltage of 3V.
Thus up to 15V in the IC has feed forward above that voltage it becomes a fixed ramp voltage of
3V.
Vin
Vramp
=
(4)
K
Where K is a constant
The feed forward topology has advantages over a fixed ramp voltage topology which will be
further examined after the Modulator Gains are defined. The constant can be any number
chosen at the time of the initial IC definition.
2. The Buck regulator topology
The buck regulator is one of the most common topologies used. It is well known how the
output voltage is related to Input voltage in equation 5.
Vout = Vin ⋅ D
(5)
D is the Duty Cycle
Substituting Equation 2 into Equation 5
Vcomp
Vramp
Vout = Vin ⋅
(6)
To get the gain we need to take the derivative of equation 6 with respect to Vcomp
.
Vin
Gain =
(7)
Vramp
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For a modulator with feed forward another step is needed to get the proper gain, equation 4
needs to be substituted into equation 7. The result for feed forward modulator gain of the buck
converter is
Vin
Gainfeedforward
=
= K
(8)
1
⋅Vin
K
3. Boost Regulator
Another widely used topology is the Boost regulator. This topology will be investigated here in
some detail since it is a little more complicated than the buck regulator. Once the boost regulator
gain is solved, all of the other topologies can be derived in the same manner. The boost
regulator Vin to Vout relationship is a follows:
1
Vout = Vin ⋅
(9)
1− D
Substituting equation 2 in for duty cycle in equation 9 we get
Vin ⋅Vramp
1
1
Vout = Vin ⋅
= Vin ⋅
=
(10)
Vcomp
1− D
[
Vramp −Vcomp
]
1−
Vramp
The next step is to take the derivative of equation 10 we get the following results:
Vin ⋅Vramp
∂Vout
Gain =
=
(11)
2
∂Vcomp
[
Vramp −Vcomp
]
Substitute equation 2 after solving for Vcomp into equation 11
Vin ⋅Vramp
Vramp − D ⋅Vramp
Vin
1− D
Gain =
=
(12)
(13)
2
2
[
]
Vramp
⋅
(
)
For a feed forward topology substitute equation 4 into 12.
K
Gainfeedforward
=
2
[
1− D
]
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4. The Topologies summarized
Table 1 shows more voltage mode modulator gain values for different topologies. These were
derived the same way as the steps outlined previously in this document. The modulator gains
are for continuous conduction current mode (CCM).
TABLE 1
Topology
Duty Cycle Relationship
Modulator Gain
Fixed Ramp
Modulator Gain
Feed forward
Buck
K
Vin
Vout = Vin ⋅ D
Vramp
K
Boost
1
Vin
Vout = Vin ⋅
2
2
[
1− D
]
1− D
Vramp
Vin
⋅
(
1− D
)
D
K
Negative Buck
Boost
1
-
Vout = Vin ⋅
⋅
2
2
1− D
[
1− D
]
Vramp
(1− D)
Vin
D
1
K
SEPIC*
Cuk*
Vout = Vin ⋅
⋅
2
2
1− D
Vramp
(1− D)
1
[
1− D
]
Vin
D
K
Vout = −Vin ⋅
⋅
2
2
1− D
Vramp
(1− D)
[
1− D
]
5. Effects on the compensation for a Buck Regulator
To see what effect the modulator has on the output filter one has to look at the open loop Bode
plot for the topology. Diagram 2 is the typical open loop filter and modulator Bode plot for a buck
regulator. The modulator gain and the filter gain are added together to get the total open loop
gain for the filter. The important thing to note is that in a fixed ramp topology, as Vin increases so
does the total gain of the open loop filter. This in turn pushes out the crossover frequency of the
filter which in turn affects the positioning of the poles and zeros of the compensation network.
This problem does not exist when the gain of the modulator is fixed as it is in the feed forward
topology.
Filter double Pole FLC
Gain DB
Crossover Frequency
20log Vin/Vramp
0
ESR Zero Fesr
Frequency Hz
Diagram 2 Open Loop Filter Bode Plot
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Diagram 3 Schematic for AC Analysis Simulations
In diagrams 4 5 and 6 we have Bode plots for phase and gain for a compensation network for
a fixed ramp voltage regulator. The compensation was not altered between different simulations
for the different input voltages. The compensation was designed for a 12V input.
Phase
Phase
Gain
Gain
Diagram 4: Vin = 12V,
Diagram 5: Vin = 16V,
Crossover frequency = 100 KHz
Crossover frequency = 73 KHz
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Phase
Gain
Diagram 6: Vin = 28V
Crossover frequency = 200 KHz
As can be clearly seen from diagrams 4, 5 and 6 as the input voltage increases so does the
gain of the modulator. This in turn increases the crossover frequency. There are two well
known effects on compensation when the crossover frequency increases but the compensation
network does not change.
1. The first is that the crossover frequency should be no more than 1/2 of the switching
frequency. This is dictated by the Sampling Theorem to try to avoid aliasing. Typically in a
design 1/5 or 1/10 of the switching frequency is used as a crossover frequency. In diagram 4 it
can be seen that the crossover frequency is 200KHz at 28V in.
2. The second one is that the phase margin will deteriorate as the crossover frequency
increases, which will affect the stability of the converter, as can be seen Diagram 4. This is
because the poles and zeros were set for a different crossover frequency to give phase boost in
a certain frequency range to have proper phase margin. As the crossover frequency increases
the phase will eventually decrease which will make the converter unstable.
This Vin gain issue is negated in the feed forward topology since the Gain is a constant K.
6. How to compensate a buck with large input voltage swings without feed forward
In the feed forward topology this is not as much of a problem, but in a fixed ramp topology to
get good stable compensation with a large input voltage swing the designer needs to consider
how the modulator affects the overall gain of the system. In a buck regulator this means that the
compensation design needs to be done at the highest Vin since this will give the designer the
highest gain. This gain should be the one used to set the crossover frequency. This approach
will guarantee that the regulator will be stable over the whole input range. The drawback of this
is that as Vin decreases, so will the crossover frequency, thus degrading the transient response.
This will be most noticeable when the input voltage range is rather large.
7. Modulator Effects on the open loop Bode plot of a Boost Regulator
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The boost converter is a lot more complicated when it comes to compensation and the effects
of the modulator on the open loop gain. The problem is that the duty cycle has a big effect on
both the filter and the modulator. The effect on the modulator is the same as in the buck
regulator Bode plot, the modulator and output filter responses are added together. In Diagram
7a and 7b are graphs showing the modulator Gain with respect to the duty cycle for a boost
regulator for specific input voltages.
100
80
60
Gain
(dB)
40
20
0
0
0.2
0.4
0.6
0.8
D
Diagram 7a Modulator gain for Vin of 7V and Vramp 1V (From Table 1)
120
100
80
Gain
(dB)
60
40
20
0
0.2
0.4
0.6
0.8
D
Diagram 7b Modulator gain for Vin of 12V and Vramp 1V (From Table 1)
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©2006 Sipex Corporation
Modulator Gain
Filter Double Pole frequency
Right Half plane Zero
RC Zero
Gain DB
2
20log Vin/(1-D)
0
Frequency Hz
Diagram 8 Open Loop Transfer Function
of a boost converter in CCM mode
1− D
Filter Double Pole
RC zero
ωLC =
L ⋅Cout
1
ωRC
=
ESR ⋅Cout
2
(1− D) ⋅ RL
Right Half Plane Zero
Modulator Gain
ωRHP
=
=
L
Vin
Mdb
2
(1− D)
‘
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©2006 Sipex Corporation
0
Phase
Duty Cycle .25
-180
Duty Cycle .5
-270
Frequency Hz
Diagram 9 Phase of a boost regulator
As can be seen from diagrams 7 and 8 and 9, it is not that straightforward when it comes to
compensation of a boost. The generic Bode plot of a boost converter in Diagram 8 clearly states
that the duty cycle plays an important role in defining the open loop gain.
As to the gain of the modulator it can significantly differ depending on the duty cycle, for Vin of
12V, at 25% duty cycle the gain of the modulator is about 25dB; at 75% percent duty cycle it is
about 45dB. Another major thing to consider is that the modulator will have a gain that is
approaching infinity as the duty cycle approaches 100%. The other complication is that the gain
curve exists for every input voltage of the boost regulator, thus complicating the design even
more. Usually as input voltage changes, so will the duty cycle of the design thus creating more
variables to deal with. One saving grace is that for a fixed output the duty cycle decreases as the
input voltage increases, which tends to help keep the modulator gain in check. This can be seen
clearly seen from equation 14 and diagrams 7a and b.
Vin
D =
1
−
(14)
Vout
When a feed forward topology is implemented, the design can be greatly simplified by having
one modulator gain curve for a specific voltage range and thus only having to deal with the
variations of the duty cycle on the analysis. (Table 1)
8. Compensating the Boost Converter
Unlike the buck converter it is much harder to compensate the boost converter for wide input
voltage swing when the output voltage is fixed, since changes in Vin will affect the duty cycle of
the converter. This type of topology typically is better suited to running in narrower duty cycle
ranges with compensation that is not very aggressive. To properly compensate the regulator the
Dec 18-06 Rev D
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©2006 Sipex Corporation
designer needs to make sure that the crossover frequency for his system occurs before the
Right Half Plane Zero (RHPzero) at a slope of -20dB. It is the right half plane zero that contributes
to a sharp decline in phase approaching -270 degrees as seen in diagram 9. The obvious
problem there is that the location of the RHPzero varies with duty cycle and load. Although this
can be discussed in more depth, the focus of this paper is on the modulator effects on the Bode
plots. Thus unlike the buck compensation, it needs to be considered earlier in the design since
the best results are when the duty cycle variation is limited to small changes around the 50%
duty cycle point. At this point is where the gain of the modulator is at its most linear with changes
in gain of 10 to 20db either way from 50% duty cycle point.
9. Summary
The modulator gain has a significant effect on the total open loop gain of the Bode plots. It is
also one of the least talked about topics in control loop theory. Hopefully this paper helped the
reader understand a small but crucial part of the compensation network.
10. Bibliography
1) Fred C. Lee, A CPES Professional Short Course at Virginia Tech Lecture Note,© 2005
2) Wu. Keng C. Pulse Width Modulated DC-DC Converters. New York: Chapman & Hall,
1997.
For further assistance:
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Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Dec 18-06 Rev D
ANP15 Voltage Mode Control
©2006 Sipex Corporation
Solved by
Application Note ANP 16
TM
Loop Compensation of Voltage-Mode Buck Converters
One major challenge in optimization of dc/dc power conversion solutions today is
feedback loop compensation. To the laymen of dc/dc power conversion circuits, this
concern can be not only difficult to understand, but a highly intimidating matter to
deal with. Various effects of feedback loop stability occur with application of
feedback compensation, which, if not properly calculated, can cause instability and
regulation failure to occur. This application note helps to clarify the more advanced
Type-III feedback loop compensation considerations in voltage-mode buck
converter applications, which are viewed as inherently more stable when compared
to current-mode conversion topologies.
Most designers believe the application of ceramic output capacitors is a good
design decision, for both their low cost, abundance of suppliers, and the inherently
low ESR. Ceramic capacitors are indeed a good choice for converter output
filtering, where relatively low capacitance is required. Ceramic capacitors offer low
Equivalent Series Resistance (ESR) that reduces output ripple. However, the
inherently low ESR of the typical ceramic output capacitor necessitates the use of a
Type-III compensation network. The Type-III compensation network, which is more
complicated than Type-II, will be explained in the following text.
Buck Converter System Block Diagram
The system block diagram of a Buck-Converter is shown in figure 1 where VIN and
V
OUt are converter input and output voltage respectively. The Error Amplifier and its
accompanying passive components comprise the compensation network
(compensation). The focus of this application note is the proper selection of these
passive components in order to meet compensation goals. Output of the
compensation network is the analog control signal Vc. The Pulse-width-Modulator
(Modulator) generates a duty-cycle D that is proportional to Vc. Duty-cycle control D
of power switches in conjunction with the filter produce the desired voltage VOUT
from VIN
.
V
IN
V
REFERENCE
Compensated Error
Amplifier
Pulse-Width
Modulator
Power switches &
LC output filter
(Power stage)
VOUT
Vc
D
(Compensation)
(Modulator)
Feedback
Figure 1. System Block Diagram of Buck-Converter
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 1 of 9
© 2006 Sipex Corp.
Open-Loop Response
System response from the input of the Modulator to the output of the power stage is
called “Open-Loop Response”. It is shown in figure 2. The LC output filter gives rise
to a “Double-Pole” that has a -180 degrees phase shift. Double-Pole frequency fLC
is given by:
1
fLC =
………………………….. (1)
2
π LC
The ESR of output capacitor C gives rise to a “ZERO” that has a +90 degree phase
shift. ESR ZERO frequency fESR is given by:
1
fESR =
……………………… (2)
2
π.C.ESR
Figure 2 shows two plots. The top plot is representative of the Open-Loop gain and
the lower plot shows the relevant phase. When the output capacitor is a small
ceramic type, fESR can be significantly larger than fLC. In this case, the phase of the
open-loop reaches -180 degrees before the ESR Zero brings the phase to -90
degrees (see figure 2).
Gain (dB)
20log(Vin/Vramp)
-40dB/dec
f
f
>>f
LC
ESR
LC
0 (dB)
-20dB/dec
0 (deg)
-90 (deg)
> -90deg/dec
Phase (deg)
+45deg/dec
-180 (deg)
Figure 2. Gain/Phase of the Open-Loop Response with ceramic output capacitor
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 2 of 9
© 2006 Sipex Corp.
Goals of Compensation
The goal of compensation is to design a feedback system such that the converter
will be stable and will quickly regulate the output against changes in input voltage or
load conditions. Quick response requires that the Loop 0dB cross-over frequency
“fc” (also known as bandwidth) be as high as practical. In general, compensation is
designed such that (fs/10)<fc<(fs/5); where fs is the switching frequency of the
converter. Stability criterion requires that the phase margin corresponding to “fc”
be greater than 45 degree where
Phase Margin = 180 degree + phase of Loop Gain
In essence we have to shape the Gain/Phase of the Error Amplifier such that when
combined with Gain/Phase of the Open-Loop of figure 2 it satisfies the above
requirements.
Type-III Compensation
Type-III compensation is realized by connecting resistors/capacitors to a controller’s
integral Error Amplifier as shown in figure 3. A nomenclature consistent with Sipex
datasheet is used. Transfer function of Type-III has two “Zeros” and two “Poles” at
the frequencies shown in figure 3. The combined effect of the Zeros results in a 180
degree phase boost. This phase boost is necessary to counter the 180 degree
phase lag due to the output filter double-Pole shown in figure 2 and generate the
required phase margin. In order to simplify the solution for the frequency of the 2nd
Zero and 1st Pole, components must be chosen so that CZ2>>CP1 and R1>>RZ3.
Further simplification can be made by making the frequency of the two Zeros
coincide. As stated above, the goal is to locate the Poles and Zeros of the
compensation such that the desired crossover frequency and corresponding phase
margin is obtained.
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 3 of 9
© 2006 Sipex Corp.
CP1
CZ3
CZ2
RZ3
RZ2
R1
Vout
-
+
Vcomp
Vreference
Conditions: CZ2>>CP1, R1>> RZ3
1/(6.28 RZ2 CZ2)
1/(6.28 RZ2 CP1)
1/(6.28 R1 CZ3)
1/(6.28 RZ3CZ3)
Gain (dB)
20log(RZ2/RZ3)
20log(RZ2/R1)
frequency (Hz)
+90
Maximum boost
possible is 180 degree
Phase (degree)
frequency (Hz)
-90
Figure 3. Type-III compensation and its associated gain/phase plots.
Six resistors and capacitors, when connected to the Error Amplifier as shown,
create a type-III compensation network. Component nomenclature is the same as
commonly used in Sipex datasheets. The frequency of the second “Zero” and first
“Pole” are simplified solutions based on choosing CZ2>>CP1, R1>>RZ3.
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 4 of 9
© 2006 Sipex Corp.
Procedure for Calculating Type-III Components
As was mentioned, when a ceramic output capacitor is applied, the open loop
phase usually drops to -180 degrees or close to it. In order to achieve the required
phase margin of 45 degrees or greater (i.e., phase greater than -135 degrees), a
type-III compensation is needed to provide sufficient phase boost. Let’s assume
that the phase of open-loop system gain is the lowest possible, i.e., 180 degrees.
To get the minimum required closed-loop phase-margin of 45 degrees the
compensation must provide a +45 degree phase margin (i.e., a boost of 95
degrees). In order to maximize the boost, Poles and Zeros must be placed as far
apart as possible. We can now outline a step-by-step procedure for calculating
component values, as follows:
1.) Let R1=68.1kΩ. This value generally provides a satisfactory solution and helps
meet the requirement R1>>RZ3
2.) Place the second Zero at 60% of output filter’s double-Pole frequency and solve
for CZ3:
1
CZ3 =
……………………………..… (3)
1
zsf • R1•
LC
Where
L and C are output inductance and capacitance respectively
zsf is Zero scale factor = 0.6
3.) To set fc to the desired value use the following equation and calculate RZ2 from:
2
• L •C +1
(
2•
π
• fc
)
Vramp
Vin
RZ2 =
x
…………….… (4)
2•π • fc •CZ3
Where
RAMP is the ramp amplitude and VIN is converter’s input voltage
c is typically set at 1/5 to 1/10 of switching frequency
V
f
fs
4.) Set the first Zero to coincide with the second Zero and calculate CZ2 from:
1
CZ2 =
……………………………. (5)
1
zsf • RZ2 •
LC
5.) Set the first Pole at switching frequency of the converter
1
f
s and solve for CP1:
CP1 =
………………………………… (6)
2 •
π • RZ2 • fs
6.) Set the second Pole also at
1
f
s and solve for RZ3:
RZ3 =
…………………………………… (7)
2 •π • CZ3• fs
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 5 of 9
© 2006 Sipex Corp.
Example 1.) Design compensation for a Buck converter with following specification:
V
V
IN
= 12V
RAMP = 1.1V
Note: Loop Compensation component calculations discussed
in this application note can be quickly iterated with the Type III
Loop Compensation Calculator on the web at:
f
s
= 900kHz
= 2.2uH
= 22uF
L
C
www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
ESR = 3mΩ
fLC and fESR (calculated from 1 and 2 above) are 22.9kHz and 2.4MHz respectively.
Since fESR/fLC=105, clearly Type-III compensation has to be used.
Following the above procedure and letting fc=fs/9, we get:
R1 = 68.1kΩ
CZ3 = 170pF
RZ2 = 17.2kΩ
CZ2 = 673pF
CP1 = 10.2pF
RZ3 = 1.04kΩ
Figure 4 plots the actual SPICE simulation supporting these correct values for the
Type-III compensation network.
Figure 4. Spice simulation showing gain/phase for zsf=0.6, cross-over
frequency
degrees
fc is just over 100kHz and corresponding phase margin is 70
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 6 of 9
© 2006 Sipex Corp.
Figure 5. Step load response corresponding to conservative compensation,
0A-2.5A, transient response is 75us
Practical Considerations (adjusting system response)
A key starting point of the above procedure is locating the Zeros at 60% of fLC
(i.e.,zsf=0.6). This, in general, provides a conservative solution. As seen in figure 4,
the phase margin of nearly 70 degrees is quite acceptable. However the tradeoff
between system response and system stability apply. As seen in figure 5, the
transient response is about 75us, not impressive for a 900kHz converter. For a
more aggressive compensation (i.e., faster transient response) locate the Zeros
closer to, or slightly above fLC (i.e., zsf > fLC). For instance if it is desired to get a
faster response for design example 1, let zsf=1.2. Recalculating components for
Example 1 we get:
R1 = 68.1kΩ
CZ3 = 85pF
RZ2 = 34.4kΩ
CZ2 = 168pF
CP1 = 5pF
RZ3 = 2.08kΩ
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 7 of 9
© 2006 Sipex Corp.
Gain/phase for zsf=1.2 are shown in figure 4 and compared to the original solution.
As can be seen, mid-frequency gain is increased by 10dB and phase margin has
decreased 10 degrees with a minimum phase of about 30 degrees. Step load
response is shown in figure 6. As seen, the response time has been reduced
(improved) to a much faster 20us.
Figure 6. Step load response corresponding to aggressive compensation,
transient response has been reduced (improved) to 20us
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 8 of 9
© 2006 Sipex Corp.
Part number Ramp amplitude (V)
SP6132/H
SP6133
SP6134/H
SP6136
SP6137
SP6138
SP6139
1.1
1.0
1.1
1.0
1.1
1.0
1.1
Figure 7- Ramp amplitude of Sipex controllers
Conclusion
With half a dozen simple, low-cost discrete components, and some creative
‘positioning’, Type-III compensation can greatly improve circuit response while
maintaining loop stability. The best part of this compensation case is the allowed
use of low cost ceramic output capacitors for the solution.
For further assistance:
Email:
Sipexsupport@sipex.com
http://www.sipex.com/content.aspx?p=support
http://www.geolink-group.com/sipex/
WWW Support page:
Live Technical Chat:
Type III Loop Compensation
Calculator:
www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
Oct11-06 Loop Compensation of Voltage-Mode Buck Converters
Page 9 of 9
© 2006 Sipex Corp.
Solved by
APPLICATION NOTE ANP20
TM
Properly Sizing MOSFETs for PWM Controllers
Fundamentals of Properly Sizing MOSFETs for Synchronous Buck
Controllers and Their Effects on Efficiency
INTRODUCTION
Today’s electronic designs are focusing more on optimizing efficiency in an
attempt to minimize unnecessary power dissipation not only to maximize battery
life in portable applications but to also assure that the application is running as
“cool” as possible.
One of the challenges facing today’s designers of synchronous buck PWM
controllers is the proper selection of the external MOSFETs. Many designers are
unaware that improper MOSFET selection can result in less than optimum
efficiency and that proper selection becomes an even more prominent
consideration as the conversion ratio increases (increasing input-to-output
voltage ratios).
This application note first reviews the fundamentals of driving a MOSFET and
then discusses the high-side and low-side MOSFET power losses. Efficiency
versus load current data for a typical application circuit using the SP6133
synchronous buck PWM controller is then presented for several configurations of
high-side and low-side MOSFETs to demonstrate the impact on efficiency for
increasing conversion ratios.
IIN
PWM Controller
High-Side
MOSFET
Driver
QH
High-Side
MOSFET
VIN
GH
IGH
L
IOUT
VOUT
Low-Side
MOSFET
Driver
QL
Low-Side
MOSFET
Optional
Schottky
Diode
COUT
Load
GL
IGL
Figure 1: Simplified Synchronous Buck Converter Output Stage Diagram
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 1 of 15
© 2006 Sipex Corporation
FUNDAMENTALS OF DRIVING MOSFETS
Since a designer must select the external high-side and low-side MOSFETs
required for synchronous PWM controllers, the fundamentals of driving these
MOSFETs will be covered before discussing the power losses. Having a clearer
understanding of the MOSFET driver and the load presented by the MOSFET will
make the MOSFET selection process and the task of estimating their power
losses less of a mystery.
A simplified synchronous buck converter diagram is shown in Figure 1. Notice
that the gates of both the high-side and low-side MOSFETs are driven by
independent MOSFET drivers which are contained within the PWM controller.
The term “synchronous” is used to describe the process of turning “on” the low-
side MOSFET when the high-side MOSFET is turned “off” (and visa versa). This
results in higher efficiencies than those obtained by the classical non-
synchronous converter that utilizes a Schottky diode in place of the low-side
MOSFET. Sometimes this Schottky diode is included in synchronous designs
and is placed in parallel with the low-side MOSFET to provide a momentary
conduction path that is lower loss than the internal body diode of the low-side
MOSFET before it is completely turned “on” by the low-side MOSFET driver.
A diagram illustrating the MOSFET driver/MOSFET interface is shown in Fig-
ure 2, and the resulting turn on and turn off switching waveforms are shown in
Figure 3. The capacitances CGS, CGD and CDS are used to model the capacitive
loading effects of the MOSFET. The key MOSFET data sheet parameters for syn-
chronous PWM buck controllers are the input capacitance CISS, the output capac-
itance COSS, the reverse capacitance CRSS, the gate-to-source threshold voltage
V
GS
(
TH), the “Miller” gate plateau voltage VGP, and the gate resistance R
the key MOSFET driver data sheet parameter is the output impedance, R
output current, I , (source or sink) of the MOSFET driver is limited by its output
impedance R and is typically specified on the data sheet as R (high-level output
G
. Also,
. The
O
G
O
O
impedance) and ROL (low-level output impedance). It is important to understand
these parameters and how they have an affect on the MOSFET switching
transients and the resulting overall efficiency of the converter.
VDD
ID
Drain
QG
CEI
MOSFET
Driver
CGD
CDS VDS
RG
RO
Gate
IG
CGS
VGS
Source
Figure 2: MOSFET Driver/MOSFET Interface.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 2 of 15
© 2006 Sipex Corporation
QG=QGS+QGD+QOD
QGD QOD
QGS
VGSF
VGSF
VGS
VGS
VGP
VGS(TH)
VOL
VGP
VGS(TH)
VOL
t
t
VDD
VDD
VDS
VDS
ID
IDD
IDD
ID
VDS(ON)
VDS(ON)
t0 t1 t2
Turn On Switching Waveforms
Figure 3: Turn On & Turn Off Switching Waveforms
t3=tR
t
t'0
t4
t5 t6=tF
t
Turn Off Switching Waveforms
The variables in Figures 2 & 3 are defined and summarized in Table 2, and time
events t thru t in Figure 3 are discussed in Table 1. When reviewing these
switching waveforms and time events, keep in mind that the switching process
happens rapidly (nano-seconds) and that the time events t0 thru t and t0 thru t
0
3
R
F
are not intended to represent static states but rather key dynamic states that
occur during the MOSFET switching process.
Time
Comment(s)
t
t
t
t
t
t
0
0
1
1
2
2
Output of MOSFET driver begins supplying gate charging current.
The gate capacitance charges, and I
to t
1
D=0 since VGS<VGS(TH).
V
The gate capacitance continues charging, and I
GS(TH) is reached; therefore, channel enhancement begins, and ID>0.
to t
0
D
increases due to increasing channel width.
The gate capacitance is fully charged, and I
D
=IDD.
to t
3
The MOSFET is operating in its “active” or “pinch off” region (VGS≥VGS(TH) and VGD≤VGS(TH)),
and CGD discharges causing VDS to decrease resulting in a “Miller” effect capacitance which
steals current from the available gate charging current resulting in an approximate constant
V
GS until CGD has fully discharged. I
GD has fully discharged; therefore, VDS is at a minimum, and the MOSFET is now operating
in its “saturation” or “triode” region (VGS≥VGS(TH) and VGD≥VGS(TH)).
VGS begins increasing again due to additional charging of the gate capacitance referred to as
D≅IDD (remains approximately at a constant value).
t
t
3
3
C
+
“overdrive” charging. The MOSFET Driver gate charging current is essentially zero once VGS
has reached its final value of VGSF. At this point, the MOSFET’s channel is fully enhanced.
Table 1: Discussion of Turn-On Time Events t0 thru t3 in Figure 3
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 3 of 15
© 2006 Sipex Corporation
Variable Description
Units
Volts
Volts
Comment(s)
V
V
GS
Gate-to-Source Voltage
Final Gate-to-Source
Voltage
Instantaneous value
VGSF >> VGS(TH)
GSF
V
GS
GP
(
TH
)
Gate-to-Source Threshold
Voltage(Channel
Enhancement Begins)
“Miller” Gate Plateau
Voltage
Volts
Volts
Obtained from MOSFET data sheet
Obtained from MOSFET data sheet
V
V
DS
(
ON
)
“On” State Drain-to-Source Volts
Voltage
VDS(ON)=(ID)(RDS(ON)) where RDS(ON) is the Drain-to-
Source “On” state resistance of the MOSFET
obtained from the data sheet
Instantaneous value
V
V
DS
Drain-to-Source Voltage
Supply Voltage
Volts
Volts
Amps
DD
Constant value
I
G
MOSFET Driver Output
Current
Drain Current
Obtained from MOSFET driver/PWM controller data
sheet
Instantaneous value
I
I
D
Amps
Amps
DD
Final Drain Current
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain “Miller”
Charge
Value of ID when MOSFET channel is fully enhanced
Q
Q
Q
G
Coulombs
Coulombs
Coulombs
Q
-
G=QGS+QGD+QOD=(CEI)(VGSF)=(CEI)(VOH)
GS
GD
-
Q
OD
Overdrive Charge After
Charging “Miller”
Capacitance
Coulombs
Farads
-
CGS
Gate-to-Source
Capacitance
C
ISS = CGS + CGD
C
GD
DS
Gate-to-Drain Capacitance Farads
C
C
RSS = CGD
C
Drain-to-Source
Capacitance
Equivalent Gate
Capacitance
Rise Time
Farads
Farads
seconds
seconds
OSS = CGD + CDS
CEI
C
EI=QG/VGSF=QG/VOH
t
t
t
R
Majority of turn on switching losses occur during this
time
F
Fall Time
Majority of turn off switching losses occur during this
time
Time
seconds
Ohms
Ohms
-
Obtained from MOSFET data sheet
R
G
O
Gate Resistance
MOSFET Driver Output
Impedance (High-Level or
Low-Level Output
Impedance)
R
R
(Low-Level Output Impedance). Obtained from
MOSFET driver/PWM controller data sheet
O=ROH (High-Level Output Impedance) or ROL
RDS(ON)
Drain-to-Source “On” State Ohms
Resistance
Obtained from MOSFET data sheet.
specified at one or more different gate-to-source
voltages.
Usually
Table 2: Definition & Summary of Variables in Figures 2 & 3
The capacitances specified on most MOSFET data sheets are Ciss (input
capacitance with VDS=0V), COSS (output capacitance with VGS=0V), and CRSS
(reverse capacitance with VGS=0V). MOSFET manufacturers prefer to specify
CRSS, COSS and CRSS instead of CGS, CGD and CDS because they can be directly
measured. The relationships between these capacitances are given by the
following equations:
(1)
(2)
(3)
CISS = CGS + CGD
COSS = CGD + CDS
CRSS = CGD
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 4 of 15
© 2006 Sipex Corporation
Since CISS, COSS and CRSS can be obtained from the MOSFET’s data sheet and
RSS=CGD, the other capacitances CGS and CDS can be easily obtained from these
equations. It is common practice to assume that CGS is a constant value and
independent of the state of the MOSFET (values of VGS, I , etc.). CGD and CDS on
C
D
the other hand are both dependent on the value of VDS; however, this relationship
will be ignored to simplify the remainder of the discussion since we are primarily
looking for approximate expressions for the turn on rise time and turn off fall time
which can be used later to estimate the MOSFET switching losses .
The times t
1
, t
2
and the time interval t
given by the following equations.
3
-t
2
during the MOSFET turn “on” period are
1
(4)
t = (ROH + RG )(CGS + CGD )ln
1
VGS (TH )
1−
VGSF
1
(5)
(6)
t = (ROH + RG )(CGS + CGD )ln
2
VGP
VGSF
1−
(
VDD −VDS(ON ) )(ROH + RG )(CGD
)
t − t =
3
2
VGSF −VGP
The majority of the turn-on switching losses in the MOSFET occur during the
time frame t -t which we will refer to as the rise time, t , and is approximately
found from equations (1) thru (6) as
3
1
R
V
−VGS (TH )
(VDD )(Crss )(ROH + RG )
GSF
(7)
tR =
+ (ROH + RG )(Ciss )ln
VGSF −VGP
VGSF −VGP
This expression will yield a fairly reasonable estimate for the turn-on switching
rise time and will be utilized in the analysis of the high-side and low-side
MOSFET power losses in the next section. As mentioned earlier, this expression
for tR assumes that CGD and CDS are both independent of the value of VDS, and the
value for VDS(ON) is assumed to be negligible. Also, the MOSFET package
parasitic inductances were ignored in order to simplify the analysis. If these
parasitics were taken into account, the rise time would be greater, so it is
probably best to use the worst-case data sheet values for CRSS, ROH, R
that yield the largest rise time value in equation (7).
G, CISS, etc
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 5 of 15
© 2006 Sipex Corporation
The time t4, and the time intervals t5-t4 and t6- t5 during the MOSFET turn “off”
period are given by the following equations.
VGSF
(8)
(9)
t = (ROL + RG )(CGS + CGD )ln
4
VGP
V
−VDS (ON )
DD
t − t = (ROL + RG )(CGD )
5
4
VGP
VGP
(10) t − t = (ROL + RG )(CGS + CGD )
6
5
VGS (TH )
As with the calculation of turn-on switching losses, the majority of the turn-off
switching losses in the MOSFET occur during the time frame t -t which we will
, and is approximately found from equations (1) thru (3)
6
4
refer to as the fall time, t
and (8) thru (9) as
F
VDD
VGP
VGP
(11) tF = (ROL + R ) C
+ Ciss
G
rss
VGS (TH )
As with the turn-on switching rise time, this expression also yields a fairly
reasonable estimate for the turn-off switching fall time and will be utilized in the
analysis of the high-side and low-side MOSFET power losses in the next section.
Pertinent data sheet values used in the calculation of tF and tF using equations
(7) and (8) are summarized in the following Table 3 for the SP6133 synchronous
buck (step-down) PWM controller driving the Vishay Siliconix Si4394DY and
Si4320DY n-channel MOSFETs. For high conversion ratio buck converters, the
Si4394DY is best used on the high-side, and the Si4320DY is best used on the
low-side (more on this later).
SP6133
9V min, 12V typ, 15V max
5V typ
Si4394DY
Si4320DY
V
DD
-
-
-
-
-
-
V
GSF
R
OH
2.5
1.5
Ω
Ω
typ, 3.9
Ω
Ω
max
max
R
OL
-
-
typ, 1.9
C
ISS
-
-
-
-
1900pF typ
530pF typ
120pF typ
6500pF typ
930pF typ
610pF typ
C
OSS
RSS
C
R
G
1.2
typ, 9.75m
0.6V min, 1.8V max, 1.2V avg 1V min, 3V max, 2V avg
2.0V typ 3.5V typ
Ω
typ
1.1
Ω typ
R
DS(ON)
GS(TH)
-
7.7m
Ω
Ω
max
3.2m
Ω
typ, 4m
Ω max
V
-
-
V
GP
Table 3: Pertinent Data Sheet Values for the SP6133, Si4394DY & Si4320DY
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 6 of 15
© 2006 Sipex Corporation
The minimum and maximum values for VGS(TH) were used to yield “average”
values since typical values were not specified on the Si4394DY and Si4320DY
data sheets.
The resulting values for t
R
and t
values of the supply voltage VDD
F
are summarized in Table 4 for several different
.
Si4394DY
12V
Si4320DY
VDD
9V
15V
5.4ns
12.6ns
9V
12V
47ns
40.4ns
15V
53ns
42.0ns
t
R
4.1ns
11.5ns
4.7ns
12.0ns
41ns
38.8ns
t
F
Table 4: tR and tF Estimates for the SP6133 Driving the Si4394DY & Si4320DY
Notice that the rise and fall time values for the Si4394DY are much smaller than
those for the Si4320DY. This is a result of the Si4394DY’s much smaller CISS
OSS and CRSS capacitance values as summarized in Table 3. These rise and
,
C
fall time values will be utilized in the next section when the high-side and low-side
MOSFET power losses are investigated.
Another method commonly employed to provide rough estimates for the turn-on
rise and turn-off fall times is to utilize the gate-to-source voltage (VGS) versus
total gate charge (QG) curve which is typically supplied on the MOSFET’s data
sheet. These curves for the Si4394DY and Si4320DY MOSFETs are shown in
the following Figure 4.
Figure 4: VGS vs. QG Curves for the Si4394DY and Si4320DY MOSFETs
The final gate-to-source voltage, VGSF, for the SP6133 was given earlier as 5V
typ, so the total gate charge, Q , can be estimated from these curves as 14nC
for the Si4394DY and 48nC for the Si4320DY. The MOSFET driver output
current, I , is approximated for both the turn-on and turn-off switching time
G
G
intervals as,
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 7 of 15
© 2006 Sipex Corporation
Si4394DY
I
G
(
ON)≡MOSFET Driver Turn-On Output Current (Source)≅VGSF/(ROH +ROH)=5V/(2.5Ω+1.2Ω)=1.35A
OFF)≡MOSFET Driver Turn-Off Output Current (Sink)≅VGSF/ROL +R )=5V/(1.5Ω+1.2Ω)=1.85A
I
G(
G
Si4320DY
I
G
(
ON)≡MOSFET Driver Turn-On Output Current (Source)≅VGSF/(ROH +RG)=5V/(2.5Ω+1.1Ω)=1.39A
OFF)≡MOSFET Driver Turn-Off Output Current (Sink)≅VGSF/ROL +R )=5V/(1.5Ω+1.1Ω)=1.92A
I
G(
G
This, of course, assumes that the MOSFET driver output current remains
constant during the turn-on and turn-off switching transients which is not the case
in reality. The turn-on rise and turn-off fall times can now be approximated for
both MOSFETs as follows.
Si4394DY
Si4320DY
tR≅Q
G/IG(ON)=14nC/1.35A=10.4ns
tR≅Q
G/IG(ON)=48nC/1.39A=34.5ns
tF
≅Q
G/IG(OFF)=14nC/1.85A=7.57ns
tF
≅Q
G/IG(OFF)=48nC/1.92A=25.0ns
Keep in mind that these are simply quick estimates and that the results found
earlier in Table 4 are going to be in better agreement with actual laboratory
measurements.
HIGH-SIDE & LOW-SIDE MOSFET POWER LOSSES
For the simplified synchronous buck converter illustrated in Figure 1, the ratio of
the input voltage to the output voltage is defined as the “conversion ratio” and is
approximately equal to the inverse of the high-side MOSFET switch duty cycle.
The high-side MOSFET duty cycle is defined as the ratio of its “on” time, tON, to
the total switching frequency period which is constant for a fixed frequency PWM
controller. The following equations summarize these relationships.
(12)
(13)
VOUT < VIN
fS ≡ PWM Switching Frequency
(14) Τ ≡ PWM Switching Frequency Period = 1/f
S
(15)
(16)
D
≡
Duty Cycle of High-Side MOSFET Switch
Conversion Ratio 1/D
≅ tON/Τ
V
IN/VOUT
≡
≅
As can be seen from these relationships, buck converters with high conversion
ratios create significant challenges for the PWM controller since the high-side
MOSFET duty cycle decreases for increasing conversion ratios. Since high
switching frequencies are generally employed in PWM controllers to reduce the
size of the inductor and capacitors, very short duration high-side MOSFET pulses
are required. For example, if VIN=15V and VOUT=1.8V, tON is found as 400ns for
a PWM switching frequency of 300kHz, but is a mere 48ns for a PWM switching
frequency of 2.5MHz. Producing PWM pulses this short in duration can prove to
be challenging for most PWM controllers since it becomes taxing to fully turn the
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 8 of 15
© 2006 Sipex Corporation
MOSFET “on” before having to turn around and turn it back “off” again making it
difficult to efficiently achieve high conversion ratios.
The power losses associated with the high-side and low-side MOSFETs are a
combination of the conduction and switching losses. The conduction losses are
a result of the I2R losses in the MOSFET when it is fully enhanced and turned
“on”, and the switching losses are a result of the MOSFET turn-on and turn-off
transitions. The high-side MOSFET power losses, PQH, and low-side MOSFET
power losses, PQL, can be approximated by the following equations.
t
+ tFH
2
RH
(17)
P
= P
+ P
≅ IOUT RDS(ON )H D +
V I
fS
QH
QH (C)
QH (SW )
IN OUT
2
t
+ tFL
2
RL
(18) P = P
+ P ≅ IOUT RDS(ON )L
QL(SW )
(1− D
)
+
V
DIODEL IOUT fS
QL
QL(C)
2
Where,
P
QH
QH
(
(
C
)
≡
High-Side MOSFET Conduction Losses
High-Side MOSFET Switching Losses
Low-Side MOSFET Conduction Losses
Low-Side MOSFET Switching Losses
P
P
P
SW) ≡
QL
QL
(C) ≡
(
SW
)
)
)
≡
)
R
DS
DS
(
ON
ON
H
L
≡
≡
High-Side MOSFET Drain-to-Source “On” State Resistance
Low-Side MOSFET Drain-to-Source “On” State Resistance
R
(
t
t
t
t
RH
≡
≡
High-Side MOSFET Turn-On Rise Time
High-Side MOSFET Turn-Off Fall Time
Low-Side MOSFET Turn-On Rise Time
Low-Side MOSFET Turn-Off Fall Time
RH
RL
FL
≡
≡
V
DIODEL ≡ Low-Side MOSFET Internal Body Diode Forward Voltage Drop
Approximate expressions for the turn-on rise and turn-off fall times were found in
the previous section and can be utilized in equation (17) to approximate the
switching power losses for the high-side and low-side MOSFETs. Keep in mind
that a MOSFET with a lower RDS(ON) will result in lower conduction losses;
however, it typically will have a higher QG resulting in higher switching losses, so
a careful balance between these characteristics should be considered to
maximize efficiency. Also, notice that the low-side MOSFET switching losses
depends on the MOSFET’s own internal body diode since it limits the voltage
drop across the MOSFET during switching transitions to about 1V for both the
Si4394DY and Si4320DY. An external Schottky diode can be added in parallel
with the low-side MOSFET to further reduce these switching losses since they
typically have forward voltage drops of just a few tenths of a volt.
As can be seen upon examination of PQH, the high-side MOSFET conduction
losses increase as RDS(ON), IOUT or D increase (or as the conversion ratio 1/D
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 9 of 15
© 2006 Sipex Corporation
decreases), and the switching losses increase as Q
increase. A similar examination of PQL shows the low-side
MOSFET conduction losses also increase as RDS , IOUT or the conversion
ratio 1/D increase (or as D decreases), and the switching losses also increase as
(and, therefore tRL and tRL), IOUT or f increase. Keep in mind that VDIODEL
will stay fairly constant for varying operational parameters such as IOUT, VOUT, D,
etc. The entire term for PQL can become negligible in some cases if a low
G (and, therefore tRH and tFH),
V
IN, IOUT or f
T
(
ON)
Q
G
S
(
SW)
forward voltage drop Schottky diode is added in parallel with the low-side
MOSFET making it a near zero-voltage-switched device.
As intuition might suggest, for a given PWM switching frequency the efficiency
peaks where conduction losses in the high-side MOSFET are equal to its
switching losses. Therefore, the high-side and low-side MOSFET selection
procedure should begin by first identifying the nominal operational values for VIIN
V
,
OUT, IOUT and fOUT. A reasonable attempt should then be made to identify a
high-side MOSFET that has parameters resulting in approximately equal
conduction and switching losses. The low-side MOSFET should then be
selected that has the lowest possible RDS(ON) that is available in a small enough
package that satisfies any space or cost constraints. Care must also be taken to
assure that the maximum junction temperature is not exceeded for each
MOSFET over the entire input voltage range at the maximum expected load
current and ambient temperature.
APPLICATION CIRCUIT
The SP6133 is a synchronous buck (step-down) PWM controller and is designed
to drive a pair of external, n-channel, enhancement mode MOSFETs at a fixed
300 kHz frequency. The part is designed for single supply operation at input
voltages ranging from 5V up to 24V and can generate output voltages as low as
0.8V and up to 95% of the input voltage. The part’s powerful internal MOSFET
gate drivers can drive the gates of external MOSFETs capable of handling output
currents as high 30A.
A schematic of the application circuit used to collect efficiency versus load
current data can be seen in Figure 5. The circuit utilizes the SP6133
synchronous buck PWM controller. Several different MOSFET configurations
were investigated using the Vishay Siliconix Si4320DY and Si4394DY n-channel
MOSFETs. The input voltage, VIN, was varied from 9V up to 15V while the
output voltage, VOUT, was held constant at 3.3V; therefore, as the input voltage is
increased the conversion ratio increases. For each MOSFET configuration and
input voltage, the load current was swept from 0A up to 10A using an electronic
DC load.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 10 of 15
© 2006 Sipex Corporation
VIN
C1
C2
22
DBST
9V-15V
GND
22µ
F
µF
VCC
16V
16V
8
7 6 5
BAT54WS
QT
CBST
CVCC
10
0805
4
µ
F
0.1µ
F
C1,C2,C3,C4
CERAMIC,1210,X5R
1
2
3
4
12
1 2 3
GL
GH
11
U1
GND SP6133
3
Ω
R
PGND
SWN
GND3
10
ISP
8
7 6 5
9
VFB
ISN
CS
RS3
NP
C6
6.8nF
QB
L1 SC5018-2R7M
0.1µ
F
4
2.7µH, 15A, 4.1mΩ
R3
CSS
1
2 3
VOUT
20.0k
Ω
,1%
47nF
UVIN
R5
RS1
C3
C4
3.30V
0-10A
PWRGD
100
µF
100µF
5.11kΩ
,1%
10.0kΩ,1%
R4
EN
C5
6.3V
6.3V
1
2
3
10.0kΩ
,1%
J1
RS2
0.01µF
GND2
PTC36SAAN
5.11kΩ,1%
CZ3
RZ3
CZ2
RZ2
R1
23.2kΩ,1%
1,500pF
560pF 1kΩ,1%
68.1k
Ω
,1%
CP1
CF1
R2
39pF
22pF
21.5kΩ
,1%
Notes:
1) All resistors & capacitors size 0603 unless other wise specified
Figure 5: Application Circuit Schematic Using the SP6133
EFFICIENCY DATA
Efficiency versus load current data for the application circuit presented in Figure
5 was collected for several configurations of high-side (QT) and low-side (QB)
MOSFETs in order to demonstrate the impact on the efficiency for increasing
conversion ratios.
Three different input voltages were used to collect the data: 9V, 12V and 15V.
The output voltage was held constant at 3.3V while the output current was swept
from 0A up to 10A. Data was collected for several different MOSFET
configurations as outlined in Table 5.
MOSFET Configuration
QT
Si4394DY Si4320DY Low Switching &
Conduction Losses
Si4320DY Si4394DY High Switching &
Conduction Losses
Si4320DY Si4320DY High Switching
Losses
Si4394DY Si4394DY High Conduction
Losses
QB
(4m
(9.75m
(4m
(9.75m
Comment
Optimum
(9.75m
(4m
(4m
(9.75m
Ω
)
Ω)
Reverse
Ω
)
Ω)
High-Side Substitute
Low-Side Substitute
Ω
)
Ω)
Ω
)
Ω)
Table 5: MOSFET Configurations Used to Collect Efficiency vs. Load
Current Data.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 11 of 15
© 2006 Sipex Corporation
As can be seen in Plot 1 the efficiency data curves for both the optimum and
reverse configurations almost overlay each other at each input voltage setting for
load currents less than about 1.5A. For load currents greater than about 2.0A
the efficiency data curves begin to diverge for each input voltage setting with the
greatest spreads occurring at the higher input voltages of 12V and 15V (higher
conversion ratios). This divergence is due to the increased conduction losses
associated with the reversed low-side MOSFET.
SP6133 Efficiency vs. Load Current for Different MOSFET Configurations @ Various Input Voltages & VOUT=3.3V
Optimum Configuration: QT=Si4394DY (9.75mΩ) QB=Si4320DY (4mΩ)
Reverse Configuration: QT=Si4320DY (4mΩ), QB=Si4394DY (9.75mΩ)
100.00
95.00
90.00
85.00
80.00
75.00
70.00
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
Optimum VIN=9V
Optimum VIN=12V
Optimum VIN=15V
Reverse VIN=9V
Reverse VIN=12V
Reverse VIN=15V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Load Current (A)
Plot 1: Efficiency vs. Load Current Data for Optimum & Reverse MOSFET
Configurations.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 12 of 15
© 2006 Sipex Corporation
Upon study of Plot 2, the greatest spread of efficiencies for the two configurations
at each input voltage setting occurs at medium load currents with convergence
occurring at the smaller and larger load currents.
SP6133 Efficiency vs. Load Current for Different MOSFET Configurations @ Various Input Voltages & VOUT=3.3V
Optimum Configuration: QT=Si4394DY (9.75mΩ) QB=Si4320DY (4mΩ)
High-Side Substitute Configuration: QT=Si4320DY (4mΩ), QB=Si4320DY (4mΩ)
100.00
95.00
90.00
85.00
80.00
75.00
70.00
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
Optimum VIN=9V
Optimum VIN=12V
Optimum VIN=15V
QH Substitute VIN=9V
QH Substitute VIN=12V
QH Substitute VIN=15V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Load Current (A)
Plot 2: Efficiency vs. Load Current Data for Optimum
& High-Side Substitute MOSFET Configurations.
Plot 3 shows some interesting results. The efficiencies at medium and light load
currents for each input voltage setting for the reverse configuration are
significantly greater than they are for the optimum configuration. Only at the
larger load currents does a reversal occur and even then, the differences in
efficiencies are less than 1%.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 13 of 15
© 2006 Sipex Corporation
SP6133 Efficiency vs. Load Current for Different MOSFET Configurations @ Various Input Voltages & VOUT=3.3V
Optimum Configuration: QT=Si4394DY (9.75mΩ) QB=Si4320DY (4mΩ)
Low-Side Substitute Configuration: QT=Si4394DY (9.75mΩ), QB=Si4394DY (9.75mΩ)
100.00
95.00
90.00
85.00
80.00
75.00
70.00
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
Optimum VIN=9V
Optimum VIN=12V
Optimum VIN=15V
QL Substitute VIN=9V
QL Substitute VIN=12V
QL Substitute VIN=15V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Load Current (A)
Plot 3: Efficiency vs. Load Current Data for Optimum & Low-Side
Substitute MOSFET Configurations.
The following Table 6 compares the peak efficiencies in addition to the
efficiencies at load currents of 1A and 10A for the various MOSFET
configurations at each input voltage setting.
MOSFET Configuration Peak Efficiency (%) Efficiency (%) @ 1A Efficiency (%) @ 10A
9V
12V
94.7
92.8
93.0
94.8
15V
93.9
91.4
91.5
94.0
9V
12V
85.5
86.1
83.5
89.1
15V
82.6
83.0
80.1
86.9
9V
12V
94.1
91.7
92.8
93.5
15V
93.2
90.6
91.2
93.0
Optimum
Reverse
95.5
94.2
94.3
95.7
89.0
89.4
87.1
91.7
94.6
92.9
93.8
94.3
High-Side Substitute
Low-Side Substitute
Table 6: Efficiency Comparison for the Various MOSFET Configurations.
As can be seen from this table, the optimum configuration clearly dominates at
the highest load current setting of 10A with the most pronounced exceptions
occurring at medium and light load currents for the low-side substitute.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 14 of 15
© 2006 Sipex Corporation
CONCLUSIONS
Proper selection of the high and low-side MOSFETs for synchronous buck PWM
controllers clearly has an affect on the overall conversion efficiency with the
effects becoming more pronounced at higher conversion ratios and load currents.
Different high and low-side MOSFETs may sometimes be necessary in order to
optimize the overall conversion efficiency; however, the additional cost and
hassle associated with having to purchase and stock two separate parts may not
justify the sometimes rather small gains in efficiency. This decision will ultimately
be driven by cost structures and the overall system requirements.
For further assistance:
Email:
Sipexsupport@sipex.com
WWW Support page:
Live Technical Chat:
Sipex Application Notes:
http://www.sipex.com/content.aspx?p=support
http://www.geolink-group.com/sipex/
http://www.sipex.com/applicationNotes.aspx
Sipex Corporation
Solved by
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA95035
tel: (408) 934-7500
faX: (408) 935-7600
TM
S
ipex Corporation reserves the right to make changes to any products described herein. Sipex
does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of
others.
Nov 16-06
Application Note: Properly Sizing MOSFETs
Page 15 of 15
© 2006 Sipex Corporation
Solved by
Design Solution # 41
TM
Reducing Parasitic Oscillations
Designed by: Shahin Maloyan
Part Numbers: SP6133/6, SP6134, SP6132
Application Description: Any noise-sensitive application where synchronous
buck converters are used.
Electrical Requirements:
Input Voltage
Output Current
5V – 24V
higher than 10A
Circuit Description:
There usually exist high-frequency parasitic oscillations at the node between the
switching FET and synchronous FET (SWN). It is not uncommon to see SWN
peak voltage as high as 2.5xVIN. The oscillations are a product of parasitic
inductance in the DC-Loop of the Printed Circuit Board (PCB) and snappy
reverse-recovery of synchronous FET’s body diode. A dissipative R-C snubber
across the synchronous FET dampens the oscillation quickly and reduces the
peak voltage.
This report includes the application schematic and a procedure for determining
the R-C snubber components Resistors and Capacitors.
Switching FET
GH
SWN
Sipex
Controller
Synchronous FET
R-C snubber
GL
Rs
Cs
Application Schematic
Oct 10-06
Design Solution 41
Page 1 of 2
© Sipex Corporation
Figure 1: SWN without R-C snubber
Figure 2: SWN with R-C snubber
Comments:
Oscillations at the switching node (SWN) are a product of parasitic inductance in
the PCB’s DC-Loop and snappy recovery of Synchronous FET’s body diode. The
parasitic inductance stores energy when the switching FET conducts. Following
the recovery of the synchronous FET’s body diode, this energy is transferred back
and forth between the parasitic inductance and output capacitance of the
synchronous FET (Coss). The oscillations stress the SWN node of the controller
plus the synchronous FET and are a potential source of Electro Magnetic
Interference.
Procedure for selecting snubber components
Let Cs = 4 x Coss
Where:
Cs is the snubber capacitor
Coss is the output capacitance of the synchronous FET. Determine the value
corresponding to VIN of the converter from the Coss graph in the FET datasheet.
As a rule of thumb use a 0.25W Resistor Rs in the 2 to 3Ω range. Place the
snubber components as close to the FET as possible.
Oct 10-06
Design Solution 41
Page 2 of 2
© Sipex Corporation
Solved by
SP6138 (3A MAX.)
TM
Evaluation Board Manual
ꢀ Easy Evaluation for the
SP6138ER1 12V Input, 0 to 3A
Output Synchronous Buck
Converter
ꢀ Precision 0.80V with 1% High
Accuracy Reference
ꢀ Small form factor
ꢀ Feature Rich: Single supply operation, Over-
current protection with auto-restart, Power
Good Output, Enable input, Fast transient
response, Supply and Output Dead Short
Circuit Shutdown Protection, Programmable
SP6138EB SCHEMATIC
Aug 24-06
SP6138 Evaluation Manual
©2006 Sipex Corporation
USING THE EVALUATION BOARD
1) Powering Up the SP6138EB Circuit
Connect the SP6138 Evaluation Board with an external +12V power supply. Connect
with short leads and large diameter wire directly to the “VIN” and “GIN” posts. Connect a
Load between the “VO” and “GO” posts, again using short leads with large diameter wire
to minimize inductance and voltage drops.
2) Measuring Output Load Characteristics
It’s best to ground any reference scope and digital meters using the Star GND post in
the center of the board. VOUT ripple can best be seen by touching the probe tip to the
pad for COUT and the scope GND collar touching the Star GND post – avoid a GND lead
on the scope which will increase noise pickup.
3) Using the Evaluation Board with Different Output Voltages
The SP6138 Evaluation Board has been tested and delivered with the output set to
3.30V. By simply changing one resistor, R2, the SP6138 can be set to other output
voltages. The relationship in the following formula is based on a voltage divider from the
output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V.
Standard 1% metal film resistors of surface mount size 0603 are recommended.
V
OUT = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ (VOUT / 0.80V ) – 1 ]
Where R1 = 68.1KΩ and for the VOUT = 0.80V setting, simply remove R2 from the
board. Furthermore, one could select the value of R1 & R2 combination to meet the
exact output voltage setting by restricting R1 resistance range such that 50KΩ ≤ R1 ≤
100KΩ for overall system loop stability.
Note that since the SP6138 Evaluation Board design was optimized for 12V down
conversion to 3.30V, changes of output voltage and/or input voltage will alter
performance from the data given in the Power Supply Data section.
POWER SUPPLY DATA
The SP6138EB is designed with an accurate 1.5% reference over line, load and
temperature. Figure 1 data shows a typical SP6138ER Evaluation Board efficiency plot,
with efficiencies to 86% and output currents to 3A. SP6138ER Load Regulation in
Figure 2 shows only 0.09% change in output voltage step response from no load to 3A
load. Figures 3 and 4 show the fast transient response of the SP6138. Start-up
response in Figures 5, 6 and 7 show a controlled start-up with different output load
behavior when power is applied where the input current rises smoothly as the soft-start
ramp increases. In Figure 8 the hiccup mode gets activated in response to an output
dead short circuit condition and will soft-start until the over-load is removed. Figures 9
and 10 show output voltage ripple less than 10mV over the complete load range.
While data on individual power supply boards may vary, the capability of the SP6138ER
of achieving high accuracy over a range of load conditions shown here is quite
impressive and desirable for accurate power supply design.
Aug 24-06
SP6138 Evaluation Manual
Page 2 of 9
©2006 Sipex Corporation
Output Voltage vs Load Current
Efficiency vs Load Current
3.36
3.35
3.34
3.33
100
90
80
70
60
50
40
Vin=12V
Vout=3.3V
Vin=12V
Vout=3.3V
0.0
0.5
1.0
1.5
2.0
Load current (A)
2.5
3.0
0.0
0.5
1.0
1.5
Load current (A)
2.0
2.5
3.0
Figure 1. Efficiency vs Load
Figure 2. Load Regulation
Vout (100mV/div)
Vout (200mV/div)
Vin=12V
Vout=3.3V
Vin=12V
Vout=3.3V
Iout (2A/div)
Iout (2A/div)
Figure 3. Load Step Response: 1->3A
Figure 4. Load Step Response: 0->3A
Vin
Vin
Vout
Vout
SoftStart
SoftStart
Iout(2A/div)
Iout(2A/div)
Figure 5. Start-Up Response: No Load
Load
Figure 6. Start-Up Response: 1A
Vin=12V
Vout=3.3V
Vout
Vin
Vout
SoftStart
Vin=12V
Vout=3.3V
SoftStart
Iout(2A/div)
Ichoke(10A/div)
Figure 7. Start-Up Response: 3A Load
Figure 8. Output Load Short Circuit
Aug 24-06
SP6138 Evaluation Manual
Page 3 of 9
©2006 Sipex Corporation
Vout Ripple(10mV/div)
Vout Ripple(10mV/div)
Vin=12V
Vout=3.3V
Vin=12V
Vout=3.3V
SW Node
SW Node
Figure 9. Output Noise at No Load
Figure 10. Output Noise at 3A Load
INDUCTORS-SURFACEMOUNT
InductorSpecification
Size
LxW(mm) Ht.(mm)
Inductance
(uH)
Manufacturer/PartNo.
SeriesR
mOhms
16.5
Isat
(A)
InductorType
Manufacturer
Website
www.cooperet.com
2.2
COOPER DR73-2R2
5.52
7.6X6.0
3.55 ShieldedFerriteCore
CAPACITORS-SURFACEMOUNT
CapacitorSpecification
RippleCurrent
Size
(A)@45C LxW(mm) Ht.(mm) (V)
Capacitance(
uF)
Manufacturer/PartNo.
AVX 08053D475MAT
AVX 08056D226MAT
ESR
ohms(max)
0.005
Voltage Capacitor
Type
2.0x1.25 1.25 16.0 X5RCeramic
Manufacturer
Website
www.avx.com
4.7
22
4.00
0.005
4.00
2.0x1.25 1.25
6.3 X5RCeramic
www.avx.com
MOSFETS-SURFACEMOUNT
MOSFETSpecification
Qg
MOSFET
Manufacturer/PartNo.
RDS(on)
ohms(max)
0.047
IDCurrent
(A)
5.9
Voltage Foot Print
Manufacturer
Website
www.vishay.com
nC(Typ) nC(Max) (V)
4.2 6.5
DualN-Ch
VISHAYSi7214DN
30.0 Power-PAK1212-8
Table 1: SP6138EB Suggested Components and Vendor Lists
Aug 24-06
SP6138 Evaluation Manual
Page 4 of 9
©2006 Sipex Corporation
LOOP COMPENSATION DESIGN
The open loop gain of the SP6138 Evaluation Board can be divided into the gain of the
error amplifier GAMP(s), PWM modulator GPWM, buck converter output stage GOUT(s),
and feedback resistor divider GFBK. In order to crossover at the selected frequency fco,
the gain of the error amplifier must compensate for the attenuation caused by the rest of
the loop at this frequency. The goal of loop compensation is to manipulate the open
loop frequency response such that its gain crosses over 0dB at a slope of –20dB/dec.
The open loop crossover frequency should be higher than the ESR zero of the output
capacitors but less than 1/5 of the switching frequency fs to insure proper operation.
Since the SP6138EB is designed with ceramic type output capacitors, a Type III
compensation circuit is required to give a phase boost of 180° in order to counteract the
effects of the output LC underdamped resonance double pole frequency.
Figure 11. SP6138EB Voltage Mode Control Loop with Loop Dynamic
Aug 24-06
SP6138 Evaluation Manual
Page 5 of 9
©2006 Sipex Corporation
The simple guidelines for positioning the poles and zeros and for calculating the
component values for a Type III compensation scheme are as follows:
Where ZSF=(f compensation double zero)/(f circuit double pole)
Here ZSF is set at 1.2.
As a particular example, consider for the following SP6138EB, 3AMAX with a type III
Voltage Loop Compensation component selections:
Vin_max = 15V
Vout = 3.30V @ 0 to 3A load
Select L = 2.2 uH => 15% current ripple.
Select Cout = 22uF Ceramic capacitors (Resr ≈ 5mΩ)
fs = 2500KHz SP6138ER1 internal Oscillator Frequency
Vramp_pp = 1.0V SP6138ER1 internal Ramp Peak-to-Peak Amplitude
Aug 24-06
SP6138 Evaluation Manual
Page 6 of 9
©2006 Sipex Corporation
Step by step design procedures:
a.
b.
c.
d.
e.
f.
R2 = 21.8Ω
CZ3 = 85pF
Let fcrsover=200KHz then:
RZ2 = 60.3kΩ
CZ2 = 96pF
CP1 = 1.1pF
g.
h.
RZ3 = 0.75KΩ
CF1 = 18pF to stabilize SP6138ER1 internal Error Amplify
The above component values were used as a starting point for compensating the
converter and after laboratory testing the values shown in the circuit schematic of page
1 were used for optimum operation.
Figure 12- Gain/Phase measurement of SP6138EB shown on page 1, cross-over
frequency (fc) is just above 200KHz with a corresponding phase of 45 degrees
Aug 24-06
SP6138 Evaluation Manual
Page 7 of 9
©2006 Sipex Corporation
PCB LAYOUT DRAWINGS
Figure 13. SP6138EB Component Placement
Figure 14. SP6138EB PCB Layout Top Side
Figure 15. SP6138EB PCB Layout Bottom Side
Aug 24-06
SP6138 Evaluation Manual
Page 8 of 9
©2006 Sipex Corporation
Figure 16. SP6138EB PCB Layout Inner Layer 1 & Inner Layer 2
Line
No.
1
Ref.
Des.
PCB
U1
Qty.
Manuf.
Manuf.
Layout
Size
Component
Vendor
Part Number
146-6599-00
SP6138ER1
Phone Number
978-667-7800
978-667-7800
1
1
Sipex
Sipex
1.175"x1.934"
QFN-16
PowerPAK
1212-8 Dual
SOD-323
7.6x6mm
0402
SP6138EB
2.5MHz Synchronous Buck Controller
2
3
4
5
6
MT,MB
DBST
L1
C1, CBST, CS
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
Vishay Semi
Vishay Semi
COOPER Bussmann
TDK
Si7214DN
SD101AWS
DR73-2R2
Dual NFET 30V, 47mOhm
15mA-30V Schottky Diode
2.20uH Coil 4.15A 16.5mOhm
0.1 uF Ceramic X5R 16V
402-563-6866
800-344-4539
561-752-5000
978-779-3111
978-779-3111
843-448-9411
843-448-9411
978-779-3111
978-779-3111
978-779-3111
978-779-3111
978-779-3111
978-779-3111
978-779-3111
800-344-4539
800-344-4539
C1005JB1C104K
C1005JB1H682K
08053D475MAT
08056D226MAT
C1608JF0J475Z
C1005JB1E103K
C1005JB1E473K
C1005CH1H060D
C1005CH1H180J
C1005CH1H101J
C1005CH1H470J
ERJ-2RKF6812X
ERJ-2RKF2152X
7
CSP
CI
CO
CVCC
C5
CSS
CP1
CF1
TDK
AVX
AVX
TDK
TDK
TDK
TDK
TDK
0402
0805
0805
0603
0402
0402
0402
0402
0402
0402
0402
0402
6.8nF Ceramic X5R 50V
8
9
4.7uF Ceramic X5R 25V 20%
22uF Ceramic X5R 6.3V 20%
4.7uF Ceramic X5R 6.3V
0.01uF Ceramic X7R 25V
47nF Ceramic X7R 25V
6pF Ceramic COG 50V 5%
18pF Ceramic COG 50V 5%
100pF Ceramic COG 25V 5%
47pF Ceramic COG 50V 5%
68.1K Ohm Thick Film Res 1%
21.5K Ohm Thick Film Res 1%
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CZ2
CZ3
R1
TDK
TDK
Panasonic
Panasonic
Not populated
Panasonic
Panasonic
Panasonic
Panasonic
Sullins
R2
R3, R4, RS3
R5
1
1
3
1
1
1
ERJ-2RKF1002X
ERJ-2RKF5492X
ERJ-2RKF1001X
ERJ-2RKF4991X
PTC36SAAN
0402
0402
0402
0402
.32x.12
.2x.1
10.0K Ohm Thick Film Res 1%
54.9K Ohm Thick Film Res 1%
1.0K Ohm Thick Film Res 1%
5.11K Ohm Thick Film Res 1%
36-Pin (3x12) Header
800-344-4539
800-344-4540
800-344-4540
800-344-4541
800-344-4539
800-344-4539
RZ2
RZ3
RS1, RS2
J1
(J1)
Sullins
STC02SYAN
Shunt
VIN, VOUT, VCC,
GIN, GO, GND, SS,
PWRGD, UVIN
26
9
Vector Electronic
K24C/M
.042 Dia
Test Point Post
800-344-4539
Table 2: SP6138EB List of Materials
ORDERING INFORMATION
Temperature Range
Model
Package Type
SP6138EB ..….........................− 40°C to +85°C.............……..SP6138 Evaluation Board
SP6138ER1............................ − 40°C to +85°C.....................................…….16-pin QFN
Aug 24-06
SP6138 Evaluation Manual
Page 9 of 9
©2006 Sipex Corporation
Reliability and Qualification Report
SP6133
Synchronous Buck Controller
Prepared by: G. West
Reviewed by: Fred Claussen
VP Quality & Reliability
Date: 05/05/06
Quality Assurance Manager
Date: 05/05/06
SP6133 Reliability Report
Page 1 of 6
Table Of Contents
Title Page
1
2
2
2
3
3
3
4
4
5
5
6
6
Table Of Contents
Device Description
Pin Out
Manufacturing Information
Package Information
Die Information
Reliability Test Summary
Life Test Data
FIT Data Calculations
MTBF Data Calculations
ESD Data (Human Body Model)
Latch-up Test
Device Description
The SP6133 is a synchronous step-down switching regulator controller optimized for high
efficiency. The part is designed to be especially attractive for single supply step down conversion
from 5V to 24V. The SP6133 is designed to drive a pair of external NFETs using a fixed 300 kHz
frequency, PWM voltage mode architecture. Protection features include UVLO, thermal
shutdown, output short circuit protection, and overcurrent protection with auto restart. The device
also features a PWRGD output and an enable input. The SP6133 is available in a space saving
16-pin QFN and offers excellent thermal performance.
Pin Out
SP6133 Reliability Report
Page 2 of 6
Manufacturing Information:
Products:
SP6133ER1
Description:
Mask Set(s):
Process:
Synchronous Buck Controller
1388DZ
0.5um Bi-CMOS
Wafer Manufacturer:
Assembly Location:
Polar Semiconductor, Inc.
Carsem - Malaysia
Package Information:
Package Type:
16LD QFN
Package Dimensions:
Moisture Sensitivity Rating:
3.0 mm x 3.0 mm
MSL-3 (Pb-free package)
General Information:
Assembly Diagram:
Brand Sheet:
Specification No. 501-3347
Specification No. FG-SP6133ER1
SP6133 Reliability Report
Page 3 of 6
SP6133 Reliability Qualification Test Summary
Stress Level
Lot Number Burn-In Temp
Sample Size
No. Fail
1000 Hrs
1000 Hrs
1000 Hrs
2143A001
2143A002
2010A001
77
77
77
0
0
0
125 °C
125 °C
125 °C
Life Test
Life testing is conducted to determine if there are any fundamental reliability related
failure mechanism(s) present in the device.
These failure mechanisms can be divided roughly into four groups:
1. Process or die related failures, such as oxide-related defects, metalization-related
defects and diffusion-related defects.
2. Assembly-related defects such as chip mount wire bond or package-related
failures.
3. Design related defects.
4. Miscellaneous, undetermined or application-induced failures.
Life Test Results
As part of the Sipex design qualification program, the Engineering group had subjected
231 SP6133ER1 parts for a 1000 hour Reliability life test at 125° C
168 hour Life test
Two hundred thirty-one parts from the three lots were subjected to the life test
profile and completed 168 hours without any part failures.
500 hour Life test
The two hundred thirty-one parts were re-introduced to the second phase of the
test, where the parts successfully completed the 500-hour life test without any
failures.
SP6133 Reliability Report
Page 4 of 6
1000 hour Life test
Two hundred thirty-one parts completed the full1000 hour life/HTOL test
successfully, without showing any significant shift in the process parameters.
FIT Rate Calculations
The FIT (failures in time) rate is the predicted number of failures per billion device-
hours. This predicted value is based upon the:
1. Life Test conditions (time and temperature, device quantity and number of failures)
are summarized under HTOL test table.
2. Activation Energy (Ea) of the potential failure modes.
The weighted Activation Energy, Ea, of observed failure mechanisms of Sipex products
has been determined to be 0.8 eV.
Based on the above criteria, the FIT rates at 25°, 55° and 70°C operation at both 60% and
90% confidence levels for the SP232E products have been calculated and are listed
below.
FIT Failure Rates for SP6133 Product
Confidence Level
+25°C
1.8
4.6
+55°C
29.6
75.2
+70°C
99.5
252.7
60%
90%
1 FIT = 1 Failure per Billion Device-Hours
MTBF Calculation for SP6133 Product
Confidence Level
+25°C
5.47E+08
2.15E+08
+55°C
3.37E+07
1.33E+07
+70°C
1.00E+07
3.96E+06
60%
90%
SP6133 Reliability Report
Page 5 of 6
ESD Testing
ESD testing was performed per method 3015.7 of MIL-STD-883E using a Keytek
Zapmaster 7/4 discharging a 100pF capacitor through a 1.5 Kohm resistor. Ten units
were subjected to three discharges of both positive and negative polarity using the
following pin combinations:
• Each pin to GND with all other pins floating.
• Each pin to IN with all other pins floating.
• IN to GND with all other pins floating.
All units passed after discharges of 2KV.
Lath-up Testing
Latch-up testing was performed on 5 units per EIAJ-ED-17. 100mA pulse currents were
applied with the unit at 85C. No failures were detected
SP6133 Reliability Report
Page 6 of 6
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