SP6652EU_技术文档

®

SP6652

1A, High Efficiency, High Frequency Current Mode PWM

Buck Regulator

FEATURES

■ 1A Output Current

■ 1.2MHz Constant Frequency Operation

■ 97% Efficiency Possible

■ Pin Selectable Forced PWM or PWM/PFM Modes

■ Ultra Low Quiecent Current in PFM Mode: 50µA

■ 500nA (Max.) Shutdown Current

■ Output Adjustable Down to 0.75V

■ No External FET's or Schottky Diode Required

■ Uses Small Value Inductors and Ceramic

Output Capacitors

■ Low Dropout Operation: 100% Duty Cycle

■ Soft Start and Thermal Shutdown Protection

■ Easy Frequency Synchonization

P_GND

S_GND

FB

10

9

1

2

3

4

5

LX

P_VIN

SP6652

8

S_VIN

10 Pin MSOP

7

COMP

SD

SYNC

MODE

6

Now Available in Lead Free Packaging

APPLICATIONS

■ Mobile Phones

■ PDA's

■ DSC's

■ MP3 Players

■ USB Devices

■ Point of Use Power

■ Small 10 Pin MSOP and 10 Pin DFN Package

DESCRIPTION

The SP6652 is high efficiency, synchronous buck regulator ideal for portable applications using

one Li-Ion cell, with up to 1A output current. The 1.2MHz switching frequency and PWM control

loop are optimized for small value inductor and ceramic output capacitor, for space constrained

portable designs. At light load, the SP6652 can operate in either PFM mode for high efficiency,

or PWM mode for constant frequency. In addition, the input voltage range of 2.7V to 5.5V;

excellent transient response, output accuracy, and ability to transition into 100% duty cycle

operation, further extending useful battery life, make the SP6652 a superior choice for a wide

range of portable power applications. The output voltage is externally programmable down to

0.75V. A logic level shutdown control, external clock synchronization, and forced-PWM or

automatic control inputs are provided. Other features include soft-start, over current protection

and 140(C over-temperature shutdown.

TYPICAL APPLICATION SCHEMATIC

V

OUT

4.7µF

3.3V at 1A

1

2

3

4

5

P

S

^LX10

GND

340k

100k

9

V

P

S

IN

VIN

SP6652

8

FB

VIN

7

COMP

SD

SYNC

MODE

6

10µF

8k

10µF

6.2nF

ENABLE

SHUTDOWN

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation

sections of the specifications below is not implied. Exposure to

absolute maximum rating conditions for extended periods of time may

affect reliability.

PV_IN,S_VIN........................................................................... -0.3V to 0.3V

_GNDto S_GND...................................................................... -0.3V to 0.3V

LX to P_GND................................................................ - 0.3V to P_VIN+0.3V

Storage Temperature .................................................. -65 °C to 150 °C

Operating Temperature ................................................. -40°C to +85°C

Lead Temperature (Soldering, 10 sec) ....................................... 300 °C

P

ELECTRICAL CHARACTERISTICS

V_IN=UV_IN=V_SDN=3.6V, V_OUT=V_FB, I_O= 0mA, T_AMB= -40°C to +85°C, typical values at 27°C unless otherwise noted.

PARAMETER

MIN

TYP

MAX UNITS

CONDITIONS

Input Voltage Operating

Range

UVLO

5.5

V

FB Set Voltage

0.735

0.75

0.01

0.765

V

T_A= 27°C, FB = COMP

FB Input Voltage

-1

-4

1

4

µA

%

V_FB= 0.8V

Overall FB Accuracy

FB = COMP

FB Set Voltage (PFM Mode)

Switching Frequency

0.758

1.2

V

1

1.4

1

MHz

µA

Ω

SYNC Tracking Frequency

SYNC Input Current

1.2

-1

0.01

0.3

SYNC Logic Threshold Low

SYNC Logic Threshold High

PWM On-Time Blanking

PMOS Switch Resistance

NMOS Switch Resistance

Inductor Current Limit (PWM Mode)

Inductor Current Limit (PFM Mode)

LX Leakage Current

0.6

1.7

1.2

50

0.25

1.4

300

0.1

60

ns

Ω

0.6

1.6

Ω

A

mA

µA

nA

mA

µA

3

SD\=0V

S_VINQuiecent Current

100

TBD

500

TBD

PFM Mode

2

PWM Mode

Shutdown, SD\=0V

1

P_VINQuiecent Current

102

V_COMP= 0.6V

I_LX= 0

1

500

2.8

PWM Mode

UVLO

2.6

2.7

V

Undervoltage Lockout

Threshold, V_INfalling

UVLO hysteresis

6

2

%

µV

µA

V

Soft Start Current

1

3

1

V_COMP= 1V

SD\, MODE Input Current

-1

0.01

SD\, MODE Logic Threshold Low

SD\, MODE Logic Threshold High

Slope Compensation

0.4

1.6

V

700

140

14

mA/µs

°C

Rising Over-Temperature Trip Point

Over-Temperature Hysteresis

ERROR AMPLIFIER

°C

Error Amplifier Transconductance

Error Amplifier Output Impedance

Error Amplifier Max Sink Current

Error Amplifier Max Source Current

0.5

1

1.5

mS

mΩ

µA

15

40

60

µA

Note: This thermal Resistance Figure Applies only to a package with the exposed pad soldered to a PCB.

Faliure to do this results in, approximately, a three-fold increase in thermal resistance.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

2

PIN DESCRIPTION

PIN NUMBER

PIN NAME

P_GND

DESCRIPTION

1

2

3

Power Ground Pin. Synchronous rectifier current returns through this pin.

Internal Ground Pin. Control circuitry returns current to this pin.

S_GND

FB

External feedback network input connection. Connect a resistor from

to ground and from FB to output voltage to control the output voltage.

Regulation point at FB=0.75V Typical.

4

5

6

7

COMP

SD\

Compensation pin for error loop. Connect an R and C in series to

ground to control open loop pole and zero.

Shutdown control input. Tie pin to VIN for normal operation, tie to

ground for shutdown. TTL input threshold.

MODE

SYNC

Connect this pin to VIN to force PWM operation and to S_GNDfor

automatic PWM/PFM selection, for a better light load efficiency.

An external clock signal can be connected to this to synchronize the

switching frequency. The part runs in PWM mode in the precence of a

sync clock.

8

9

S_VIN

P_VIN

LX

Internal supply voltage. Control circuitry is powered from from this pin.

Use an RC filter close to the pin to cut down supply noise.

Supply voltage for the output driver stage. Inductor charging current

passes through this pin.

10

Inductor switching node. Inductor tied between this pin and the output

capacitor to create regulated output voltage.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

3

FUNCTIONAL DIAGRAM

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

4

DETAIL DESCRIPTION

keep the effective current slope compensation

constant (remembering current is being com-

pensated, not voltage) the voltage slope must be

proportional to R_PMOS. To account for this, the

slope compensation voltage is internally gener-

ated with a bias current that is also proportional

Current Mode Control and Slope

Compensation

The SP6652 is designed to use low value ce-

ramic capacitors and low value inductors, to

reduce the converter’s volume and cost in por-

table devices Current mode PWM control was,

therefore, chosen for the ease of compensation

whenusingceramicoutputcapacitorsandbetter

transient line rejection, which is important in

battery powered applications. Current mode

control spreads the two poles of the output

power train filter far apart so that the modulator

gain crosses over at -20dB/decade instead of

the usual -40dB/decade. The external compen-

sationnetworkis, simply, aseriesRCconnected

between ground and the output of the internal

transconductance error amplifier.

to R_PMOS

.

Over Current Protection

In steady state closed loop operation the voltage

at the COMP pin controls the duty cycle. Due to

the current mode control and the slope compen-

sation, this voltage will be:

V(COMP)(I_LPK*R_PMOS+MC_V*T_ON+V_BE(Q1)

The COMP node will be clamped when the its

voltage tries to exceed V(BLIM) + V_BE(Q1).

The V_BE(Q1) term is cancelled by V_BE(Q2) at

the output of the translator. The correct value of

clamp voltage is, therefore:

Itiswellknownthatanunconditionalinstability

exists for any fixed frequency current-mode

converter operating above 50% duty cycle. A

simple, constant-slope compensation is chosen

to achieve stability under these conditions. The

most common high duty cycle application is a

Li-Ion battery powered regulator with a 3.3V

output (D ≥ 90%). Since the current loop is

critically damped when the compensation slope

(denoted MC_V) equals the negative discharge

slope (denoted M2_V), the amount of slope com-

pensation chosen is, therefore:

V(BLIM) = IL(MAX)* RPMOS + MCV *tON

The I_L(MAX)term is generated with a bias current

that is proportional to R_PMOS, to keep the value

of current limit approximately constant over

process and temperature variations, while the

MC_V*T_ONis generated by a peak-holding cir-

cuit that senses the amplitude of the slope com-

M2 = dI_L/dT_OFF=-V_OUT/L = -3.3V/4.7µH =

-702mA/µs

pensation ramp at the end of T_ON

.

There is minimum on-time (T_ON) generated

even if the COMP node is at 0V, since the peak

current comparator is reset at the end of a charge

cycle and is held low during a blanking time

after the start of the next charge cycle. This is

necessary to swamp the transients in the induc-

tor current ramp around switching times. The

minimum T_ON(50ns, nominally) is not suffi-

cient for the COMP node to keep control of the

current when the output voltage is low. The

inductor current tends to rise until the energy

loss from the discharge resistances are equal to

M2_V= M2*R_PMOS

MC_V= -M2_V= 702mA/µs*0.2Ω = 140mV/µs,

for RPMOS = 0.20Ω

The inductor current is sensed as a voltage

acrossthePMOSchargingswitchandtheNMOS

synchronousrectifier(seeBLOCKDIAGRAM)

Duringinductorcurrentcharge,V(PVIN)-V(LX)

represents the charging current ramp times the

resistance of the PMOS charging switch. To

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

5

DETAIL DESCRIPTION: Contunued

Automatic Mode Selection

the energy gained during the charge phase. For

this reason, the clock frequency is cut in half

when the feedback pin is below 0.3V, effec-

tively reducing the minimum duty cycle in half.

Above V(FB)=0.3V the clock frequency is nor-

mal (see TYPICAL OPERATIONG CHAR-

ACTERISTICS: Inductor current vs. VOUT)

If the MODE pin is connected to SVIN, the part

willbeforcedintoaPWM-onlyregulationmode.

IftheMODEpinisconnectedtoS_GND, themode

selection circuitry decides whether the con-

vertershouldbeinPWMorPFMmode,depend-

ing on the load. Light loads call for the PFM

loop, which is forced into DCM as well. Me-

dium to heavy loads activate the PWM loop.

PFM Control for Light Loads

If the MODE pin is connected to S_GND, under

light load conditions the SP6652 will transition

to a PFM regulation mode. In this mode of

operation, V(FB) is compared to the reference

voltage plus 7.5mV, nominally (see BLOCK

DIAGRAM). This sets the regulation point 1%

higher than the PWM regulation voltage to

prevent bouncing between modes at loading

conditions near threshold.

StartingfromaPWMstate, thePeakandTrough

Current Detector window comparator monitors

the peak inductor current during charge and the

trough inductor current during discharge. Both

the peak and trough are monitored because the

ripple current varies considerably across the

application spectrum. The lossless inductor cur-

rent ripple is:

When V_OUTfalls below the PFM regulation

point the voltage loop comparator issues a com-

mand to turn on the PMOS switch to the output

stage logic. The current sensing comparator

compares the voltage across that switch to a

reference set up by a biased replica of the PMOS

switch, to set the peak PFM inductor current

(nominally 300 mA). This comparator stops the

chargingcycleandinitiatesthedischargethrough

the synchronous NMOS rectifier.

I_L(RIPPLE)=(V_IN-V_OUT)*(V_OUT/V_IN)*(1/L*f_CLK

)

Wheref_CLKistheswitchingfrequency(1.2MHz,

nominally).

If the peak inductor current is below 100mA or

the trough reaches 0mA (or less) during one

cycle, then the current is defined as low enough

for PFM mode. This has to happen during 32

consecutive clock cycles before the output sig-

nal goes high and switches modes. This delay is

to avoid prematurely switching into PFM mode

during a negative load transient.

Any new charging cycles are inhibited until a

third comparator, the under-current compara-

tor, which is setup to detect the instant when the

inductor is fully discharged (NMOS V_DS>0)

enables the voltage loop. This keeps the PFM

modeindiscontinuousconductionmode(DCM).

Once in PFM mode, the regulated output volt-

age will be 1% higher than in PWM and con-

tinue regulating there, as described in the PFM

Control For Light Loads section. When the load

increases past the point where the PFM mode

can regulate while remaining in DCM (which is

l 1/2 of the peak inductor current in PFM, or 1/

2*300mA=150mA),theoutputvoltagewillstart

dropping. When it falls 1% below the reference

voltage, that is 2% below the PFM regulation

point, the PWM Mode Comparator will switch

and set the Mode Control latch to PWM mode.

A timer disables both the Current Loop and

Trough Current comparators 7µs after entering

DCM, to save supply current under very light

load conditions. The normal light load supply

current is, nominally, 135µA whereas the very

light load supply current is 60µA.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

6

DETAIL DESCRIPTION: Contunued

Voltage Loop and Compensation

in PWM Mode

The low frequency pole for L1=5µH is 4kHz,

the second pole is 500kHz, and the gain-band-

width is 20kHz. The total loop crossover fre-

The voltage loop section of the circuit consists

of the error amplifier and the translator circuits

(see functional diagram). The input of the volt-

age loop is the 0.75V reference voltage minus

the divided down output voltage at the feedback

pin. The output of the error amplifier is trans-

lated from a ground referred signal (the COMP

node) to a power input voltage referred signal.

The output of the voltage loop is fed to the

positive terminal of the Current Loop compara-

tor, and represents the peak inductor current

necessary to close the loop.

th

quency is chosen to be 200kHz, which is 1/6 of

the clock frequency. This sets the 2nd modula-

tor pole at 2.5 times the crossover frequency.

Therefore the gain of the error amplifier can be

200kHz/20kHz = 10 at the first modulator pole

of 4kHz. The error amp transconductance is

1mS, so this sets the RZ resistor value in the

compensation network at 10/1mS = 10kΩ. The

zero frequency is placed at the first pole to

provide at total system response of -20dB/de-

cade (the zero from the error amp cancels the

first modulator pole, leaving the 1 pole rolloff

from the error amp pole). The compensation

capacitor becomes:

The total power supply loop is compensated

with a series RC network connected from the

COMP pin to ground. Compensation is simple

due to current-mode control. The modulator has

two dominant poles: one at a low frequency, and

one above the crossover frequency of the loop,

as seen in the graph below, Linearized Modula-

tor Frequency Response vs. Inductor Value.

Cc=1/(2*π*Rz*pole1)=1/(6.28*10kΩ*4kHz)

= 4nF

20K 2.0M 50K

1

2

3

16K 1.6M 40K

12K 1.2M 30K

8K 0.8M 20K

4K 0.4M 10K

>>

0

3u

2u

4u

5u

6u

Gbw_modfb

L1VAL

7u

8u

9u

10u

1

Mod_pole1

3

2

Mod_pole2

Conditions: V_IN=5V, V_OUT=3.3V, f_CLK=1.2MHz, C_OUT=10µF, and MC_V=132mV/µs. The inductor is varied from

2µH to 10µH

Linearized Modulator Frequency Response vs. Inductor Value.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

7

APPLICATIONS INFORMATION

L1

VOUT

4.7µH

1

10

9

PGND

SGND

FB

LX

PVIN

R_FBH

2

3

4

5

VIN

R1

8

SVIN

C3

10µF

10Ω

7

COMP

SD

SYNC

MODE

R_FBL

Cc

8k

6

C1

10µF

C2

1µF

SP6652

Rz

16.2nF

SD

MODE

SYNC

Complete Application Circuit.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

8

PACKAGE: 10 PIN MSOP

(ALL DIMENSIONS IN MILLIMETERS)

D

e1

Ø1

E/2

R1

R

E1

E

Gauge Plane

L2

Ø

Ø1

Seating Plane

L

L1

1

2

e

Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)

10-PIN MSOP

Dimensions in (mm)

JEDEC MO-187

(BA) Variation

MIN NOM MAX

A

-

1.1

0

-

0.15

A1

A2

b

0.75 0.85 0.95

0.17

0.08

-

0.27

0.23

(b)

c

-

WITH PLATING

D

E

3.00 BSC

4.90 BSC

3.00 BSC

0.50 BSC

2.00 BSC

0.60

E1

c

e

e1

L

0.4

-

0.80

BASE METAL

L1

L2

N

-

0.95

0.25

-

D

b

-

10

-

R

0.07

0º

-

A2

R1

Ø

-

A

8º

15º

Ø1

0º

-

A1

1

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

9

PACKAGE: 10 PIN DFN

Bottom View

Top View

D

b

e

D/2

1

2

E/2

E2

E

K

L

Pin 1 identifier to be located within this shaded area.

Terminal #1 Index Area (D/2 * E/2)

D2

A

A1

A3

Side View

DIMENSIONS

Minimum/Maximum

(mm)

10 Pin DFN

(JEDEC MO-229,

VEED-5 VARIATION)

COMMON HEIGHT DIMENSION

SYMBOL

MIN NOM MAX

0.80 0.90 1.00

A

A1

A3

b

D

D2

e

0.02 0.05

0.20 REF

0

0.18

0.25 0.30

3.00 BSC

2.20 2.70

0.50

-

PITCH

3.00 BSC

E

E2

K

1.40

0.20

-

1.75

-

L

0.30 0.40 0.50

10 PIN DFN

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

10

ORDERING INFORMATION

Operating Temperature Range Package Type

Part Number

SP6652EU .................................................. -40°C to +85°C ........................................................ 10 Pin MSOP

SP6652EU/TR ............................................ -40°C to +85°C ........................................................ 10 Pin MSOP

SP6652ER .................................................. -40°C to +85°C ........................................................... 10 Pin DFN

SP6652ER/TR ............................................ -40°C to +85°C ........................................................... 10 Pin DFN

Available in lead free packaging. To order add "-L" suffix to part number.

Example: SP6652EU/TR = standard; SP6652EU-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2,500 for MSOP and 3,000 for DFN.

Corporation

ANALOGEXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

11


型号：	SP6652EU
厂家：	SIPEX CORPORATION
描述：	1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator 1A ，高效率，高频率电流模式PWM降压稳压器稳压器
文件：	总11页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6652EU [SIPEX]

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