SP7655_技术文档

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Advanced

SP7655

Wide Input Voltage Range 8A, 300kHz, Buck Regulator

SP7655

FEATURES

■ 2.5V to 28V Step Down Achieved Using Dual Input

DFN PACKAGE

7mm x 4mm

■ Output Voltage down to 0.8V

■ 8A Output Capability

■ Built in Low R_DSONPower Switches (15 mΩ typ)

■ Highly Integrated Design, Minimal Components

■ 300 kHz Fixed Frequency Operation

■ UVLO Detects Both V_CCand V_IN

P

GND

1

2

3

26

25

24

23

LX

TOP VIEW

Heatsink Pad 1

Connect to Lx

P

GND

4

5

LX

V

FB

22 V

CC

COMP

UVIN

GND

SS

21 GND

20 GND

6

7

Heatsink pad 2

Connect to GND

■ Over Temperature Protection

■ Short Circuit Protection with Auto-Restart

■ Wide BW Amp Allows Type II or III Compensation

■ Programmable Soft Start

8

9

19

18

GND

BST

V

IN 10

17

16

NC

LX

■ Fast Transient Response

Heatsink pad 3

V

IN 11

IN 12

Connect to V

IN

■ High Efficiency: Greater than 95% Possible

■ Asynchronous Start-Up into a Pre-Charged Output

■ Small 7mm x 4mm DFN Package

15 LX

14

LX

IN 13

Now Available in Lead Free Packaging

DESCRIPTION

The SP7655 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be

especially attractive for dual supply, 12V or 24V distributed power systems step down with 5V used to power the

controller.ThislowerV_CCvoltageminimizespowerdissipationinthepartandisusedtodrivethetopswitch.TheSP7655

is designed to provide a fully integrated buck regulator solution using a fixed 300kHz frequency, PWM voltage mode

architecture. Protection features include UVLO, thermal shutdown and output short circuit protection. The SP7655 is

available in the space saving DFN package.

TYPICAL APPLICATION CIRCUIT

U1

SP7655

L1

1

2

3

4

26

25

24

23

PGND

GND

LX

VOUT

3.30V

0-6A

2.2uH, Irate=8A

RZ2

CZ2

RZ3

15k,1%

7.15k,1%

1,000pF

C3

R1

47uF

6.3V

CP1

5

6

7

8

9

22

21

20

19

18

68.1k,1%

VFB

VCC

CZ3

22pF

150pF

COMP

UVIN

GND

SS

GND

BST

NC

CVCC

2.2uF

CF1

ENABLE

100pF

DBST

RSET

21.5k,1%

(note 2)

10

17

16

15

14

SD101AWS

CSS

VIN

47nF

11

12

13

VIN

LX

CBST

68,00pF

VIN

+5V VCC

12V

fs=300Khz

C1

22uF

16V

C4

Notes:

1. U1 Bottom-Side Layout should

has three contacts isolated from

one another Vin SWNODE and GND

22uF

16V

GND

2. RSET=54.48/(Vout-0.8V)

(KOhm)

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

1

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation sections

of the specifications below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect reliability.

GH ......................................................................... -0.3V to BST+0.3V

GH-SWN ......................................................................................... 7V

All other pins .......................................................... -0.3V to V_CC+0.3V

V_CC.................................................................................................. 7V

V_IN^{...........................................................................................................................................}30V

I_LX^{............................................................................................................................................}10A

BST ............................................................................................... 35V

BST-SWN ......................................................................... -0.3V to 7V

SWN ................................................................................... -1V to 30V

Storage Temperature .................................................. -65°C to 150°C

Power Dissipation ...................................... Internally Limited via OTP

Lead Temperature (Soldering, 10 sec) ...................................... 300°C

ESD Rating .......................................................................... 2kV HBM

Thermal Resistance ϑ_JC^{....................................................................................}5°C/W

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: -40°C < T_AMB< 85°C, -40°C<Tj<125°C, 4.5V < V_CC< 5.5V, 3V<Vin<28V, BST=LX + 5V, LX =

GND = 0V, UVIN = 3.0V, CV_CC= 1µF, C_COMP= 0.1µF, C_SS= 50nF, Typical measured at V_CC= 5V.

The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.

PARAMETER

MIN. TYP. MAX. UNITS

CONDITIONS

QUIESCENT CURRENT

V_CCSupply Current (No switching)

V_CCSupply Current (switching)

BST Supply Current (No switching)

BST Supply Current (switching)

1.5

11

3

mA

V_FB=0.9V

♦

TBD

0.4

0.2

5.0

TBD

PROTECTION: UVLO

V_CCUVLO Start Threshold

V_CCUVLO Hysteresis

UVIN Start Threshold

UVIN Hysteresis

4.00

100

2.3

4.25

200

2.5

4.5

300

2.65

400

1

V

mV

V

♦

200

300

mV

µA

UVIN Input Current

UVIN= 3.0V

ERROR AMPLIFIER REFERENCE

2X Gain Config., Measure

VFB; V_CC=5 V, T=25ºC

Error Amplifier Reference

0.792

0.788

0.800

0.808

0.812

V

Error Amplifier Reference

Over Line and Temperature

♦

Error Amplifier Transconductance

Error Amplifier Gain

6

60

150

50

4

mA/V

dB

No Load

COMP Sink Current

µA

V_FB=0.9V, COMP= 0.9V

V_FB=0.7V, COMP= 2..2V

V_FB= 0.8V

COMP Source Current

V_FBInput Bias Current

Internal Pole

µA

200

nA

MHz

V

COMP Clamp

2.5

-2

V_FB=0.7V, TA=25ºC

COMP Clamp Temp. Coefficient

mV/ºC

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

2

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: -40°C < T_AMB< 85°C, -40°C<Tj<125°C, 4.5V < V_CC< 5.5V, 3V<Vin<28V, BST=LX + 5V, LX =

GND = 0V, UVIN = 3.0V, CV_CC= 1µF, C_COMP= 0.1µF, C_SS= 50nF, Typical measured at V_CC= 5V.

The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.

PARAMETER

MIN. TYP. MAX. UNITS

CONDITIONS

CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH

Ramp Amplitude

RAMP Offset

0.92

1.1

1.28

V

T_A= 25ºC, RAMP COMP

until GH starts Switching

RAMP Offset Temp. Coefficient

GH Minimum Pulse Width

-2

mV/ºC

ns

♦

90

180

Maximum Duty Ratio

Measured just before

pulsing begins

Maximum Controllable Duty Ratio

92

97

%

Maximum Duty Ratio

100

210

%

Valid for 20 cycles

Internal Oscillator Ratio

300

10

360

0.3

kHz

TIMERS: SOFTSTART

SS Charge Current:

µA

♦

SS Discharge Current:

1

mA

Fault Present, SS = 0.2V

PROTECTION: Short Circuit & Thermal

Measured V_REF(0.8V) -

V_FB

Short Circuit Threshold Voltage

Hiccup Timeout

0.2

0.25

200

20

V

ms

V_FB= 0.5V

Number of Allowable Clock Cycles

at 100% Duty Cycle

Cycles

Minimum GL Pulse After 20 Cycles

Thermal Shutdown Temperature

Thermal Recovery Temperature

Thermal Hysteresis

0.5

145

135

10

Cycles

ºC

V_FB= 0.7V

ºC

OUTPUT: POWER STAGE

V

= 5V ; I_OUT= 6A T_AMB

=^C2^C5ºC

High Side Switch R_DSON

15

mΩ

V

= 5V ; I_OUT= 6A T_AMB

=^C2^C5ºC

Synchronous Lowside Switch R_DSON

Maximum Output Current

mΩ

8

A

200lfm, 25ºC

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

3

PIN DESCRIPTION

Pin #

Pin Name

Description

1-3

P_GND

Ground connection for the synchronous rectifier

Ground Pin. The control circuitry of the IC and lower power driver are

referenced to this pin. Return separately from other ground traces to the (-)

terminal of Cout.

4,8,19-21

5

GND

V_FB

Feedback Voltage and Short Circuit Detection pin. It is the inverting input

of the Error Amplifier and serves as the output voltage feedback point for

the Buck Converter. The output voltage is sensed and can be adjusted

through an external resistor divider. Whenever V drops 0.25V below the

positive reference, a short circuit fault is detected^Fa^Bnd the IC enters hiccup

mode.

Output of the Error Amplifier. It is internally connected to the inverting input

of the PWM comparator. An optimal filter combination is chosen and

connected to this pin and either ground or V_FBto stabilize the voltage

mode loop.

6

COMP

UVLO input for Vin voltage. Connect a resistor divider between V_INand

UV_INto set minimum operating voltage

7

9

UVIN

SS

Soft Start. Connect an external capacitor between SS and GND to set the

soft start rate based on the 10µA source current. The SS pin is held low

via a 1mA (min) current during all fault conditions.

Input connection to the high side N-channel MOSFET. Place a decoupling

capacitor between this pin and PGND.

10-13

V_IN

14-16,23-26

17

LX

Connect an inductor between this pin and V_OUT

No Connect

NC

THEORY OF OPERATION

General Overview

The SP7655 is a fixed frequency, voltage mode,

synchronousPWMregulatoroptimizedforhigh

efficiency. The part has been designed to be

especially attractive for high voltage applica-

tions utilizing 5V to power the controller and

2.5V to 28V for step down conversion.

The SP7655 contains two unique control fea-

tures that are very powerful in distributed appli-

cations. First, asynchronous driver control is

enabled during start up, to prohibit the low side

switch from pulling down the output until the

high side switch has attempted to turn on. Sec-

ond, a 100% duty cycle timeout ensures that the

low side switch is periodically enhanced during

extended periods at 100% duty cycle. This guar-

antees the synchronized refreshing of the BST

capacitor during very large duty ratios.

The heart of the SP7655 is a wide bandwidth

transconductance amplifier designed to accom-

modate Type II and Type III compensation

schemes. Aprecision0.8Vreference, presenton

the positive terminal of the error amplifier per-

mits the programming of the output voltage

down to 0.8V via the V_FBpin. The output of the

error amplifier, COMP, compared to a 1.1V

peak-to-peak ramp is responsible for trailing

edge PWM control. This voltage ramp, and

PWM control logic are governed by the internal

oscillator that accurately sets the PWM fre-

quency to 300kHz.

The SP7655 also contains a number of valuable

protection features. Programmable V_INUVLO

allowstheusertosettheexactvalueatwhichthe

conversion voltage can safely begin down con-

version, and an internal V_CCUVLO which en-

sures that the controller itself has enough volt-

age to properly operate. Other protection fea-

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

4

THEORY OF OPERATION

Thermal and Short-Circuit

Protection

tures include thermal shutdown and short-cir-

cuit detection. In the event that either a thermal,

short-circuit, or UVLO fault is detected, the

SP7655 is forced into an idle state where the

output drivers are held off for a finite period

before a restart is attempted.

Because the SP7655 is designed to drive large

output current, there is a chance that the power

converter will become too hot. Therefore, an

internal thermal shutdown (145°C) has been

included to prevent the IC from malfunctioning

at extreme temperatures.

Soft Start

“Soft Start” is achieved when a power converter

ramps up the output voltage while controlling

the magnitude of the input supply source cur-

rent. In a modern step down converter, ramping

up the positive terminal of the error amplifier

controls soft start. As a result, excess source

current can be defined as the current required to

charge the output capacitor.

A short-circuit detection comparator has also

been included in the SP7655 to protect against

an accidental short at the output of the power

converter. This comparator constantly monitors

the positive and negative terminals of the error

amplifier, and if the V_FBpin falls more than

250mV (typical) below the positive reference, a

short-circuit fault is set. Because the SS pin

overridestheinternal0.8Vreferenceduringsoft

start, the SP7655 is capable of detecting short-

circuit faults throughout the duration of soft

start as well as in regular operation.

I

_VIN= C_OUT* (DV_OUT/ DT_SOFT-START)

The SP7655 provides the user with the option to

program the soft start rate by tying a capacitor

from the SS pin to GND. The selection of this

capacitor is based on the 10uA pull up current

present at the SS pin and the 0.8V reference

voltage. Therefore, the excess source can be

redefined as:

Handling of Faults:

Upon the detection of power (UVLO), thermal,

or short-circuit faults, the SP7655 is forced into

an idle state where the SS and COMP pins are

pulled low and both switches are held off. In the

eventofUVLOfault, theSP7655remainsinthis

idle state until the UVLO fault is removed.

Upon the detection of a thermal or short-circuit

fault, aninternal200ms timerisactivated. Inthe

event of a short-circuit fault, a re-start is at-

tempted immediately after the 200ms timeout

expires. Whereas, when a thermal fault is de-

tected the 200ms delay continuously recycles

and a re-start cannot be attempted until the

thermal fault is removed and the timer expires.

IV_IN= C_OUT* (DV_OUT*10µA / (C_SS* 0.8V)

Under Voltage Lock Out (UVLO)

The SP7655 contains two separate UVLO com-

parators to monitor the bias (V_CC) and conver-

sion (V_IN) voltages independently. The V_CC

UVLO threshold is internally set to 4.25V,

whereas the V_INUVLO threshold is program-

mable through the UVIN pin. When the UVIN

pinisgreaterthan2.5V, theSP7655ispermitted

to start up pending the removal of all other

faults. Both the V_CCand V_INUVLO compara-

tors have been designed with hysteresis to pre-

vent noise from resetting a fault.

Error Amplifier and Voltage Loop

Since the heart of the SP7655 voltage error loop

is a high performance, wide bandwidth

transconductance amplifier. Because of the

amplifier’s current limited (+/-150µA)

transconductance, there are many ways to com-

pensate the voltage loop or to control the COMP

pin externally. If a simple, single pole, single

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

5

THEORY OF OPERATION

zero response is desired, then compensation can

be as simple as an RC to ground. If a more

complex compensation is required, then the

amplifier has enough bandwidth (45° at 4 MHz)

andenoughgain(60dB)torunTypeIIIcompen-

sation schemes with adequate gain and phase

margins at cross over frequencies greater than

50kHz.

V

BST

GH

Voltage

V

SWN

V(V

CC)

GL

Voltage

0V

The common mode output of the error amplifier

is 0.9V to 2.2V. Therefore, the PWM voltage

ramp has been set between 1.1V and 2.2V to

ensureproper0%to100%dutycyclecapability.

The voltage loop also includes two other very

importantfeatures. Oneisanasynchronousstart

up mode. Basically, the synchronous rectifier

can not turn on unless the high side switch has

attempted to turn on or the SS pin has exceeded

1.7V. This feature prevents the controller from

“dragging down” the output voltage during

startup or in fault modes. The second feature is

a100%dutycycletimeoutthatensuressynchro-

nized refreshing of the BST capacitor at very

high duty ratios. In the event that the high side

NFET is on for 20 continuous clock cycles, a

reset is given to the PWM flip flop half way

through the 21st cycle. This forces GL to rise for

the cycle, in turn refreshing the BST capacitor.

The boost capacitor is used to generate a high

voltage drive supply for the high side switch,

which is 5V above V_IN.

V(V

)

IN

SWN

Voltage

-0V

-V(Diode) V

V(V )+V(V

IN

)

CC

BST

Voltage

V(V

)

CC

TIME

Setting Output Voltages

The SP7655 can be set to different output

voltages. The relationship in the following

formula is based on a voltage divider from the

output to the feedback pin VFB, which is set

to an internal reference voltage of 0.80V.

Standard 1% metal film resistors of surface

mount size 0603 are recommended.

Power MOSFETs

Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ (

Vout / 0.80V ) – 1 ]

The SP7655 contains a pair of integrated low

resistanceN-channelswitchesdesignedtodrive

up to 10A of output current. Care should be

taken to de-rate the output current based on the

thermal conditions in the system such as ambi-

enttemperature,airflowandheatsinking.Maxi-

mum output current could be limited by thermal

limitations of a particular application by taking

advantage of the integrated over temperature

protective scheme employed in the SP7655.

The SP7655 incorporates a built-in over-tem-

peratureprotectiontopreventinternaloverheat-

ing.

Where R1 = 68.1KΩ and for Vout = 0.80V

setting, simply remove R2 from the board.

Furthermore, one could select the value of R1

and R2 combination to meet the exact output

voltage setting by restricting R1 resistance

range such that 50KΩ < R1 < 100KΩ for

overall system loop stability.

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

6

APPLICATIONS INFORMATION

Inductor Selection

I_PP

There are many factors to consider in selecting

the inductor including core material, inductance

vs. frequency, current handling capability, effi-

ciency, size and EMI. In a typical SP7655 cir-

cuit, the inductor is chosen primarily for value,

saturationcurrentandDCresistance. Increasing

the inductor value will decrease output voltage

ripple, but degrade transient response. Low in-

ductor values provide the smallest size, but

cause large ripple currents, poor efficiency and

moreoutputcapacitancetosmoothoutthelarger

ripple current. The inductor must be able to

handle the peak current at the switching fre-

quency without saturating, and the copper resis-

tance in the winding should be kept as low as

possible to minimize resistive power loss. A

good compromise between size, loss and cost is

to set the inductor ripple current to be within

20% to 40% of the maximum output current.

I_PEAK= I_{OUT (max)}

+

2

and provide low core loss at the high switching

frequency. Low cost powdered iron cores have

a gradual saturation characteristic but can intro-

duceconsiderableACcoreloss,especiallywhen

the inductor value is relatively low and the

ripplecurrentishigh.Ferritematerials,although

more expensive, and have an abrupt saturation

characteristic with the inductance dropping

sharply when the peak design current is ex-

ceeded. Nevertheless, they are preferred at high

switchingfrequenciesbecausetheypresentvery

low core loss while the designer is only required

to prevent saturation. In general, ferrite or

molypermalloy materials are a better choice for

all but the most cost sensitive applications.

The switching frequency and the inductor oper-

ating point determine the inductor value as fol-

lows:

Optimizing Efficiency

The power dissipated in the inductor is equal to

the sum of the core and copper losses. To mini-

mizecopperlosses,thewindingresistanceneeds

to be minimized, but this usually comes at the

expense of a larger inductor. Core losses have a

more significant contribution at low output cur-

rent where the copper losses are at a minimum,

and can typically be neglected at higher output

currentswherethecopperlossesdominate.Core

loss information is usually available from the

magnetic vendor. Proper inductor selection can

affect the resulting power supply efficiency by

more than 15%!

V_OUT(V_{IN (max)}−V_OUT

)

L =

V_{IN (max)}F_SK_rI_{OUT (max)}

where:

f_S= switching frequency

Kr = ratio of the AC inductor ripple current to

the maximum output current

The peak to peak inductor ripple current is:

Thecopperlossintheinductorcanbecalculated

using the following equation:

V_OUT(V_{IN (max)}−V_OUT

)

P_L(Cu)= I_L²_(RMS)R_WINDING

I_PP

=

V_IN(max)F_SL

where I_L(RMS)is the RMS inductor current that

can be calculated as follows:

Once the required inductor value is selected, the

proper selection of core material is based on

peak inductor current and efficiency require-

ments. The core must be large enough not to

saturate at the peak inductor current

2

1

3

I_PP

I_OUT(max)

I_L(RMS)= I_OUT(max)1 +

(

)

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

7

APPLICATIONS INFORMATION

F_S= Switching Frequency

D = Duty Cycle

_OUT= Output Capacitance Value

Output Capacitor Selection

The required ESR (Equivalent Series Resis-

tance) and capacitance drive the selection of the

type and quantity of the output capacitors. The

ESR must be small enough that both the resis-

tive voltage deviation due to a step change in the

load current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load transient,

the output capacitor must supply all the addi-

tional current demanded by the load until the

SP7655 adjusts the inductor current to the new

value.

C

Input Capacitor Selection

The input capacitor should be selected for ripple

current rating, capacitance and voltage rating.

The input capacitor must meet the ripple current

requirement imposed by the switching current.

In continuous conduction mode, the source cur-

rent of the high-side MOSFET is approximately

a square wave of duty cycle V_OUT/V_IN. More

accurately the current wave form is trapezoidal,

given a finite turn-on and turn-off, switch tran-

sition slope. Most of this current is supplied by

the input bypass capacitors. The RMS current

handling capability of the input capacitors is

determined at maximum output current and

under the assumption that the peak

In order to maintain V_OUT,the capacitance must

be large enough so that the output voltage is

helped up while the inductor current ramps to

the value corresponding to the new load current.

Additionally, the ESR in the output capacitor

causes a step in the output voltage equal to the

current. Because of the fast transient response

and inherent 100%/0% duty cycle capability

providedbytheSP7655whenexposedtooutput

load transient, the output capacitor is typically

chosen for ESR, not for capacitance value.

to peak inductor ripple current is low, it is given

by:

I_CIN(RMS)= I

_OUT(max)√D(1 - D)

The worse case occurs when the duty cycle D is

50% and gives an RMS current value equal to

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main

contributor to output voltage ripple. The maxi-

mum allowable ESR required to maintain a

specifiedoutputvoltageripplecanbecalculated

by:

I

_OUT/2.

Select input capacitors with adequate ripple

current rating to ensure reliable operation.

The power dissipated in the input capacitor is:

R_ESR≤ ∆V_OUT

P

= I_C²_{IN (rms)}R_ESR(CIN)

I_PK-PK

CIN

where:

This can become a significant part of power

losses in a converter and hurt the overall energy

transfer efficiency. The input voltage ripple

primarily depends on the input capacitor ESR

and capacitance. Ignoring the inductor ripple

current, the input voltage ripple can be deter-

mined by:

∆V_OUT= Peak to Peak Output Voltage Ripple

I

_PK-PK= Peak to Peak Inductor Ripple Current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

²+ (I_PPR_ESR

)

I_PP(1 – D)

2

∆V_OUT

=

C_OUTF_S

(

)

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

8

APPLICATIONS INFORMATION

The first step of compensation design is to pick

the loop cross over frequency. High cross over

frequencyisdesirableforfasttransientresponse,

but often jeopardizes the power supply stability.

Cross over frequency should be higher than the

ESR zero but less than 1/5 of the switching

frequency or 60kHz. The ESR zero is contrib-

uted by the ESR associated with the output

capacitors and can be determined by:

I

_{OUT (MAX )}V_OUT(V_IN−V_OUT)

∆V_IN= I_out(max)R_{ESR(CIN )}

+

2

F_SC_INV_IN

The capacitor type suitable for the output capac-

itors can also be used for the input capacitors.

However, exercise extra caution when tantalum

capacitorsareused.Tantalumcapacitorsareknown

for catastrophic failure when exposed to surge

current, and input capacitors are prone to such

surge current when power supplies are connected

“live” to low impedance power sources. Although

tantalum capacitors have been successfully em-

ployed at the input, it is generally not recom-

mended.

1

ƒ_Z(ESR)

=

2π C_OUTR_ESR

The next step is to calculate the complex conju-

gate poles contributed by the LC output filter,

Loop Compensation Design

1

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to cross

over at the desired frequency cut-off (FCO), the

gain of the error amplifier has to compensate for

the attenuation caused by the rest of the loop at

this frequency. The goal of loop compensation

is to manipulate loop frequency response such

that its cross-over gain at 0db, results in a slope

of -20db/dec.

ƒ_P(LC)

=

2π L C_OUT

When the output capacitors are of a Ceramic

Type, the SP7655 Evaluation Board requires a

Type III compensation circuit to give a phase

boostof180°inordertocounteracttheeffectsof

an under damped resonance of the output filter

at the double pole frequency.

Type III Voltage Loop

PWM Stage

Output Stage

Compensation

G_AMP(s) Gain Block

G_PWMGain

Block

G

_OUT(s) Gain

Block

V_IN

(SRz2Cz2+1)(SR1Cz3+1)

(SR_ESRC_OUT+ 1)

+

V_REF

(Volts)

V_OUT

(Volts)

_

V_{RAMP_PP}

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)

[S^2LC_OUT+S(R_ESR+R_DC) C_OUT+1]

Notes: R_ESR= Output Capacitor Equivalent Series Resistance.

_DC= Output Inductor DC Resistance.

R

V_{RAMP_PP}= SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> R_ESR& R_DC

Voltage Feedback

G

_FBKGain Block

R₂

(R₁R₂)

V_REF

V_OUT

or

+

V_FBK

(Volts)

SP7655 Voltage Mode Control Loop with Loop Dynamic

Definitions:

R

_ESR= Output Capacitor Equivalent Series Resistance

_DC= Output Inductor DC Resistance

_{RAMP_PP}= SP7655 internal RAMP Amplitude Peak to Peak Voltage

Conditions:

C_Z2 >> Cp1 and R1 >> Rz3

Output Load Resistance >> R_ESRand R_DC

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

9

APPLICATIONS INFORMATION

Gain

(dB)

Error Amplifier Gain

Bandwidth Product

Condition:

C22 >> CP1, R1 >> RZ3

20 Log (RZ2/R1)

Frequency

(Hz)

Bode Plot of Type III Error Amplifier Compensation.

CP1

RZ2

CZ2

RZ3

CZ3

V

OUT

5

-

+

R1

6

VFB

68.1k, 1%

COMP

R

SET

CF1

+

0.8V

-

R

-0.8)

(kΩ)

=54.48/ (V

OUT

SET

Type III Error Amplifier Compensation Circuit

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

10

PACKAGE: 26 PIN DFN

D

(7 x 4 mm)

E

Top View

A

A3

A1

Side View

b

e

L

E2

DIMENSIONS in

26 Pin DFN

D2

(mm)

D3

SYMBOL

MIN

MAX

NOM

0.800 0.850 0.900

0.000

0.178 0.203 0.228

0.17

6.95 7.00 7.05

2.05 2.10

A

0.050

-

A1

A3

b

Bottom View

0.22

0.27

D

2.00

D2

D3

e

1.78 1.83 1.88

0.45 0.50 0.55

3.95 4.00 4.05

E

2.830

2.780

2.730

0.350 0.400 0.450

E2

L

26 Pin DFN

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

11

ORDERING INFORMATION

Package

Part Number

Temperature

SP7655ER/TR.........................................-40°C to +85°C ................................. 26 Pin 7 X 4 DFN

SP7655ER-L/TR .....................................-40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN

/TR = Tape and Reel

Pack quantity is 3000 DFN.

Corporation

ANALOGEXCELLENCE

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 08/17/04

SP7655 Wide Input Voltage Range 8A, 300kHz, Buck Regulator

12


型号：	SP7655
厂家：	SIPEX CORPORATION
描述：	Wide Input Voltage Range 8A, 300kHz, Buck Regulator 宽输入电压范围8A ， 300kHz的，降压型稳压器稳压器
文件：	总12页 (文件大小：121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP7655 [SIPEX]

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