CXD1915R [SONY]
Digital Video Encoder; 数字视频编码器
| 型号： | CXD1915R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Digital Video Encoder |
| 文件： | 总50页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1915R
Digital Video Encoder
Description
80 pin LQFP (Plastic)
The CXD1915R is a digital video encoder designed
for DVDs, set top boxes, digital VCRs and other
digital video equipment. This device accepts ITU-
R601 format Y, Cb and Cr data and ITU-R656 format
Y, Cb and Cr data, and the data are encoded to
composite video and separate Y/C video (S-video)
signals and converted to RGB/YUV signals.
Features
Absolute Maximum Ratings
• NTSC, PAL, MPAL and 4.43NTSC encoding modes
• Composite video and separate Y/C video (S-video)
signal output
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
VSS – 0.5 to +4.6
VSS – 0.5 to +7.0
V
V
VO VSS – 0.5 to VDD + 0.5 V
• R, G, B/Y, U, V (BetaCam/SMPTE level) signal
output
• Operating temperature
Topr
–20 to +75
°C
°C
• 8/16-bit pixel data input modes
• 13.5Mpps pixel rate
• Storage temperature
Tstg
–55 to +150
• 12.27 and 14.75Mpps square pixel rates
• External synchronization using HSYNC, VSYNC
and FID inputs, or internal synchronization
• Supports interlace and non-interlace modes
• On-chip 100% color bar generator
• OSD function
(VSS = 0V)
Recommended Operating Conditions
• Supply voltage
• Input voltage
VDD
VIN
3.3 ± 0.3
V
V
VSS to 5.5
• Operating temperature
Topr
• ITU-R656 code signal EAV decoding
• Supports I2C bus (400kHz) and Sony SIO
• Closed Caption (line 21, line 284) encoding
• VBID encoding
0 to +70
°C
I/O Capacitance
• Input capacitance
CI
9 (Max.)
pF
pF
• WSS encoding
• Output capacitance CO
11 (Max.)
• 10-bit 6-channel DAC
• Macrovision Pay-Per-View copy protection system
Note) Test conditions: VDD = VI = 0V, fM = 1MHz
1
Rev. 7.1.L1
• Monolithic CMOS single 3.3V power supply
• 80-pin plastic LQFP
1
This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of
the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse
engineering or disassembly is prohibited.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99422-PS
CXD1915R
– 2 –
CXD1915R
Pin Description
Pin
Symbol
No.
I/O
I
Description
Field ID input.
This signal indicates the field ID when resetting the vertical sync.
High indicates 1st field.
1
F1
Low indicates 2nd field.
Vertical sync reset input in active Low. This pin is pulled up. This is used for
synchronizing the phases of the external and internal vertical sync signals. When
XVRST = Low, the internal digital sync generator is reset according to the F1 status.
I
I
2
3
XVRST
XIICEN
Serial interface mode select input. This pin is pulled up.
When XIICEN = Low, Pins 4, 5, 6 and 8 are I2C bus mode.
When XIICEN = High, Pins 4, 5, 6 and 8 are Sony SIO mode.
This pin's function is selected by XIICEN (Pin 3). This pin is pulled up.
When XIICEN = High, this pin is Sony SIO mode; XCS chip select input.
When XIICEN = Low, this pin is I2C bus mode; SA slave address select input
signal which selects the I2C bus slave address.
I
4
5
XCS/SA
SI/SDA
This pin's function is selected by XIICEN (Pin 3).
I/O When XIICEN = High, this pin is Sony SIO mode; SI serial data input.
When XIICEN = Low, this pin is I2C bus mode; SDA input/output.
This pin's function is selected by XIICEN (Pin 3).
O
—
I
When XIICEN = High, this pin is Sony SIO mode; SO serial output.
When XIICEN = Low, this pin is not used and output is high impedance.
6
7
8
SO
Digital ground.
VSS1
This pin's function is selected by XIICEN (Pin 3).
When XIICEN = High, this pin is Sony SIO mode; SCK serial clock input.
When XIICEN = Low, this pin is I2C bus mode; SCL input.
SCK/SCL
—
I
Digital ground.
9
VSS2
System clock input.
To generate the correct subcarrier frequency, precise 27MHz is required.
10
11
12
13
SYSCLK
VSS3
—
I
Digital ground.
System reset input in active Low.
Set to Low for 40 clocks (SYSCLK) or more during power-on reset.
XRST
VSS4
—
Digital ground.
Pixel data clock signal output for 13.5MHz.
O
A 13.5MHz signal frequency divided from the system clock (SYSCLK) is output
and used as the clock signal when 16-bit pixel data is input.
14
15
PDCLK
VDD1
—
Digital power supply.
Field ID input/output.
When SYNCM (Pin 72) = High, the CXD1915R is set to master mode and outputs
as follows.
When control register bit "FIDS" = "1":
I/O
Low indicates 1st field and High indicates 2nd field.
When control register bit "FIDS" = "0":
16
FID
High indicates 1st field and Low indicates 2nd field.
When SYNCM (Pin 72) = Low, the CXD1915R is set to slave mode and this pin
becomes the field ID input.
– 3 –
CXD1915R
Pin
No.
Symbol
VSYNC
I/O
I/O
Description
Vertical sync signal input/output.
When SYNCM (Pin 72) = High, this pin is the vertical sync signal output.
When SYNCM = Low, this pin is the vertical sync signal input, and the falling
edge is detected during the 1st field to reset the internal circuits.
17
18
Horizontal sync signal input/output.
When SYNCM (Pin 72) = High, this pin is the horizontal sync signal output.
When SYNCM = Low, this pin is the horizontal sync signal input, and the falling
edge is detected during the 1st field to reset the internal circuits.
HSYNC
I/O
Composite sync output when using RGB output.
19
20
CSYNC
BF
O
O
Burst flag output. The burst flag is synchronized with the composite video signal
(CP-OUT) and indicates its color burst signal position.
Digital ground.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VSS5
—
I
PD0
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to PD7]
When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr
signal inputs. When control register bit "PIF MODE" = "1", these are Y signal
inputs.
PD1
I
PD2
I
PD3
I
Digital power supply.
VDD2
—
I
PD4
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
input. [PD0 to PD7]
When control register bit "PIF MODE" = "0", these are multiplexed Y, Cb, and Cr
signal inputs. When control register bit "PIF MODE" = "1", these are Y signal
inputs.
PD5
I
PD6
I
PD7
I
Digital ground.
VSS6
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
—
—
PD8/TD0
PD9/TD1
PD10/TD2
PD11/TD3
VSS7
Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]
When control register bit "PIF MODE" = "0", these inputs are not used. When control
register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.
In test mode, these are used for the internal circuit test data bus. The test data
bus is available only for the device vendor.
Digital ground.
PD12/TD4
PD13/TD5
PD14/TD6
PD15/TD7
VDD3
Upper 8-bit pixel data inputs when 16-bit pixel data is input/test data bus. [PD8 to PD15]
When control register bit "PIF MODE" = "0", these inputs are not used. When control
register bit "PIF MODE" = "1", these are multiplexed Cb and Cr signal inputs.
In test mode, these are used for the internal circuit test data bus. The test data
bus is available only for the device vendor.
Digital power supply.
Not connected inside the IC.
NC
DAC reference current output.
Connect resistance "16R" which is 16 times output resistance "R".
43
IREF
O
DAC reference voltage input.
Sets the DAC output full-scale width.
44
45
VREF
I
10-bit DAC output. This pin outputs the composite signal.
– 4 –
CP-OUT
O
CXD1915R
Pin
No.
Symbol
AVDD1
I/O
Description
—
—
O
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Analog power supply.
Analog ground.
AVSS1
C-OUT
VB
10-bit DAC output. This pin outputs the chroma (C) signal.
Connect to ground via a capacitor of approximately 0.1µF.
Connect to analog power supply via a capacitor of approximately 0.1µF.
10-bit DAC output. This pin outputs the luminance (Y) signal.
Analog power supply.
O
VG
O
Y-OUT
AVDD2
AVSS2
B-OUT
AVSS4
G-OUT
AVDD3
AVSS3
R-OUT
VSS8
O
—
—
O
Analog ground.
10-bit DAC output. This pin outputs the B and U signals.
Analog ground.
—
O
10-bit DAC output. This pin outputs the G and Y signals.
Analog power supply.
—
—
O
Analog ground.
10-bit DAC output. This pin outputs the R and V signals.
Digital ground.
—
I
TVSYNC
TD8
Test pin. This pin is pulled up. Normally this pin should be open.
I/O
I/O
I/O
—
Test data inputs/outputs. These pins should be open.
In test mode, these are used for the internal circuit test data bus.
The test data bus is available only for the device vendor.
TD9
TD10
VDD4
Digital power supply.
Test mode control. This pin is pulled up.
Normally this pin should be open.
XTEST
I
I
I
I
66
67
68
69
OSDSW/
XTEST1
These pins are pulled up. The functions of these pins are selected by XTEST
(Pin 66).
When XTEST = High, these are OSD data inputs.
When XTEST = Low, these are test mode control inputs.
The test mode is available only for the device vendor.
ROSD/
XTEST2
GOSD/
XTEST3
BOSD/
XTEST4
I
I
70
71
XTEST5
Test pin. This pin is pulled up. Normally this pin should be open.
Master/slave switching. This pin is pulled up.
SYNCM
I
I
72
73
When SYNCM = High, the CXD1915R is set to master mode.
When SYNCM = Low, the CXD1915R is set to slave mode.
Control register bit "PIX_EN" default value control.
This pin is pulled up.
PIXCON
VSS9
TDI
—
I
74
75
Digital ground.
Test mode control input. This pin is pulled up.
– 5 –
CXD1915R
Pin
No.
Symbol
TMS
I/O
Description
76
77
78
I
O
I
Test mode control input. This pin is pulled up.
Test output. This pin should be open.
Test mode control input. Fix to High.
TDO
TCK
Test mode reset input. Set to Low for 40 clocks (SYSCLK) or more during power-
on reset.
79
80
TRST
I
VDD5
—
Digital power supply.
– 6 –
CXD1915R
Electrical Characteristics
DC Characteristics
(Ta = 0 to +70°C, VSS = 0V)
Measurement
conditions
Typ. Max. Unit
Measurement pins
Item
Symbol
Min.
8
1
1
2
2
VIH1
VIL1
VIH2
VIL2
0.7VDD
V
V
V
V
VDD = 3.3 ± 0.3V
VDD = 3.3 ± 0.3V
VDD = 3.3 ± 0.3V
VDD = 3.3 ± 0.3V
Input High voltage
Input Low voltage
Input High voltage
Input Low voltage
0.2VDD
8
0.7VDD
0.3VDD
IOH = –8.0mA
VDD = 3.3 ± 0.3V
3
3
4
4
5
5
6
7
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
IIL1
VDD – 0.4
V
V
Output High voltage
Output Low voltage
Output High voltage
Output Low voltage
Output High voltage
Output Low voltage
Input leak current
IOL = 8.0mA
VDD = 3.3 ± 0.3V
0.4
IOH = –4.0mA
VDD = 3.3 ± 0.3V
VDD – 0.4
V
IOL = 4.0mA
VDD = 3.3 ± 0.3V
0.4
V
IOH = –2.0mA
VDD = 3.3 ± 0.3V
2.4
V
IOL = 4.0mA
VDD = 3.3 ± 0.3V
0.4
–100 –40
40
V
VI = 0V
VDD = 3.3 ± 0.3V
–240
–40
µA
VI = 0 to 5.5V
VDD = 3.3 ± 0.3V
II2
µA
Input leak current
Supply current
9
IDD
35
mA
VDD = 3.3 ± 0.3V
Notes:
1
F1, XVRST, XIICEN, XCS/SA, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TVSYNC,
TD8 to TD10, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON, TDI, TMS, TCK, TRST
2
3
4
5
6
SI/SDA, SCK/SCL
SO, PDCLK, CSYNC, BF
TDO
FID, VSYNC, HSYNC, TD0 to TD10
XVRST, XIICEN, XCS, TVSYNC, XTEST, OSDSW, ROSD, GOSD, BOSD, XTEST5, SYNCM, PIXCON,
TDI, TMS
7
8
9
F1, SI/SDA, SCK/SCL, SYSCLK, XRST, FID, VSYNC, HSYNC, PD0 to PD15, TD8 to TD10, TCK, TRST
The CXD1915R supports input from 5V devices.
Not including analog current
– 7 –
CXD1915R
DAC Characteristics
(AVDD = 3.3V, R = 200Ω, VREF = 1.35V, Ta = 25°C)
Item
Symbol
n
Measurement conditions
Min.
Typ.
10
Max.
Unit
bit
Resolution
Linearity error
EL
–2.4
–0.9
6.25
2.4
0.9
7.25
2
LSB
LSB
mA
mV
V
Differential linearity error
Output full-scale current
Output offset voltage
Output full-scale voltage
ED
IFS
6.75
VOS
VFS
1.20
1.20
1.35
1.35
1.50
Precision guaranteed output
voltage range
VOC
1.50
V
– 8 –
CXD1915R
AC Characteristics
1. Serial port interface
fSCK
tPWLSCK
tPWHSCK
SCK
XCS
tCSS
tCSH
tSIS
tSIH
SI
tSOD
tSOH
SO
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
DC
100
100
150
150
50
Typ.
Max.
3
Unit
MHz
ns
fSCK
SCK clock rate
t
t
t
t
t
t
t
t
PWLSCK
PWHSCK
CSS
SCK pulse width Low
SCK pulse width High
ns
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
ns
CSH
ns
SIS
ns
SIH
10
ns
SOD
Serial output delay time from SCK
Serial output hold time from SCK
30
ns
SOH
3
ns
CL = 35pF
– 9 –
CXD1915R
2. F1
SYSCLK
tFS
tFH
F1
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
10
0
Typ.
Max.
Unit
ns
tFS
FH
F1 setup time to SYSCLK
F1 hold time to SYSCLK
t
ns
3. OSDSW, ROSD, GOSD, BOSD
SYSCLK
tOS
tOH
OSDSW
ROSD
GOSD
BOSD
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
10
0
Typ.
Max.
Unit
ns
tOS
OH
OSD setup time to SYSCLK
OSD hold time to SYSCLK
t
ns
– 10 –
CXD1915R
4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID
fSYSCLK
tPWHCLK
tPWLCLK
SYSCLK
PDCLK
tPDCLKD
tPDCLKD
tCOD
tCOH
1
1
VSYNC
HSYNC
FID
1
CSYNC
BF
1 In master mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
SYSCLK clock rate
Symbol
Min.
Typ.
27
Max.
Unit
fSYSCLK
MHz
SYSCLK pulse width Low
SYSCLK pulse width High
t
t
t
t
t
PWLCLK
PWHCLK
PDCLKD
COD
11
11
ns
ns
PDCLK delay time from SYSCLK
20
26
ns
ns
Control output delay time from SYSCLK
Control output hold time from SYSCLK
COH
3
ns
CL = 35pF
5. 8-bit mode
(1) Pixel data interface
SYSCLK
tPDS
tPDH
PD0 to PD7
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
PDS
Min.
11
0
Typ.
Max.
Unit
ns
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
t
t
PDH
ns
– 11 –
CXD1915R
(2) XVRST
SYSCLK
tVS
tVH
XVRST
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
10
0
Typ.
Max.
Unit
ns
XVRST setup time to SYSCLK
XVRST hold time to SYSCLK
t
VS
VH
ns
t
(3) HSYNC, VSYNC, FID
SYSCLK
tSYS
tSYH
1
HSYNC
1
VSYNC
1
FID
1 In slave mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
SYS
Min.
10
0
Typ.
Max.
Unit
ns
Sync signal setup time to SYSCLK
Sync signal hold time to SYSCLK
t
t
ns
SYH
– 12 –
CXD1915R
6. 16-bit mode
(1) Pixel data interface
PDCLK
tPDS
tPDH
PD0 to PD15
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
23
0
Typ.
Max.
Unit
ns
t
PDS
PDH
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
t
ns
(2) XVRST
PDCLK
tVS
tVH
XVRST
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
Min.
20
0
Typ.
Max.
Unit
ns
XVRST setup time to PDCLK
XVRST hold time to PDCLK
t
t
VS
VH
ns
– 13 –
CXD1915R
(3) HSYNC, VSYNC, FID
PDCLK
tSYS
tSYH
1
HSYNC
1
VSYNC
1
FID
1 In slave mode
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Item
Symbol
SYS
Min.
20
0
Typ.
Max.
Unit
ns
Sync signal setup time to PDCLK
Sync signal hold time to PDCLK
t
t
ns
SYH
– 14 –
CXD1915R
Description of Functions
The CXD1915R converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A)
or PAL (ITU-R624; B, G, H, I) format.
The CXD1915R first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit
parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts the Cb and Cr
signals into the U and V signals, respectively, interpolates 4:2:2 to 4:4:4, and then modulates the signals with
the digital subcarrier inside the CXD1915R to create the chroma (C) signal.
The Y and chroma (C) signals are oversampled at double speed to reduce SIN (X)/(X) roll-off, and then added
to become the digital composite signal.
The 10-bit DAC converts the digital composite, Y/C, U, V, and RGB signals into analog signals.
1. Pixel input format
The pixel input format is selected according to the value of bit 4 (PIF MODE) of control register address 01H as
shown in Table 1-1 below.
When "PIF MODE" is "0", the image data (multiplexed Y, Cb, and Cr data) input from PD0 to PD7 are sampled
at the rising edge of SYSCLK as shown in the chart on the following page. When "PIF MODE" is "1", the image
data (PD0 to PD7: Y data, PD8 to PD15: multiplexed Cb and Cr data) input from PD0 to PD15 are sampled at
the rising edge of PDCLK.
PIF Mode
PD15 to 8
NA
PD7 to 0
Y/Cb/Cr
Y
0 (8 bit mode)
1 (16 bit mode)
Cb/Cr
Table 1-1
Also, the pixel input data timing is determined according to bits 3 and 2 (PIX TIM) of control register address
01H as shown in Table 1-2 below.
When "PIF MODE" is "0", Cb0 of the image data (Cb0, Y0, Cr0 and Y1) input from PD0 to PD7 is sampled at
the respective rising edge of SYSCLK after the fall of HSYNC.
(Default: Cb0 is sampled at the rising edge of the second SYSCLK after the fall of HSYNC.)
When "PIF MODE" is "1", Y0 and Y1 data are input to PD0 to PD7, multiplexed Cb0 and Cr0 data are input to
PD8 to PD15, and Y0 and Cb0 are sampled at the respective rising edge of PDCLK after the fall of HSYNC.
(Default: Y0 and Cb0 are sampled at the rising edge of the second PDCLK after the fall of HSYNC.)
PIX TIM
Timing phase
0
0
1
0
1
#0 (default)
0
1
1
#1
#2
#3
Table 1-2
– 15 –
CXD1915R
Pixel Data Input Timing
1
2
3
4
5
SYSCLK
1
2
3
PDCLK
HSYNC
[16-bit mode]
Y0
Y1
Y2
Y3
Y4
Y5
PD0 to PD7
#0 #1
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
PD8 to PD15
Y0
Y1
Y2
Y3
Y4
#2 #3
Cb0
Cr0
Cb2
Cr2
Cb4
[8-bit mode]
Cb0
Y0
Cr0 Y1 Cb2 Y2
Cr2
Y3
Cb4 Y4
Cr4
Y5
Cb6
Y4
PD0 to PD7
#0
#1
Cb0 Y0
Cr0
Y1 Cb2
Y2
Cr2
Y3
Y3 Cb4
Cb4 Y4
#2
#3
Cb0 Y0
Cr0
Y1 Cb2 Y2
Cr2
Cr4
Y5
Cb0
Y0 Cr0
Y1 Cb2 Y2
Cr2
Y3 Cb4
Y4
Cr4
PD0
PD1
:
Pixel data 0 (LSB)
Pixel data 1
:
PD8
PD9
:
Pixel data 0 (LSB)
Pixel data 1
:
PD7
Pixel data 7 (MSB)
PD15
Pixel data 7 (MSB)
– 16 –
CXD1915R
2. Serial interface
The CXD1915R supports both the I2C bus (high-speed mode) and Sony serial interface modes. These modes
can be selected by the XIICEN input pin as shown in Table 2-1 below.
H
L
XIICEN
SI/SDA
SONY SIO Mode
I2C Mode
SI
SCK
SDA
SCL
SCK/SCL
XCS/SA
SO
XCS
SA
SO
High-Z
Table 2-1
2-1. I2C bus interface
The CXD1915R becomes an I2C bus slave transceiver, and supports the 7-bit slave address and the high-
speed mode (400K bits/s).
2-1-1 Slave address
Two kinds of slave address (88H, 8CH) can be selected by the SA signal as shown in Table 2-2 below.
A6
1
A5
0
A4
0
A3
0
A2
1
A1
SA
A0
0
R/W
X
Table 2-2
2-1-2. Write cycle
A
start address
A
A
A
S
Slave address
W
write data
write data
P
"0"
from master to slave
from slave to master
D7
D6
D5
D4
D3
D2
D1
D0
start address
ADR[4:0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start
address register of this IC as the start address of the control register. In subsequent cycles, the data supplied
from the master is written in the addresses indicated by the control register address. The set control register
address is automatically incremented with the transfer completion of each byte of data.
– 17 –
CXD1915R
2-1-3. Read cycle
Slave address
read address
read data
R
A
A
A
P
S
"1"
from master to slave
from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and
only the ID code (address 0CH, 0DH) is read out. During the read cycle, the start address is automatically set
to 0CH.
Note: In Sony SIO mode, addresses from 00H to 0DH can be read out.
2-1-4. Handling of general call address (00H)
The general call address is ignored and there is no ACK response.
– 18 –
CXD1915R
2-2. Sony serial interface
The Sony serial interface uses the SCK, XCS, SI and SO signals.
The serial interface is active when the XCS signal is Low and transmits and receives signals to and from the
host.
The first byte after the XCS signal becomes Low is set up as a serial control command. Its data includes a
control register address and read/write mode information for the interface. (See 2-2-1. Serial control command
format.)
The control register address is automatically incremented with the transfer completion of each byte of data. In
write mode, the SI signal of the serial input data is sampled at the rising edge of the SCK signal. In read mode,
the register value is read out as the SO signal of the serial output data at the falling edge of the SCK signal,
and is variable. In this case, the SI signal of the serial input data is ignored.
Serial Interface Timing
SCK
XCS
SI
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D1
D2
Serial Data
D2 D3 D4
D3
D4
D5
D5
D6
D6
D7
LSB
Serial Control Command
MSB
LSB
MSB
SO
D0
D7
Serial Interface Sequence
SCK
XCS
SI
00H
FFH
00H
11H
01H
CEH
02H
Internal address
Control register
address set
Control register address
auto-increment
Control register address
auto-increment
Control Register Address
Control Register Data
00H
01H
02H
FFH
11H
CEH
2-2-1. Serial control command format
D7
D6
D5
D4
D3
D2
D1
D0
WR
ADR[4:0]
WR:
Read/write mode
When this bit is "1":
The serial interface is write mode, and the SI signal of the serial input data is written in the
register.
When this bit is "0":
The serial interface is read mode, and the register value is read out as the SO signal of the
serial output data.
ADR[4:0]: Control register address setting (Initial value of the address)
– 19 –
CXD1915R
3. XVRST, F1
The XVRST and F1 signals are used to synchronize with the external V sync.
The XVRST and F1 signals are sampled at the rising edge of SYSCLK, and the F1 signal is sampled when
XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is
reset to the 2nd field. When XVRST is set to High, the digital sync generator starts operation, and the
sequence of the 1st or 2nd field starts.
[8-bit mode]
XVRST Timing (1st Field)
SYSCLK
XVRST
F1 “H”
Start of 1st field (NTSC: 4H)
(PAL: 1H)
VSYNC
FID
HSYNC
XVRST Timing (2nd Field)
SYSCLK
XVRST
F1 “L”
Start of 2nd field (NTSC: 266H)
(PAL: 313H)
VSYNC
FID
1/2H
HSYNC
– 20 –
CXD1915R
[16-bit mode]
XVRST Timing (1st Field)
PDCLK
XVRST
F1 “H”
Start of 1st field (NTSC: 4H)
(PAL: 1H)
VSYNC
FID
HSYNC
XVRST Timing (2nd Field)
PDCLK
XVRST
F1 “L”
Start of 2nd field (NTSC: 266H)
(PAL: 313H)
VSYNC
FID
1/2H
HSYNC
– 21 –
CXD1915R
4. External synchronization
The CXD1915R can select master or slave operation using the SYNCM input pin.
When the SYNCM signal is Low, the CXD1915R is set to slave mode, and synchronizes to an external source
using the HSYNC, VSYNC and FID I/O pin inputs.
The signal combinations used for external synchronization are set by bit 7 (SSEL) of control register 03H.
Register setting
1
HSYNC
Used
VSYNC
Ignored
Used
FID
Used
Used
Ignored
0 (default)
4-1. V synchronization
4-1-1. When SSEL = 0 (default), the CXD1915R identifies the data as the 1st field when the falling edges of
the HSYNC and VSYNC signals match, or as the 2nd field when the falling edges do not match. The
CXD1915R performs synchronization reset only during the 1st field.
VSYNC
HSYNC
CPSYNC
4-1-2. When SSEL = 1, operation is reset to the 1st field at the falling edge of the FID signal. In this case, set
bit 7 (FIDS) of control register 00H to High (default).
FID
HSYNC
CPSYNC
4-2. H synchronization
The horizontal line is reset by detecting the falling edge of the HSYNC signal.
Be sure to perform reset at the precise period.
– 22 –
CXD1915R
5. Closed caption
The CXD1915R supports closed caption encoding.
ASCII data for closed captions are encoded in line 21 and line 284 by adding a parity bit to every ASCII data
set up in control registers 04H, 05H (data #1 and #2 for line 21) and 06H, 07H (data #1 and #2 for line 284).
The control registers (04H to 07H) are double-buffered and ASCII data, which are set up by the serial
interface, are synchronized with the VSYNC signal.
Automatic reset on/off can be selected for ASCII data which has been synchronized with VSYNC by changing
the setting of bit 5 (CCRST) of control register address 03H.
When CCRST = "1", the control registers (04H, 05H or 06H, 07H) are automatically reset in sync with the rise
of the next VSYNC.
When CCRST = "0" (default), the control registers (04H, 05H or 06H, 07H) are not reset, and the data set last
is held.
Closed Caption Data Renewal Timing
When CCRST = "1"
Field
Field 4
Field 1
VSYNC
Control registers 04H and 05H set
NEW DATA
SI/SDA
Data 21H
Front-end buffer
OLD DATA
NEW DATA
(7'h00)
Data 21H
Rear-end buffer
OLD DATA
DATA RESET (7'h00)
DATA A
NEW DATA
Data 284H
Front-end buffer
DATA A
Data 284H
Rear-end buffer
(7'h00)
Field 2
Field
Field 1
VSYNC
Control registers 06H and 07H set
NEW DATA
SI/SDA
Data 284H
Front-end buffer
(7'h00)
OLD DATA
NEW DATA
Data 284H
Rear-end buffer
OLD DATA
DATA RESET (7'h00)
DATA A
NEW DATA
Data 21H
Front-end buffer
DATA A
Data 21H
Rear-end buffer
(7'h00)
– 23 –
CXD1915R
When CCRST = "0"
Field
Field 4
Field 1
VSYNC
SI/SDA
Control registers 04H and 05H set
NEW DATA
Data 21H
Front-end buffer
OLD DATA
NEW DATA
Data 21H
Rear-end buffer
OLD DATA
DATA A
NEW DATA
Data 284H
Front-end buffer
Data 284H
Rear-end buffer
DATA A
Field
Field 1
Field 2
VSYNC
Control registers 06H and 07H set
NEW DATA
SI/SDA
Data 284H
Front-end buffer
OLD DATA
NEW DATA
Data 284H
Rear-end buffer
OLD DATA
DATA A
NEW DATA
Data 21H
Front-end buffer
Data 21H
Rear-end buffer
DATA A
Double Buffer for Closed Caption
SI/SDA
04H
VSYNC
Load
ASCII data #1
Closed Caption Signal Waveform
HSYNC Color
Burst
Clock Run-In
Start Bits
ASCII Data #1
ASCII Data #2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
– 24 –
CXD1915R
6. VBID (Video ID)
The CXD1915R supports encoding of Video ID (Provisional Standard EIAJ CPX-1204) to discriminate the
aspect ratio. VBID is 14-bit data as shown in Table 6-1, and becomes 20-bit data with the addition of 6-bit
CRCC. These data are superimposed on lines 20 and 283 during the vertical blanking period of NTSC video
signals and output.
The data setting in Table 6-1 below is done by writing data in control registers (08H and 09H) via the serial
interface. These control registers (08H and 09H) are double-buffered, and the VBID data are renewed in sync
with the VSYNC signal.
bit-No.
Contents
"1"
"0"
1
2
3
Transmission aspect ratio Full-mode (16:9)
4:3
Normal
A
B
Image display format
Undefined
Letter-box
Word 0
4
5
6
Identification information about video and other signals (audio signals, etc.)
incidental to images which are transmitted simultaneously
Word 1
Word 2
4-bit width Identification signal incidental to Word 0
4-bit width Identification signal and information incidental to Word 0
Table 6-1
Double Buffer for VBID
SI
08H
VSYNC
Load
Word 0
VBID Data Renewal Timing
VSYNC
SI
Control register 08H set
NEW DATA
Data #1
OLD DATA
NEW DATA
– 25 –
CXD1915R
VBID Code Allocation
The VBID data are composed of Word 0 = 6 bits (Word 0-A = 3 bits and Word 0-B = 3 bits), Word 1 = 4 bits,
Word 2 = 4 bits, and CRCC = 6 bits.
bit 0 ···
··· bit 20
Data
Word 1
4 bits
Word 2
4 bits
CRCC
6 bits
0-A
0-B
Word 0
6 bits
VBID Signal Waveform
Ref.
bit 1 bit 2 bit 3
· · ·
bit 20
2.235µs ± 20ns
49.1µs ± 0.5µs
11.2µs ± 0.6µs
1H
– 26 –
CXD1915R
7. WSS (Widescreen Signaling)
The CXD1915R supports WSS encoding to discriminate the aspect ratio. WSS is 14-bit data as shown in
Table 7-1. These data are superimposed on line 23 during the vertical blanking period of PAL video signals
and output.
The data setting in Table 7-1 below is done by writing data in control registers (0AH and 0BH) via the serial
interface. These control registers (0AH and 0BH) are double-buffered, and the WSS data are renewed in sync
with the VSYNC signal.
Group 1
Group 2
Aspect ratio information (4 bits)
PAL plus related information (4 bits)
b0 to b3
b4 to b7
0001 Normal
1000 Letter-box 14:9 Center
0100 Letter-box 14:9 Top
1101 Letter-box 16:9 Center
0010 Letter-box 16:9 Top
1011 Letter-box > 16:9 Center
0111 Full-mode 14:9
bit 4
Camera/Film mode
bits 5 to 7 Reserved
(Color plus)
(Helper)
(BasebandHelper)
1110 Full-mode 16:9
b3 is odd parity.
Group 3
Subtitle information (3 bits)
b8 to b10
Group 4
Undefined (3 bits)
b11 to b13
Reserved
Bit 8
Bits 9, 10
00
TeleText subtitle enable/disable
No subtitle
10
01
11
Subtitle inside screen
Subtitle in black portion
Reserved
Table 7-1
Double Buffer for WSS
SI
0AH
VSYNC
Load
Group1, 2
WSS Data Renewal Timing
VSYNC
Control register 0AH set
NEW DATA
SI
Data #1
OLD DATA
NEW DATA
– 27 –
CXD1915R
WSS Signal Waveform
bit 0 bit 1 bit 2
· · ·
bit 13
649
71.4 IRE
RUN Start
-IN Code
256
20
0 IRE
11.03µs
10.67µs
16.59µs
8. RGB/YUV output
The CXD1915R has an RGB/YUV output function. RGB and YUV can be switched by setting bit 2 (RGB_UV)
of control register address 03H.
Also, the UV level can be selected from BetaCam or SMPTE by setting bit 0 (BTCM) of address 03H. During
RGB output, when bit 1 (GSYNC) of control register address 03H is "1", the sync signal is added to the G
signal and output; when bit 1 (GSYNC) is "0", the sync signal is not added.
9. Support of interlace/non-interlace modes
The CXD1915R can be switched to the interlace and non-interlace modes by varying the setting of bit 1
(INTERLS) of control register address 01H. During the non-interlace mode, the 1st field is repeatedly output.
Number of lines/field
Register setting value
INTERLS
NTSC
PAL
0 (non-interlace)
1 (interlace)
262
312
262.5
312.5
– 28 –
CXD1915R
10. Support of NTSC, PAL, MPAL and 4.43NTSC
The CXD1915R can convert to NTSC, PAL, MPAL and 4.43NTSC analog TV signals by setting bits 2, 1 and 0
(ENC MODE) of control register address 00H.
Register setting value
ENC MODE
Number of
lines/field
Subcarrier line
phase difference
Subcarrier
frequency [MHz]
Encoding mode
0
0
0
1
0
0
1
0
0
1
1
1
PAL
NTSC
625/50
525/60
525/60
525/60
±135°
±180°
±135°
±180°
4.4336 (10 ± 1cycles)
3.5795 (9 ± 1cycles)
3.5756 (9 ± 1cycles)
4.4336
MPAL
4.43NTSC
11. OSD
The CXD1915R can be switched to OSD mode by setting bit 6 (OSDEN) of control register address 02H. At
this time, if OSDSW (Pin 67) = 1, the OSD input pin is enabled.
Also, the luminance level can be selected from the four levels of 25%, 50%, 75% and 100% by varying the
setting of bits 5 and 4 (Y_LEV) of control register address 02H. This allows 29-color (7 colors × 4 levels +
black) OSD output. (Up to 8 colors can be displayed at once.)
Color
White
Yellow
Cyan
ROSD (Pin 68)
GOSD (Pin 69)
BOSD (Pin 70)
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
Green
Magenta
Red
Blue
Black
12. Support of square pixels
The CXD1915R can be switched to support square pixels by setting bit 4 (SQPIX) of control register address
00H.
MPAL and 4.43NTSC cannot be used in square pixel mode.
Pixel clock frequency [MHz]
Register setting value
Mode
SQPIX
NTSC
PAL
0
1
Normal mode
13.5
13.5
Square pixel mode
12.272727
14.75
13. On-chip 100% color bar generator
The CXD1915R can display an ITU_R100% color bar from its internal generator by setting bit 7 (CBAR) of
control register address 02H.
– 29 –
CXD1915R
14. ITU-656EAV decoding
The CXD1915R decodes the EAV of the ITU-656 1st field and performs internal synchronization every 4 fields
for NTSC or every 8 fields for PAL by setting bit 3 (D1 MODE) of control register address 03H.
– 30 –
CXD1915R
– 31 –
CXD1915R
– 32 –
CXD1915R
– 33 –
CXD1915R
– 34 –
CXD1915R
Sync Signal Timing
0.148µs
0.148µs
2.3µs
29.5µs
27.1µs
4.67µs
1/2H
63.555µs
NTSC Equalizing Pulse and Sync Pulse Signal Waveform
0.296µs
0.296µs
2.37µs
29.63µs
27.3µs
4.67µs
1/2H
64µs
PAL Equalizing Pulse and Sync Pulse Signal Waveform
– 35 –
CXD1915R
Control Register Map
BIT
Function Selection #1
7
6
5
4
3
2
1
0
Address
ENC
MODE
MASK
EN
PIX
EN
R/W
FIDS
00H
SQPIX
SET UP
ENC MODE
Encoding mode
000: PAL encoding mode
001: NTSC encoding mode (Default)
010: Inhibit
011: MPAL encoding mode
100: Inhibit
101: 4.43NTSC encoding mode
110: Inhibit
111: Inhibit
SET UP
SQPIX
PIX EN
Setup enable
0: No setup level, black level = blanking level
1: 7.5 IRE setup level insertion (Default)
Square pixel
0: Disable square pixel mode (13.5MHz) (Default)
1: Enable square pixel mode
Pixel data enable
PIXCON input pin = High 0: Disable input pixel data
1: Enable input pixel data (Default)
PIXCON input pin = Low 0: Disable input pixel data (Default)
1: Enable input pixel data
MASK EN
FIDS
Mask enable
0: Pixel data through during vertical blanking period
1: Pixel data reject during vertical blanking period (Default)
FID polarity select
SYNCM input pin = High
0: 1st field High, 2nd field Low
1: 1st field Low, 2nd field High (Default)
SYNCM input pin = Low
Fixed to "1".
– 36 –
CXD1915R
BIT
Function Selection #2
7
6
5
4
3
2
1
0
PIF
MODE
FREE
RUN
Address
01H
DAC MODE
PIX TIM
R/W
INTERLS
FREERUN
Free running
0: Reset applied every 4 fields during NTSC or every 8 fields during PAL and MPAL (Default)
1: No SCH timing reset
INTERLS
PIX TIM
Interlace mode switching
0: Non-interlace mode
1: Interlace mode (Default)
Pixel input timing
00: #0 (Default)
01: #1
10: #2
11: #3
PIF MODE
Pixel input format
0: 8-bit mode, multiplexed Y, Cb, Cr (4:2:2) (Default)
1: 16-bit mode, Y and multiplexed Cb, Cr (4:2:2)
DAC MODE
DAC output activity
000: Non-active
001: CP-Out active
010: Inhibit
011: Video signal (Y, C, CP) -Out active (Default)
100: Inhibit
101: R, G, B-Out and CP-Out active
110: Inhibit
111: All outputs active
– 37 –
CXD1915R
BIT
Function Selection #3
7
4
3
2
1
0
6
5
Address
CBAR
R/W
OSDEN
Y_LEV
WSS
CC Mode
VBID
02H
CC MODE
Closed caption encoding mode
00: Disable closed caption encoding (Default)
01: Enable encoding in 1st field (Line 21)
10: Enable encoding in 2nd field (Line 284)
11: Enable encoding in both fields
WSS
WSS encoding enable
0: Disable WSS encoding (Default)
1: Enable WSS encoding
VBID
VBID encoding mode
0: Disable VBID encoding (Default)
1: Enable VBID encoding
Y_LEV
OSD luminance level select
00: 100% (Default)
01: 25%
10: 50%
11: 75%
OSDEN
CBAR
OSD enable
0: Disable OSD (Default)
1: Enable OSD
Color bar enable
0: Disable on-chip color bar output (Default)
1: Enable on-chip color bar output (ITU_R100% color bar)
– 38 –
CXD1915R
BIT
Function Selection #4
7
4
3
2
1
0
6
5
D1
MODE
Address
SSEL
BF
R/W
CCRST
RGB_UV GSYNC
BTCM
03H
BTCM
UV output level control
0: SMPTE
1: BetaCam (Default)
GSYNC
RGB_UV
D1 MODE
CCRST
BF
G-on SYNC enable
0: Disable (Default)
1: Enable
RGB/YUV output mode switching
0: YUV (Default)
1: RGB
ITU-R656 EAV decoding
0: Disable ITU-R656 EAV decoding (Default)
1: Enable ITU-R656 EAV decoding
Closed caption character reset enable
0: Disable (Default)
1: Enable
Burst flag enable
0: Disable burst flag
1: Enable burst flag (Default)
SSEL
Sync select
Selects the sync signal used during slave mode.
HSYNC VSYNC
FID
0: Used
1: Used
Used Ignored (Default)
Ignored Used
– 39 –
CXD1915R
BIT
Closed Caption Character #1 (Line 21H)
7
6
5
4
3
2
1
0
0
0
Address
04H
ASCII Data #1
(Default: 0H)
R/W
R/W
R/W
Closed Caption Character #2 (Line 21H)
7
6
5
4
3
2
1
Address
05H
ASCII Data #2
(Default: 0H)
Closed Caption Character #1 (Line 284H)
7
6
5
4
3
2
1
Address
06H
ASCII Data #1
(Default: 0H)
Closed Caption Character #2 (Line 284H)
7
7
7
6
5
5
5
4
3
2
1
0
0
0
Address
07H
ASCII Data #2
(Default: 0H)
R/W
R/W
R/W
VBID #1
6
4
3
3
2
1
Word 0
Address
08H
Word 0-B
Word 0-A
VBID #2
6
4
2
1
Address
09H
Word 2
Word 1
WSS #1
7
6
5
4
3
2
1
0
Group 2
bit 6
Group 1
bit 1
Address
0AH
R/W
R/W
bit 7
bit 5
bit 4
bit 3
bit 2
bit 0
WSS #2
7
6
5
4
3
2
1
0
Group 4
bit 12
Group 3
bit 9
Address
0BH
bit 13
bit 11
bit 10
bit 8
– 40 –
CXD1915R
BIT
Device ID #1
7
6
5
4
3
2
1
0
Address
0CH
ID Code
(Lower) 15H
RO
ID code
Identification: 15H
Device ID #2
7
6
5
4
3
2
1
0
Address
0DH
ID Code
(Upper) 19H
RO
ID code
Identification: 19H
– 41 –
CXD1915R
Video Signal Timing (NTSC, 7.5 IRE Setup)
806
806
WHITE LEVEL
748
655
597
100 IRE
506
448
7.5 IRE
355
297
BLACK LEVEL
BLANK LEVEL
256
40 IRE
36
SYNC LEVEL
NTSC Y (luminance) signal output waveform
7.5 IRE setup
832
622
512
402
20 IRE
BLANK LEVEL
COLOR BURST
192
NTSC C (chroma) signal output waveform
7.5 IRE setup
– 42 –
CXD1915R
Video Signal Timing (NTSC, No Setup)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
SYNC LEVEL
256
40 IRE
36
NTSC Y (luminance) signal output waveform
859
622
512
402
20 IRE
BLANK LEVEL
COLOR BURST
165
NTSC C (chroma) signal output waveform
– 43 –
CXD1915R
Video Signal Timing (PAL)
806
806
WHITE LEVEL
744
643
580
100 IRE
482
419
318
BLANK LEVEL
SYNC LEVEL
256
43 IRE
20
PAL Y (luminance) signal output waveform
859
630
21.5 IRE
512
BLANK LEVEL
394
COLOR BURST
165
PAL C (chroma) signal output waveform
– 44 –
CXD1915R
RGB Signal Output Waveform
R signal
806
806
257
257
805
805
256
256
WHITE LEVEL
BLANK LEVEL
806
100 IRE
256
G signal
806
807
806
806
256
256
256
256
WHITE LEVEL
806
100 IRE
256
BLANK LEVEL
WHITE LEVEL
During G-on SYNC (NTSC)
806
100 IRE
256
40 IRE
BLANK LEVEL
SYNC LEVEL
36
During G-on SYNC (PAL)
806
WHITE LEVEL
100 IRE
256
BLANK LEVEL
SYNC LEVEL
43 IRE
20
B signal
806
257
808
259
803
256
806
256
WHITE LEVEL
BLANK LEVEL
806
100 IRE
256
– 45 –
CXD1915R
UV Output Level
Color Difference (U) Signal
SMPTE LEVEL
Beta Cam LEVEL
782
901
690
768
603
643
512
512
421
381
334
256
242
123
NTSC
NTSC, No setup
871
750
633
512
391
274
153
NTSC, Setup
787
787
693
693
605
605
512
512
419
419
331
331
237
237
PAL
PAL
– 46 –
CXD1915R
Color Difference (V) Signal
SMPTE LEVEL
Beta Cam LEVEL
782
901
738
838
555
574
512
512
512
512
469
450
286
186
242
123
NTSC
NTSC, No setup
871
813
570
453
211
153
NTSC, Setup
787
787
742
742
556
556
512
468
468
282
282
237
237
PAL
PAL
– 47 –
CXD1915R
Internal Filter Characteristics
Interpolation Filter Characteristic
0
–10
–20
–30
–40
–50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Frequency [MHz]
Chrominance Filter Characteristic
0
–20
–40
–60
–80
–100
0
1
2
3
4
5
6
7
8
9
10
Frequency [MHz]
– 48 –
CXD1915R
DAC Application Circuit
CXD1915R
AVDD
VG
0.1µF
3.2kΩ
1kΩ
VREF
IREF
AVSS
CP-OUT
Y-OUT
C-OUT
Buff AMP
LPF
G/Y-OUT
B/U-OUT
R/V-OUT
75Ω
0.1µF
VB
200Ω
VSS
Application Circuit
CXD1915R
(Video encoder)
MPEG decoder
8
8
Y
C
PD0 to PD7
PD8 to PD15
FID
FID
HSYNC
VSYNC
DCLK
CLK
HSYNC
VSYNC
PDCLK
SYSCLK
13.5MHz
27MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 49 –
CXD1915R
Package Outline
Unit: mm
80PIN LQFP (PLASTIC)
14.0 ± 0.2
12.0 ± 0.1
60
41
40
61
A
21
(0.22)
80
1
20
+ 0.05
0.127 – 0.02
+ 0.08
0.18 – 0.03
0.5
0.13
+ 0.2
1.5 – 0.1
M
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
LQFP-80P-L01
LQFP080-P-1212
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42 ALLOY
0.5g
JEDEC CODE
– 50 –
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