CXD2309Q [SONY]
10-bit 50MSPS RGB 3-channel D/A Converter; 10位50MSPS RGB三通道D / A转换器
| 型号： | CXD2309Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | 10-bit 50MSPS RGB 3-channel D/A Converter |
| 文件： | 总16页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2309Q
10-bit 85MSPS 3-Channel D/A Converter
Description
48 pin QFP (Plastic)
The CXD2309Q is a 10-bit high-speed D/A
converter for video band, featuring RGB 3-channel
input/output. This is ideal for use in high-definition
TVs and high-resolution displays.
Features
• Resolution 10-bit
• Maximum conversion speed 85MSPS
• RGB 3-channel input/output
• Differential linearity error ±0.5 LSB
• Low power consumption 275 mW
(200 Ω load for 2 Vp-p output)
• Single +5 V power supply
• Low glitch
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage AVDD, DVDD
• Input voltage (All pins)
7
V
VIN
VDD+0.5 to VSS–0.5
0 to 15
V
• Output current
IOUT
mA
• Storage temperature
Tstg
• 48-pin QFP package
–55 to +150
°C
Structure
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25
DVDD, DVSS 4.75 to 5.25
Silicon gate CMOS IC
V
V
• Reference input voltage
VREF
0.5 to 2.0
9 (min.)
V
ns
°C
• Clock pulse width
TPW1, TPW0
• Operating temperature
Topr
–20 to +85
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E94341B01
CXD2309Q
Block Diagram
43
42
AVSS
RO
1
2
3
(LSB) R0
4LSB’S
CURRENT
CELLS
R1
R2
R3
4
5
R4
R5
6LSB’S
CURRENT
CELLS
LATCHES
LATCHES
LATCHES
DECODER
DECODER
6
7
R6
8
R7
9
R8
CLOCK
GENERATOR
10
(MSB) R9
31
RCK
45
44
AVSS
GO
(LSB) G0 11
G1 12
4LSB’S
CURRENT
CELLS
G2 13
G3 14
G4 15
6LSB’S
CURRENT
CELLS
16
17
18
19
20
G5
G6
DECODER
DECODER
G7
G8
CLOCK
GENERATOR
(MSB) G9
32
GCK
47
46
AVSS
BO
21
22
23
24
25
26
27
28
29
30
(LSB) B0
4LSB’S
CURRENT
CELLS
B1
B2
B3
41
40
39
AVDD
AVDD
AVDD
B4
6LSB’S
CURRENT
CELLS
DECODER
DECODER
B5
B6
B7
B8
CLOCK
GENERATOR
(MSB) B9
38
37
36
VG
33
48
BCK
VREF
IREF
DVDD
BIAS VOLTAGE
GENERATOR
CURRENT CELLS
(FOR FULL SCALE)
35
34
VB
DVSS
—2—
CXD2309Q
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VREF
VG
B3
B2
AVDD
AVDD
AVDD
RO
B1
B0 (LSB)
G9 (MSB)
G8
AVSS
GO
G7
G6
AVSS
BO
G5
G4
AVSS
DVDD
G3
G2
10 11 12
1
2
3
4
5
6
7
8
9
to 35
48
1
Digital system
Analog system
,
36 to 47
Pin Description and Equivalent Circuit
Pin No. Symbol I/O
Equivalent circuit
Description
1 to 10 R0 to R9
11 to 20 G0 to G9
21 to 30 B0 to B9
Digital input.
1 pin R0 (LSB) to 10 pin R9 (MSB)
11 pin G0 (LSB) to 20 pin G9 (MSB)
21 pin B0 (LSB) to 30 pin B9 (MSB)
DVDD
I
to
33
1
31
32
RCLK
GCLK
DVSS
Clock input.
33
34
BCLK
DVSS
—
O
Digital ground.
DVDD
DVDD
Connect an approximately 0.1µF
capacitor.
35
VB
35
DVSS
—3—
CXD2309Q
Pin No.
36
Symbol
IREF
I/O
O
Equivalent circuit
Description
Reference current output.
Connect an “RIR” resistor which are
16 times the output resistance
“ROUT”.
AVDD
AVDD
36
AVDD
Reference voltage input.
AVDD
37
38
VREF
I
AVSS
Sets an output full-scale value.
37
38
AVSS
AVSS
Connect an approximately 0.1µF
capacitor.
VG
O
39 to 41
42
AVDD
RO
—
Analog power supply.
AVDD
42
Current output. Output can be
obtained by connecting a resistor
(200 Ω typ.).
44
46
44
46
GO
BO
O
AVSS
AVSS
43, 45, 47
48
AVSS
DVDD
—
—
Analog ground.
Digital power supply.
—4—
CXD2309Q
Electrical Characteristics
(fCLK=85 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, RIR=3.3 kΩ, Ta=25°C)
Item
Symbol
n
Measurement conditions
Min.
Typ.
10
Max.
Unit
bit
Resolution
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +85 °C
Conversion speed
fCLK
0
85
MSPS
Integral non-linearity error
EL
–2.0
–0.5
2.0
0.5
LSB
LSB
Endpoint
Differential non-linearity error ED
Precision guaranteed
VOC
1.8
1.92
1.92
2.0
V
output voltage range
Output full-scale voltage
VFS
FSR
IFS
1.8
0
2.0
3
V
%
1
Output full-scale ratio
Output full-scale current
Output offset voltage
Glitch energy
9.0
9.6
10
1
mA
mV
pV•s
VOS
GE
When “0000000000” data input
ROUT=100 Ω, 1 Vp-p output
50
42
40
55
50
48
55
When 10 MHz
sin wave input
When 1 MHz
sin wave input
When 10 MHz
FCLK=50 MHz
FCLK=85 MHz
FCLK=50 MHz
FCLK=85 MHz
FCLK=50 MHz
40
50
Crosstalk
CT
dB
dB
SN ratio
SNR
IDD
58
9
Supply current
mA
sin wave output FCLK=85 MHz
VREF
Analog input resistance
Input capacitance
RIN
CI
CO
VIH
VIL
IIH
IIL
1
MΩ
pF
Output capacitance
125
pF
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
2.15
–5
Digital input voltage
Digital input current
V
0.85
5
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
µA
Setup time
ts
4
1
ns
ns
ns
ns
ns
Hold time
th
Propagation delay time
Rise time
tPD
tr
14
26.5
26.0
Fall time
tf
Full-scale voltage of channel
1
Full-scale output ratio =
–1 × 100 (%)
Average of the full-scale voltage of the channels
Electrical Characteristics Measurement Circuit
Analog Input Resistance
Measurement Circuit
+5.25V
}
Digital Input Current
AVDD, DVDD
A
CXD2309Q
AVSS, DVSS
V
—5—
CXD2309Q
Conversion Rate Measurement Circuit
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
AVSS
GO
42
43
44
10bit
COUNTER
with
200
AVSS
200
LATCH
OSCILLOSCOPE
VB
35
AVSS
BO
45
46
AVSS
200
0.1µ
DVSS
RCK
CLK
31
32
33
AVSS
47
38
37
36
AVSS
AVDD
50MHz
SQUARE
WAVE
GCK
BCK
VG
VREF
IREF
2V
0.1µ
3.3k
AVSS
Setup Time
Hold Time
Measurement Circuit
}
Glitch Energy
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
AVSS
GO
42
43
44
10bit
COUNTER
with
200
AVSS
LATCH
OSCILLOSCOPE
200
VB
35
AVSS
BO
45
46
0.1µ
AVSS
200
DELAY
CONTROLLER
DVSS
RCK
31
32
33
AVSS
47
38
AVSS
AVDD
CLK
GCK
BCK
VG
VREF
IREF
50MHz
SQUARE
WAVE
DELAY
CONTROLLER
2V
37
36
0.1µ
3.3k
AVSS
Crosstalk Measurement Circuit
DVDD
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
42
43
44
200
DIGITAL
WAVEFORM
GENERATOR
AVSS
GO
AVSS
200
SPECTRUM
ANALYZER
VB
35
AVSS
BO
45
46
0.1µ
AVSS
200
DVSS
RCK
31
32
33
AVSS
47
38
AVSS
AVDD
CLK
GCK
BCK
VG
VREF
IREF
50MHz
SQUARE
WAVE
2V
37
36
0.1µ
3.3k
AVSS
—6—
CXD2309Q
DC Characteristics Measurement Circuit
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
AVSS
GO
42
43
44
200
CONTROLLER
AVSS
200
DVM
VB
35
AVSS
BO
45
46
0.1µ
AVSS
200
DVSS
RCK
CLK
31
32
33
AVSS
47
38
37
36
AVSS
AVDD
50MHz
SQUARE
WAVE
GCK
BCK
VG
VREF
IREF
2V
0.1µ
3.3k
AVSS
Propagation Delay Time Measurement Circuit
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
42
43
44
10bit
COUNTER
with
200
AVSS
GO
AVSS
200
LATCH
OSCILLOSCOPE
VB
35
AVSS
BO
45
46
0.1µ
AVSS
200
DELAY
CONTROLLER
DVSS
RCK
31
32
33
AVSS
47
38
37
36
AVSS
AVDD
CLK
50MHz
SQUARE
WAVE
GCK
BCK
VG
VREF
IREF
DELAY
CONTROLLER
2V
0.1µ
3.3k
AVSS
SNR Measurement Circuit
R0 to R9
1 to 10
G0 to G9
11 to 20
B0 to B9
21 to 30
RO
ALL “1”
ALL “1”
42
43
44
200
DIGITAL
WAVEFORM
GENERATOR
AVSS
GO
AVSS
200
SPECTRUM
ANALYZER
VB
35
AVSS
BO
45
46
0.1µ
AVSS
200
DVSS
RCK
31
32
33
AVSS
47
38
AVSS
AVDD
CLK
GCK
BCK
VG
VREF
IREF
50MHz
SQUARE
WAVE
2V
37
0.1µ
3.3k
36
AVSS
—7—
CXD2309Q
Description of Operation
Timing Chart
tPW1
tPW0
1.5V
1.5V
CLK
ts th
ts th
ts th
DATA
100%
90%
D/A OUT
50%
tPD
10%
0%
tr
tf
I/O Correspondence Table (output full-scale voltage: 2.00 V)
Input code
Output voltage
MSB
LSB
1 1 1 1 1 1 1 1 1 1
2.0 V
:
1 0 0 0 0 0 0 0 0 0
:
1.0 V
0 0 0 0 0 0 0 0 0 0
0 V
—8—
CXD2309Q
Notes on Operation
• Selecting the Output Resistance
CXD2309Q is a current output type D/A converter. The output voltage can be obtained by connecting the
resistor ROUT to the current output pins RO, GO and BO.
Specifications:
Output full-scale voltage VFS = 1.8 to 2.0 [V]
Output full-scale current IFS = 9.0 to 10.0 [mA]
Calculate the output resistance from VFS = IFS × ROUT. Connect a resistance sixteen times the output
resistance to the reference current output pin IREF. In some cases, as this value may not exist, a similar
value can be used instead.
Note that the VFS will be the following.
VFS = VREF × 16ROUT/RIR
VREF is the voltage set at the reference voltage input pin VREF, ROUT is the resistor to be connected to the
current output pins RO, GO, BO and RIR is the resistor to be connected to the IREF. Power consumption can
be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data
setting time. Set the best values according to the purpose of use.
• Correlation between Data and Clock
For CXD2309Q to display the desired performance as a D/A converter, the data transmitted from outside and
the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in
“Electrical Characteristics”.
• Power supply, ground
Separate the analog and digital signals around the device to reduce noise effects. Bypass the power supply
pin to each ground with a 0.1 µF ceramics capacitor as near as possible to the pin for both the digital and
analog signals.
• Latch up
Analog and digital power supplies must be able to share the same power supply of the board. This is to
prevent latch up caused by potential difference between the two pins when the power is turned on.
• IREF
The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not
to attach to this pin because its output may become unstable.
• VG pin
It is recommended to use a 1 µF capacitor to improve the AC characteristics though the typical capacitance
value externally connected to the VG pin is 0.1 µF.
• Output full-scale voltage
For the applications using the RGB signal, the color balance may be broken up when the RO, GO and BO
output full-scale voltages are used with not adjustment.
—9—
CXD2309Q
Application Circuit
C
C
R2
Clock input
36 35 34 33 32 31 30 29 28 27 26 25
R3
R4
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
C
B ch input
C
C
LSB
MSB
R1
R1
R1
G ch input
10 11 12
1
2
3
4
5
6
7
8
9
R ch
input
AVDD
AVSS
DVDD
DVSS
• When the power supply (AVDD and DVDD) is 5.0 V.
• R1=200 Ω
• R2=3.3 kΩ
• R3=3.0 kΩ
• R4=2.0 kΩ
• C=0.1 µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—10—
CXD2309Q
Latch Up Prevention
The CX2309Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pin 39, 40 and 41) and DVDD (Pin 48), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
DVDD
AVDD
39 40 41
AVDD
48
DVDD
+5V
+5V
CXD2309Q
DIGITAL IC
C
C
AVSS
DVSS
34
43 45 47
AVSS
b. When analog and digital supplies are from a common source
(i)
DVDD
39 40 41
AVDD
48
DVDD
+5V
CXD2309Q
DIGITAL IC
C
C
AVSS
DVSS
34
43 45 47
AVSS
(ii)
DVDD
39 40 41
AVDD
48
DVDD
+5V
CXD2309Q
DIGITAL IC
C
C
AVSS
DVSS
34
43 45 47
AVSS
—11—
CXD2309Q
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
DVDD
AVDD
39 40 41
AVDD
48
DVDD
+5V
+5V
CXD2309Q
DIGITAL IC
C
C
AVSS
DVSS
34
43 45 47
AVSS
b. When analog and digital supplies are from common source
(i)
DVDD
AVDD
39 40 41
AVDD
48
DVDD
+5V
CXD2309Q
DIGITAL IC
C
C
AVSS
DVSS
34
43 45 47
AVSS
(ii)
DVDD
AVDD
39 40 41
AVDD
48
DVDD
+5V
CXD2309Q
DIGITAL IC
C
AVSS
DVSS
34
43 45 47
AVSS
—12—
CXD2309Q
Example of Representative Characteristics
2.0
100
1.0
50
0
1.0
2.0
0
100
200
Reference voltage VREF [V]
Output resistance ROUT [Ω]
Fig. 1. Reference voltage vs. Output full-scale voltage
Fig. 2. Output resistance vs. Glitch energy
70
60
50
40
1.95
sin wave output
1.90
∆V=0.02mV/°C
0
–25
0
25
Ambient temperature Ta [°C]
Fig. 3. Ambient temperature vs. Output full-scale voltage
50
75
1 2
5
10
20
30
40 42
Output frequency Fo [MHz]
Fig. 4. Output frequency vs. Supply current
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
—13—
CXD2309Q
fout=1MHz sin wave
IDD
fout=10MHz sin wave
IDD
60
50
40
30
20
10
60
50
40
30
20
10
IA [Analog]
IA [Analog]
ID [Digital]
ID [Digital]
50
20
85
20
50
85
Clock frequency FCLK [MHz]
Fig. 5. Clock frequency vs. Supply current
Clock frequency FCLK [MHz]
Fig. 6. Clock frequency vs. Supply current
60
50
40
30
20
10
0
–10
–20
sin wave output
0
1
2
5
10
Output frequency Fo [MHz]
Fig. 7. Output frequency vs. Cross talk
20
42
0
1
2
5
10
Output frequency Fo [MHz]
Fig. 8. Output frequency vs. Output level
20
50
(Including primary hold characteristics sinx/x)
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
—14—
CXD2309Q
50
40
30
1000
500
0
1
2
5
10
Output frequency Fo [MHz]
Fig. 9. Output frequency vs. SNR
20
50
–1
0
1
5
6
Input voltage [V]
500
1000
Fig. 10. Input terminal V-I characteristics
Standard Measurement Conditions
• AVDD=DVDD=5.0 V
• VREF=2.0 V
• FCLK=85 MHZ
• ROUT=200 Ω
• RIR=3.3 kΩ
• Ta=25 °C
—15—
CXD2309Q
Package Outline Unit : mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
0.15
36
25
24
37
+ 0.2
0.1 – 0.1
48
13
1
12
+ 0.15
0.3 – 0.1
0.8
0.24
M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER / PALLADIUM
PLATING
SONY CODE
EIAJ CODE
QFP-48P-L04
QFP048-P-1212
42/COPPER ALLOY
0.7g
JEDEC CODE
PACKAGE MASS
—16—
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