CXD2400 [SONY]
Timing Controller for CCD cameras; 时序控制器的CCD相机
| 型号： | CXD2400 |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Controller for CCD cameras |
| 文件： | 总22页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2400R
Timing Controller for CCD cameras
Description
48 pin LQFP (Plastic)
The CXD2400R is a timing controller for CCD
camera systems which use the ICX044/045,
ICX054/055 or other black/white CCD image
sensors.
Features
• Supports EIA/CCIR standards
• Electronic iris (electronic shutter) function
• Sync signal generation function
Applications
CCD cameras
• Supports external synchronization
• Supports non-interlacing
• Supports field/frame accumulation
• Oscillator frequency: 1212 fh
Structure
Silicon gate CMOS IC
(EIA: 19.0699MHz; CCIR: 18.9375MHz)
The characteristics of CCD image sensors are
guaranteed for field accumulation operation.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
Vss – 0.5 to +7.5
Vss – 0.5 to VDD + 0.5
Vss – 0.5 to VDD + 0.5
–20 to +75
V
V
Vo
V
•
•
Operating temperature Topr
Storage temperature Tstg
°C
°C
–55 to +150
Recommended Operating Conditions
• Supply voltage 5.0V ± 0.25
–20 to +75
V
•
Operating temperature
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93308D75-PS
CXD2400R
– 2 –
CXD2400R
Pin Configuration (Top View)
35
32
31 30 29 28 27 26 25
36
34 33
37
38
39
40
41
42
43
44
45
46
47
24 CVSS
23
EXT
SPUPV/ED0
HPLL
VR/SYNC
ESYNC
NIL
22 SPDNV/ED2
21 CVDD
20
19
18
17
Vreg
VDD1
LSEL
VDD2
VSS2
TEST
IRIN/ED1
16 PS
HCOMP
LCIN
15
14
13
IRENB
ENB
LCOUT
CKI 48
XSUB
1
2
3
4
5
6
7
8
9
10 11 12
Pin Description
Pin
Symbol
No.
I/O
—
Description
1
2
3
4
5
6
7
8
9
AVDD
H1
Power supply (for H1, H2)
2
O
O
H1 clock output for CCD horizontal register drive
H2 clock output for CCD horizontal register drive
GND (for H1, H2)
2
H2
AVss
RG
—
5
O
Reset gate pulse output
Vss1
XV2
XV1
XSG1
—
GND
O
O
O
O
O
O
O
XV2 clock output for CCD vertical register drive
XV1 clock output for CCD vertical register drive
CCD sensor charge readout pulse output
XV3 clock output for CCD vertical register drive
CCD sensor charge readout pulse output
XV4 clock output for CCD vertical register drive
CCD discharge pulse output
10 XV3
11 XSG2
12 XV4
13 XSUB
XSUB pulse output ON/OFF control (with pull-up resistance)
Low: XSUB pulse output stop; high: XSUB pulse output
14 ENB
15 IRENB
16 PS
I
I
I
Low: Electronic shutter mode; high: electronic iris mode (with pull-up resistance)
Electronic shutter speed input switchover (with pull-up resistance)
Low: Serial input; high: parallel input
1
17 IRIN/ED1
18 Vss2
I
Iris signal input/shutter speed setting; clock input in serial mode.
—
—
GND
19 VDD1
Power supply
– 3 –
CXD2400R
Pin
No.
Symbol
I/O
Description
20 Vreg
21 CVDD
—
—
Bias current supply for comparator
Power supply (for comparator)
SPDNV
/ED2
Shutter speed down reference voltage/
Shutter speed setting; data input in serial mode
1
22
23
I
SPUPV
/ED0
Shutter speed up reference voltage/
Shutter speed setting; strobe input in serial mode
1
I
24 CVss
25 SHP
26 SHD
27 EIA
—
GND (for comparator)
1
O
O
Precharge level sample-and-hold pulse
Data sample-and-hold pulse
1
I
Low: EIA; high: CCIR (with pull-down resistance)
Field accumulation/frame accumulation, odd field/even field switchover
(with pull-down resistance)
28 FL/FR
I
29 CLP2
30 CLP1
31 Vss3
32 FLD
O
O
Pulse output for clamp
Pulse output for clamp
—
O
O
O
O
O
O
I
GND
Field identification signal output High: odd field; low: even field
Vertical drive output
33 VD
34 HD
Horizontal drive output
35 SYNC
36 CBLK
37 EXT
Composite sync output
Composite blanking output
External sync/internal sync identification signal High: external sync; Low: internal sync
Horizontal drive signal input (with pull-up resistance)
38 HPLL
39 VR/SYNC
40 ESYNC
41 NIL
I
Vertical drive signal input/composite sync input (with pull-up resistance)
Low: SYNC sync or internal sync; high: VD/HD sync (with pull-down resistance)
Low: interlace mode; high: non-interlace mode (with pull-down resistance)
I
I
Line number selection pin (with pull-down resistance)
Low: EIA 262H/CCIR 312H; high: EIA 263H/CCIR 313H
42 LSEL
I
43 VDD2
44 TEST
45 HCOMP
46 LCIN
47 LCOUT
48 CKI
—
I
Power supply
Fixed to low level (with pull-down resistance)
H comparator output
4
O
2
I
O
I
LC oscillation (crystal oscillator) inverter input
LC oscillation (crystal oscillator) inverter output
Clock input
3
3
O
O
O
O
O
1 → POWERED BUFFER
2 → Hdriver Cell
3 → OSCILLATOR Cell
4 → Phase Comparater
5 → RGdriver Cell
I
I
I
1 → Comparater Input
2 → OSCILLATOR Cell
3 → Input cell with feedback resistance
– 4 –
CXD2400R
Electrical Characteristics
1) DC Characteristics
(VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item
Symbol
VDD
Conditions
Min.
4.75
Typ.
5.0
Max.
5.25
Unit
V
Supply voltage
0.7VDD
V
VIH1
Input voltage 1
(All input pins except those below)
0.3VDD
VDD
V
VIL1
Input voltage 2
(Pins 22, 23 only in electronic
iris mode)
VIN2
VIN3
2.0
V
V
Input voltage 3
(Pin 17 only in electronic
iris mode)
VSS
VDD
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5
VOH6
VOL6
RFB
IOH = –2mA
VDD – 0.8
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
Output voltage 1
(All output pins except those below)
IOL = 4mA
0.4
0.4
IOH = –4mA
IOL = 8mA
VDD – 0.8
VDD – 0.8
VDD – 0.8
VDD/2
Output voltage 2
(Pins 25, 26)
IOH = –8mA
IOL = 8mA
Output voltage 3
(Pin 5)
0.4
ICH = –20mA
ICL = 20mA
IOH = –3mA
IOL = 3mA
Output voltage 4
(Pins 2, 3)
0.4
Output voltage 5
(Pin 47)
VDD/2
IOH = –4mA
IOL = 4mA
VDD – 0.8
Output voltage 6
(Pin 45)
0.4
2.5M
75k
VIN = Vss or VDD
VIL = 0V
250k
25k
1M
50k
50k
Feedback resistance
Pull-up resistance
RPU
RPD
VIH = VDD
25k
75k
Pull-down resistance
VDD = 5V
IDD
ICX054AL in normal
operating state
36
mA
Current consumption
Power consumption: 180mW typ., ICX054AL load (in normal operating state)
2) Input/output capacitance
Item
(VDD = V1 = 0V, fM = 1MHz)
Symbol Min.
Typ.
Max.
9
Unit
pF
Input pin capacitance
Output pin capacitance
CIN
COUT
11
pF
Input/output pin capacitance CI/O
11
pF
– 5 –
CXD2400R
3) Comparator characteristics
Item
(VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Symbol Min.
Typ.
Max.
50
Unit
mV
mV
Input offest voltage
Indefinite region
VOS
Vf
± 10
Note) 1. Input offset voltage and indefinite region
5.0V
Input offset voltage and indefintie region are
existed in the comparator which builds in this IC
as shown right figure. Note that this when
designing external circuit.
Indefinite region
10mV
10mV
Pins 22 and 23
(SPDNV and SPUPV)
50mV
50mV
Input offset voltage
Input offset voltage
2. Pins 22 and 23 for electronic iris mode
Use it in this state of Pin 22 (SPDNV) > Pin 23
(SPUPV).
10mV
10mV
Indefinite region
GND
Mode Control
Symbol
ENB
Pin
No.
I/O
Low
High
Remarks
14
15
I
I
XSUB stop
XSUB output
Electronic iris
IRENB
PS
Electronic shutter
Valid only when ENB is high.
Valid only when ENB is
high and IRENB is low.
16
I
Serial input
Parallel input
IRIN/ED1
SPDNV/ED2
SPUPV/ED0
EIA
17
22
23
27
I
I
I
I
Electronic iris control signal input pin
(IRENB = high)
Shutter speed setting pin
(IRENB = Low)
Valid only when ENB is
high.
EIA
CCIR
Valid only when NIL is high
and EXT is low.
Odd field
Even field
Frame accumulation
VD/HD sync
FL/FR
28
I
Field accumulation
All other modes.
SYNC sync
Internal sync
ESYNC
HPLL
40
38
I
I
Internal sync
SYNC sync
VD/HD sync
:
:
:
HPLL (Open)
VR/SYNC (Open)
HPLL (Open)
VR/SYNC (SYNC input)
HPLL (HD input)
VR/SYNC (VD input)
VR/SYNC
39
I
NIL
41
42
I
I
Interlace
Non-interlace
Valid only when EXT is low.
EIA
:
:
262H
312H
EIA
:
:
263H
313H
Valid only when EXT is low
and NIL is high.
LSEL
CCIR
CCIR
Switchover between
internal and external sync
is autonatically identified
by input state at Pins 38,
39 and 40.
EXT
37
O
Internal sync
External sync
The characteristics of CCD image sensors are quaranteed for field acccumulation operation.
– 6 –
CXD2400R
Mode Tables
1) Internal sync mode
HPLL pin (Pin 38)
: Open
VR/SYNC pin (Pin 39) : Open
ESYNC pin (Pin 40)
: Open
Non-interlace
Even field
Interlace
2
2
Odd field
Field
readout
Frame
readout
Field
readout
Frame
readout
Field
readout
Frame
readout
3
3
3
1
XSUB pulse OFF
O
O
O
O
O
O
O
O
O
×
×
×
O
O
O
×
×
×
Electronic shutter ON
Electronic iris ON
1
EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
O: Can be used.
×: Cannot be used.
The characteristics of CCD image sensors are guaranteed for field accumulation operation.
2
3
Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
2) SYNC sync (external sync) mode
HPLL pin (Pin 38)
: Open
VR/SYNC pin (Pin 39) : SYNC input
ESYNC pin (Pin 40) : Open
Non-interlace
Interlace
2
2
Odd field
Even field
Field
readout
Frame
readout
Field
readout
Frame
readout
Field
readout
Frame
readout
3
3
3
1
O
O
O
O
O
O
×
×
×
×
×
×
×
×
×
×
×
×
XSUB pulse OFF
Electronic shutter ON
Electronic iris ON
1
EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
O: Can be used.
×: Cannot be used.
2
3
Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
The characteristics of CCD image sensors are guaranteed for field accumulation operation.
– 7 –
CXD2400R
3) VD/HD sync (external sync) mode
HPLL pin (Pin 38)
VR/SYNC pin (Pin 39) : VD input
ESYNC pin (Pin 40) : VDD (power supply)
: HD input
VD input with normal cycle
VD input with
longer cycle than
normal interlace
Non-interlace
Interlace
2
2
Odd field
Field
readout readout
Even field
Field
Frame
readout readout
Frame
Field
Frame
Field
Frame
3
3
3
3
readout readout
readout readout
1
XSUB pulse OFF
Serial input
O
O
O
O
O
O
×
×
O
O
×
×
O
×
×
×
electronic shutter ON
Parallel input
electronic shutter ON
O
O
O
O
∆
×
×
∆
×
×
×
×
×
×
Electronic iris ON
O
O
1
EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
O: Can be used.
∆: The shutter speed may change
2
3
Line number is 262H or 263H for EIA and 312H or 313H for CCIR.
The characteristics of CCD image sensors are guaranteed for field
accumulation operation.
from its value in the interlace mode.
×: Cannot be used.
Note) Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with
longer cycle than normal are input to the VR/SYNC pin.
– 8 –
CXD2400R
Electronic Shutter/Iris
By setting ENB pin (Pin 14) high, the XSUB pulse is output for a specific period to activate the electronic
shutter and electronic iris.
1) Electronic iris (IRENB = high, PS = any level)
Symbol
IRIN/ED1
Pin No.
17
Function
Iris signal input
SPDNV/ED2
SPUPV/ED0
22
Shutter speed down reference voltage
Shutter speed up reference voltage
23
2) Parallel input electronic shutter (IRENB = low, PS = high)
Symbol
SPUPV/ED0
IRIN/ED1
Pin No.
23
Mode
H
H
H
L
H
H
H
L
L
L
H
H
L
L
H
L
H
L
L
L
L
L
17
SPDNV/ED2
22
H
H
EIA:
1/100
CCIR:
1/120
1/250
1/500
1/1000 1/2000 1/5000 1/10000 1/100000
Shutter speed
– 9 –
CXD2400R
3) Serial input electonic shutter (IRENB = low, PS = high)
Serial input data format
D7 D6
D5
D4
D3 D2
D1
D0
SPDNV/ED2
IRIN/ED1
SPUPV/ED0
The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise.
Typical shutter speed
EIA
CCIR
shutter speed
Load value
00h
shutter speed
Load value
00h
1/100000
1/10000
1/5000
1/2000
1/1000
1/500
1/80000
1/10000
1/5000
1/2000
1/1000
1/500
4Eh
4Ah
6Ah
65h
87h
82h
9Ch
97h
ACh
A7h
CAh
1/250
C5h
1/250
EDh
1/100
E1h
1/120
AC Characteristics
SPDNV/ED2
ts2
th2
IRIN/ED1
ts1
ts0
SPUPV/ED0
tw0
Symbol
Min.
20ns
20ns
20ns
20ns
20ns
Max.
—
ts2
th2
ts1
tw0
ts0
SPDNV (ED2) setup time for IRIN (ED1) rise
SPDNV (ED2) hold time for IRIN (ED1) rise
IRIN (ED1) setup time for SPUPV (ED0) rise
SPUPV (ED0) pulse width
—
—
50µs
—
SPUPV (ED0) setup time for IRIN (ED1) rise
– 10 –
CXD2400R
External Synchronization
1) External/internal sync selection
External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and
ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations.
VR/SYNC pin: SYNC signal VR/SYNC pin: VD signal
VR/SYNC pin: Open
HPLL pin: Open
Input pattern
HPLL pin: Open
HPLL pin: HD signal
ESYNC pin: Open
ESYNC pin: VDD (power supply) ESYNC pin: Open
EXT pin output
Sync state
High
High
Low
External sync
External sync
Internal sync
Note) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal.
The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the
signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for
improving the oscillation accuracy for internal synchronization.
2) Modes for external synchronization
Field accumulation
O
Frame accumulation
O
Interlace
×
×
SYNC
synchronization
(Cannot be accomplished
since interlace operation
is the prior condition.)
(Cannot be accomplished
since interlace operation
is the prior condition.)
Non-interlace
Interlace
O
O
VD/HD
synchronization
×
Non-interlace
O
(Not practically applicable since
the sensitivity is halved.)
The characteristics of CCD image sensors are guaranteed for field accumulation operation.
3) Reset operation
SYNC synchronization
The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA, V reset is
performed so that the VDO pulse falls at the count of 259H (262.5 – 3.5H) from the fall of the VR1 pulse. For
CCIR, it is reset in such a way that the VDO pulse falls at the count of 309H (312.5 – 3.5H). For these reasons,
it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard.
VD/HD synchronization
V reset is performed so that the VDO pulse falls 1H later after detecting the fall of the VD (VDR) pulse supplied
externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference
between the VDR pulse and HDO pulse which is locked horizontally at PLL circuit identifies whether the field is
odd or even. (VDR must have a pulse width of 2H or more.)
– 11 –
CXD2400R
– 12 –
CXD2400R
– 13 –
CXD2400R
– 14 –
CXD2400R
– 15 –
CXD2400R
– 16 –
CXD2400R
– 17 –
CXD2400R
– 18 –
CXD2400R
TG+SG Timing Chart
ICX054AL
52.4ns (EIA)
52.8ns (CCIR)
CK
H1
26.2ns (EIA)
26.4ns (CCIR)
RG
CCD OUT
SHP
SHD
– 19 –
CXD2400R
– 20 –
CXD2400R
– 21 –
CXD2400R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
36
25
24
37
48
A
13
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
+ 0.08
1.5 – 0.1
0.18 – 0.03
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
LQFP-48P-L01
SONY CODE
EIAJ CODE
PLATING
LQFP048-P-0707
42/COPPER ALLOY
0.2g
JEDEC CODE
PACKAGE MASS
– 22 –
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