CXD2450R [SONY]
Timing Generator for Progressive Scan CCD Image Sensor; 时序发生器逐行扫描CCD图像传感器
| 型号： | CXD2450R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for Progressive Scan CCD Image Sensor |
| 文件： | 总30页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2450R
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2450R is a timing generator IC which
generates the timing pulses for performing progressive
scan readout for digital still camera and personal
computer image input applications using the
ICX098AK CCD image sensor.
48 pin LQFP (Plastic)
This chip has a built-in vertical driver.
Features
• Base oscillation frequency 36.81MHz (2340fH)
• Monitoring readout allowed
• High-speed/low-speed electronic shutter function
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
• Signal processor IC system clock generation
1170fH, 780fH
Absolute Maximum Ratings
• Supply voltage
VDD
VM
VH
VL
VSS – 0.5 to +7.0
VL – 0.5 to +26.0
VL – 0.5 to +26.0
VL – 0.5 to +26.0
VSS – 0.5 to VDD + 0.5
V
V
V
V
V
V
• Vertical/horizontal sync (SSG) timing generation
• Input voltage
VI
• Output voltage
VO VSS – 0.5 to VDD + 0.5
Applications
• Digital still cameras
• Personal computer image input
• Operating temperature
Topr
• Storage temperature
Tstg
–20 to +75
°C
°C
–55 to +150
Structure
Silicon gate CMOS IC
Recommended Operating Conditions
• Supply voltage
Pin Configuration
VDDa, VDDb, VDDc, VDDd 3.0 to 3.6
V
V
V
V
VM
VH
VL
0.0
14.5 to 15.5
–5.0 to –6.0
35
32
31 30 29 28 27 26 25
36
34 33
• Operating temperature
37
38
DSGAT
MCK
24 VDD5
23
Topr
–20 to +75
°C
3/2MCK
VM 39
40
22 1/2MCK
21
Applicable CCD Image Sensors
ICX098AK (Type 1/4 CCD)
V1
PBLK
V3 41
20 VSS4
19 XRS
V2a 42
43
44
45
46
18
17
16
15
VH
V2b
XSHD
XSHP
VSUB
VL
VDD4
XCLPDM
OSCO 47
48
14 VDD3
13
OSCI
H2
1
2
3
4
5
6
7
8
9
10 11 12
Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97819A9X
CXD2450R
Block Diagram
13
18 19
14 12
11
8
9
10 16 17
20
OSCI
48
OSCO
47
21
PBLK
XCLPDM
XCLPOB
ID
15
7
3MCK
1
1/3
Pulse Generator
4
1/2
23
22
3/2MCK
1/2MCK
3
WEN
1/2
CLD 35
HRI
differential
MCK
38
40 V1
42 V2a
Latch
V2b
V3
44
41
6
VDD1
VDD5
VDD6
24
26
45 VSUB
43 VH
Latch
SSG
V Driver
VM
39
1/390
46 VL
2
VSS1
VSS5
1/2
36
Register
1/525
31
37
5
27 28 29 30
25
32
33
34
– 2 –
CXD2450R
Pin Description
Pin
Symbol
No.
I/O
Description
1
2
3MCK
Vss1
I
Internal main clock. (2340fH)
GND
—
Memory write timing.
Stop control possible using the serial interface data.
3
4
WEN
ID
O
O
Vertical direction line identification pulse output.
Stop control possible using the serial interface data.
5
6
TEST
I
IC test pin; normally fixed to GND. (With pull-down resistor)
3.3V power supply. (Power supply for common logic block)
VDD1
—
CCD optical black signal clamp pulse output.
Stop control possible using the serial interface data.
7
XCLPOB
O
8
VDD2
RG
—
O
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output. (780fH)
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
Vss2
Vss3
H1
—
—
O
GND
CCD horizontal register clock output. (780fH)
CCD horizontal register clock output. (780fH)
3.3V power supply. (Power supply for H1/H2)
CCD dummy signal clamp pulse output.
3.3V power supply. (Power supply for CDS system)
CCD precharge level sample-and-hold pulse output. (780fH)
CCD data level sample-and-hold pulse output. (780fH)
H2
O
VDD3
XCLPDM
VDD4
XSHP
XSHD
XRS
—
O
—
O
O
O
Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH)
GND
Vss4
PBLK
—
O
Pulse output for horizontal and vertical blanking interval pulse cleaning.
Horizontal direction pixel identification pulse output.
Stop control possible using the serial interface data.
22
1/2MCK
O
System clock output for signal processing IC. (1170fH)
Stop control possible using the serial interface data.
23
24
25
3/2MCK
VDD5
O
—
I
3.3V power supply. (Power supply for common logic block)
Internal system reset input. High: Normal status, Low: Reset status
Always input one reset pulse after power-on.
RST
26
27
28
29
VDD6
SSI
—
3.3V power supply. (Power supply for common logic block)
Serial interface data input for internal mode settings.
Serial interface clock input for internal mode settings.
Serial interface strobe input for internal mode settings.
I
I
I
SSK
SEN
CHKSUM enable. (With pull-down resistor)
High: Sum check invalid, Low: Sum check valid
30
EBCKSM
I
– 3 –
CXD2450R
Pin
No.
Symbol
FRO
I/O
O
Description
Vertical sync signal output.
31
32
Stop control possible using the serial interface data.
Horizontal sync signal output.
HRO
O
Stop control possible using the serial interface data.
33
34
HRI
FRI
I
I
Horizontal sync signal input.
Vertical sync signal input.
Clock output for analog/digital conversion IC. (780fH)
Phase adjustment in 60° units possible using the serial interface data.
35
36
CLD
O
VSS5
—
GND
Control input used to stop drive pulse generation for CCD image sensor,
37
DSGAT
I
sample-and-hold IC and analog/digital conversion IC. High:Normal status,Low:Stop status
Controlled pulse can be changed using the serial interface data.
38
39
40
41
42
43
44
45
46
47
48
MCK
VM
O
—
O
O
O
—
O
O
—
O
I
System clock output for signal processor IC. (780fH)
GND (GND for vertical driver)
V1
CCD vertical register clock output. (Binary output)
CCD vertical register clock output. (Binary output)
CCD vertical register clock output. (Ternary output)
15.0V system power supply. (Power supply for vertical driver)
CCD vertical register clock output. (Ternary output)
CCD electronic shutter pulse output.
V3
V2a
VH
V2b
VSUB
VL
–5.5V system power supply. (Power supply for vertical driver)
Inverter output for oscillation.
OSCO
OSCI
Inverter input for oscillation.
– 4 –
CXD2450R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
VDDa
VDDb
VDDc
VDDd
VH
Conditions
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Supply voltage 5
Supply voltage 6
Supply voltage 7
VDD2
V
V
V
V
V
V
V
3.3
3.6
VDD3
3.0
3.3
3.6
VDD4
3.0
VDD1, VDD5, VDD6
3.3
3.6
3.0
VH
VM
VL
15.0
0.0
15.5
—
14.5
—
VM
VL
–5.5
–5.0
–6.0
0.8VDDd
RST, DSGAT,
SSI, SSK, SEN,
FRI, HRI
VIH1
V
V
1
Input voltage 1
0.2VDDd
VIL1
1 ,
2
0.8VDDd
0.7VDDd
VIH2
VIL2
V
V
V
V
V
V
V
V
EBCKSM
TEST
Input voltage 2
0.2VDDd
0.3VDDd
0.4
VIH3
VIL3
2
Input voltage 3
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
VOH1
VOL1
VOH2
VOL2
VDDa – 0.8
Output voltage 1 RG
VDDb – 0.8
Output voltage 2 H1, H2
0.4
VDDc – 0.8
XSHP, XSHD,
Output voltage 3 XRS, PBLK,
XCLPDM
VOH3
VOL3
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
V
V
0.4
V
V
V
V
DDd – 0.8
DDd – 0.8
DDd – 0.8
DDd – 0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VOH4
VOL4
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
VOH8
VOL8
VOM9
VOL9
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.6mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –4.0mA
Pull-in current where IOL = 5.4mA
Feed current where IOM = –5.0mA
Pull-in current where IOL = 10.0mA
3/2MCK, MCK,
Output voltage 4
CLD
0.4
0.4
Output voltage 5 1/2MCK
XCLPOB, ID,
Output voltage 6
WEN
0.4
Output voltage 7 FRO, HRO
Output voltage 8 VSUB
Output voltage 9 V1, V3
0.4
VH – 0.25
VL + 0.25
VL + 0.25
VM + 0.25
VL + 0.25
VM – 0.25
VH – 0.25
VOH10 Feed current where IOH = –7.2mA
VOM101 Pull-in current where IOM = 5.0mA
Output voltage
V2a, V2b
10
VOM102 Feed current where IOM = –5.0mA VM – 0.25
VOL10
Pull-in current where IOL = 10.0mA
1
These input pins do not have protective diodes on the internal power supply side.
These input pins have internal pull-down resistors.
The above table indicates the condition for 3.3V drive of low voltage drive blocks.
2
3
– 5 –
CXD2450R
(Within the recommended operating conditions)
Inverter I/O Characteristics for Oscillation
Item
Pins
OSCI
Symbol
LVth
VIH
Conditions
Min.
Typ.
Max.
Unit
V
Logical Vth
VDDd/2
0.7VDDd
V
Input voltage
OSCI
VIL
0.3VDDd
V
Feed current where
IOH = –6.0mA
VOH
VOL
VDDd/2
V
OSCO
Output voltage
Pull-in current where
IOL = 6.0mA
VDDd/2
5M
V
Ω
Feedback resistor OSCI, OSCO RFB
VIN = VDDd or Vss
500k
20
2M
Oscillation
OSCI, OSCO f
frequency
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Unit
V
Item
Pins
Symbol
LVth
VIH
Conditions
Min.
0.7VDDd
0.3
Typ.
Max.
Logical Vth
VDDd/2
V
Input voltage
3MCK
V
VIL
0.3VDDd
Vp-p
Input amplification
VIN
fmax 50MHz sine wave
1
Input voltage is the input voltage characteristics for direct input from an external source. Input amplification
is the input amplification characteristics in the case of input through capacitor.
(VH = 15.0V, VM = GND, VL = –5.5V)
Switching Characteristics
Item Symbol
Unit
ns
ns
ns
ns
ns
ns
V
Conditions
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
150
150
50
Max.
300
300
100
200
300
100
1.0
TTLM
TTMH
TTLH
TTML
TTHM
TTHL
VCLH
VCLL
VCMH
VCML
VL to VM
VM to VH
VL to VH
VM to VL
VH to VM
VH to VL
Rise time
100
150
50
Fall time
—
V
—
1.0
Output noise
voltage
V
—
1.0
V
—
1.0
1
The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2
For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
– 6 –
CXD2450R
Switching Waveforms
TTMH
90%
TTHM
90%
VH
10%
10%
TTLM
90%
TTML
90%
V2a (V2b)
VM
VL
10%
10%
TTLM
90%
TTML
90%
VM
VL
V1 (V3)
10%
10%
TTLH
TTHL
VH
90%
90%
VSUB
10%
10%
VL
Waveform Noise
VH
VCMH
VCML
VCLH
VCLL
VL
– 7 –
CXD2450R
Measurement Circuit
Serial interface data
+3.3V
–5.5V
+15.0V
36
25
24
37
C1
R1
R1
C2
C2
C2
C2
C6
C6
C6
C1
R1
C1
R1
C1
R2
C3
C5
48
13
1
12
3MCK
C4
C5
R1: 68W
R2: 15W
C1: 450pF
C2: 2200pF
C3: 500pF
C4: 30pF
C5: 100pF
C6: 10pF
– 8 –
CXD2450R
AC Characteristics
1) AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
ts1
SSK
0.2VDDd
th1
ts2
SEN
SEN
0.2VDDd
ts3
0.8VDDd
th2
(Within the recommended operating conditions)
Symbol
ts1
Definition
Min.
20
Typ.
Max. Unit
ns
ns
ns
ns
ns
SSI setup time, activated by the rising edge of SSK
SSI hold time, activated by the rising edge of SSK
SSK setup time, activated by the rising edge of SEN
SSK hold time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SSK
20
th1
20
ts2
20
th2
20
ts3
2) Serial interface clock internal loading characteristics
Example: During recording drive mode
FRI
HRI
V2a
Enlarged view
HRI
0.2VDDd
V2a
ts4
th4
0.8VDDd
SEN
0.2VDDd
Note) Be sure to maintain a constantly high SEN logic level near the falling edge of HRI immediately before
the readout period.
(Within the recommended operating conditions)
Symbol
ts4
Definition
Min.
Typ.
Max. Unit
ns
ns
SEN setup time, activated by the falling edge of HRI
SEN hold time, activated by the falling edge of HRI
0
0
th4
– 9 –
CXD2450R
3) Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2450R at the timing shown in 2) above. However, one
exception to this is when the data such as SSGSEL and STB is loaded to the CXD2450R and controlled at the
rising edge of SEN. For STB, see control data D62 to D63 STB in "Description of Operation".
0.8VDDd
SEN
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
5
Typ.
Max. Unit
ns
100
tpdPULSE
Output signal delay, activated by the rising edge of SEN
4) RST loading characteristics
0.8VDDd
RST
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
Definition
Min.
35
Typ.
Max. Unit
ns
tw1
RST pulse width
5) Phase discrimination characteristics using FRI and HRI input
When the HRI logic level is low tpd1 after
the falling edge of FRI
When the HRI logic level is high tpd1 after
the falling edge of FRI
FRI
FRI
0.2VDDd
0.2VDDd
tpd1
HRI
tpd1
HRI
The field is discriminated as an ODD field
.
The field is discriminated as an EVEN field
.
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Typ.
Max. Unit
1300
ns
1100
Field discrimination clock phase, activated by the falling edge of FRI
– 10 –
CXD2450R
6) FRI and HRI loading characteristics
0.2VDDd
FRI, HRI
MCK
0.2VDDd
ts5
0.8VDDd
th5
MCK load capacitance = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Miin.
Typ.
Min.
Unit
ns
FRI and HRI setup time, activated by the rising edge of MCK
FRI and HRI hold time, activated by the rising edge of MCK
ts5
th5
10
0
ns
7) Output timing characteristics using DSGAT
DSGAT
0.2VDDd
H1, H2, RG, XSHP, XSHD, XRS,
PBLK, XCLPDM, XCLPOB, CLD
0.2VDDd
tpDSGAT
However, V2a, V2b and VSUB are fixed to the voltage level applied to the VH pin, and V1 and V3 are fixed to
the voltage level applied to the VM pin.
H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF,
XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
Definition
Miin.
Typ.
Min.
100
Unit
ns
Time until the above outputs go low after the fall of DSGAT
tpDSGAT
8) Output variation characteristics
0.8VDDd
MCK
WEN, ID
tpd2
WEN and ID load capacitance = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Miin.
20
Typ.
Min.
40
Unit
ns
tpd2
Time until the above outputs change after the rise of MCK
– 11 –
CXD2450R
9) H1 and RG waveform characteristics
0.9VDDb
0.9VDDb
H1
0.1VDDb
0.9VDDa
0.1VDDb
trH1
tfH1
0.9VDDa
RG
0.1VDDa
trRG
0.1VDDa
tfRG
VDDb = 3.3V, Topr = 25°C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF
(Within the recommended operating conditions)
Symbol
trH1
Definition
Min.
Typ.
10
10
3
Max. Unit
H1 rise time
H1 fall time
RG rise time
RG fall time
ns
ns
ns
ns
tfH1
trRG
tfRG
3
(Within the recommended operating conditions)
Min. Typ. Max. Unit
10) I/O pin capacitance
Symbol
Definition
CIN
9
pF
pF
pF
Input pin capacitance
Output pin capacitance
I/O pin capacitance
COUT
CI/O
11
11
– 12 –
CXD2450R
Description of Operation
Pulses output from the CXD2450R are controlled by the RST and DSGAT pins and by the serial interface data
shown below. The details of control by the serial interface data and a description of operation are as follows.
SSI
SSK
SEN
00 01 02 03 04 05 06 07 08 09 10 11
58 59 60 61 62 63 64 65 66 67 68 69 70 71
The CXD2450R basically loads and reflects the serial interface data sent in the above format in the readout
portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which V2a and
V2b take the ternary level.
There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these
data are distinguished by referring to the former as control data and the latter as adjustment data.
An example of the initialization data for the CXD2450R control data is shown below. This data is based on the
Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin
initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the
3/2MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71
CHKSUM is valid.
MSB
LSB
D71 D70 D69 D68 D67 D66 D65 D64 D63 D62 D61 D60 D59 D58 D57 D56
1
0
1
0
1
1
0
1
0
0
0
0
0
0
1
0
MSB
LSB
D55 D54 D53 D52 D51 D50 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSB
LSB
D07 D06 D05 D04 D03 D02 D01 D00
1
0
0
0
0
0
0
1
The adjustment data does not normally need to be set. However, when adjustment is difficult due to the
system configuration or for other reasons, the data considered most appropriate at that time should be set as
the initialization data.
– 13 –
CXD2450R
Control Data
Data
Symbol
Function
Chip switching
Data = 0
Data = 1
When a reset
All 0
D00
to
D07
CHIP
See D00 to D07 CHIP.
See D08 to D15 CTGRY.
D08
to
D15
CTGRY
SMD
Category switching
All 0
All 0
All 0
All 0
D16
to
D17
See D16 to D35
Electronic shutter mode.
Electronic shutter mode setting
D18
to
D25
Electronic shutter vertical interval
setting
See D16 to D35
Electronic shutter mode.
Shut.FRM
Shut.HD
—
D26
to
D35
Electronic shutter horizontal interval
setting
See D16 to D35
Electronic shutter mode.
D36
to
D47
—
OFF
—
—
ON
—
—
All 0
0
D48 EXPOSE
Recording exposure setting switching
—
D49
to
—
All 0
D50
Monitoring
OFF
Recording
ON
D51 PSMT
Drive mode switching
0
0
0
0
0
0
0
0
0
D52 SSGSEL
D53 WENSEL
D54 CLPSEL
D55 IDSEL
Internal SSG operation switching
WEN pulse operation switching
XCLPOB pulse operation switching
ID pulse operation switching
ON
OFF
ON
OFF
OFF
ON
OFF
ON
D56 HMCKSEL
D57 TMCKSEL
D58 HMCKREV
D59 TMCKREV
D60
1/2MCK pulse operation switching
3/2MCK pulse operation switching
1/2MCK pulse reset polarity switching
3/2MCK pulse reset polarity switching
ON
OFF
Positive polarity Negative polarity
Negative polarity Positive polarity
to
D61
DSG
Pulse generation control
IC pin status control
Check sum bit
All 0
All 0
All 0
See D60 to D61 DSG table.
See D62 to D63 STB table.
See D64 to D71 CHKSUM.
D62
to
D63
STB
D64
to
D71
CHKSUM
– 14 –
CXD2450R
Detailed Description of Each Data
D00 to D07 CHIP
The serial interface data is loaded to the CXD2450R when D00 and D07 are 1. However, this assumes that
either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high.
MSB
LSB
Function
Loading to the CXD2450R
D07 D06 D05 D04 D03 D02 D01 D00
1
0
0
0
0
0
0
1
Note that when SEN is shared with other ICs and identification is performed using CHIP-ID, the CXD2450R
data must be positioned immediately before the load timing, that is to say at the very end.
D08 to D15 CTGRY
Of the data provided to the CXD2450R by the serial interface, the CXD2450R loads D16 and subsequent
data to the control data register side when D08 is 0, and to the adjustment data register side when D08 is 1.
However, this assumes that the CXD2450R is selected by CHIP and that either the EBCKSM pin is low and
D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high.
MSB
LSB
Function
D15 D14 D13 D12 D11 D10 D09 D08
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Loading to the control data register side
Loading to the adjustment data register side
Note that the CXD2450R cannot apply both categories simultaneously during the same vertical interval. Also,
care should be taken as the data is overwritten even if the same category is applied.
D16 to D35 Electronic shutter mode
The CXD2450R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the
data from D18 to D35 differs according to the mode, and is explained in detail below.
D17
X
D16
0
Description of operation
VSUB stopped mode
0
1
High-speed/low-speed shutter mode
HTSG control mode
1
1
The electronic shutter data is expressed as shown in the table below using Shut.HD as an example.
MSB
LSB
D35 D34 D33 D32 D31 D30 D29 D28 D27 D26
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
1
C
3
Shut.HD is expressed as 1C3h .
[VSUB stopped mode]
During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60 s during monitoring drive
mode, and 1/30 s during recording drive mode.
– 15 –
CXD2450R
[High-speed/low-speed shutter mode]
During this mode, the data has the following meanings.
Symbol
Shut.FRM
Shut.HD
Data
Description
D18 to D25 Shutter speed data (number of vertical intervals) specification
D26 to D35 Shutter speed data (number of horizontal intervals) specification
The CXD2450R does not distinguish between the high-speed shutter and low-speed shutter modes. The
interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time,
Shut.FRM controls the ternary level output at V2a and V2b, and Shut.HD controls the VSUB output.
Concretely, when specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed
shutter, or in other words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until
this interval is finished.
However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode
is monitoring drive mode and 1/30s units during recording mode. For monitoring drive mode, care should be
taken as the Shut.HD value has an offset. This is so that the CXD2450R can obtain basically the same
exposure time for the same Shut.HD value during high-speed shutter independent of the drive mode.
Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: µs)
Monitoring drive mode:
T = Shut.FRM 1.66834 104 + {(20Ch – Shut.HD) 780 + 447} 81.5 10–3 (000h ≤ Shut.HD ≤ 20Ch)
FRI
V2a
Shut.FRM
Shut.HD-106h
VSUB
SMD
Shut. FRM
Shut. HD
WEN
01
01
01
00h
01h
00h
1A6h
1DDh
1A6h
During monitoring drive mode/low-speed shutter mode
Recording drive mode:
T = Shut.FRM 3.33667 104 + {(20Ch – Shut.HD) 780 + 447} 81.5 10–3 (000h ≤ Shut.HD ≤ 20Ch)
FRI
V2a
Shut.HD
Shut.FRM
VSUB
SMD
Shut. FRM
Shut. HD
WEN
01
01
01h
00h
1DDh
1A6h
During recording drive mode/low-speed shutter mode
– 16 –
CXD2450R
Electronic shutter speed table [Shut.FRM/Shut.HD]
Shut.FRM Shut.HD Shutter speed (s)
Shut.FRM
00h
Calculation results (s)
1/27450
1/10000
1/4403
1/2077
1/1010
1/498
Shut.HD Shutter speed (s) Calculation results (s)
1
00h
00h
00h
00h
00h
00h
00h
00h
00h
20Ch
20Bh
209h
205h
1FDh
1EDh
1CEh
18Fh
16Fh
1/27000
1/10000
1/4500
1/2000
1/1000
1/500
107h
20Ch
1D8h
20Ch
18Bh
109h
0D2h
083h
000h
1/60
1/60
1/50
1/30
1/60
1/60
1/50
1/30
1/8
2
2
2
01h
01h
02h
2
07h
1/8
1/6
2
09h
1/6
3
3
3
1/250
1/251
00h
1/50
1/40
1/30
1/50
1/40
1/30
1/125
1/125
00h
1/100
1/100
00h
1
2
3
One VSUB pulse is generated for odd fields and two for even fields.
These are the settings during monitoring drive mode.
These are the settings during recording drive mode.
Note) Input prohibited data:
Monitoring drive mode
000h to 106h
Recording drive mode and monitoring drive mode 20Dh to 3FFh
[HTSG control mode]
During this mode, the data from D18 to D35 is invalid.
The ternary level outputs at V2a and V2b are controlled, and the shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical interval to the vertical period during which V2a and V2b
are stopped as shown in the figure.
FRI
V2a
VSUB
Vck
SMD
WEN
01
11
01
During HTSG control mode
– 17 –
CXD2450R
D48 EXPOSE
0: No operation
1: VSUB for recording exposure is generated.
This control specification is such that one VSUB pulse is always generated during the horizontal interval
immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This
mode is closely related to D51 PSMT, so see D51 regarding the control.
D51 PSMT
0: Driving is controlled in accordance with monitoring drive mode under the assumption that the vertical/
horizontal sync signals are input.
1: Driving is controlled in accordance with recording drive mode under the assumption that the vertical/
horizontal sync signals are input.
See the timing charts for the vertical/horizontal sync signals in accordance with each mode.
Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be
cleaned.
Concretely, this operation is supported by generating VSUB, but the CXD2450R facilitates this control by
using D48 EXPOSE. (See the figure.)
FRI
V2a
VSUB
Exposure time
WEN
SMD
EXPOSE
PSMT
00
00
00
0
00
0
0
1
0
0
1
0
Mode
Monitoring
Recording
Monitoring
Monitoring
Image of switching from monitoring drive mode to recording drive mode
D52 SSGSEL
0: Internal SSG functions are stopped.
1: Internal SSG functions operate, and FRO and HRO are generated.
When generation is stopped, these pulses are fixed low.
D53 WENSEL
0: WEN is generated.
1: WEN generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
– 18 –
CXD2450R
D54 CLPSEL
0: XCPOB generation is stopped.
1: XCPOB is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D55 IDSEL
0: ID generation is stopped.
1: ID is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D56 HMCKSEL
0: 1/2MCK generation is stopped.
1: 1/2MCK is generated.
When generation is stopped, operation is the same as for D52 SSGSEL.
D57 TMCKSEL
0: 3/2MCK is generated.
1: 3/2MCK generation is stopped.
When generation is stopped, operation is the same as for D52 SSGSEL.
D58 HMCKREV
0: 1/2MCK reset when positive polarity.
1: 1/2MCK reset when negative polarity.
D59 HMCKREV
0: 3/2MCK reset when negative polarity.
1: 3/2MCK reset when positive polarity.
D60 to D61 DSG
The CXD2450R can apply stop control to the CCD pulses and pulses for the sample-and-hold and
analog/digital conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the
controlled pulses can be switched as follows using the serial interface data.
D61
0
D60
0
Operating mode
No control performed
CCD pulse stop control
0
1
1
0
Sample-and-hold and analog/digital conversion IC pulse stop control
1
1
CCD pulse and sample-and-hold and analog/digital conversion IC pulse stop control
Here, CCD pulses refer to the H1, H2, RG, V1, V2a, V2b, V3 and VSUB pulses. Sample-and-hold and
analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD pulses.
See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each pulse.
– 19 –
CXD2450R
D62 to D63 STB
This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the
CXD2450R and controlled immediately at the rise of the SEN input.
Operating mode
D63
X
D62
0
Symbol
CAMERA
SLEEP
Normal operating mode
1
0
1
Sleep mode
1
1
Standby mode
STNBY
1
Mode for the status which does not require CCD drive when playing back recorded data within the system.
The pin status during each mode is shown in the table below.
Pin
1
Symbol
3MCK
Vss1
Pin
CAMERA
ACT
CAMERA SLEEP
STNB
Y
Symbol
SLEEP
ACT
—
STNB
Y
25 RST
26 VDD6
27 SSI
ACT
ACT
ACT
—
L
ACT
2
WEN
ID
3
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
ACT
ACT
ACT
ACT
L
L
L
28 SSK
29 SEN
30 EBCKSM
31 FRO
32 HRO
33 HRI
34 FRI
4
L
TEST
VDD1
5
—
—
L
6
XCLPOB
VDD2
7
ACT
ACT
L
L
8
L
—
L
RG
9
ACT
ACT
L
Vss2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
—
L
Vss3
35 CLD
36 Vss5
37 DSGAT
38 MCK
39 VM
H1
ACT
ACT
—
L
L
H2
ACT
ACT
ACT
ACT
—
ACT
L
L
VDD3
—
L
XCLPDM
VDD4
ACT
L
40 V1
ACT
ACT
ACT
VM
VM
VM
VH
—
L
XSHP
XSHD
XRS
41 V3
ACT
ACT
ACT
VM
L
L
L
42 V2a
43 VH
VH
L
—
L
Vss4
44 V2b
45 VSUB
46 VL
ACT
ACT
VH
VH
VH
—
L
PBLK
1/2MCK
3/2MCK
VDD5
ACT
ACT
ACT
VH
L
L
L
—
L
47 OSCO
48 OSCI
ACT
ACT
ACT
ACT
ACT
ACT
ACT
—
Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status.
Also, VH and VM indicate the voltage levels applied to VH (Pin 43) and VM (Pin 39), respectively, in
the control status.
– 20 –
CXD2450R
D64 to D71 CHKSUM
This is the check sum bit. Apply the data shown below.
MSB
LSB
D07 D06 D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10 D09 D08
D23 D22 D21 D20 D19 D18 D17 D16
D31 D30 D29 D28 D27 D26 D25 D24
D39 D38 D37 D36 D35 D34 D33 D32
D47 D46 D45 D44 D43 D42 D41 D40
D55 D54 D53 D52 D51 D50 D49 D48
D63 D62 D61 D60 D59 D58 D57 D56
+) D71 D70 D69 D68 D67 D66 D65 D64
→ CHKSUM
0
0
0
0
0
0
0
0
→ Reflected when the total is 0.
– 21 –
CXD2450R
– 22 –
CXD2450R
– 23 –
CXD2450R
– 24 –
CXD2450R
– 25 –
CXD2450R
– 26 –
CXD2450R
– 27 –
CXD2450R
– 28 –
CXD2450R
Application Circuit Block Diagram
DRV OUT
VRT
10
D0 to 9
CCD
CCD OUT
S/H
A/D
ICX098AK
CXA2006Q
CXD2310AR
VRB
18 19
7
35
17
21 15
H1
H2
12
13
9
3/2MCK
1/2MCK
23
22
RG
ID
4
Signal
Processor
Block
WEN
3
TG
CXD2450R
MCK
V1
V2a
38
40
42
44
41
45
FRI
34
HRI
V2b
33
V-Dr
HRO
32
V3
SSG
37
5
25
30 27 28 29
FRO
VSUB
31
1
48
47
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the three –5.5V, +15.0V and +3.3V power supplies, be sure to start up the –5.5V and +15.0V power
supplies in the following order to prevent the VSUB pin of the CCD image sensor from going to negative
potential.
15.0V
t1
20%
0V
20%
t2
–5.5V
t2 ≥ t1
– 29 –
CXD2450R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
36
25
24
37
48
A
13
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5 ± 0.08
+ 0.2
+ 0.08
1.5 – 0.1
0.18 – 0.03
0.1
0.1 ± 0.1
0° to 10°
NOTE: “ ” Dimensions do not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY / PHENOL RESIN
SOLDER/PALLADIUM
PLATING
LQFP-48P-L01
QFP048-P-0707
SONY CODE
EIAJ CODE
42/COPPER ALLOY
0.2g
JEDEC CODE
PACKAGE WEIGHT
– 30 –
相关型号：
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