CXD3030R [SONY]

Micro Peripheral IC;


型号：	CXD3030R
厂家：	SONY CORPORATION
描述：	Micro Peripheral IC
文件：	总2页 (文件大小：41K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

System-on-a-Chip (SoC) Device Supports 48× Speed CD-ROM Drives

Digital Signal-processing IC for CD-ROM Systems

CXD3030R

■

Implements all the digital signal

processing required for playback

in a single chip.

A CD-ROM playback speed of 48× has finally been achieved.

We can say that the CD-ROM has reached the transfer rates of hard

disks only a few years ago.

Integrates digital servo control,

digital signal processing, a CD-

ROM decoder, ATAPI interface,

and DRAM on a single chip.

The CD-ROM is now indispensable in personal computers for in-

stalling application software.

The CXD3030R system-on-a-Chip (SoC) product represents an opti-

mal selection for compact basic design, energy-saving design, and

increased speed.

■

Playback speeds: Up to 48×

Provides even higher mounting

densities by including on-chip

RAM.

The CXD3030R is a system-on-a-Chip

(SoC) product that integrates digital

servo control, digital signal processing,

a CD-ROM decoder, ATAPI interface,

and DRAM on a single chip. It supports

playback speeds up to 48×.

Digital Signal Processing

Digital Servo Control

The CXD3030R supports playback

speeds up to 48×. Since this speed is 48

times the speed at which audio CDs are

played back, the CD-ROM certainly has

progressed to surprising speeds. The

built-in buffered audio play function al-

lows this device to play back CD-DA

audio while actually reading the disc in

high-speed CAV mode. An extensive

set of power saving functions are also

provided since an increasingly high

percentage of notebook personal

computers include a CD-ROM drive. In

addition to providing functions that

lower power consumption in the

standby state, this device also achieves

reduced power consumption during

playback.

While the CD-ROM optical system

includes several adjustment points, the

CXD3030R can automatically set all of

these to optimal values. It includes a

6-stage cascaded digital filter as the

tracking filter, and can flexibly support

different pickups and playback speeds.

The inclusion of an on-chip wide cap-

ture PLL circuit allows the CXD3030R

to be freely set up to get the maximum

performance from the drive mechanism,

providing support for both CAV tech-

niques using an FG signal, and partial

CAV techniques that take into account

the limitations on the speeds the motor

can provide. A drive with a short ac-

cess time can be designed by using the

mode in which the VCO is controlled

by a microcomputer and the pull-in time

after access is minimized.

ATAPI

Sony has led the industry by integrat-

ing on a single chip an interface and a

decoder that support ATAPI ULTRA

DMA (33). It goes without saying that

the CXD3030R implements all related

operations even while reaching a speed

of 48×.

When I joined Sony, 2× speed

drives had just been released.

It’s impressive how far we’ve

come since then. Although the

economy has its ups and

downs, technology is always

progressing. While I know that

my fantasies of my salary in-

creasing as fast as technology

are unreasonable, I am aware

that technology has advanced

this far through the efforts of

many people in many areas.

I recommend that you experi-

ence this speed directly.

CXD3030R

RF amp.

Disc

CXA2581

Digital

signal

ROM

decoder

block

1-bit

D/A

converter

DRAM

Audio out

transaction

block

Spindle motor

pickup

Digital

servo

block

ATAPI interface

block

Control

block

Driver

ATAPI bus

Sub CPU

System control

microcomputer (SPC970)

■ Figure 1 System Block Diagram for 48× Speed CD-ROM System-on-a-Chip LSI System

XTLO

XTLI

138

139

Data block

DRV^DD

DRVSS

32K RAM

1-Mbit DRAM

PCO 44

FILI 43

Clock

gen.

Digital PLL

ASY

Data

processor

FILO 42

CLTV 45

EFM

110 to 113,

DMA

sequencer

Address

gen.

115 to 118,

120 to 123,

125 to 128

DMA FIFO

HDB0 to F

RFAC 47

ASYI 49

Sync. protector

ASYO 50

Error

correction

block

Priority resolver

WFCK 27

SCOR 60

Timing generator

ATAPI registers

Subcode

deinterleave

& ECC

SQCK 62

SQSO 61

CD-

DSP

I/F

Subcode Q

processor

Subcode P to W

processor

12-byte packet FIFO

95, 96 HCS0, 1

97 to 99 HA0 to 2

CPU

Main data

CLV

MDP 12

Interface

(Serial I/F)

error correction

Descrambler

Sync. control

processor

104 XHRD

105 XHWR

102 XHAC

106 HDRQ

101 HINT

100 XS16

103 REDY

94 DASP

93 XPDI

107 XHRS

Auto sequencer

PWMI 13

Digital out

Host

I/F

Servo block

FOK

MIRR

DFCT

ADIO 33

D/A converter

block

RFDC 34

CE 35

TE 36

DAC

I/F

OP amp.

analog

8-bit

A/D

SE 37

FE 38

8 Fs

1-bit DAC

Servo DSP

DAC

Clock

gen.

Sub CPU I/F

OP amp.

VC 39

58 14 57 56

63 10

142 143 135 134

130

131

69 70 74 75 76 77 to 83 84 to 91

■ Figure 2 CXD3030R Block Diagram

CXD3030R [SONY]

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