CXD3048R [SONY]

CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost; CD数字信号处理器，内置数字伺服+防震内存控制器+数字高和低音增强


型号：	CXD3048R
厂家：	SONY CORPORATION
描述：	CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost CD数字信号处理器，内置数字伺服+防震内存控制器+数字高和低音增强内存控制器数字信号处理器 CD
文件：	总205页 (文件大小：1481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD3048R

CD Digital Signal Processor with Built-in Digital Servo +

Shock-proof Memory Controller + Digital High & Bass Boost

Description

The CXD3048R is a digital signal processor LSI for CD

players. This LSI incorporates a digital servo, high & bass

boost, shock-proof memory controller, 1-bit DAC and

analog low-pass filter.

120 pin LQFP (Plastic)

Features

• All digital signal processing during playback is

performed with a single chip

• Highly integrated mounting possible due to a built-in RAM

Digital Signal Processor (DSP) Block

• Supports CAV (Constant Angular Velocity) playback

• Frame jitter free

• 0.5× to 4× speed continuous playback possible

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports 1× to 4× speed playback

• Supports variable pitch playback

• The bit clock, which strobes the EFM signal, is

generated by the digital PLL.

Digital Filter, DAC and Analog Low-pass Filter Blocks

• Digital dynamic bass boost and high boost

Bass Boost: 4th-order IIR 24dB/Oct

+10dB/+14dB/+18dB/+22dB

High Boost: Second-order IIR 12dB/Oct

+4dB/+6dB/+8dB/+10dB

• Independent turnover frequency selection possible

Bass Boost: 125Hz/160Hz/200Hz

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error correction

C1: double correction, C2: quadruple correction

Supported during 4× speed playback

• Noise reduction during track jumps

• Auto zero-cross mute

• Subcode demodulation and subcode-Q data error

detection

• Digital spindle servo

High Boost: 5kHz/7kHz

• Digital dynamics (compressor)

Volume increased by +5dB at low level

• 8× oversampling digital filter

(attenuation: 61dB, ripple within band: ±0.0075dB)

• Digital signal output possible after boost

• Serial data format selectable from (output) 20 bits/

18 bits/16 bits (rearward truncation, MSB first)

• Digital attenuation: – ∞, –60 to +6dB, 2048 steps (linear)

• Soft mute

• 16-bit traverse counter

• Asymmetry correction circuit

• CPU interface on serial bus

• Digital de-emphasis

• High-cut filter

• Error correction monitor signal, etc. output from a new

CPU interface

• Servo auto sequencer

Applications

CD players

• Fine search performs track jumps with high accuracy

• Digital audio interface outputs

• Digital level meter, peak meter

Structure

Silicon gate CMOS IC

• Bilingual compatible

• VCO control mode

• CD TEXT data demodulation

• Digital Out can be generated from the audio serial

input. (also supported after shock-proof and digital

bass boost processing, subcode-Q addition function)

Absolute Maximum Ratings

• Supply voltage V^DD, AVDD

• Input voltage V^I

• Output voltage V^O

• Storage temperature Tstg

• Supply voltage difference

AV^SS– VSS

Vss – 0.5 to +3.5

Vss – 0.3 to VDD + 0.3

–55 to +150

°C

–0.3 to +0.3

Digital Servo (DSSP) Block

AV^DD– VDD

–0.3 to +0.3V (AVDD < 1.7V)

–0.3 to +1.0V (AVDD = 1.7 to 2.7V)

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment functions

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages

Recommended Operating Conditions

• Supply voltage

V^DD, AVDD0, 3, XVDD

AV^DD1, 2, DVDD

• Operating temperature Topr

1.7 to 2.7

VDD to 2.7

–20 to +75

°C

Focus filter: 5 stages

Shock-proof Memory Controller Block

• Supports an external 4M-bit/16M-bit DRAM

• Time axis-based data linking

• ADPCM compression method (uncompressed/4 bits/

6 bits/8 bits)

I/O Pin Capacitance

• Input capacitance

• Output capacitance

C^I

C^O

7 (max.)

V^DD= VI = 0V

f^M= 1MHz

Note) Measurement conditions

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E02653A37

CXD3048R

Block Diagram

TES1

TEST

XRST

Clock

Error

Generator

Corrector

LRCK

BCK

Selector

EFM

demodulator

D/A

Interface

RFAC

ASYI

ASYO

BIAS

PCMD

Asymmetry

Corrector

Digital

OUT

DOUT

32K

RAM

XPCK

FILO

FILI

A0 to A11

D0 to D3

Sub Code

Processor

Digital

PLL

XEMP

XWIH

XQOK

XRAS

XWE

PCO

CLTV

Shock-proof

Memory

Controller +

Compression/

Expansion

MDP

Digital

CLV

PWMI

XCAS

XWRE

XRDE

XSOE

SENS

DATA

XLAT

CPU

Interface

SYSM

LRMU

LRCKI

BCKI

CLOK

SCOR

SBSO

EXCK

SQSO

SQCK

Servo

Auto

Sequencer

DAC

PCMDI

HPL

Signal

Processor

Block

HPR

Memory Controller,

Bass Boost Block

AOUT1

VREFL

LPF

AOUT2

VREFR

LPF

Servo Block

SCLK

COUT

SSTP

ATSK

SERVO

Interface

MIRR

DFCT

FOK

MIRR

DFCT

FOK

RFDC

SERVO DSP

PWM GENERATOR

FFDR

FRDR

TFDR

TRDR

SFDR

SRDR

FOCUS PWM

GENERATOR

OPAmp

Analog SW Converter

A/D

FOCUS SERVO

TRACKING PWM

GENERATOR

TRACKING

SERVO

IGEN

SLED PWM

GENERATOR

SLED SERVO

– 2 –

CXD3048R

Pin Configuration

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

VSS1

TEST

TES1

VSS2

FRDR

FFDR

TRDR

TFDR

SRDR

SFDR

SSTP

MDS

MDP

C176

VDD2

LRCK

LRCKI

PCMD

PCMDI

BCK

AVDD2

AOUT2

VREFR

AVSS2

AVSS1

VREFL

AOUT1

AVDD1

XVSS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

XTAO

47 XTAI

46 XVDD

45 HVDD

44 HPR

43 HPL

42 HVSS

41 XTSL

40 EXCK

39 SBSO

38 XWIH

37 XEMP

36 SQSO

35 SCLK

34 SQCK

33 VSS0

32 R4M

31 XWRE

BCKI

DVDD

A10

A11

TEST3

TEST4

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

– 3 –

CXD3048R

Pin Description

Power Pin

supply No.

Symbol I/O Value

Description

XRAS

XWE

1, 0 DRAM row address strobe signal.

1, 0 DRAM data input enable signal.

1, 0 DRAM data bus 1.

I/O

1, 0 DRAM data bus 0.

1, 0 DRAM data bus 3.

1, 0 DRAM data bus 2.

TEST1

TEST2

XCAS

Test pin. Do not connect.

1, 0 DRAM column address strobe signal.

1, 0 WFCK output. XOE is output by switching with the command.

1, 0 DRAM address 9.

DRAM

I/F

10 WFCK

11 A9

12 A8

1, 0 DRAM address 8.

13 A7

1, 0 DRAM address 7.

14 DV^SS

15 A6

—

DRAM interface GND.

—

1, 0 DRAM address 6.

1, 0 DRAM address 5.

1, 0 DRAM address 4.

16 A5

17 A4

DRAM readout enable signal input. XRDE monitor is output by switching

with the command.

18 XRDE

19 VDD0

20 CLOK

21 DATA

22 SENS

1, 0

—

I/O

—

Digital power supply.

Serial data transfer clock input from CPU. SQSO and SENS readout

clocks are output by switching with the command.

Serial data input from CPU.

SENS output to CPU. SQSO data is output by switching with the

command.

1, Z, 0

Latch input from CPU. The serial data is latched at the falling edge. XLAT

which is low for 6µs or more is enabled.

23 XLAT

24 XSOE

25 SYSM

Clock input mode switching from CPU. Valid when $A4 ENXSOE = 1.

Mute input. Muted when high.

Digital

Word clock output f = 2Fs. GRSCOR is output by switching with the

command.

26 WDCK

27 SCOR

1, 0

High output when the subcode sync is detected. SCOR, which is

interpolated in the IC, is output by switching with the command.

28 XRST

29 PWMI

System reset. Reset when low.

Spindle motor external control input.

Subcode Q OK input. XQOK monitor is output by switching with the

command.

30 XQOK

31 XWRE

1, 0

I/O

DRAM write enable signal input. XWRE monitor is output by switching

with the command.

– 4 –

CXD3048R

Power Pin

supply No.

Symbol I/O Value

Description

Microcomputer clock output. R8M and C4M are output by switching with

the command.

32 R4M

1, 0

—

33 Vss0

34 SQCK

35 SCLK

Digital GND.

—

SQSO readout clock input.

SENS serial data readout clock input.

Subcode Q 80-bit and PCM peak and level data output. CD TEXT data

output.

36 SQSO

1, 0

Digital

37 XEMP

38 XWIH

39 SBSO

40 EXCK

1, 0 DRAM readout prohibited signal.

1, 0 Write to DRAM prohibited signal.

1, 0 Subcode P to W serial output.

SBSO readout clock input.

Crystal selection input. Low when the crystal is 16.9344MHz; high when

the crystal is 33.8688MHz.

41 XTSL

42 HV^SS

43 HPL

44 HPR

45 HV^DD

46 XVDD

—

Headphone GND.

—

1, 0 Lch headphone PDM output.

1, 0 Rch headphone PDM output.

H/P

—

Headphone power supply.

Master clock power supply.

—

Crystal oscillation circuit input. The master clock is externally input from

this pin.

47 XTAI

X'tal

48 XTAO

49 XVSS

Crystal oscillation circuit output.

Master clock GND.

50 AVDD1

51 AOUT1

52 VREFL

53 AV^SS1

54 AVSS2

55 VREFR

56 AOUT2

57 AVDD2

58 TES1

59 TEST

60 V^SS1

—

Analog power supply.

—

Analog Lch analog output.

Lch

Analog Lch reference voltage.

—

Analog GND.

Analog Rch reference voltage.

Analog Rch analog output.

Rch

—

Analog power supply.

Test pin. Normally GND.

Digital GND.

—

OR signal output of Lch, Rch "0" detection flag (AND output) and SYSM.

Only "0" detection flag is output by switching with the command.

61 LRMU

1, 0

Digital

62 DOUT

63 ATSK

64 DFCT

65 FOK

1, 0 Digital Out output.

1, 0 Anti-shock input/output.

1, 0 Defect signal input/output.

1, 0 Focus OK signal input/output.

I/O

– 5 –

CXD3048R

Power Pin

supply No.

Symbol I/O Value

Description

Mirror signal input/output.

66 MIRR

1, 0

I/O

Track number count signal input/output. SCOR is output by switching with

the command.

67 COUT

C2PO output. MNT3 and GTOP are output by switching with the

command.

68 C2PO

69 GFS

1, 0

Digital

GFS output. MNT2 and XROF are output by switching with the command.

XUGF output. MNT0, RFCK, C4M and QRCVD are output by switching

with the command.

70 XUGF

XPCK output. MNT1, FSTO and GTOP are output by switching with the

command.

71 XPCK

1, 0

Digital power supply.

72 V^DD1

73 PCO

74 FILI

—

Master PLL charge pump output.

Master PLL filter input.

1, Z, 0

Master PLL (slave = digital PLL) filter output.

Multiplier VCO1 control voltage input.

Wide-band EFM PLL VCO2 control voltage input.

Wide-band EFM PLL charge pump output.

Analog GND.

75 FILO

76 CLTV

77 VCTL

78 VPCO

79 AV^SS3

80 ASYO

81 ASYI

82 BIAS

83 AV^DD3

84 RFAC

85 AVDD0

86 IGEN

87 AV^SS0

88 RFDC

89 CE

Analog

1, Z, 0

—

ASYM

EFM full-swing output (low = Vss, high = VDD).

Asymmetry comparator voltage input.

Asymmetry circuit constant current input.

Analog power supply.

1, 0

—

EFM signal input.

Analog power supply.

—

Operational amplifier constant current input.

Analog GND.

—

RF signal input.

Center servo analog input or E input.

Tracking error signal input or F input.

Sled error signal input or B input.

Focus error signal input or A input.

Center voltage input.

A/D

90 TE

91 SE

92 FE

93 VC

Digital GND.

94 VSS2

95 FRDR

96 FFDR

97 TRDR

98 TFDR

99 SRDR

100 SFDR

—

Focus drive output.

1, 0

Focus drive output.

Digital

Tracking drive output.

Sled drive output.

– 6 –

CXD3048R

Power Pin

supply No.

Symbol I/O Value

Description

Disc innermost detection signal input.

101 SSTP

102 MDS

Spindle drive output.

1, Z, 0

Spindle motor servo control output.

103 MDP

104 C176

Digital

176.4kHz output. 88.2kHz for quasi-double speed setting.

Low output when XRST = low.

1, 0

Digital power supply.

105 V^DD2

106 LRCK

107 LRCKI

108 PCMD

109 PCMDI

110 BCK

111 BCKI

112 DV^DD

113 A3

—

D/A interface. LR clock output f = Fs.

D/A interface. LR clock input.

D/A interface. Serial data output. (two's complement, MSB first)

D/A interface. Serial data input. (two's complement, MSB first)

D/A interface. Bit clock output.

D/A interface. Bit clock input.

DRAM interface power supply.

DRAM address 3.

1, 0

—

1, 0

DRAM

I/F

DRAM address 2.

114 A2

DRAM address 1.

115 A1

DRAM address 0.

116 A0

DRAM address 10.

117 A10

DRAM address 11. Write prohibition factor is input by switching with the

command.

118 A11

1, 0

I/O

Test pin. Do not connect.

119 TEST3

120 TEST4

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the

EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 32K RAM exceeds the ±28 frame jitter margin.

• C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.

• R8M is the 8.4672MHz output.

• FSTO is the 2/3 frequency-division output of the XTAI pin.

• SOUT is the serial data output inside the servo block.

• SOCK is the serial data readout clock output inside the servo block.

• XOLT is the serial data latch output inside the servo block.

– 7 –

CXD3048R

Monitor Pin Output Combinations

Command bit

Output data

MONSEL SRO1 MTSL1 MTSL0

XUGF

MNT0

RFCK

C4M

XPCK

MNT1

XPCK

FSTO

SOCK

GTOP

GFS

C2PO

MNT3

GTOP

C2PO

COUT

SCOR

MIRR

—

MNT2

XROF

GFS

SOUT

QRCVD

XOLT

GFS

—

—: don't care

– 8 –

CXD3048R

Electrical Characteristics

1. DC Characteristics (VDD1 = 2.5 ± 0.2V, VDD2 (logic) = 1.8 ± 0.1V, DVSS = VSS = 0V, Topr = –20 to +75°C)

Applicable

pins

Typ. Max. Unit

Item

Conditions

Min.

1.7

VIH

VIL

Vt+

Vt–

High level input voltage

Low level input voltage

High level input voltage

Low level input voltage

Input voltage

(1)

13, 15

0.7

1.7

Input voltage

(2)

0.7

Schmitt input

Vt+ –

Vt–

Hysteresis

0.4

VOH

VOL

I^OH= –4mA

I^OL= 4mA

High level output voltage

Low level output voltage

2.0

Output

voltage

12, 13

0.4

VIN = VSS or

VDD

II (1)

II (2)

µA

–10

Input leak current (1)

Input leak current (2)

VIN = VSS or

V^DD

(VDD = AVDD = 2.5 ± 0.2V, Vss = AVss = 0V, Topr = –20 to +75°C)

Applicable

Typ. Max. Unit

Item

Conditions

Min.

pins

Input voltage

(1)

VIH (1)

VIL (1)

High level input voltage

Low level input voltage

1.7

1, 2,

0.7

Input voltage

(2)

VIN (2) Analog input

Vt+

Input voltage

V^SS

1.7

VDD

High level input voltage

Low level input voltage

Input voltage

(3)

Vt–

0.7

Schmitt input

Vt+ –

Vt–

Hysteresis

0.4

VOH (1) I^OH= –4mA

VOL (1) IOL = 4mA

VOH (2) IOH = –2mA

VOL (2) IOL = 2mA

VOH (3) IOH = –0.28mA

VOL (3) IOL = 0.36mA

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

2.0

2, 8,

Output

voltage (1)

10, 15

0.4

Output

voltage (2)

0.4

V^DD– 0.5

V^DD

Output

voltage (3)

0.4

1, 3,

VIN = VSS or

Input leak current (1)

Input leak current (2)

Input leak current (3)

II (1)

VDD

µA

–10

–40

–10

VIN = VSS or

II (2)

VDD

VIN = 0.25VDD

II (3)

to 0.75VDD

Tri-state output leak current

(when high impedance)

VO = VSS or

VDD

IOZ

– 9 –

CXD3048R

(VDD = AVDD = 1.8 ± 0.1V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Applicable

Typ.

Max. Unit

Item

Conditions

Min.

pins

Input voltage

(1)

VIH (1)

V^IL(1)

High level input voltage

Low level input voltage

0.65VDD

1, 2,

0.35VDD

Input voltage

(2)

VIN (2) Analog input

Vt+

Input voltage

VSS

VDD

High level input voltage

Low level input voltage

0.65VDD

Input voltage

(3)

Vt–

0.35VDD

Schmitt input

Vt+ –

Vt–

Hysteresis

0.4

VOH (1) IOH = –2.4mA

V^OL(1) I^OL= 2.4mA

VOH (2) IOH = –1.4mA

V^OL(2) I^OL= 1.4mA

VOH (3) IOH = –0.28mA

VOL (3) IOL = 0.36mA

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

VDD – 0.4

VDD

2, 8,

Output

voltage (1)

10, 16

0.4

VDD – 0.4

VDD

0.4

Output

voltage (2)

V^DD– 0.5

VDD

0.4

Output

voltage (3)

1, 3,

VIN = VSS or

Input leak current (1)

Input leak current (2)

Input leak current (3)

II (1)

VDD

µA

–10

–40

–10

VIN = VSS or

II (2)

VDD

VIN = 0.25VDD

II (3)

to 0.75VDD

Tri-state output leak current

(when high impedance)

VO = VSS or

VDD

IOZ

Applicable pins

TEST, TES1

COUT, MIRR, DFCT, FOK, XQOK, XWRE, ATSK

SYSM, DATA, XSOE, XTSL

SSTP, PWMI

SQCK, EXCK, XRST, CLOK, SCLK, XLAT

VCTL, FILI, CLTV, ASYI, IGEN, BIAS

RFDC, CE, TE, SE, FE, VC

XEMP, XWIH, SQSO, SBSO, XUGF, XPCK, GFS, C2PO, SCOR, WDCK, SFDR, SRDR, TFDR, TRDR,

FFDR, FRDR, ASYO, DOUT, C176

R4M

SENS, MDP, VPCO, PCO, MDS

FILO

A0 to A10, XRAS, XCAS, XWE, WFCK, LRCK, BCK, PCMD

D0 to D3, XRDE, A11

LRCKI, BCKI

PCMDI

HPL, HPR

– 10 –

CXD3048R

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, Vss = AVss = 0V, Topr = –20 to +75°C)

Item

Symbol

f^MAX

Min.

Typ.

Max.

Unit

Oscillation

frequency

MHz

(b) When inputting pulses to XTAI pin

(V^DD= AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, Vss = AVss = 0V, Topr = –20 to +75°C)

Item

Symbol

Min.

Typ.

Max.

500

Unit

High level pulse

width

WHX

WLX

Low level pulse

width

500

Pulse cycle

1000

Input high level

Input low level

0.7VDD

VIHX

VILX

0.2VDD

Rise time,

fall time

R, t

WLX

tWHX

IHX

IHX × 0.9

XTAI

DD/2

IHX × 0.1

ILX

Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor.

– 11 –

CXD3048R

(2) CLOK, DATA, XLAT, SQCK and EXCK pins

(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Clock frequency

Symbol

f^CK

Min.

Typ.

Max.

0.65

Unit

MHz

WCK

Clock pulse width

750

300

750

30000

Setup time

Hold time

Delay time

30000

0.65

Latch pulse width

EXCK SQCK frequency

EXCK SQCK pulse width

COUT frequency (during input)

COUT pulse width (during input)

MHz

750

7.5

kHz

µs

Only when $44 and $45 are executed.

1/fCK

WCK

tWCK

CLOK

DATA

XLAT

tWSC

tWL

EXCK

SQCK

COUT

tWT

1/fT

SBSO

SQSO

(3) R4M pin (when $A4X CKOUTSL2 = CKOUTSL1 = 0)

(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Output frequency

Output duty

Symbol

fOUT

Min.

Typ.

4.2336

Max.

Unit

MHz

DOUT

VOUT

Output amplitude

VDD

– 12 –

CXD3048R

(4) SCLK pin

XLAT

SCLK

DLS

tSPW

. . .

1/fSCLK

Serial Read Out Data

(SENS)

MSB

LSB

(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

SCLK frequency

SCLK pulse width

Delay time

Symbol

Min.

Typ.

Max.

Unit

MHz

fSCLK

SPW

DLS

31.3

µs

(5) COUT, MIRR and DFCT pins

Operating frequency

(VDD = AVDD = 1.8 ± 0.1V and 2.5 ± 0.2V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Symbol

f^COUT

Min.

Typ.

Max.

Unit Conditions

COUT maximum

operating frequency

kHz

MIRR maximum

operating frequency

fMIRR

kHz

DFCT maximum

operating frequency

fDFCTH

kHz

When using a high-speed traverse TZC.

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.11VDD to 0.23VDD

A + B

•

≤ 25%

During complete RF signal omission.

When settings related to DFCT signal generation are Typ.

– 13 –

CXD3048R

1-bit DAC and LPF Block Analog Characteristics

(VDD = AVDD = 2.6V, VSS = AVSS = 0V, Ta = +25°C)

Item

Symbol

THD

Conditions

Crystal

384Fs

768Fs

Min.

Typ.

Max.

0.016

Unit

0.009

Total harmonic

distortion

1kHz sine wave, 0dB data,

20kHz LPF

1kHz sine wave, 0dB data,

AMUT OFF (Using A-weighting

filter 20kHz LPF)

384Fs

768Fs

Signal-to-noise

ratio

S/N

Fs = 44.1kHz in all cases.

The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

22µF

100Ω

AOUT1 (2)

VREFL (R)

Audio Analyzer

100kΩ

2200pF

1µF

LPF external circuit diagram ($A560C400 PDMSEL = 1)

768Fs/384Fs

Rch

Lch

DATA

Audio Analyzer

TEST DISC

CXD3048R

Block diagram of analog characteristics measurement

(VDD = AVDD = 2.6V, VSS = AVSS = 0V, Ta = +25°C)

Item

Symbol

Min.

640

Typ.

658

Max.

Unit

mVrms

kΩ

Applicable pins

VOUT

Output voltage

Load resistance

CVREF

VREF pin capacitance

µF

Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.

Applicable pins

AOUT1, AOUT2

VREFL, VREFR

– 14 –

CXD3048R

Contents

[1] CPU Interface

§1-1. CPU Interface Timing...................................................................................................................... 16

§1-2. CPU Interface Command Table ...................................................................................................... 16

§1-3. CPU Command Presets ................................................................................................................. 32

§1-4. Description of SENS Signals .......................................................................................................... 43

§1-5. Description of Commands .............................................................................................................. 45

[2] Subcode Interface

§2-1. P to W Subcode Readout ............................................................................................................. 101

§2-2. 80-bit Subcode-Q Readout ........................................................................................................... 101

[3] Description of Modes

§3-1. CLV-N Mode .................................................................................................................................. 108

§3-2. CLV-W Mode ................................................................................................................................. 108

§3-3. CAV-W Mode................................................................................................................................. 108

§3-4. VCO-C Mode ................................................................................................................................ 109

[4] Description of Other Functions

§4-1. Channel Clock Recovery by Digital PLL Circuit ........................................................................... 112

§4-2. Frame Sync Protection ................................................................................................................. 114

§4-3. Error Correction ............................................................................................................................ 114

§4-4. DA Interface .................................................................................................................................. 115

§4-5. Digital Out ..................................................................................................................................... 118

§4-6. Servo Auto Sequence ................................................................................................................... 124

§4-7. Digital CLV .................................................................................................................................... 132

§4-8. CD-DSP Block Playback Speed ................................................................................................... 133

§4-9. Description of DAC Block and Shock-proof Memory Controller Block Circuits ............................ 133

§4-10. DAC Block Input Timing ................................................................................................................ 134

§4-11. Description of DAC Block Functions............................................................................................. 135

§4-12. LPF Block...................................................................................................................................... 140

§4-13. Description of Shock-proof Memory Controller Block Functions.................................................. 141

§4-14. CPU to DRAM Access Function ................................................................................................... 146

§4-15. Asymmetry Correction .................................................................................................................. 150

§4-16. CD TEXT Data Demodulation....................................................................................................... 151

[5] Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System ............................................................ 153

§5-2. Digital Servo Block Master Clock (MCK)...................................................................................... 154

§5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...................................................... 155

§5-4. E:F Balance Adjustment Function ................................................................................................ 156

§5-5. FCS Bias Adjustment Function..................................................................................................... 156

§5-6. AGCNTL Function......................................................................................................................... 158

§5-7. FCS Servo and FCS Search ........................................................................................................ 160

§5-8. TRK and SLD Servo Control ........................................................................................................ 161

§5-9. MIRR and DFCT Signal Generation ............................................................................................. 162

§5-10. DFCT Countermeasure Circuit ..................................................................................................... 163

§5-11. Anti-shock Circuit .......................................................................................................................... 163

§5-12. Brake Circuit ................................................................................................................................. 164

§5-13. COUT Signal................................................................................................................................. 165

§5-14. Serial Readout Circuit................................................................................................................... 165

§5-15. Writing to Coefficient RAM ........................................................................................................... 166

§5-16. PWM Output ................................................................................................................................. 166

§5-17. Servo Status Changes Produced by LOCK Signal ...................................................................... 167

§5-18. Description of Commands and Data Sets .................................................................................... 167

§5-19. List of Servo Filter Coefficients..................................................................................................... 195

§5-20. Filter Composition ......................................................................................................................... 197

§5-21. TRACKING and FOCUS Frequency Response ........................................................................... 203

[6] Application Circuit.................................................................................................................................. 204

Explanation of abbreviations

AVRG: Average

AGCNTL: Auto gain control

FCS: Focus

TRK: Tracking

SLD: Sled

DFCT: Defect

– 15 –

CXD3048R

[1] CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes.

The interface timing chart is shown below. (See 2. AC Characteristics in Electrical Characteristics, for the

details of the AC characteristics.)

750ns to 30µs

CLOK

D18 D19 D20 D21 D22 D23

DATA

750ns or more

(6µs or more

when $AAX

MLAT ON)

XLAT

Valid

Registers

• The internal registers are initialized by a reset when XRST = 0.

§1-2. CPU Interface Command Table

Total bit length for each register

Total bit length

8 bits

0 to 2

8 to 24 bits

16 bits

4 to 6

20 bits

32 bits

28 bits

20 bits

– 16 –

Command Table ($0X to 1X)

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Data 5

Command

ter

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

—

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

—

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

—

FOCUS SERVO OFF,

0V OUT

FOCUS

0 0 0 0

—

CONTROL

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

—

FOCUS SEARCH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

—

BRAKE OFF

TRACKING

CONTROL

0 0 0 1

TRACKING GAIN

NORMAL

—

TRACKING GAIN UP

FILTER SELECT 1

—

TRACKING GAIN UP

FILTER SELECT 2

—: don't care

Command Table ($2X to 3X)

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Data 5

Command

ter

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

—

TRACKING SERVO

OFF

—

TRACKING SERVO

—

FORWARD TRACK

JUMP

REVERSE TRACK

JUMP

TRACKING

CONTROL

0 0 1 0

—

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED

MOVE

REVERSE SLED

MOVE

Address

Data 1

Data 2

Data 3

Data 4

Data 5

Regis-

ter

Command

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

—

SLED KICK LEVEL

—

(±1 × basic value) (default)

SLED KICK LEVEL

—

(±2 × basic value)

SELECT

0 0 1 1

SLED KICK LEVEL

(±3 × basic value)

SLED KICK LEVEL

(±4 × basic value)

—: don't care

Command Table ($340X)

Address 1 Address 2 Address 3

Address 4

Data 1

D6 D5

Data 2

D2 D1

Regis-

ter

Command

D23 to D20 D19 to D16 D15 to D12 D11 D10 D9

KRAM DATA (K00)

SLED INPUT GAIN

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

SELECT

0 0 1 1

0 1 0 0

0 0 0 0

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

Command Table ($341X)

Address 1 Address 2 Address 3

Address 4

Data 1

D6 D5

Data 2

D2 D1

Regis-

ter

Command

D23 to D20 D19 to D16 D15 to D12 D11 D10 D9

KRAM DATA (K10)

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

SELECT

0 0 1 1

0 1 0 0

0 0 0 1

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

Command Table ($342X)

Address 1 Address 2 Address 3

Address 4

Data 1

D6 D5

Data 2

D2 D1

Regis-

ter

Command

D23 to D20 D19 to D16 D15 to D12 D11 D10 D9

KRAM DATA (K20)

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

SELECT

0 0 1 1

0 1 0 0

0 0 1 0

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

Not used

KRAM DATA (K2F)

Not used

Command Table ($343X)

Address 1 Address 2 Address 3

Address 4

Data 1

D6 D5

Data 2

D2 D1

Regis-

ter

Command

D23 to D20 D19 to D16 D15 to D12 D11 D10 D9

KRAM DATA (K30)

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

Not used

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

SELECT

0 0 1 1

0 1 0 0

0 0 1 1

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

Not used

Command Table ($344X)

Address 1 Address 2 Address 3

Address 4

Data 1

D6 D5

Data 2

D2 D1

Regis-

ter

Command

D23 to D20 D19 to D16 D15 to D12 D11 D10 D9

KRAM DATA (K40)

KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1)

KRAM DATA (K47)

Not used

SELECT

0 0 1 1

0 1 0 0

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

Not used

KRAM DATA (K4F)

Not used

Command Table ($348X to 3FX)

Address 1 Address 2

D23 to D20 D19 to D16 D15 D14 D13 D12 D11 D10 D9

PGFS PGFS PFOK PFOK

Data 1

Data 2

Data 3

Address 3

Regis-

ter

Command

MRS MRT1 MRT0

PGFS, PFOK, RFAC

DOUT

A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT

SEL EN

EN1 DMUT WOD EN EN2

SFBK SFBK

LB1 LB2 LB2

Booster Surf Brake

Booster

SN SM

THB FHB TLB1 FLB1 TLB2

ON ON ON ON ON

HBST HBST LB1S LB1S LB2S LB2S

IDF IDF IDF IDF

DF IDFT IDFT

LPDF INV

DFCT

SELECT

0 0 1 1

0 1 0 0

SL3 SL2 SL1 SL0

SLS

RFDC

Address 3

Data 1

Data 3

D2 D1

Data 2

D6 D5

D15 D14 D13 D12 D11 D10 D9

—

FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1

FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1

FCS Bias Limit

FCS Bias Data

—

TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 Traverse Center Data

—: don't care

Command Table ($34FX to 3FX) cont.

Address 1

Address 2

Data 1

Data 2

Data 3

D6 D5

Data 4

D2 D1

Regis-

ter

Command

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FCS search, AGF

TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 TRK jump, AGT

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move

VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel

DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIF

Serial data readout

FCS Bias, Gain,

Surf jump / brake

FBONFBSS FBUP FBV1 FBV0

TJD0 FPS1 FPS0 TPS1 TPS0 SVDA SJHD INBK MTI0

FPG FPG TPG TPG

Gain

SELECT

0 0 1 1

FOCUS

FZC

SRQ1 SRQ0

ASYO

SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT

Mirr, DFCT, FOK

TZC, COUT, Bottom,

MIRR

COSSCOTS CETZ CETF COT2 COT1 MOT2

BTS1 BTS0 MRC1 MRC0

SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SDF6 SDF5 SDF4 SDF3

SLD filter

F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD

LKIN COIN MDFI MIRI XT1D Filter

AGG4 XT4D XT2D

DRR2DRR1 DRR0

ASFG FTQ

SRO1

AGHF ASOT Clock, others

Command Table ($34FX to 3FX) cont.

Address 1

Address 2

Address 3

Data 1

Data 2

Data 3

Regis-

ter

Command

D23 to D20

D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

SYG3 SYG2 SYG1 SYG0

FFS

System GAIN

FZB3 FZB2 FZB1 FZB0 FZA3 FZA2 FZA1 FZA0

SELECT

0 0 1 1

FSUD

FFS5 FFS4 FFS3 FFS2 FFS1 FFS0 FOCUS

Command Table ($4X to EX)

Address

D2 D1

Data 1

Data 2

Data 3

Data 4

Regis-

Command

ter

—

Auto sequence

AS3

AS2

TR2

AS1

AS0

MT3

MT2

MT1

MT0

LSSL

—

Blind (A, E),

Brake (B),

TR3

SD3

TR1

SD1

TR0

SD0

—

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

SD2

KF3

2048

KF2

KF1

512

KF0

256

—

Auto sequence (N)

track jump

32768 16384 8192 4096

1024

128

count setting

MODE

CD- DOUT DOUT

WSEL

VCO

VCO1

CS0

ASHS SOCT0

KSL3 KSL2 KSL1 KSL0

specification

ROM Mute Mute-F

SEL2

SEL1

Function

DSPB ASEQ

BiliGL BiliGL

MAIN SUB

FLFC

specification

ON-OFF ON-OFF

—: don't care

Command Table ($4X to EX) cont.

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Command

ter

Audio CTRL

Signal select

Mute

ATT

PCT1 PCT2

RSL1 RSL0

SOC2

DTSL1 DTSL0 MCSL1 MCSL0

AD7

SDSL2 SDSL1 SDSL0

ZMUTA SMUT AD10 AD9

DAC HiCut

AD8

AD6

AD5

AD4

BST

PDM

SEL

PWDN ZDPL WOC

OBIT1 OBIT0

EMPH FILTER CL

Bass boost

BBST BBST

Vdwn1 Vdwn0

BBON1 BBON0 HBON1 HBON0 BBSL1 BBSL0 HBSL1 HBSL0

COMP

AD7

AD5

AD4

SMUT AD10 AD9

DAC HiCut

AD8

AD6

BST

PDM

SEL

PWDN ZDPL XWOC

EMPH FILTER CL

Headphone

BBST BBST

Vdwn1 Vdwn0

BBON1 BBON0 HBON1 HBON0 BBSL1 BBSL0 HBSL1 HBSL0

COMP

GTOP NOLIM SPSL

XOE

OUT

Shock-proof

READ2 REFSEL REFON

SDTO

MSL2 MSL1 MSL0

memory setting

XQOK XWRE CHECK WDCK COM

Shock-proof

XQOK XWRE XRDE XSOEO XSOEO2 ADDRST

OUT

memory control

DOUT subcode-Q

setting

SubQA3 SubQA2 SubQA1 SubQA0

SubQD7 SubQD6 SubQD5 SubQD4

DRWR DRADR

DRD15 DRD14 DRD13 DRD12

DRAM I/F

DADR19 DADR18 DADR17 DADR16 DADR15 DADR14 DADR13 DADR12

Command Table ($4X to EX) cont.

Address

D2 D1

Data 1

Data 2

D2 D1

ADPON BITSL1 BITSL0

Data 3

Data 4

Regis-

ter

Command

Compression

setting

ADP

GRSEL

EFM playability

ARDTEN

AVW

enhancement setting

Sync expansion

specification

SFP5 SFP4 SFP3 SFP2 SFP1 SFP0

DSP DSSP ASYM ESP

LPF DSUB ASEQ

HCAV ERCNT

SLEEP SLEEP

Sleep setting

ADCPS

PCOL

SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP

Variable pitch

setting

VARI VARI WTC SCSY SENS SENS SENS SENS

ON USE C2PO (sub) SEL3 SEL2 SEL1 SEL0

Spindle servo

setting

SYG3 SYG2 SYG1 SYG0 MDP

MDP

MDS

CTL

MDP

LPWR2

EA OUTSL1 OUTSL0

CTL4

Traverse monitor

counter setting

32768 16384 8192 4096

Gain Gain Gain Gain

2048

1024

512

256

128

Spindle servo

Gain

PCC1 PCC0 SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SPR1 SRP0

coefficient setting

MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0

Gain

CLV CTRL

SPD mode

VP7

VP6

VP5

VP4

VP3

VP2

VP1

VP0

CLVS

CTL1 CTL0

Gain

INV

CM3

CM2

CM1

CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON

CAV1 CAV0

VPCO

Command Table ($4X to EX) cont.

Data 5

D2 D1

SCSY SOCT1 TXON TXOUT OUTL1 OUTL0

Data 6

Data 7

Regis-

Command

Data 3

Data 4

Address

Data 1

Data 2

ter

D2 D1

MODE

SCOR

SEL

1 0 0 0

1 0 0 1

ERC4

OUTL2

specification

Function

DIV4

specification

0 0

—

AUDIO CTRL

Signal select

EN CKOUT CKOUT SLD

max

0 1 0 0

XSOE

SL2

SL1

BBIN C2PO7 C2PO6 C2PO5 C2PO4 C2PO3 C2PO2 C2PO1 C2PO0

0 0 1

0 1

AD3

AD2

AD1

AD0

setup

Bass boost

0 1 0 1

BBST BBST BBST BBST

1 0

Vup1

Vup0

Uth

Lth

PDM

INV

1 1

1 0 1 0

0 0 1

0 1

AD3

AD2

AD1

AD0

Headphone

0 1 1 0

BBST BBST BBST BBST

1 0

Vup1

Vup0

Uth

Lth

PDM

INV

1 1

ADDRST

SEL

STA

SEL

XWI

XWI SPSL WQR

H1 COM MON

A11

SEL

READ READ MON

S2 S1 SEL

Shock-proof

0 1 1 1

1 0 0 1

ADRMO

memory setting

DOUT subcode-Q

setting

0 0 0 0

SubQD3 SubQD2 SubQD1 SubQD0

—: don't care

Command Table ($4X to EX) cont.

Data 5

D2 D1

Data 6

D2 D1

Data 7

D2 D1

Regis-

Command

Address

Data 1

Data 2

Data 3

Data 4

ter

DRD11 DRD10 DRD9 DRD8 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 DRD0

1 1 1 0

1 1 1 1

1 0 0 1

DRAM I/F

DADR11 DADR10 DADR9 DADR8 DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 DADR1 DADR0

ADPCM ADPCM

Compression

setting

1 0 1 0

1 0 1 1

ORMU

MUTE

1 0 1 0

EFM playability

enhancement

setting

Sync expansion

specification

REF

1 1 0 0

1 1 1 1

OV3

OV2

OV1

OV0

SLIM1 SLIM0 OV4

MDP MDP MDP

SEL2

Spindle servo

setting

MDP

CTL3 CTL2 CTL1 CTL0

Traverse monitor

counter setting

1 0 1 1

1 1 0 0

1 1 0 1

MTSL1 MTSL0 ASYE MD2

Spindle servo

EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0

—

coefficient setting

CLV CTRL

—: don't care

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

Address

Data 1

Data 2

Data 3

Data 4

Data 5

Regis-

ter

Command

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

—

FOCUS

FOCUS SERVO OFF,

0V OUT

0 0 0 0

0 0 0 1

0 0 1 0

—

CONTROL

TRACKING

CONTROL

TRACKING GAIN UP

FILTER SELECT 1

—

TRACKING

MODE

TRACKING SERVO OFF

SLED SERVO OFF

Address

Data 1

Data 2

Data 3

Data 4

Data 5

Regis-

ter

Command

SELECT

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

—

SLED KICK LEVEL

0 0 1 1

—

(±1 × basic value) (default)

Address 1

Address 2

Address 3

Data 1

Data 2

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

KRAM DATA

See "Coefficient ROM Preset Values Table"

0 0 1 1

($3400XX to $344FXX)

—: don't care

Command Preset Table ($348X to 34FX)

Address 1 Address 2

Regis-

Data 1

Data 2

Data 3

Address 3

Command

ter

D23 to D20 D19 to D16 D15 D14 D13 D12 D11 D10 D9

PGFS, PFOK, RFAC

DOUT

Booster Surf Brake

Booster

SELECT

0 0 1 1

0 1 0 0

DFCT

Address 3

Data 1

Data 3

Data 2

D15 D14 D13 D12 D11 D10 D9

—

FCS Bias Limit

—

FCS Bias Data

Traverse Center Data

—: don't care

Command Preset Table ($34FX to 3FX) cont.

Address 1

Address 2

Data 1

Data 2

Data 3

Data 4

D2 D1

Regis-

ter

Command

D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

FCS search, AGF

TRK jump, AGT

FZC, AGC, SLD move

DC measure, cancel

Serial data read out

FCS Bias, Gain,

Surf jump / brake

Gain

SELECT

0 0 1 1

FOCUS

ASYO

MIRR, DFCT, FOK

TZC, COUT, Bottom,

MIRR

SLD filter

Filter

Clock, others

Command Preset Table ($34FX to 3FX) cont.

Address 1

Address 2

Address 3

Data 1

Data 2

Data 3

D2 D1

Regis-

ter

Command

D23 to D20

D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9

System GAIN

FOCUS

SELECT

0 0 1 1

Command Preset Table ($4X to EX)

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Command

ter

—

Auto sequence

—

Blind (A, E),

Brake (B),

—

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

—

Auto sequence (N)

track jump count

setting

MODE setting

Function

specification

—: dun't care

Command Preset Table ($4X to EX) cont.

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Command

ter

Audio CTRL

Signal select

Bass boost

Headphone

Shock-proof

memory setting

Shock-proof

memory control

DOUT subcode-Q

setting

DRAM I/F

Command Preset Table ($4X to EX) cont.

Address

Regis-

Data 1

Data 2

Data 3

Data 4

Command

ter

Compression

setting

EFM playability

enhancement setting

Sync expansion

specification

Sleep setting

Variable pitch

setting

Spindle servo

setting

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

Command Preset Table ($4X to EX) cont.

Data 5

Data 6

Data 7

Regis-

Command

Data 3

Data 4

Address

Data 1

Data 2

ter

MODE

1 0 0 0

1 0 0 1

specification

Function

—

specification

0 0

—

AUDIO CTRL

Signal select

0 1 0 0

0 0 1

0 1

0 1 0 1

Bass boost

1 0

1 0 1 0

1 1

0 0 1

0 1

0 1 1 0

Headphone

1 0

1 1

Shock-proof

0 1 1 1

memory setting

—: don't care

Command Preset Table ($4X to EX) cont.

Data 5

Data 6

Data 7

Regis-

Command

Data 3

0 0 0 0

Data 4

Address

Data 1

Data 2

ter

DOUT subcode-Q

setting

1 0 0 1

1 1 1 0

1 1 1 1

DRAM I/F

Compression

setting

1 0 1 0

1 0 1 1

EFM playability

enhancement

setting

Sync expansion

specification

1 1 0 0

1 1 1 1

Spindle servo

setting

Traverse monitor

counter setting

1 0 1 1

1 1 0 0

1 1 0 1

Spindle servo

—

coefficient setting

CLV CTRL

—: don't care

CXD3048R

(Coefficient ROM Preset Values Table (1))

ADDRESS

DATA

CONTENTS

K00

K01

K02

K03

K04

K05

K06

K07

K08

K09

K0A

K0B

K0C

K0D

K0E

K0F

SLED INPUT GAIN

SLED LOW BOOST FILTER A-H

SLED LOW BOOST FILTER A-L

SLED LOW BOOST FILTER B-H

SLED LOW BOOST FILTER B-L

SLED OUTPUT GAIN

FOCUS INPUT GAIN

SLED AUTO GAIN

FOCUS HIGH CUT FILTER A

FOCUS HIGH CUT FILTER B

FOCUS LOW BOOST FILTER A-H

FOCUS LOW BOOST FILTER A-L

FOCUS LOW BOOST FILTER B-H

FOCUS LOW BOOST FILTER B-L

FOCUS PHASE COMPENSATE FILTER A

FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K1A

K1B

K1C

K1D

K1E

K1F

FOCUS PHASE COMPENSATE FILTER B

FOCUS OUTPUT GAIN

ANTI SHOCK INPUT GAIN

FOCUS AUTO GAIN

HPTZC / Auto Gain HIGH PASS FILTER A

HPTZC / Auto Gain HIGH PASS FILTER B

ANTI SHOCK HIGH PASS FILTER A

HPTZC / Auto Gain LOW PASS FILTER B

Fix

TRACKING INPUT GAIN

TRACKING HIGH CUT FILTER A

TRACKING HIGH CUT FILTER B

TRACKING LOW BOOST FILTER A-H

TRACKING LOW BOOST FILTER A-L

TRACKING LOW BOOST FILTER B-H

TRACKING LOW BOOST FILTER B-L

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K2A

K2B

K2C

K2D

K2E

K2F

TRACKING PHASE COMPENSATE FILTER A

TRACKING PHASE COMPENSATE FILTER B

TRACKING OUTPUT GAIN

TRACKING AUTO GAIN

FOCUS GAIN DOWN HIGH CUT FILTER A

FOCUS GAIN DOWN HIGH CUT FILTER B

FOCUS GAIN DOWN LOW BOOST FILTER A-H

FOCUS GAIN DOWN LOW BOOST FILTER A-L

FOCUS GAIN DOWN LOW BOOST FILTER B-H

FOCUS GAIN DOWN LOW BOOST FILTER B-L

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

FOCUS GAIN DOWN DEFECT HOLD GAIN

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

FOCUS GAIN DOWN OUTPUT GAIN

Not used

Fix indicates that normal preset values should be used.

– 41 –

CXD3048R

ADDRESS

DATA

CONTENTS

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K3A

K3B

K3C

K3D

K3E

K3F

SLED INPUT GAIN (Only when TRK gain up2 is accessed with SFSK = 1.)

ANTI SHOCK LOW PASS FILTER B

Not used

ANTI SHOCK HIGH PASS FILTER B-H

ANTI SHOCK HIGH PASS FILTER B-L

ANTI SHOCK FILTER COMPARATE GAIN

TRACKING GAIN UP2 HIGH CUT FILTER A

TRACKING GAIN UP2 HIGH CUT FILTER B

TRACKING GAIN UP2 LOW BOOST FILTER A-H

TRACKING GAIN UP2 LOW BOOST FILTER A-L

TRACKING GAIN UP2 LOW BOOST FILTER B-H

TRACKING GAIN UP2 LOW BOOST FILTER B-L

TRACKING GAIN UP PHASE COMPENSATE FILTER A

TRACKING GAIN UP PHASE COMPENSATE FILTER B

TRACKING GAIN UP OUTPUT GAIN

Not used

K40

K41

K42

K43

K44

K45

K46

TRACKING HOLD FILTER INPUT GAIN

TRACKING HOLD FILTER A-H

TRACKING HOLD FILTER A-L

TRACKING HOLD FILTER B-H

TRACKING HOLD FILTER B-L

TRACKING HOLD FILTER OUTPUT GAIN

TRACKING HOLD FILTER INPUT GAIN

(Only when TRK gain up2 is accessed with THSK = 1.)

Not used

FOCUS HOLD FILTER INPUT GAIN

FOCUS HOLD FILTER A-H

FOCUS HOLD FILTER A-L

FOCUS HOLD FILTER B-H

FOCUS HOLD FILTER B-L

K47

K48

K49

K4A

K4B

K4C

K4D

K4E

K4F

FOCUS HOLD FILTER OUTPUT GAIN

Not used

– 42 –

CXD3048R

§1-4. Description of SENS Signals

SENS output

Microcomputer

serial register

ASEQ = 0

ASEQ = 1

Output data length

(latching not required)

$0X

FZC

—

$1X

$2X

TZC

$30 to $37

$38

SSTP

AGOK

XAVEBSY

$38

See §5-18. Description of Commands and Data

Sets "$39".

$39X

8 to 16 bits

$3A

FBIAS Count STOP

—

$3B to $3F

$4X

SSTP

XBUSY

FOK

$5X

$6X

$A0 to $A8

$AA to $AF

GFS

—

$BX

COMP

COUT

OV64

COMP

COUT

OV64

—

$CX

$EX

$7X, 8X, 9X, DX, FX

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.

SSTP is output in all other cases.

– 43 –

CXD3048R

Description of SENS Signals

SENS output

The SENS pin is high impedance.

XBUSY

Low while the auto sequencer is in operation, high when operation terminates.

Outputs the same signal as the FOK pin.

High for "focus OK".

FOK

GFS

High when the regenerated frame sync is obtained with the correct timing.

Counts the number of tracks set with Reg.B.

COMP

High when Reg.B is latched, low when COUT is counted for the initial Reg.B number.

Counts the number of tracks set with Reg.B.

High when Reg.B is latched, toggles each time COUT is counted for the Reg.B number.

While $44 and $45 are being executed, toggles with each COUT 8-count instead of the

Reg.B number.

COUT

OV64

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing

through the sync detection filter.

– 44 –

CXD3048R

§1-5. Description of Commands

The meaning of the data for each address on the XLAT pin side is explained below.

$4X commands

Data 1

Data 2

Data 3

Command

MAX timer value

MT2 MT1

Timer range

AS3

AS2

AS1

AS0

MT3

MT0 LSSL

Command

AS3

AS2

AS1

AS0

Cancel

Fine Search

Focus-On

RXF

1 Track Jump

10 Track Jump

2N Track Jump

M Track Move

RXF

RXF = 0 Forward

RXF = 1 Reverse

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump commands ($44, $45 and $48 to $4D) are canceled, $25 is sent and the auto sequence

is interrupted.

MAX timer value

Timer range

MT3

23.2ms

1.49s

MT2

11.6ms

0.74s

MT1

5.8ms

0.37s

MT0

2.9ms

0.18s

LSSL

• To disable the MAX timer, set the MAX timer value to "0".

$5X commands

Timer

Blind (A, E), Overflow (C, G)

Brake (B)

TR3

TR2

TR1

TR0

0.18ms

0.36ms

0.09ms

0.18ms

0.045ms

0.09ms

0.022ms

0.045ms

– 45 –

CXD3048R

$6X commands

Data 1

Data 2

KICK (D)

KICK (F)

SD3

Timer

SD2

SD1

SD0

KF3

KF2

KF1

KF0

SD3

SD2

SD1

5.8ms

2.9ms

SD0

When executing KICK (D) $44 or $45

When executing KICK (D) $4C or $4D

23.2ms

11.6ms

5.8ms

2.9ms

1.45ms

Timer

KF3

KF2

KF1

KF0

0.72ms

0.36ms

0.18ms

0.09ms

KICK (F)

$7X commands

Auto sequence track jump count setting

Data 1

Data 2

Data 3

Data 4

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

2¹⁵2¹⁴2¹³2¹²2¹¹2¹⁰2⁹2⁸2⁷2⁶2⁵2⁴2³2²2¹2⁰

Auto sequence track

jump count setting

• This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is

executed and to set the jump count when fine search is executed for auto sequencer.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count

depends on the mechanical limitations of the optical system.

• When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track

moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is

counted.

– 46 –

CXD3048R

$8X commands

Data 1

D2 D1

CD- DOUT DOUT

Data 2

D2 D1

Command

MODE

VCO

SEL2

VCO

SEL1

WSEL

ASHS SOCT0

specification ROM Mute Mute-F

Command bit C2PO timing

Processing

CDROM mode; average value interpolation and pre-value hold are not

performed.

CDROM = 1

CDROM = 0

1-3

Audio mode; average value interpolation and pre-value hold are performed.

Command bit

Processing

DOUT Mute = 1 When Digital Out is on ($B MD2 = 1), DOUT output is muted.

DOUT Mute = 0 When Digital Out is on, DOUT output is not muted.

Command bit

Processing

DOUT Mute F = 1 When Digital Out is on ($B MD2 = 1), DA output is muted.

DOUT Mute F = 0 DA output mute is not affected when Digital Out is either on or off.

MD2 Other mute conditions

DOUT Mute DOUT Mute F DOUT output

DA output for 48-bit slot

0dB

OFF

– ∞dB

0dB

– ∞dB

0dB

– ∞dB

See "Mute conditions" (1) to (5) under $AX commands for other mute conditions.

When $A4 DTSL1 = 1, the Digital Out from the bass boost or shock-proof is selected. See the description

of Digital Out.

– 47 –

CXD3048R

Command bit

WSEL = 1

WSEL = 0

Sync protection window width

±26 channel clock

Application

Anti-rolling is enhanced.

±6 channel clock

Sync window protection is enhanced.

In normal-speed playback, channel clock = 4.3218MHz.

Command bit

Function

ASHS = 0

ASHS = 1

The command transfer rate from the auto sequencer to the DSSP block is set to normal speed.

The command transfer rate from the auto sequencer to the DSSP block is set to half speed.

See "§4-8. CD-DSP Block Playback Speed" for settings.

Command bit

Processing

Subcode-Q is output from the SQSO pin.

SOCT0

SOCT1

The spindle speed measurement result is output from the SQSO pin. Input the

readout clock to SQCK. (See Timing Chart 2-5.)

Various signals are output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-4.)

The error rate is output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-6.)

$8X command TXOUT = 0 and $A8X command SDTO OUT = 0 must be set.

Data 2

D2 D1

Data 3

D2 D1

Command

MODE

specification

VCO

SEL2

VCO

SEL1

ASHS SOCT0

KSL3 KSL2 KSL1 KSL0

See above.

Command bit

VCOSEL2 = 0

VCOSEL2 = 1

Processing

Multiplier PLL VCO2 is set to normal speed.

Multiplier PLL VCO2 is set to approximately twice the normal speed.

Command bit

Processing

KSL3

KSL2

Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/1 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/2 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/4 frequency-divided.

Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/8 frequency-divided.

– 48 –

CXD3048R

Command bit

VCOSEL1 = 0

VCOSEL1 = 1

Processing

Wide-band PLL VCO1 is set to normal speed.

Wide-band PLL VCO1 is set to approximately twice the normal speed.

Command bit

Processing

KSL1

KSL0

Output of wide-band PLL VCO2 is 1/1 frequency-divided.

Output of wide-band PLL VCO2 is 1/2 frequency-divided.

Output of wide-band PLL VCO2 is 1/4 frequency-divided.

Output of wide-band PLL VCO2 is 1/8 frequency-divided.

Block Diagram of VCO Internal Path

VCO1SEL

1/1

1/2

No.1 VCO1

No.2 VCO1

To DSP interior

1/4

1/8

VCO1CS0

KSL3, 2

VCO1 internal path

1/1

1/2

VCO2SEL

VCO2

To DSP interior

1/4

1/8

KSL1, 0

VCO2 internal path

– 49 –

CXD3048R

$8X commands cont.

Data 4

Data 5

D2 D1

Data 6

D2 D1

Command

MODE

VCO1

CS0

SCOR

SEL

ERC4

SCSY SOCT1 TXON TXOUT OUTL1 OUTL0

See page 48.

specification

Command bit

VCO1CS0 = 0

VCO1CS0 = 1

Processing

Selects the No. 1 VCO1.

Selects the No. 2 VCO1.

The CXD3048R has two multiplier PLL VCO1s, and this command selects one of these VCO1s.

The two VCOs are No. 2 and No. 1 in order of the maximum frequency.

The block diagrams for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to KSL3 and VCO1CS0

shown on the previous page.

Command bit

ERC4 = 0

Processing

C2 error double correction is performed when DSPB = 1.

C2 error quadruple correction is performed even when DSPB = 1.

ERC4 = 1

Command bit

SCOR SEL = 0

SCOR SEL = 1

Processing

WDCK signal is output.

GRSCOR (protected SCOR) is output.

Used when outputting GRSCOR from the WDCK pin.

Command bit

Processing

SCSY = 0

SCSY = 1

No processing.

GRSCOR (protected SCOR) synchronization is applied again.

Used to resynchronize GRSCOR.

The rising edge signal of this command bit is used internally, so when resynchronizing GRSCOR, first return

the setting to "0" and then set to "1".

GRSCOR is the crystal accuracy SCOR signal obtained by removing the motor wow component.

This signal is synchronized with PCMDATA.

The resynchronization conditions are when GTOP = high.

Command bit

TXON = 0

Processing

When CD TEXT data is not demodulated, set TXON to "0".

When CD TEXT data is demodulated, set TXON to "1".

TXON = 1

See "§4-16. CD TEXT Data Demodulation".

– 50 –

CXD3048R

Command bit

TXOUT = 0

TXOUT = 1

Processing

Various signals except for CD TEXT are output from the SQSO pin.

CD TEXT data is output from the SQSO pin.

See "§4-16. CD TEXT Data Demodulation".

Command bit

Processing

OUTL1 = 0

OUTL1 = 1

WDCK and XPCK are output.

WDCK and XPCK outputs are set low.

Command bit

OUTL0 = 0

OUTL0 = 1

Processing

PCMD, BCK and LRCK are output.

PCMD, BCK and LRCK outputs are set low.

Data 7

Command

MODE

specification

OUTL2

Command bit

OUTL2 = 0

OUTL2 = 1

Processing

WFCK is output.

WFCK is set low.

The $A7X command XOE OUT must be set to "0".

– 51 –

CXD3048R

$9X commands

Data 1

D2 D1

Data 2

Command

BiliGL BiliGL

MAIN SUB

Function

specification

DSPB ASEQ

ON-OFFON-OFF

FLFC

Command bit

DSPB = 0

Processing

Normal-speed playback, C2 error quadruple correction.

Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1)

DSPB = 1

Normally FLFC = 0.

In CAV-W mode, set FLFC to "1" independently of the playback speed.

Command bit

BiliGL SUB = 0

BiliGL SUB = 1

BiliGL MAIN = 0

STEREO

SUB

BiliGL MAIN = 1

MAIN

Mute

Definition of bilingual capable MAIN, SUB and STEREO

The left channel input is output to the left and right channels for MAIN.

The right channel input is output to the left and right channels for SUB.

The left and right channel inputs are output to the left and right channels, respectively, for STEREO.

Data 3

Data 4

Data 5

Command

Function

specification

Data 6

Data 7

DIV4

This switches the digital PLL master clock.

Either the conventional mode or the 2/3 mode (2/3 of the conventional clock) can be selected.

Command bit

DIV4 = 0

Processing

Digital PLL master clock; conventional mode. (preset)

Digital PLL master clock; 2/3 mode.

DIV4 = 1

Note) Do not set DIV4 to "1" when DSPB = 0.

– 52 –

CXD3048R

$AX commands

Data 1

Data 2

Command

Audio CTRL

Mute

ATT PCT1 PCT2

SOC2

Command bit

Mute = 0

Meaning

Command bit

ATT = 0

Meaning

Attenuation off.

–12dB

Mute off if other mute

conditions are not set.

ATT = 1

Mute on. Peak register

reset.

Mute = 1

Mute conditions

(1) When register A mute = 1.

(2) When register 8 DOUT Mute F = 1 and Digital Out is on ($B command MD2 = 1).

(3) When GFS stays low for over 35ms (during normal-speed).

(4) When register 9 BiliGL MAIN = Sub = 1.

(5) When register A PCT1 = 1 and PCT2 = 0.

(1) to (3) perform zero-cross muting with a 1ms time limit.

Command bit

ECC error correction ability

Meaning

Normal mode

PCM Gain

PCT1

PCT2

× 0dB

Mute

C1: double; C2: quadruple

C1: double; C2: double

Level meter mode

Peak meter mode

Normal mode

× 0dB

Description of level meter mode (see Timing Chart 1-4.)

• When the LSI is set to this mode, it performs digital level meter functions.

• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.

The initial 80 bits are subcode-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are

15-bit PCM data (absolute values) and an L/R flag.

The final bit (L/R flag) is high when the 15-bit PCM data is from the left channel and low when the data is

from the right channel.

• The PCM data is reset and the L/R flag is inverted after one readout.

Then the measurement for the maximum value continues until the next readout.

– 53 –

CXD3048R

Description of peak meter mode (see Timing Chart 1-5.)

• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from

the left or right channel.

The 96-bit clock must be input to SQCK to read out this data.

• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal

In other words, the PCM maximum value register is not reset by the readout.

• To reset the PCM maximum value register to "0", set PCT1 = PCT2 = 0 or set the $AX command Mute.

• The subcode-Q absolute time is automatically controlled in this mode.

In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in

the memory. Normal operation is conducted for the relative time.

• The final bit (L/R flag) of the 96-bit data is normally "0".

• The pre-value hold and average value interpolation data are fixed to level (– ∞) for this mode.

Command bit

SOC2 = 0

Processing

The SENS signal is output from the SENS pin as usual.

The SQSO pin signal is output from the SENS pin.

SOC2 = 1

SENS output switching

• This command is used to output the SQSO pin signal from the SENS pin.

When SOC2 = 0, SENS output is performed as usual.

When SOC2 = 1, the SQSO pin signal is output from the SENS pin.

At this time, the readout clock is input to the SCLK pin.

Note) Perform the SOC2 switching when SQCK = SCLK = high.

Data 6

Data 3

Data 4

Data 5

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Audio CTRL

– 54 –

CXD3048R

$A4 commands (preset: $A4C800)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DTSLDTSLMCSL MCSL

SDSL SDSL SDSL

RSL1RSL0

(Signal select)

Data 7

D3 D2 D1 D0

Data 5

Data 6

D3 D2 D1 D0 D3 D2 D1 D0

max

EN CKOUT CKOUT SLD max

max

C2PO3 C2PO2 C2PO1 C2PO0

XSOE SL2 SL1 BBIN C2PO7 C2PO6 C2PO5 C2PO4

RSL1, RSL0:

These bits set the external buffer RAM.

RSL1

RSL0

Processing

The external buffer RAM is set to 4M bits.

No selected.

The external buffer RAM is set to 16M bits.

: preset

DTSL1, DTSL0: See the second half of the description of $A4 commands.

MCSL1:

This bit sets the DAC block master clock.

When "0", the DAC block master clock is set to 16.9344MHz (384fs). (default)

When "1", the DAC block master clock is set to 33.8688MHz (768fs).

This bit sets the shock-proof memory controller block master clock.

When "0", the shock-proof memory controller block master clock is set to 16.9344MHz (384fs).

(default)

MCSL0:

When "1", the shock-proof memory controller block master clock is set to 33.8688MHz (768fs).

This bit switches the command input method.

ENXSOE:

When "0", the command transfer clock and the SENS serial data readout clock are input

from the respective pins. (default)

When "1", the command transfer clock and the SENS serial data readout clock are input

from the CLOK pin.

The clock input is switched with the XSOE pin. At this time, connect the SCLK pin to high.

ENXSOE XSOE pin

CLOK pin

SCLK pin

SENS serial data readout

clock input

Command transfer clock input

SENS serial data readout

clock input

Command transfer clock input

SENS serial data readout

clock input

Connect to high.

Command transfer clock input Connect to high.

In addition, when ENXSOE is set to "1" and the SQSO pin signal output is read from the

SENS pin, the command input method is as follows.

At this time, connect the SCLK and SQCK pins to high.

See the command descriptions for $A command SOC2 and $8 commands TXOUT, SOCT0

and SOCT1.

– 55 –

CXD3048R

$A8 $8

SDTO TX SOC SOC

OUT OUT T0

ENXS XSOE $A

CLOK pin

SENS pin

pin SOC2

Command transfer

clock input

High or low output

SENS serial data

readout clock input

SENS output

Subcode-Q readout

clock input

Subcode-Q output

Readout clock input of Spindle speed

the spindle speed

measurement result

measurement

result output

Various signal readout Various signal

clock input

output

Error rate readout

clock input

Error rate output

CD TEXT data

readout clock input

CD TEXT data

output

Readout clock input of Shock-proof

shock-proof memory

controller serial data

memory controller

serial data output

: don't care

See "§1-4. Description of SENS Signals" for the SENS output.

See Timing Chart 2-5 for the spindle speed measurement result.

The output signals are PER7 to PER0, FOK, GFS, LOCK, EMPH, ALOCK and VF9 to

VF0. For details, see Timing Chart 2-4.

For the error rate timing, see Timing Chart 2-6.

CKOUTSL2, CKOUTSL1:

These bits select the clock output from the R4M pin.

When the crystal is 16.9344MHz and XTSL = high, the output frequency is halved.

CKOUTSL2 CKOUTSL1

Processing

4.2336MHz output

8.4672MHz (R8M) output

4.2336MHz (C4M) output

Changes in CAV-W mode and variable pitch mode.

: preset

DTSL1, DTSL0: These bits select the data output from the DOUT pin.

In external mode, the data input through the LRCKI, BCKI and PCMDI pins is used.

DOUT output in the following tables is valid when $34A commands DOUT EN1 and DOUT

EN2 are both 1. In this case, see "$34A commands".

When $34A commands DOUT EN1 and DOUT EN2 are both 0, see "§4-5-2. Digital Out

from DA Interface Input".

At this time, the data from the CD DSP is output from the DOUT pin with a subcode is added.

– 56 –

CXD3048R

SDSL2, SDSL1: These bits select the data input to the DAC block and the data output from the PCMD pin.

SLDBBIN:

This bit selects the data input to the DAC block and the data output from the PCMD and

DOUT pins.

max C2PO7 to max C2PO0:

These bits set the C2PO conditions.

max C2PO7 to max C2PO0

00000000 to 11111111

Ptocessing

The C2PO upper limit value reflected to mon C2PO and

added to the write prohibited condition.

When SLDBBIN = 0, the internally connected data is selected. (default)

DTSL1 DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block DOUT output

PCMD output

DSP mode

DSP & DAC mode

Shock-proof memory

controller mode

Shock-proof

memory controller memory controller

mode

Shock-proof

Shock-proof memory

controller & DAC mode

& DAC mode

DSP mode

DSP & DAC mode

Shock-proof memory

controller mode

Shock-proof

memory controller memory controller

mode

Shock-proof

Shock-proof memory

controller & DAC mode

mode

DSP mode

DSP & DAC mode

Shock-proof memory

controller mode

DSP mode

Shock-proof

memory controller

mode

Shock-proof memory

controller & DAC mode

DSP mode

DSP & DAC mode

Shock-proof memory

controller mode

External mode

Shock-proof

memory controller

mode

Shock-proof memory

controller & DAC mode

: preset

¹: The relationship between LRCK, BCK and PCMD changes according to the setting value.

When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency

changes when SDSL0 is switched.

When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and

PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set

SDSL1 and SDSL0 to the same value.

– 57 –

CXD3048R

When SLDBBIN = 1, the data input from the LRCKI, BCKI and PCMDI pins is selected.

DTSL1 DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block

DOUT output

PCMD output

DSP mode

External & DAC mode

External & DAC

mode

Shock-proof memory

controller mode

External & DAC mode

DSP mode

External & DAC mode

Shock-proof memory

controller mode

Shock-proof

memory controller

mode

External & DAC mode

DSP mode

External mode

External & DAC mode

DSP mode

Shock-proof memory

controller mode

External & DAC mode

DSP mode

External & DAC mode

External mode

Shock-proof memory

controller mode

External & DAC mode

¹: The relationship between LRCK, BCK and PCMD changes according to the setting value.

When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency

changes when SDSL0 is switched.

When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and

PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set

SDSL1 and SDSL0 to the same value.

– 58 –

CXD3048R

$A5 commands (when Data 2 D3 = 0, D2 = 0) (preset: $A504000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

AD7 AD6 AD5 AD4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

ZMUT

SMUT AD10 AD9 AD8

(Bass boost)

Data 5

Data 6

D3 D2 D1 D0 D3 D2 D1 D0

AD3 AD2 AD1 AD0 setup

ZMUTA:

This bit sets the zero detection analog mute on/off.

When "0", zero detection analog mute is on. (default)

When "1", zero detection analog mute is off.

When zero data is detected for both the left and right channels, the LPF block output is set

to center output.

SMUT:

This bit sets the soft mute on/off.

When "0", soft mute is off. (default)

When "1", soft mute is on.

AD10 to AD0:

These bits set the attenuation data. The attenuation data consists of 11 bits, and is set as

follows.

Attenuation data

7FF (h)

Audio output

+6.02dB

7FE (h)

+6.016dB

402 (h)

401 (h)

+0.017dB

+0.0085dB

400 (h)

0dB

3FF (h)

3FE (h)

–0.0085dB

–0.017dB

001 (h)

–60.206dB

000 (h)

– ∞

: preset

The audio output from 001 (h) to 7FF (h) is obtained using the following equation:

Attenuation data

Audio data output = 20 log

[dB]

1024

setup:

This bit can shorten the rise time of the VREFL and VREFR pins.

When "0", the rise time is not shortened. (default) (Recommendation setting when the

external capacitance is 1µF or less.)

When "1", the rise time is shortened. (Recommendation setting when the external

capacitance exceeds 1µF.)

Return setup to 0 after the VREFL and VREFR pins rise. (setup = 0 for normal use)

– 59 –

CXD3048R

$A5 commands (when Data 2 D3 = 0, D2 = 1) (preset: $A540A4)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

PDM OBIT OBIT

DAC HiCut BST

EMPH FILTER CL

PWDN ZDPL WOC

(Bass boost)

SEL

Data 5

D3 D2 D1 D0

PWDN:

ZDPL:

This bit sets the DAC block operation mode.

When "0", the DAC block clock is stopped. This makes it possible to reduce power

consumption. (default)

The zero detection flag for the headphone volume circuit side is output from the LRMU pin.

When "1", the DAC block operates normally.

This bit sets the zero detection flag polarity.

When "0", the LRMU pin is set low during mute. (default)

When "1", the LRMU pin is set high during mute.

When WOC = 1, the DAC sync window opens. This is used to synchronize the DAC.

This bit sets the digital de-emphasis on/off.

WOC:

DAC EMPH:

When "0", digital de-emphasis is off. (default)

When "1", digital de-emphasis is on.

HiCutFILTER:

BSTCL:

This bit sets the high-cut filter on/off.

When "0", the high-cut filter is off. (default)

When "1", the high-cut filter is on.

This bit sets the bass boost level clear on/off.

1: On; the set bass boost level is cleared to 0dB.

0: Off; normal operation (default)

PDMSEL:

This bit switches the PDM signal output from the DAC block.

When "0", connect the external resistors and capacitors to the VREFL and VREFR pins. (default)

When "1", connect the external capacitors to the VREFL and VREFR pins.

100Ω

AOUT1 (2)

Analog out

AOUT1 (2)

VREFL (R)

Analog out

2200pF

22kΩ

VREFL (R)

1µF

LPF external circuit example (PDMSEL = 1)

LPF external circuit example (PDMSEL = 0)

OBIT1, OBIT0: These bits set the word length of the serial data output from the PCMD pin.

The serial data word length can be selected only when the data output from the PCMD pin

is set to DAC output.

OBIT1

OBIT0

Serial data word length

20 bits

18 bits

16 bits

: preset

– 60 –

CXD3048R

$A5 commands (when Data 2 D3 = 1, D2 = 0) (preset: $A58000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

BBONBBONHBONHBON BBSL BBSL

HBSL HBSL BBST BBST

(Bass boost)

Vdwn1 Vdwn0

Data 5

D3 D2 D1 D0

BBST BBST BBST BBST

Vup1 Vup0 Uth Lth

BBON1, BBON0: These bits set the bass boost on/off and the turnover frequency.

BBON1

BBON0

Processing

Bass boost is off.

Bass boost is on and the turnover frequency is set to 125Hz.

Bass boost is on and the turnover frequency is set to 160Hz.

Bass boost is on and the turnover frequency is set to 200Hz.

: preset

HBON1, HBON0:These bits set the high boost on/off and the turnover frequency.

HBON1

HBON0

Processing

High boost is off.

High boost is on and the turnover frequency is set to 5kHz.

High boost is on and the turnover frequency is set to 7kHz.

: preset

BBSL1, BBSL0: These bits set the boost level for bass boost.

BBSL1

BBSL0

Processing

The boost level for bass boost is set to 10dB.

The boost level for bass boost is set to 14dB.

The boost level for bass boost is set to 18dB.

The boost level for bass boost is set to 22dB.

: preset

HBSL1, HBSL0: These bits set the boost level for high boost.

HBSL1

HBSL0

Processing

The boost level for high boost is set to 4dB.

The boost level for high boost is set to 6dB.

The boost level for high boost is set to 8dB.

The boost level for high boost is set to 10dB.

: preset

– 61 –

CXD3048R

BBST Vdwn1, BBST Vdwn0: These bits set the boost attack time (Vol Down) for bass and high boost.

Processing

BBST Vdwn1 BBST Vdwn0

The boost attack time for bass and high boost is set to standard.

The boost attack time for bass and high boost is set to fast.

The boost attack time for bass and high boost is set to slow.

: preset

BBST Vup1, BBST Vup0: These bits set the boost release time (Vol Up) for bass and high boost.

BBST Vup1 BBST Vup0

Processing

The boost release time for bass and high boost is set to standard.

The boost release time for bass and high boost is set to fast.

The boost release time for bass and high boost is set to slow.

: preset

BBST Uth:

BBST Lth:

This bit sets the bass and high boost Uth.

When "0", Uth is set to –1.9dB. (default)

When "1", Uth is set to –0.9dB.

This bit sets the bass and high boost Lth.

When "0", Lth is set to –12dB. (default)

When "1", Lth is set to –4.4dB.

When the volume rises above Uth, the boost level is reduced. The speed at which the boost level is reduced

is the attack time.

When the volume falls below Lth, the boost level is increased up to the setting value. The speed at which the

boost level is increased is the release time.

$A5 commands (when Data 2 D3 = 1, D2 = 1) (preset: $A5C000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

COMP

(Bass boost)

Data 5

D3 D2 D1 D0

PDM

INV

COMP ON:

PDM INV:

This bit sets the compressor on/off.

When "0", the compressor is off. (default)

When "1", the compressor is on.

This bit sets the DAC block PDM signal polarity.

When "0", the polarity is set to non-inverted. (default)

When "1", the polarity is set to inverted.

– 62 –

CXD3048R

$A6 commands (when Data 2 D3 = 0, D2 = 0) (preset: $A604000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

AD7 AD6 AD5 AD4

SMUT AD10 AD9 AD8

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

(Headphone)

Data 5

D3 D2 D1 D0

AD3 AD2 AD1 AD0

SMUT:

This bit sets the soft mute on/off.

When "0", soft mute is off. (default)

When "1", soft mute is on.

AD10 to AD0:

These bits set the attenuation data. The attenuation data consists of 11 bits, and is set as

follows.

Attenuation data

7FF (h)

Audio output

+6.02dB

7FE (h)

+6.016dB

402 (h)

401 (h)

+0.017dB

+0.0085dB

400 (h)

0dB

3FF (h)

3FE (h)

–0.0085dB

–0.017dB

001 (h)

–60.206dB

000 (h)

– ∞

: preset

The audio output from 001 (h) to 7FF (h) is obtained using the following equation:

Attenuation data

Audio data output = 20 log

[dB]

1024

– 63 –

CXD3048R

$A6 commands (when Data 2 D3 = 0, D2 = 1) (preset: $A640A4)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

PDM

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DAC HiCut BST

EMPH FILTER CL

PWDN ZDPL WOC

(Headphone)

SEL

Data 5

D3 D2 D1 D0

PWDN:

ZDPL:

This bit sets the headphone block operation mode.

When "0", the headphone block clock is stopped. This makes it possible to reduce power

consumption. (default)

When "1", the headphone block operates normally.

This bit sets the zero detection flag polarity. The zero detection flag for the headphone

volume circuit is output from the LRMU pin when $A6 PWDN = 0.

When "0", the LRMU pin is set low during mute. (default)

When "1", the LRMU pin is set high during mute.

When WOC = 1, the headphone sync window opens. This is used to synchronize the DAC.

This bit sets the digital de-emphasis on/off.

WOC:

DAC EMPH:

When "0", digital de-emphasis is off. (default)

When "1", digital de-emphasis is on.

HiCutFILTER:

BSTCL:

This bit sets the high-cut filter on/off.

When "0", the high-cut filter is off. (default)

When "1", the high-cut filter is on.

This bit sets the bass boost level clear on/off.

1: On; the set bass boost level is cleared to 0dB.

0: Off; normal operation (default)

PDMSEL

This bit switches the PDM signal output from the headphone block.

1 output

0 output

1 output

0 output

PDMSEL = 0

PDMSEL = 1

Left channel side waveform (Right channel side waveform is inverted.)

– 64 –

CXD3048R

$A6 commands (when Data 2 D3 = 1, D2 = 0) (preset: $A68000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

BBONBBONHBONHBON BBSL BBSL

HBSL HBSL BBST BBST

(Headphone)

Vdwn1 Vdwn0

Data 5

D3 D2 D1 D0

BBST BBST BBST BBST

Vup1 Vup0 Uth Lth

BBON1, BBON0: These bits set the bass boost on/off and the turnover frequency.

BBON1

BBON0

Processing

Bass boost is off.

Bass boost is on and the turnover frequency is set to 125Hz.

Bass boost is on and the turnover frequency is set to 160Hz.

Bass boost is on and the turnover frequency is set to 200Hz.

: preset

HBON1, HBON0:These bits set the high boost on/off and the turnover frequency.

HBON1

HBON0

Processing

High boost is off.

High boost is on and the turnover frequency is set to 5kHz.

High boost is on and the turnover frequency is set to 7kHz.

: preset

BBSL1, BBSL0: These bits set the boost level for bass boost.

BBSL1

BBSL0

Processing

The boost level for bass boost is set to 10dB.

The boost level for bass boost is set to 14dB.

The boost level for bass boost is set to 18dB.

The boost level for bass boost is set to 22dB.

: preset

HBSL1, HBSL0: These bits set the boost level for high boost.

HBSL1

HBSL0

Processing

The boost level for high boost is set to 4dB.

The boost level for high boost is set to 6dB.

The boost level for high boost is set to 8dB.

The boost level for high boost is set to 10dB.

: preset

– 65 –

CXD3048R

BBST Vdwn1, BBST Vdwn0:

These bits set the boost attack time (Vol Down) for bass and high boost.

BBST Vdwn1 BBST Vdwn0

Processing

The boost attack time for bass and high boost is set to standard.

The boost attack time for bass and high boost is set to fast.

The boost attack time for bass and high boost is set to slow.

: preset

BBST Vup1, BBST Vup0:

These bits set the boost release time (Vol Up) for bass and high boost.

BBST Vup1 BBST Vup0

Processing

The boost release time for bass and high boost is set to standard.

The boost release time for bass and high boost is set to fast.

The boost release time for bass and high boost is set to slow.

: preset

BBST Uth:

BBST Lth:

This bit sets the bass and high boost Uth.

When "0", Uth is set to –1.9dB. (default)

When "1", Uth is set to –0.9dB.

This bit sets the bass and high boost Lth.

When "0", Lth is set to –12dB. (default)

When "1", Lth is set to –4.4dB.

When the volume rises above Uth, the boost level is reduced. The speed at which the boost level is reduced

is the attack time.

When the volume falls below Lth, the boost level is increased up to the setting value. The speed at which the

boost level is increased is the release time.

$A6 commands (when Data 2 D3 = 1, D2 = 1) (preset: $A6C000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

COMP

(Headphone)

Data 5

D3 D2 D1 D0

PDM

INV

COMP ON:

PDM INV:

This bit sets the compressor on/off.

When "0", the compressor is off. (default)

When "1", the compressor is on.

This bit sets the headphone block PDM signal polarity.

When "0", the polarity is set to non-inverted. (default)

When "1", the polarity is set to inverted.

– 66 –

CXD3048R

$A7 commands (preset: $A7200000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

_(ShockA_-p7_roof

XOE

SL GTOP NOLIM SPSLREAD REF REF

MSL2 MSL1 MSL0

OUT

SEL ON

memory setting)

XQOK XWRE CHECK WDCK COM

Data 5

Data 6

Data 7

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

STA XWI XWI SPSLWQR A11 READREAD MON

SEL H2 H1 COM MON SEL S2

S1 SEL

ADDRST ADR

SEL

SL XQOK:

SL XWRE:

This bit sets the XQOK control mode.

When "0", XQOK should be controlled for the period from when SCOR goes high until

GRSCOR goes high. (default)

When "1", XQOK should be controlled for the period while GRSCOR is high.

This bit sets the XWRE control mode.

When "0", XWRE should be controlled for the period from when SCOR goes high until

GRSCOR goes high. (default)

When "1", XWRE should be controlled for the period while GRSCOR is high.

GTOP CHECK:This bit controls GRSCOR generation when GTOP is high.

When "0", the GRSCOR generation circuit is not resynchronized even when GTOP is high.

When "1", the GRSCOR generation circuit is resynchronized when GTOP goes high. (default)

NOLIM WDCK: Always set to "1".

SPSL COM:

This bit sets whether to control XQOK, XWRE and XRDE with pins or serial data.

When "0", XQOK, XWRE and XRDE should be controlled with pins. (default)

When "1", XQOK, XWRE and XRDE should be controlled with serial data ($A8).

Note) The Data 3 D3 and Data 6 D1 bits should be switched somultaneously.

READS2, READS1:

This bit sets the audio data readout speed from the shock-proof memory controller block.

READ2 READS2 READS1 Readout speed setting

1× speed readout

0.5× speed readout

0.25× speed readout

—

2× speed readout

: preset

The shock-proof memory controller interior should be resynchronized after the readout speed

is switched. Execute the $AAX ADPWO command for resynchronization.

– 67 –

CXD3048R

REF SEL:

This bit sets the DRAM refresh rate. (Use this bit in conjunction with the $AC command

REFSEL2.)

REFSEL2 REFSEL

Reflesh rate

11.51ms/2048 times

5.81ms/2048 times

46.44ms/2048 times

23.22ms/2048 times

: preset

REF ON:

This bit sets the DRAM refresh function on/off.

When "0", the refresh function is off. (default)

When "1", the refresh function is on.

XOE OUT:

This bit switches the WFCK pin output mode.

When "0", WFCK is output from the WFCK pin. (default)

When "1", XOE is output from the WFCK pin.

MSL2 to MSL0: These bits set the DRAM area that can be accessed from the microcomputer.

MSL2

MSL1

MSL0 DRAM area that can be accessed from the microcomputer

The entire DRAM area can be used as audio data.

32K bits

64K bits

128K bits

256K bits

512K bits

1M bits

2M bits

: preset

ADDRST SEL: This bit selects the address reset mode.

When "0", the conventional address reset is used. (default)

When "1", the address is reset by the ADDRST command.

This bit selects the remaining valid addresses.

ADRMO:

XWIH2:

When "0", the conventional remaining valid addresses are displayed. (default)

When "1", the remaining addresses from 0000000 to 1111111 are displayed.

The XWIH condition addition is selected.

When "0", the condition is added. (default)

When "1", the write speed condition is added to the write prohibited condition.

The XWIH condition addition is selected.

XWIH1:

When "0", the condition is not added. (default)

When "1", the condition of failure access to DRAM is added to the write prohibited condition.

This bit selects the XWRE, XQOK and XRDE outputs.

When "0", XWRE, XQOK and XRDE output is prohibited. (default)

When "1", XWRE, XQOK and XRDE output is allowed.

WQR MON:

– 68 –

CXD3048R

A11 SEL:

STA SEL:

This bit selects the A11 pin function.

When "0", the A11 pin is used as the A11 pin. (default)

When "1", the A11 pin is used as a low-active write prohibit factor.

This bit selects the shock-proof memory controller status output.

When "1", the conventional ESP status is output. (See §4-13-3.)

When "0", the new shock-proof memory controller status is output. (default)

The status readout when STA SEL = 0 is as follows.

Signal

D0 XWPHD

Description

0: Write prohibited

1: Address updated

0: No valid data

D1 QRCVD

D2 XEMP

D3 monGRSCOR 1: GRSCOR present

D4 monC2PO

D5 GTOP

1: C2PO of the setting value or higher present

1: GTOP present in the preceding GRSCOR

Don't care.

—

D7 AM13

D8 AM14

D9 AM15

D10 AM16

D11 AM17

D12 AM18

D13 AM19

D14 AM20

D15 AM21

D16

Address monitor

—

Don't care.

D17

Don't care.

D18 monADPCM

D19 XFUL

1: ADPCM compression error

0: No write area

D20 ROF

1: The DSP SRAM has overflowed.

1: The speed limit is exceeded for more than the set number

during one GRSCOR.

D21 SPOVER

D22 NOWR

1: Access is failed in the shock-proof memory controller.

Don't care.

D23

—

MONSEL:

This bit selects the COUT, XUGF, MIRR and XPCK pin functions.

When "0", these pins output the signals corresponding to the SRO1, MTSL1 and MTSL0

commands. (See the table on page 8.)

When "1", these pins output SCOR, QRCVD and GTOP, respectively.

– 69 –

CXD3048R

$A8 commands (preset: $A8F8)

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

XSOEO ADDR

SDTO

OUT

(Shock-proof

memory control)

XQOKXWRE XRDE XSOEO

XQOK, XWRE, XRDE:

When $A7 command SPSL COM = 1, XQOK, XWRE and XRDE are controlled with serial

data. (default: 1)

XSOEO:

This bit controls the serial data from the shock-proof block.

Shock-proof block data is loaded to the serial readout register by detecting the falling edge

of XSOEO.

XSOEO2:

ADDRST:

SDTO OUT:

This bit is used when the microcomputer reads data from the DRAM. (default: 1)

The shock-proof memory controller block loads the data from the DRAM to the serial

readout register by detecting the fall of XSOEO2.

This command is valid when $A7 command ADDRST SEL = 1.

When "0", no operations are performed. (default)

When "1", the VWA, WA and RA are all reset.

This bit is used to output serial data from the shock-proof block to the SQSO pin.

When "0", various signals are output from the SQSO pin. For details on these signals, see

$8X commands SOCT1, SOCT0 and TXOUT. (default)

When "1", the shock-proof block serial data is output from the SQSO pin.

– 70 –

CXD3048R

$A9 commands (preset: $A90000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

SubQ SubQ SubQ SubQ

A3 A2 A1 A0

(DOUT subcode-Q

setting)

Data 5

Data 6

Data 7

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

SubQ SubQ SubQ SubQ

SubQA3 to SubQA0, SubQD7 to SubQD0:

These bits set the Ubit inside the DOUT generation circuit in the DAC block. Note that these

bits have no effect on the DOUT generation circuit in the CD DSP block.

SubQA3 SubQA2 SubQA1 SubAD0 SubQD7 SubQD6 SubQD5 SubQD4 SubQD3 SubQD2 SubQD1 SubQD0

Setting contents

Control, address

Q10 Q11 Q12 Q13 Q14 Q15 Q16 Movement number

Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 INDEX number

Elapsed time within a

movement (minutes)

Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32

Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40

Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48

Elapsed time within a

movement (seconds)

Elapsed time within a

movement (frames)

Q49 Q50 Q51 Q52 Q53 Q54 Q55 Q56 (Set to "0".)

Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Absolute time (minutes)

Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Absolute time (seconds)

Q73 Q74 Q75 Q76 Q77 Q78 Q79 Q80 Absolute time (frames)

DON DCL DUP1 DUP0 DLD

(Control command)

DON: This bit sets the Ubit output on/off inside the DOUT generation circuit in the DAC block.

When "0", Ubit is not output. (default)

When "1", Ubit is output.

DCL: This bit clears the elapsed time within a movement to "0".

The elapsed time is cleared to "0" at the falling edge of DCL (DCL = 1 → 0). (default: DCL = 1)

DUP1: This bit sets the absolute time counter operate/stop.

When "0", the absolute time counter is stopped. (default)

When "1", the absolute time counter operates.

DUP0: This bit sets the elapsed time within a movement counter operate/stop.

When "0", the elapsed time within a movement counter is stopped. (default)

When "1", the elapsed time within a movement counter operates.

DLD: This bit is used when setting the INDEX number, elapsed time within a movement, and absolute

time.

When "0", the settings cannot be changed. (default)

When "1", the settings can be changed. Note that "0" is output for the INDEX number, elapsed

time within a movement, and absolute time while DLD = 1.

The control, address and movement number settings can be changed regardless of the DLD setting.

– 71 –

CXD3048R

$A9E commands (preset: $A9E00000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

A9E

(DRAM I/F)

DRD15 DRD14 DRD13 DRD12

DRWR DRADR

Data 5

Data 6

Data 7

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DRD11 DRD10 DRD9 DRD8 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 DRD0

DRWR:

This bit sets write/read for access from the microcomputer to the DRAM.

When "0", the read from DRAM mode is set. (default)

When "1", the write to DRAM mode is set.

DRADR:

This bit sets the address control method for access from the microcomputer to the DRAM.

When "0", relative address control is set. (default)

When "1", absolute address control is set.

DRD15 to DRD0: These bits set the data to be written to the DRAM for access from the microcomputer to

the DRAM.

$A9F commands (preset: $A9F00000)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

DADR DADR DADR DADR

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

A9F

(DRAM I/F)

DADR DADR DADR DADR

Data 5

Data 6

Data 7

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR

DADR19 to DADR0:

These bits set the DRAM address for access from the microcomputer to the DRAM.

– 72 –

CXD3048R

$AA commands (preset: $AA00004)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

SEL

ADP BIT BIT

ON SL1 SL0

ADP

(Compression

setting)

Data 5

Data 6

D3 D2 D1 D0 D3 D2 D1 D0

ADPCM ADPCM

ORMU

SEL

MUTE

ADPON:

This bit sets audio data compressed/uncompressed.

When "0", the audio data uses uncompressed mode. (default)

When "1", the audio mode is compressed mode.

BITSL1, BITSL0: These bits set the audio data compression mode.

BITSL1 BITSL0

Compression mode

4 bits

6 bits

8 bits

: preset

ADPWO:

The CD-DSP block LRCK and shock-proof memory controller block LRCK are resynchronized.

This command should be used when the read speed is changed by $A7 commands

READ2, READS2 and READS1.

When "0", not resynchronized. (default)

When "1", resynchronized.

Note) • Set the $AD command CDDSP SLEEP to 0 for resynchronization.

• ADPWO should be returned to "0" after ADPWO is set to "1" and one or more

LRCK cycle of CD-DSP block is waited.

GRSEL:

This bit selects the GRSCOR signal output. Note that GRSCOR is output from the WDCK

pin when $8 command SCOR SEL = 1.

When "0", the GRSCOR signal is output at the timing used inside the shock-proof memory

controller block. (default)

When "1", the GRSCOR signal generated by the CD DSP block is output.

This bit selects ADPCM compensation.

ADPCM SEL:

When "0", ADPCM is not compensated.

When "1", ADPCM is compensated.

ADPCM MUTE: This bit sets mute at ADPCM compensation.

When "0", it does not mute at ADPCM compensation.

When "1", it mutes at ADPCM compensation.

ORMU:

This bit controls the output signal from the LRMU pin.

When "0", the "0" detection flag for Lch and Rch (AND output) is output.

When "1", the OR output is made with the "0" detection flag for Lch and Rch (AND output)

and SYSM.

– 73 –

CXD3048R

$AB commands (preset: $AB000000)

Data 4

D3 D2 D1 D0

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

(EFM playability

enhancement

setting)

ARD

TEN

Data 5

Data 6

Data 7

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

ARDTEN:

This is the EFM playability enhancement setting.

When "0", the EFM playability enhancement function is off.

When "1", the EFM playability enhancement function is on.

Set this command in the condition when a disc is not being played back.

– 74 –

CXD3048R

$AC commands (preset: $AC0C001)

Data 1

Data 2

Data 3

Data 4

D3 D2 D1 D0

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

(Sync expansion

specification)

AVW

SFP5 SFP4 SFP3 SFP2 SFP1 SFP0

Data 5

Data 6

D3 D2 D1 D0 D3 D2 D1 D0

REF SLIM SLIM

OV4 OV3 OV2 OV1 OV0

SEL2

AVW:

This bit sets the sync protection window width automatic expansion function.

When "0", the sync protection window width automatic expansion function is off.

When "1", the sync protection window width automatic expansion function is on.

This setting is not affected by the sync forward protection times setting SFP5 to SFP0.

The sync protection window width (±6 channel clocks when WSEL = 0, ±26 channel

clocks when WSEL = 1) is widened 32 channel clocks at a time each time a sync mark

is inserted during the interval from the 16th forward protection until GFS goes high. When

the maximum window width is reached (when the window width exceeds 588 channel

clocks), GTOP goes high.

SFP5 to SFP0: These bits set the frame sync forward protection times. The setting range is from 1 to 3F (h).

For details on frame sync protection, see "§4-2. Frame Sync Protection".

Part of this command bit register is also used by $C SFP3 to SFP0. Of $AC SFP3 to

SFP0 or $C SFP3 to SFP0, the command bit setting made last is valid. When using an

existing status, set the value with $C SFP5 to SFP0. When using the $AC commands,

set $AC SFP3 to SFP0 to the value set by $C SFP3 to SFP0.

REFSEL2:

SLIM1, 0:

This bit sets the refresh rate to DRAM.

See the description of $A7 command REFSEL.

This bit sets the DRAM write speed limit value.

SLIM1

SLIM0

Write speed limit value

Up to 4.0× speed write

Up to 4.5× speed write

Up to 5.0× speed write

Up to 5.5× speed write

: preset

Note) This command is valid when $A7X XWIH2 = 1.

This bit sets the limit value of the speed violation number for one GRSCOR which is

reflected to XWIH.

OV4 to OV0:

OV4 to OV0

Limit value of speed violation number

Can be set from 1 to 31 times.

00000 to 11111

: Preset value: 00001

Note) • The violation speed is set with the $AC commands SLIM 1 and 0.

• This command is valid when $A7X XWIH2 = 1.

– 75 –

CXD3048R

$AD commands (preset: $AD040)

Data 4

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

HCAV ERCNT

SLEEP SLEEP

DSP DSSP ASYM ESP

SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP

LPF DSUB ASEQ

PCOL

ADCPS

(Sleep setting)

ADCPS:

This bit sets the operating mode of the DSSP block A/D converter.

When "0", the operating mode of the DSSP block A/D converter is set to normal. (default)

When "1", the operating mode of the DSSP block A/D converter is set to power saving.

This bit sets the operating mode of the DSP block.

DSP SLEEP:

When "0", the DSP block operates normally. (default)

When "1", the DSP block clock is stopped. This makes it possible to reduce power

consumption.

DSSP SLEEP: This bit sets the operating mode of the DSSP block.

When "0", the DSSP block operates normally. (default)

When "1", the DSSP block clock is stopped. In addition, the A/D converter and operational

amplifier in the DSSP block are set to standby mode. This makes it possible to reduce

power consumption.

ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1/VCO2.

When "0", the asymmetry correction circuit and VCO1/VCO2 operate normally. (default)

When "1", the operational amplifier in the asymmetry correction circuit is set to standby

mode. In addition, the multiplier PLL VCO1 and wide-band PLL VCO2 oscillation are

stopped. This makes it possible to reduce power consumption.

ESP SLEEP:

This bit sets the operating mode of the shock-proof memory controller block.

When "0", the shock-proof memory controller block operates normally. (default)

When "1", the shock-proof memory controller block clock is stopped. This makes it possible

to reduce power consumption.

LPF SLEEP:

This bit sets the operating mode of the analog low-pass filter block.

When "0", the analog low-pass filter block operates normally.

When "1", the analog low-pass filter block is set to standby mode. (default) This makes it

possible to reduce power consumption.

DSUB SLEEP: This bit sets the operating mode of the Ubit generation block inside the DOUT generation

circuit in the DAC block. This setting has no effect on the DOUT generation circuit in the

CD DSP block.

When "0", the Ubit generation block operates normally. (default)

When "1", The clock for the Ubit generation block inside the DOUT generation circuit in the

DAC block is stopped. This makes it possible to reduce power consumption. Also, in this

case Ubit is set to "0".

ASEQ SLEEP: This bit sets the operation mode of the servo auto sequencer block.

When "0", the servo auto sequencer operates normally. (default)

When "1", the servo auto sequencer block clock is stopped. This makes the power

consumption to be reduced.

PCOL:

The PCOL pin in DSP sleep mode is fixed to low.

When "0", the PCO pin gradually becomes low by the external filter time constant. (default)

When "1", the PCO pin digitally becomes low.

Note) Set DSP SLEEP to "1" so that DSP sleep mode is entered.

HCAV SLEEP: This bit sets the hard CAV block operation mode.

When "0", the hard CAV block operates normally. (default)

When "1", the hard CAV block clock is stopped. This makes the power consumption to be

reduced.

ERCNT SLEEP: This bit sets operation mode for the error rate counter block.

When "0", normally operates. (default)

When "1", the clock in the error rate counter block stops. This reduces the power consumption.

The DAC block clock can be stopped by setting $A5 command PWDN (when Data 2 D3 = 0, D2 = 1).

– 76 –

CXD3048R

$AE commands (preset: $AE0)

Data 4

D3 D2 D1 D0

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

(Variable pitch

setting)

VARI VARI WTC SCSY SENS SENS SENS SENS

ON USE C2PO (sub) SEL3 SEL2 SEL1 SEL0

Processing

Command bit

VARION = 0

VARION = 1

Variable pitch mode is off. (The internal clock uses the crystal reference.)

Variable pitch mode is on. (The internal clock uses the VCO2 reference.)

Command bit

VARIUSE = 0

VARIUSE = 1

Processing

Set VARIUSE = 0 when not using variable pitch mode.

Set VARIUSE = 1 when using variable pitch mode.

See "$DX commands" for the variable pitch range and example of use.

WTC C2PO:

This bit selects the write prohibit factor to DRAM.

When "0", write prohibition is not allowed by the C2PO error number or external input.

When "1", write prohibition is allowed by the C2PO error number or external input.

Use this command only when $8 CDROM = 0.

• Use this command in conjunction with the $AX command A11 SEL and $A4 commands

max C2PO7 to max C2PO0.

SCSY (sub):

This bit sets the GRSCOR resynchronization period.

See the $8X command SCSY. (Set the $8X command to "0" when using this bit.)

SENS SEL3 to SENS SEL0:

SENS SENS SENS SENS

SEL3 SEL2 SEL1 SEL0

SDTO TEXT SOCT SOCT XSOE XSOE

SENS switching

SENS serial data

Subcode Q

SOC2

OUT OUT

Various signals

Error rate

CD-TEXT

Shock-proof memory

controller status

Special area read

Special area status

VF0 to VF9

– 77 –

CXD3048R

$AF commands (preset: $AF8000)

Data 4

D3 D2 D1 D0

Data 1

Data 2

Data 3

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

MDS MDP

CTL UP

MDP

CTL4

SYG3 SYG2 SYG1 SYG0 MDP

EA EA EA

MDP

EA OUTSL1 OUTSL0

(Spindle servo

setting)

LPWR2

Data 5

D3 D2 D1 D0

MDP MDP MDP MDP

CTL3 CTL2 CTL1 CTL0

SYG3EA to SYG0EA:

These bits set the spindle drive output gain. However, this is valid only in CLV-N mode.

SYG3EA SYG2EA SYG1EA SYG0EA

GAIN

0 (– ∞dB)

0.125 (–18.1dB)

0.250 (–12.0dB)

0.375 (–8.5dB)

0.500 (–6.0dB)

0.625 (–4.1dB)

0.750 (–2.5dB)

0.875 (–1.2dB)

1.000 (0.0dB)

1.125 (+1.0dB)

1.250 (+1.9dB)

1.375 (+2.8dB)

1.500 (+3.5dB)

1.625 (+4.2dB)

1.750 (+4.9dB)

1.875 (+5.5dB)

: preset

MDP OUTSL1, MDP OUTSL0:

These bits set the spindle drive output method.

MDP OUTSL1

MDP OUTSL0

Spindle drive output

Ternary output from the MDP pin

Binary output from the MDS and MDP pins

Command-based MDP and MDS output control

: preset

– 78 –

CXD3048R

LPWR2:

The low output (brake pulse) of the MDP pin can be masked.

When "0", binary output is high or low output, and ternary output is high, low or high

impedance output. (default)

When "1", high or high impedance is output. This makes it possible to mask the brake pulse.

This bit sets the PWM output polarity according to the setting from the microcomputer.

(valid when MDP OUTSL1 = 0 and MDP OUTSL0 = 1)

When "0", the MDS pin output is set low.

MDS CTL:

MDP UP:

When "1", the MDS pin output is set high.

This bit switches the MDP pin according to the setting from the microcomputer. (valid when

MDP OUTSL1 = 0 and MDP OUTSL0 = 1)

When "0", the MDP pin output is set to PWM output.

When "1", the MDP pin output is set high.

MDP CTL4 to MDP CTL0:

These bits set the PWM output value according to the setting from the microcomputer.

(valid when MDP OUTSL1 = 0 and MDP OUTSL0 = 1)

The carrier frequency is 176.4kHz. (88.2kHz when set to quasi-double speed)

At the minimum value (MDP CTL4 to MDP CTL0 = 0), the MDP pin output is set low.

At the maximum value (MDP CTL4 to MDP CTL0 = 1F (h)), the MDP pin output is set high

for 31/32 intervals.

Note that when $AF command MDP UP = 1, the MDP pin output is set high regardless of

the MDP CTL4 to MDP CTL0 setting value.

Command-based MDP and MDS output control (MDP OUTSL1 = 0, MDP OUTSL0 = 1)

(1) Timing Chart 1 LPWR2 = 0, MDP UP = 0, MDP CTL4 to MDP CTL0 = 10 (h)

5.67µs (176kHz)

MDP

The MDP waveform ratio is set by MDP CTL4 to MDP CTL0.

When MDP CTL4 to MDP CTL0 = 10 (h), 10 (h)/20 (h) intervals are high.

(2) Timing Chart 2 LPWR2 = 0, MDP UP = 1, MDP CTL4 to MDP CTL0 = 10 (h)

MDP

When MDP UP = 1, MDP is fixed high regardless of MDP CTL4 to MDP CTL0.

(3) Timing Chart 3 LPWR2 = 1, MDP UP = 0, MDP CTL4 to MDP CTL0 = 10 (h)

MDP

When LPWR2 = 1, the low output of MDP binary output becomes high impedance.

– 79 –

CXD3048R

$BX commands

This command sets the traverse monitor count.

Data 1

Data 2

Data 3

Data 4

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

2¹⁵2¹⁴2¹³2¹²2¹¹2¹⁰2⁹2⁸2⁷2⁶2⁵2⁴2³2²2¹2⁰

Traverse monitor

count setting

• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control

goes off.

• The traverse monitor count is set to monitor the traverse status using the SENS outputs COMP and COUT.

The monitor output is set as follows.

Data 5

D2 D1

Data 6

Command

Traverse monitor

count setting

MTSL1 MTSL0 ASYE MD2

Command bit

Output data

MTSL1

MTSL0

XUGF

XPCK

MNT1

XPCK

FSTO

GFS

MNT2

XROF

GFS

C2PO

MNT3

GTOP

C2PO

MINT0

RFCK

C4M

: preset

However, the $39 command SRO1 and $A7 command MON SEL must be set to "0".

Command bit

ASYE = 1

Processing

Asymmentry is on.

Asymmentry is off.

ASYE = 0

: preset

Command bit

MD2 = 0

Processing

Digital Out on/off control. Off when "0".

Digital Out on/off control. On when "1".

MD2 = 1

: preset

– 80 –

CXD3048R

$CX commands

Data 1

D2 D1

Gain Gain Gain Gain Gain Gain

Data 2

Command

D2 D1

Spindle servo

PCC1 PCC0

coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0

Gain

CLV CTRL ($DX)

CLVS

• CLVS mode gain setting: GCLVS

Gain

MDS1 MDS0

Gain

CLVS

GCLVS

–12dB

–6dB

0dB

+6dB

• CLVP mode gain setting: GMDP: GMDS

Gain

MDP1 MDP0

Gain

MDS1 MDS0

Gain

GMDP

GMDS

–6dB

0dB

–6dB

0dB

+6dB

• DCLV overall gain setting: GDCLV

Gain

DCLV1 DCLV0

Gain

GDCLV

0dB

+6dB

+12dB

Command bit

Processing

PCC1

PCC0

The VPCO signal is output.

The VPCO pin output is high impedance.

The VPCO pin output is low.

The VPCO pin output is high.

• This command controls the VPCO pin signal.

The VPCO output can be controlled with this setting.

– 81 –

CXD3048R

Data 3

D2 D1

Data 4

D2 D1

Command

Spindle servo

coefficient setting

SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0

Command bit

SFP3 to SFP0

Processing

Sets the number of frame sync forward protection times. The setting range is from 1 to F (h).

Command bit

Processing

SRP3 to SRP0

Sets the number of frame sync backward protection times. The setting range is from 1 to F (h).

See "§4-2. Frame Sync Protection" regarding frame sync protection.

• The CXD3048R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC7 to EDC0

from the SQSO pin and monitor this data using a microcomputer.

In order to output error rate data, set $C commands for C1 and C2 individually, and set $8 commands

SOCT0 and SOCT1 to "1". Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.

Data 5

D2 D1

Data 6

D2 D1

Command

Spindle servo

coefficient setting

EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0

Preset value: 00h

Error rate monitor commands

Command bit

Prpcessing

EDC7 = 0 EDC6

EDC5

The [No C1 errors, pointer reset] count is output When "1".

The [One C1 error corrected, pointer reset] count is output When "1".

The [No C1 errors, pointer set] count is output When "1".

EDC4

EDC3

The [One C1 error corrected, pointer set] count is output When "1".

The [Two C1 errors corrected, pointer set] count is output When "1".

The [C1 correction impossible, pointer set] count is output When "1".

EDC2

EDC1

7350-frame count cycle mode ¹When "0".

73500-frame count cycle mode ²When "1".

EDC0

EDC7 = 1 EDC6

EDC5

The [No C2 errors, pointer reset] count is output When "1".

The [One C2 error corrected, pointer reset] count is output When "1".

The [Two C2 errors corrected, pointer reset] count is output When "1".

The [Three C2 errors corrected, pointer reset] count is output When "1".

The [Four C2 errors corrected, pointer reset] count is output When "1".

The [C2 correction impossible, pointer copy] count is output When "1".

The [C2 correction impossible, pointer set] count is output When "1".

EDC4

EDC3

EDC2

EDC1

EDC0

The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively,

and output every 7350 frames.

The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively,

and output every 73500 frames.

– 82 –

CXD3048R

$DX commands

Data 1

Command

Gain

CLVS

CLV CTRL

See "$CX commands".

Description

Command bit

TB = 0

Bottom hold at a cycle of RFCK/32 in CLVS mode.

Bottom hold at a cycle of RFCK/16 in CLVS mode.

Peak hold at a cycle of RFCK/4 in CLVS mode.

Peak hold at a cycle of RFCK/2 in CLVS mode.

TB = 1

TP = 0

TP = 1

Data 2

D2 D1

Data 3

D2 D1

Data 4

Command

CLV CTRL

VP7

VP6 VP5

VP4 VP3

VP2 VP1

VP0

CTL1 CTL0

The settings in CAV-W mode are as follows.

Command bit

Processing

Sets the spindle rotational velocity.

VP0 to VP7

Command bit

Processing

VPCTL1

VPCTL0

The setting of VP0 to VP7 is multiplied by 1.

The setting of VP0 to VP7 is multiplied by 2.

The setting of VP0 to VP7 is multiplied by 3.

The setting of VP0 to VP7 is multiplied by 4.

The above setting should be "0", "0" except for the CAV-W operating mode.

– 83 –

CXD3048R

The rotational velocity R of the spindle can be expressed with the following equation.

256 – n

R: Relative velocity at normal speed = 1

n: VP0 to VP7 setting value

R =

× l

l: Multiple set by VPCTL0, VPCTL1

Command bit

Description

VP0 to VP7 = F0 (h)

Playback at half (normal) speed

VP0 to VP7 = E0 (h) Playback at normal (double) speed

VP0 to VP7 = C0 (h)

Playback at (quadruple) speed

Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.

2. Values in parentheses are for when DSPB is "1".

3.5

2.5

DSPB = 1

1.5

DSPB = 0

0.5

VP0 to VP7 setting value [h]

– 84 –

CXD3048R

The settings in variable pitch mode are as follows.

Command bit

Processing

VPCTL1 to VPCTL0,

VP7 to VP0

Sets the pitch for variable pitch mode.

The pitch setting can be expressed with the following equation.

P: Pitch setting value

–n

P =

[%]

n: VPCTL1 and VPCTL0, VP7 to VP0 setting value (two's complement,

VPCTL1 = sign bit)

Command bit

VPCTL0 VP7 to VP0

00 (H)

Command setting

example

Pitch setting value [%]

VPCTL1

+51.2

$D60080

—

FF (H)

00 (H)

—

+25.7

+25.6

$D6FF80

$D600C0

FF (H)

00 (H)

—

+0.1

0.0

$D6FFC0

$D60000

FF (H)

00 (H)

—

–25.5

–25.6

$D6FF00

$D60040

E7 (H)

–48.7

$D6E740

The pitch setting range is from –48.7 to +51.2%.

The plus pitch setting should not exceed the playback speed given in the Recommended Operating Conditions.

An example of variable pitch mode commands is shown below.

$EX001 (Sets INV VPCO = 1.)

$AE4

$AEC

(Setting to enable variable pitch mode.)

(Turns on variable pitch mode. The internal clock uses the VCO2 reference.)

$D60A00 (Sets the pitch to –1.0%.)

$D60000 (Sets the pitch to 0.0%.)

$AE4

(Turns off variable pitch mode. The internal clock uses the crystal reference.)

– 85 –

CXD3048R

$EX commands

Command

Data 1

D2 D1

Data 2

D2 D1

Data 3

D2 D1

CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON

SPD mode

Command bit

Mode

Description

CM3

CM2

CM1

CM0

STOP Spindle stop mode.

KICK Spindle forward rotation mode.

Spindle reverse rotation mode. Valid only when LPWR = 0

in any mode.

BRAKE

Rough servo mode. When the RF-PLL circuit isn't locked,

CLVS this mode is used to pull the disc rotations within the RF-

PLL capture range.

CLVP PLL servo mode.

Automatic CLVS/CLVP switching mode.

CLVA

Used for normal playback.

See Timing Charts 1-6 to 1-29.

In the digital CLV servo, the sampling frequency of the internal digital filter is switched simultaneously with

the switching of CLVP/CLVS.

Then, the CLVS mode cut-off frequency fc is 70Hz when $D command TB = 0 or 140Hz when $D command

TB = 1.

Spindle control can be set to the ternary output of only MDP or the binary outputs of MDP and MDS by

$AF commands MDPOUTSL1 and MDPOUTSL0.

Command bit

Mode

Description

INV

VPCO

EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON

Crystal reference CLV

servo.

CLV-N

CLV-W

CAV-W

VCO2 reference CLV

servo.

Used for playback in

CLV-W mode.

Spindle control with

VP0 to VP7.

Spindle control with the

external PWM.

VCO-C VCO control

Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.

Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.

– 86 –

CXD3048R

Timing chart –

Ternary output

Timing chart –

Mode

LPWR

LPWR2

Command

Binary output

1-18 (a)

1-18 (b)

1-18 (c)

1-19 (a)

1-19 (b)

1-19 (c)

1-20 (a)

1-20 (b)

1-20 (c)

1-21 (a)

1-21 (b)

1-21 (c)

1-22 (a)

1-22 (b)

1-22 (c)

KICK

BRAKE

STOP

KICK

1-6 (a)

1-6 (b)

1-6 (c)

1-7 (a)

1-7 (b)

1-7 (c)

1-8 (a)

1-8 (b)

1-8 (c)

1-9 (a)

1-9 (b)

1-9 (c)

1-10 (a)

1-10 (b)

1-10 (c)

CLV-N

BRAKE

STOP

KICK

CLV-W

CAV-W

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

Timing chart –

Ternary output

Timing chart –

Binary output

Mode

LPWR

LPWR2

CLV-N

1-11

1-23

1-12

1-24

CLV-W

CAV-W

1-13

1-25

1-14 (EPWM = 0)

1-15 (EPWM = 0)

1-16 (EPWM = 1)

1-17 (EPWM = 1)

1-26 (EPWM = 0)

1-27 (EPWM = 0)

1-28 (EPWM = 1)

1-29 (EPWM = 1)

– 87 –

CXD3048R

Timing chart –

Ternary output

Timing chart –

Mode

LPWR

LPWR2

Command

Binary output

1-30 (a)

1-30 (b)

1-30 (c)

1-31 (a)

1-31 (b)

1-31 (c)

1-32 (a)

1-32 (b)

1-32 (c)

1-33 (a)

1-33 (b)

1-33 (c)

KICK

BRAKE

STOP

KICK

1-8 (a)

1-8 (b)

1-8 (c)

CLV-W

1-8 (a)

1-8 (b)

1-8 (c)

BRAKE

STOP

KICK

1-10 (a)

1-10 (b)

1-10 (c)

1-10 (a)

1-10 (b)

1-10 (c)

BRAKE

STOP

KICK

CAV-W

BRAKE

STOP

Timing chart –

Ternary output

Timing chart –

Binary output

Mode

LPWR

LPWR2

1-13

1-34

CLV-W

1-13

1-35

1-15 (EPWM = 0)

1-17 (EPWM = 1)

1-36 (EPWM = 0)

1-37 (EPWM = 0)

1-38 (EPWM = 1)

1-39 (EPWM = 1)

CAV-W

Data 4

Command

SPD mode

Gain Gain

CAV1 CAV0

INV

VPCO

See page 86.

• This sets the gain when controlling the spindle with VP7 to

Gain

CAV1

Gain

CAV0

Gain

VP0 in CAV-W mode.

0dB

Note) The Gain CAV1 and Gain CAV0 commands are invalid

–6dB

–12dB

–18dB

for spindle control with the external PWM.

– 88 –

Timing Chart 1-3

LRCK

48 bit slot

WDCK

CDROM = 0

C2PO

If C2 Pointer = 1,

data is NG

Rch 16-bit C2 Pointer

Lch 16-bit C2 Pointer

CDROM = 1

C2PO

C2 Pointer for upper 8 bits

C2 Pointer for lower 8 bits

C2 Pointer for upper 8 bits

C2 Pointer for lower 8 bits

Rch C2 Pointer

Lch C2 Pointer

Timing Chart 1-4

750ns to 120µs

SQCK

CRCF

D13

D14

L/R

SQSO

Subcode Q data

See "Subcode Interface"

15-bit peak data

Absolute value display, LSB first

Peak data

L/R flag

WFCK

SQCK

SQSO

96 clock pulses

L/R

CRCF

R/L

CRCF

16 bits

96-bit data

Peak data of this section

Hold section

Level Meter Timing

Timing Chart 1-5

WFCK

SQCK

96 clock pulses

CRCF

Measurement

CRCF

Measurement

Peak Meter Timing

CXD3048R

Ternary output from MDP pin ($AF MDPOUTSL1 = 0, MDPOUTSL0 = 0)

Timing Chart 1-6

CLV-N mode LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-7

CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-8

CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 0

KICK

BRAKE

STOP

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-9

CAV-W mode LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-10

CAV-W mode LPWR = 1, LPWR2 = 0

KICK

BRAKE

STOP

MDP

(a) KICK

(b) BRAKE

– 92 –

CXD3048R

Timing Chart 1-11

CLV-N mode LPWR = 0, LPWR2 = 0

n · 236 (ns) n = 0 to 31

Acceleration

MDP

132kHz

7.6µs

Deceleration

Timing Chart 1-12

CLV-W mode LPWR = 0, LPWR2 = 0

Acceleration

MDP

264kHz

3.8µs

Deceleration

Timing Chart 1-13

CLV-W mode LPWR = 1, LPWR2 = 0

Acceleration

MDP

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-14

CAV-W mode EPWM = LPWR = 0, LPWR2 = 0

Acceleration

MDP

264kHz

3.8µs

Deceleration

Timing Chart 1-15

CAV-W mode EPWM = 0, LPWR = 1, LPWR2 = 0

Acceleration

MDP

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

– 93 –

CXD3048R

Timing Chart 1-16

CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0

PWMI

Acceleration

MDP

Deceleration

Timing Chart 1-17

CAV-W mode EPWM = LPWR = 1, LPWR2 = 0

PWMI

MDP

Acceleration

The BRAKE pulse is masked when LPWR = 1.

Binary output from MDP and MDS pins ($AF MDPOUTSL1 = 1, MDPOUTSL0 = 0)

Timing Chart 1-18

CLV-N mode LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-19

CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

– 94 –

CXD3048R

Timing Chart 1-20

CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 0

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

MDS

MDP

Timing Chart 1-21

CAV-W mode LPWR = 0, LPWR2 = 0

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-22

CAV-W mode LPWR = 1, LPWR2 = 0

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

– 95 –

CXD3048R

Timing Chart 1-23

CLV-N mode LPWR = 0, LPWR2 = 0

MDS

Acceleration

Deceleration

MDP

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

Output waveforms with DCLV = 1

Timing Chart 1-24

CLV-W mode LPWR = 0, LPWR2 = 0

MDS

Acceleration

Deceleration

MDP

264kHz

3.8µs

Output waveforms with DCLV = 1

Timing Chart 1-25

CLV-W mode LPWR = 1, LPWR2 = 0

MDS

Acceleration

MDP

264kHz

3.8µs

Output waveforms with DCLV = 1

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-26

CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 0

Acceleration

Deceleration

MDP

264kHz

3.8µs

MDS

– 96 –

CXD3048R

Timing Chart 1-27

CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 0

Acceleration

MDP

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

MDS

Timing Chart 1-28

CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0

PWMI

Acceleration

MDS

MDP

Deceleration

Timing Chart 1-29

CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 0

PWMI

MDS

Acceleration

MDP

– 97 –

CXD3048R

Timing Chart 1-30

CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 1

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-31

CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 1

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-32

CAV-W mode LPWR = 0, LPWR2 = 1

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

Timing Chart 1-33

CAV-W mode LPWR = 1, LPWR2 = 1

KICK

BRAKE

STOP

MDS

MDP

MDS

MDP

(a) KICK

(b) BRAKE

– 98 –

CXD3048R

Timing Chart 1-34

CLV-W mode LPWR = 0, LPWR2 = 1

MDS

Acceleration

Deceleration

MDP

264kHz

3.8µs

Output waveforms with DCLV = 1

Timing Chart 1-35

CLV-W mode LPWR = 1, LPWR2 = 1

MDS

Acceleration

MDP

264kHz

3.8µs

Output waveforms with DCLV = 1

The BRAKE pulse is masked when LPWR = 1.

Timing Chart 1-36

CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 1

Acceleration

Deceleration

MDP

264kHz

3.8µs

MDS

– 99 –

CXD3048R

Timing Chart 1-37

CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 1

Acceleration

MDP

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

MDS

Timing Chart 1-38

CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 1

PWMI

Acceleration

MDS

MDP

Deceleration

Timing Chart 1-39

CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 1

PWMI

MDS

Acceleration

MDP

– 100 –

CXD3048R

[2] Subcode Interface

There are two methods for reading out a subcode externally.

The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK.

The subcode-Q can be read out after checking CRC of the 80 bits in the subcode frame.

The subcode-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR

comes correctly and CRCF is high.

§2-1. P to W Subcode Readout

Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)

§2-2. 80-bit Subcode-Q Readout

Fig. 2-2 shows the peripheral block of the 80-bit subcode-Q register.

• First, subcode-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC

check circuit.

• 96-bit subcode-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are

loaded into the parallel/serial register.

When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC

check) has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,

although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.

The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when

SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,

the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial

In other words, while reading out with a clock cycle shorter than this time constant, these registers will not be

rewritten by CRCOK and others.

• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial

For ring control 1, input and output are shorted during peak meter and level meter modes.

For ring control 2, input and output are shorted during peak meter mode.

This is because the register is reset with each readout in level meter mode, and to prevent readout

destruction in peak meter mode.

As a result, the 96-bit clock must be input in peak meter mode.

• The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak

meter mode" on page 95. See Timing Chart 2-3.

• The clock is input from the SQCK pin to perform these operations. The high and low intervals of the clock

should be between 750ns and 120µs.

– 101 –

CXD3048R

Timing Chart 2-1

Internal

PLL clock

4.3218 ± ∆MHz

WFCK

SCOR

EXCK

SBSO

750ns max

S0 · S1

WFCK

SCOR

EXCK

SBSO

S0·S1

Same

Subcode P.Q.R.S.T.U.V.W Read Timing

– 102 –

Block Diagram 2-2

(AFRAM)

(ASEC)

(AMIN)

ADDRS CTRL

80-bit S/P Register

SUBQ

SIN

B C D E F G H

Order

Inversion

H G F E D C B

80-bit P/S Register

ABS time load control

for peak value

Monostable

multivibrator

SHIFT

SQCK

CRCC

LOAD CONTROL

CRCF

Mix

Ring control 1

16-bit P/S register

Ring control 2

SQSO

Peak detection

Timing Chart 2-3

WFCK

SCOR

Determined by mode

SQSO

SQCK

CRCF1

CRCF2

80 or 96 Clock

Monostable

multivibrator

(Internal)

270 to 400µ when SQCK = high.

750ns to 120µs

SQCK

SQSO

CRCF

ADR0

ADR1

ADR2

ADR3

CTL0

CTL1

CTL2

CTL3

300ns max

Timing Chart 2-4

Example: $802000 latch

Set SQCK high during this interval.

XLAT

750ns or more

Internal signal latch

SQCK

SQSO

PER0

PER1

PER2

PER3

PER4

PER5

PER6

PER7

C1F0

C1F1

C1F2

C2F0

C2F1

C2F2

FOK

GFS

LOCK EMPH ALOCK

VF0

VF1

VF2

VF3

VF4

VF5

VF6

VF7

VF8

VF9

Signal

Description

PER0 to PER7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.

FOK

GFS

Focus OK.

High when the frame sync and the insertion protection timing match.

GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin

outputs low.

LOCK

EMPH

ALOCK

High when the playback disc has emphasis.

GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight

consecutive samples, this pin outputs low.

Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB,

VF9 = MSB.

VF0 to VF9

C1F2

C1F1

C1F0

Description

No C1 errors; C1 pointer reset

One C1 error corrected; C1 pointer reset

—

C2F2

C2F1

C2F0

Description

No C2 errors; C2 pointer reset

One C2 error corrected; C2 pointer reset

Two C2 errors corrected; C2 pointer reset

Three C2 errors corrected; C2 pointer reset

Four C2 errors corrected; C2 pointer reset

—

No C1 errors; C1 pointer set

One C1 error corrected; C1 pointer set

Two C1 errors corrected; C1 pointer set

C1 correction impossible; C1 pointer set

C2 correction impossible; C1 pointer copy

C2 correction impossible; C2 pointer set

CXD3048R

Timing Chart 2-5

Measurement interval (approximately 3.8µs)

Reference window

(132.2kHz)

Measurement pulse

(V16M/2)

Measurement counter

VF0 to VF9

Load

The relative velocity of the disc can be obtained with the following equation.

m + 1

R =

(R: Relative velocity, m: Measurement results)

VF0 to VF9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated

from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63

when it is rotating at double speed (when DSPB is low).

XLAT

Set SQCK high during this period.

750ns or more

SQCK

"H" or "L"

SQSO

VF0

VF1

VF2

VF3

VF4

VF5

VF6

VF7

VF8

VF9

– 106 –

Timing Chart 2-6

XLAT

SQCK

SQSO

C1 MSB 19 18 17 16 15 14 13 12 11 10

19 18 17 16 15 14 13 12 11 10

C1 error rate

C2 error rate

CXD3048R

[3] Description of Modes

This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations

for each mode are described below.

§3-1. CLV-N Mode

This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL

capture range is ±150kHz.

§3-2. CLV-W Mode

This is the wide capture range mode. This mode allows the conventional PLL to follow the rotational velocity of

the disc. This rotational following control uses the built-in VCO2. The spindle is the same CLV servo as for the

conventional series. Operation using the built-in VCO2 is described below.

When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is

stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc,

then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin.

CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must

return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow

according to the microcomputer software in CLV-W mode is shown in Fig. 3-2.

In CLV-W mode (normal), low power consumption is achieved by setting LPWR high. Control was formerly

performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set

high, deceleration pulses are not output, thereby achieving low power consumption mode.

Note) The capture range for this mode is theoretically up to the signal processing limit.

§3-3. CAV-W Mode

This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the

desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the

external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command

and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed

to quadruple speed. (See "$DX commands".) When controlling the spindle with the external PWM, the PWMI

pin is binary input which becomes KICK during high intervals and BRAKE during low intervals.

The microcomputer can know the rotational velocity using the internal master clock frequency as the

parameter. With XTAL (XTAI, XTAO) (384Fs) as the reference frequency, the result after measuring the high

interval by the internal master clock is output in 10 bits (VP0 to VP9) from the new CPU interface. These

measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple

speed. These values match those of the 256 – n for control with VP0 to VP7. (See Timing Chart 2-5.)

In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire

system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other

output signals from this LSI change according to the rotational velocity of the disc.

Note) The capture range for this mode is theoretically up to the signal processing limit.

Note) Set FLFC to "1" for this mode

– 108 –

CXD3048R

§3-4. VCO-C Mode

This is VCO control mode. In this mode, the oscillation frequency of the internal master clock (VCLK) can be

controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The VCLK oscillation frequency can be

expressed by the following equation.

1 (256 – n)

n: VP0 to VP7 setting value

1: VPCTL0, 1 setting value

VCLK =

The VCO1 oscillation frequency is determined by VCLK. The VCO1 frequency can be expressed by the

following equation.

• When DSPB = 0

VCO1 = VCLK ×

• When DSPB = 1

VCO1 = VCLK ×

– 109 –

CXD3048R

Operation mode

Spindle mode

CAV-W

CLVS

CLV-W

CLVP

Rotational velocity

Target speed

KICK

Time

LOCK

ALOCK

Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode

CLV-W Mode

CLV-W MODE

START

KICK

$E8000

Mute OFF $A00XXXX

CAV-W $E665X

(CLVA)

ALOCK = H ?

YES

CLV-W $E60CX

(CLVA)

(WFCK PLL)

YES

ALOCK = L ?

Fig. 3-2. CLV-W Mode Flow Chart

– 110 –

CXD3048R

VCO-C Mode

Access START

What is the playback speed when access ends?

(How many minutes

of absolute time?)

Calculate VP0 to VP7.

(Calculate n)

Switch to VCO control mode.

EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0

HIFC = VPON = 1

Transfer

$E00510

Transfer

Transfer VP0 to VP7. (

corresponds to VP0 to VP7.)

$DX

Track Jump

Subroutine

Switch to normal-speed playback mode.

EPWM = SFSL = VC2C = LPWR = 0

SPDC = ICAP = HIFC = VPON = 1

Transfer

$E66500

Access END

Fig. 3-3. Access Flow Chart Using VCO Control

– 111 –

CXD3048R

[4] Description of other functions

§4-1. Channel Clock Recovery by Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to

11T.

In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T,

that is the channel clock, is necessary.

In an actual player, a PLL is necessary to recover the channel clock because the fluctuation in the spindle

rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 4-1.

The CXD3048R has a built-in three-stage PLL.

• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary.

The output of this first-stage PLL is used as a reference for all clocks within the LSI.

• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.

• The third-stage PLL is a digital PLL that recovers the actual channel clock.

• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the

secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency

components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields

better playability. However, in this case the capture range becomes ±50kHz.

• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to

the conventional secondary loop.

– 112 –

CXD3048R

Block Diagram 4-1

CLV-W

CAV-W

Spindle rotation information

Clock input

XTAI

VPCO

1/2

1/32

CLV-N

XTSL

1/2

1/l

1/n

CLV-W

CAV-W

/CLV-N

LPF

l = 1, 2, 3, 4

(VPCTL0, 1)

n = 1 to 256

(VP7 to 0)

VCOSEL2

Microcomputer

control

VCTL

1/K

VCO2

(KSL1, KSL0)

2/1 MUX

VPON

1/M

1/N

PCO

FILI

FILO

CLTV

1/K

VCO1

(KSL3, KSL2)

VCOSEL1

Digital PLL

RFPLL

– 113 –

CXD3048R

§4-2. Frame Sync Protection

• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be

recognized, the data is processed as error data because the data cannot be recognized. As a result,

recognizing the frame sync properly is extremely important for improving playability.

• In the CXD3048R, window protection and forward protection/backward protection have been adopted for

frame sync protection. These functions achieve very powerful frame sync protection. There are two window

widths; one for cases where a rotational disturbance affects the player and the other for cases where there is

no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 12 , and the

backward protection counter to 3 . Concretely, when the frame sync is being played back normally and then

cannot be detected due to scratches, etc., a maximum of 12 frames are inserted. If the frame sync cannot be

detected for 13 frames or more, the window opens to resynchronize the frame sync.

In addition, immediately after the window opens and the resynchronization is executed, if a proper frame

sync cannot be detected within 3 frames, the window opens immediately.

Default values. These values can be set as desired by $C commands SFP3 to SFP0 and SRP3 to SRP0.

§4-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity.

For C2 correction, the code is created with 24-byte information and 4-byte parity.

Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.

• The CXD3048R uses refined super strategy to achieve double correction for C1 and quadruple correction for

C2.

• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the

C1 error status, the playback status of the EFM signal and the operating status of the player.

• The correction status can be monitored externally.

See Table 4-2.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an

average value interpolation was made for the data.

MNT3

MNT2

MNT1

MNT0

Description

C1 pointer reset

No C1 errors;

One C1 error corrected;

C1 pointer reset

—

No C1 errors;

C1 pointer set

C2 pointer reset

—

One C1 error corrected;

Two C1 errors corrected;

C1 correction impossible;

No C2 errors;

One C2 error corrected;

Two C2 errors corrected;

Three C2 errors corrected;

Four C2 errors corrected;

C2 correction impossible;

C1 pointer copy

C2 pointer set

Table 4-2.

– 114 –

CXD3048R

Timing Chart 4-3

Normal-speed PB

400 to 500ns

RFCK

MNT3

t = Dependent on error

condition

C1 correction

C2 correction

MNT2

MNT1

MNT0

Strobe

§4-4. DA Interface

• The DA interface supports the 48-bit slot interface.

48-bit slot interface

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.

When LRCK is high, the data is for the left channel.

The output format from the bass boost block supports 18 bits and 20 bits in addition to 16 bits.

– 115 –

Timing Chart 4-4

48-bit Slot Normal-speed Playback

LRCK

(44.1K)

BCK

(2.12M)

WDCK

PCMD

L14

L13 L12

L11 L10

Rch MSB

Lch MSB (15)

48-bit Slot Double-speed Playback

LRCK

(88.2K)

BCK

(4.23M)

WDCK

PCMD

Rch MSB

Lch MSB (15)

Timing Chart 4-5 (DAC output selected)

SDSL1 = 1, OBIT1 = 0, OBIT0 = 1

LRCK

(44.1K)

BCK

(2.12M)

WDCK

PCMD

L16 L15

L14

L13 L12

L11 L10

Rch MSB

Lch MSB (17)

SDSL = 1, OBIT1 = 0, OBIT0 = 0

PCMD

L14

L13 L12

L11 L10

L18 L17 L16 L15

Lch MSB (19)

CXD3048R

§4-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,

and the type 2 form 2 format for the manufacture of software.

The CXD3048R supports type 2 form 1.

This LSI supports two kinds of Digital Out generation methods; generation from the PCM data read out from

the disc, and generation from the DA interface inputs (PCMDI, LRCKI, BCKI).

The timing accuracy of output data depends on the signal accuracy input

to XTAI, XTAO pins in CLV-N mode, and the built-in VCO accuracy in VCO-C mode.

§4-5-1. Digital Out from PCM Data

The Digital Out is generated from the PCM data which is read out from the disc.

The clock accuracy of the channel status is automatically set to level II when the crystal clock is used and to

level III in CAV-W mode, VCO-C mode or variable pitch mode. In addition, the subcode-Q data matched twice

in succession with CRC check are input to the initial 4 bits (bits 0 to 3).

DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1.

Therefore, DOUT is set to off by setting the $B command MD2 to "0".

Digital Out C bit

From sub Q

ID0 ID1 COPY Emph

0/1

176

bit0 to 3 Subcode-Q control bits that matched twice in succesion with CRCOK

bit29

VPON or VARION: 1

Crystal: 0

Table 4-5-1.

– 118 –

CXD3048R

§4-5-2. Digital Out from DA Interface Input

The Digital Out is generated from the DA interface input.

Validity Flag and User Data

The Validity Flag is fixed to "0".

The User Data is fixed to "0" or it can be output according to the format by setting 0 data.

For the Q data, first set the Q1 to Q80 data using the $A90 to $A99 commands, then the set data can be

output according to the digital interface format using the $A9A command. In addition, CRC operations are

performed internally on the Q81 to Q96 data and then this data is output.

The data is output in the order shown in Table 4-5-2.

The setting flow is shown in Figs. 4-5 (a) and 4-5 (b). Fig. 4-5 (a) shows the case when changing all the data,

and Fig. 4-5 (b) the case when changing the INDEX, movement time and absolute time.

1164

Q96

Table 4-5-2.

– 119 –

CXD3048R

Channel Status Data

For the Channel Status Data, bits 0, 6 and 7 are fixed to "0". The following items can be set by bits 1, 2, 3 and 8.

a) Digital data/audio data

b) Digital copy enabled/prohibited

c) With/without emphasis

d) Category code (2 types possible)

Digital Out C bit

A/D COPYEMPH

SEL

CAT

176

Table 4-5-3.

Note) In this method, DOUT can be set to off by setting $B command MD2 to "0" and $34A command

DOUT EN to "0".

– 120 –

CXD3048R

START

$A900

$A990

Set the subcode-Q information.

Input with BCD code.

Wait time 13.3ms

Output the subcode-Q information.

Start the movement time and absolute time counts.

$A9A0F0

(DON = H, DUP1 = H, DUP0 = H)

Stop subcode-Q information output to D-out.

Stop the movement time and absolute time counts.

$A9A040

(DON = L, DUP1 = L, DUP0 = L)

$A900

$A990

Set the subcode-Q information.

Input with BCD code.

Wait time 13.3ms

Input $A9A0F0

(DON = H, DUP1 = H, DUP0 = H)

(Output the changed subcode-Q information.)

Fig. 4-5(a). Flow Chart for Settings Using Q Data

START

$A900

$A990

Set the subcode-Q information.

Input with BCD code.

Wait time 13.3ms

Output the subcode-Q information.

Start the movement time and absolute time counts.

$A9A0F0

(DON = H, DUP1 = H, DUP0 = H)

$A9A0C8

(DUP1 = L, DUP0 = L, DLD = H)

(Stop the movement time and absolute time counts.)

$A920

$A930

INDEX

Movement

time

Note) The INDEX, movement and absolute time data

$A950

$A970

output to D-out while making the settings is all "0".

Absolute

time

$A990

Wait time 13.3ms

Input $A9A0F0

(DUP1 = H, DUP0 = H, DLD = L)

(Output the changed subcode-Q information.)

Fig. 4-5(b). Flow Chart for Settings Using Q Data

– 121 –

CXD3048R

Digital Audio Data Input

The input signal of the digital audio data is input through the DAC input signal pins PCMDI, LRCKI and BCKI.

The input format supports the 48-bit slot, MSB first.

Mute Function

By setting the command bit DOUT_DMUT to "1", all the audio data portions in the Digital Out output can be

set to "0" without altering the Channel Status Data.

Input/Output Synchronization Circuit

In normal operation, the DAC automatically synchronizes with the input LRCK. However, synchronization may

not be achieved when the input data contains much jitter or during power-on, etc. In such cases, internal

operation should be forcibly resynchronized by setting the $34A command DOUT WOD to "1". Forced

synchronization is also required when the operating frequency is changed such as switching between CLV and

CAV, etc. Be sure to set DOUT WOD to "0" and then to "1" for forced resynchronization.

Resynchronization clears the internal frame counter so that the count starts over from frame 0 after the

resynchronization processing. In cases where automatic resynchronization processing is not desirable or the

user wants to do it manually, set the $34A command WINEN to "0" to disable the resynchronization circuit.

DOUT Circuit Clock System

For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the

DAC block. Set MCSL to "1" for 768fs, and to "0" for 384fs.

– 122 –

DOUT Block Input Timing Chart

48-bit slot

LRCK

BCKI

PCMDI

L14 L13

L12 L11 L10

Rch MSB

Lch MSB (15)

CXD3048R

§4-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence

command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move

are executed automatically.

The servo block operates according to the built-in program during the auto sequence execution (when XBUSY =

low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands

are accepted.) When the auto sequencer is used, $9X command A.SEC ON-OFF is turned on.

In addition, when using the auto sequence, turn the A.SEQ ON-OFF of register 9 on.

When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of

100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes

from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).

In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external

disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY

format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed

auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like

$40). See "[1] $4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by

inputting $4X0.

Although this command is explained in the format of $4X in the following command descriptions, the timer

value and timer range are actually sent together from the CPU.

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.

If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with

focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition,

blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling

edge of FZC after FZC has been continuously high for a longer time than E.

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled

servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are

not involved in this sequence.

• 1-track jump

When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance

with Fig. 4-7. Set blind A and brake B with register 5.

• 10-track jump

When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in

accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after

kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator.

Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle

becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

– 124 –

CXD3048R

• 2N-track jump

When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in

accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2¹⁶tracks,

note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps

when N is less than 16, and MIRR is used when N is 16 or more.

Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is

that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• Fine search

When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed

in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved

by controlling the traverse speed, and a longer distance jump can be performed by controlling the sled. The

track jump count N is set with register 7. N can be set to 2¹⁶tracks. After kicking the actuator and sled, the

traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with

number of tracks during which COMP falls with register B. After N tracks have been counted through COUT,

the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the

actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.)

Then, the tracking and sled servos are turned on.

Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should

be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For

example, set the target track count N – α for the traverse monitor counter which is set with register B, and

COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be set again.

• M-track move

When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in

accordance with Fig. 4-11. M can be set to 2¹⁶tracks. Like the 2N-track jump, COUT is used for counting

the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move

is executed by moving only the sled, and is therefore suited for moving across several thousand to several

ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted

through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator

has stabilized.

– 125 –

CXD3048R

Auto focus

Focus search-up

FOK = H

YES

Check whether FZC is

continuously high for

the period of time E set

with register 5.

FZC = H

YES

FZC = L

YES

Focus servo ON

END

Fig. 4-6-(a). Auto Focus Flow Chart

$47 Latch

XLAT

FOK

FZC

BUSY

Command for

DSSP block

$08

Blind E

$03

Fig. 4-6-(b). Auto Focus Timing Chart

– 126 –

CXD3048R

1 Track

Track FWD kick

sled servo OFF

(REV kick for REV jump)

WAIT

(Blind A)

COUT =

YES

Track REV

kick

(FWD kick for REV jump)

WAIT

(Brake B)

Track, sled

servo ON

END

Fig. 4-7-(a). 1-Track Jump Flow Chart

$48 (REV = $49) Latch

XLAT

COUT

BUSY

Blind A

Brake B

Command for

DSSP block

$25

$28 ($2C)

$2C ($28)

Fig. 4-7-(b). 1-Track Jump Timing Chart

– 127 –

CXD3048R

10 Track

Track, sled

FWD kick

WAIT

(Blind A)

(Counts COUT × 5)

COUT = 5 ?

YES

Track, REV

kick

Checks whether the COUT cycle

is linger than overflow C.

C = Overflow ?

YES

Track, sled

servo ON

END

Fig. 4-8-(a). 10-Track Jump Flow Chart

$4A (REV = $4B) Latch

XLAT

COUT

BUSY

COUT 5 counts

Blind A

Overflow C

$25

Command for

DSSP block

$2E ($2B)

$2A ($2F)

Fig. 4-8-(b). 10-Track Jump Timing Chart

– 128 –

CXD3048R

2N Track

Track, sled

FWD kick

WAIT

(Blind A)

Counts COUT for the first 16 times

and MIRR for more times.

COUT (MIRR) = N

YES

Track REV

kick

C = Overflow

YES

Track servo

WAIT

(Kick D)

Sled servo

END

Fig. 4-9-(a). 2N-Track Jump Flow Chart

$4C (REV = $4D) Latch

XLAT

COUT

(MIRR)

BUSY

COUT (MIRR)

N counts

Kick D

Blind A

$2A ($2F)

Overflow C

$26 ($27)

Command for

DSSP block

$2E ($2B)

$25

Fig. 4-9-(b). 2N-Track Jump Timing Chart

– 129 –

CXD3048R

Fine Search

Track Servo ON

Sled FWD Kick

WAIT

(Kick D)

Track Sled

FWD Kick

WAIT

(Kick F)

Traverse

Speed Ctrl

(Overflow G)

COUT = N?

YES

Track Servo ON

Sled REV Kick

WAIT

(Kick D)

Track Sled

Servo ON

END

Fig. 4-10-(a). Fine Search Flow Chart

$44 (REV = $45) Latch

XLAT

COUT

BUSY

Kick D

$26 ($27)

Kick F

Kick D

$27 ($26)

Traverse Speed Control (Overflow G)

Command for

DSSP block

COUT N counts

$2A ($2F)

$25

Fig. 4-10-(b). Fine Search Timing Chart

– 130 –

CXD3048R

M Track Move

Track Servo OFF

Sled FWD Kick

WAIT

(Blind A)

Counts COUT for M < 16.

Counts MIRR for M ≥ 16.

COUT (MIRR) = M

YES

Track, Sled

Servo OFF

END

Fig. 4-11-(a). M-Track Move Flow Chart

$4E (REV = $4F) Latch

XLAT

COUT

(MIRR)

BUSY

COUT (MIRR)

M counts

Blind A

$22 ($23)

Command for

DSSP block

$20

Fig. 4-11-(b). M-Track Move Timing Chart

– 131 –

CXD3048R

§4-7. Digital CLV

Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the

sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes.

In addition, the digital spindle servo gain is variable.

Digital CLV

CLVS U/D

MDS Error

Measure

MDP Error

Measure

Oversampling

Filter-1

2/1 MUX

CLV P/S

Gain

MDS

Gain

MDP

1/2

Mux

Gain

DCLV

CLV P/S

Oversampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

PWMI

Mode Select

LPWR

MDP

CLVS U/D: Up/down signal from CLVS servo

MDS error: Frequency error for CLVP servo

MDP error: Phase error for CLVP servo

PWMI:

Spindle drive signal from the microcomputer for CAV servo

Fig. 4-12. Block Diagram

– 132 –

CXD3048R

§4-8. CD-DSP Block Playback Speed

In the CXD3048R, the following playback modes can be selected through different combinations of the XTAI,

XTSL pins, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division

commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.

Mode

XTAI

XTSL

DSPB VCOSEL1

ASHS Playback speed

Error correction

768Fs

384Fs

0/1

1×

2×

4×

1×

2×

1×

C1: double; C2: quadruple

C1: double; C2: double

C1: double; C2: quadruple

C1: double; C2: double

C1: double; C2: quadruple

C1: double; C2: double

0/1

Actually, the optimal value should be used together with KSL3 and KSL2.

When $8 command ERC4 = 1, C2 is quadruple correction even when DSPB = 1.

The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for

details.

§4-9. Description of DAC Block and Shock-proof Memory Controller Block Circuits

The CXD3048R inputs data from the CD-DSP block to the DAC block via the shock-proof memory controller

block.

The data from the shock-proof memory controller block is output externally as bass-boosted data via the DBB

circuit.

When not using the DAC block, the data from the shock-proof memory controller block can be output directly to

the outside of the LSI.

Also, when not using the shock-proof memory controller, the data can be input directly from the CD-DSP block

to the DAC block.

The DAC block output format supports 16, 18 or 20 bits.

– 133 –

§4-10. DAC Block Input Timing

Fig. 4-13 shows the input timing chart to the DAC block.

The CXD3048R can transfer data from the CD-DSP block to the DAC block via an external route. This allows the data to be sent to the DAC block via an

audio DSP, etc.

Normal-speed Playback

LRCKI

(44.1k)

BCKI

(2.12M)

L14 L13

L12 L11 L10

Rch MSB

Lch MSB (15)

PCMDI

Double-speed Playback

LRCKI

(88.2k)

BCKI

(4.23M)

PCMDI

Lch MSB (15)

Rch MSB

Fig. 4-13. Input Timing to the DAC Block

CXD3048R

§4-11. Description of DAC Block Functions

Zero Data Detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0"

or all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is

performed independently for the left and right channels.

Mute flag output

The LRMU pin goes active when any one of the following conditions is met. (when $AA command ORMU = 0)

The polarity can be selected by the $A5X command ZDPL.

• When zero data is detected

• When a high signal is input to the SYSM pin and the state continues for approximately 300ms

• When the $A5 command SMUT is set and the state continues for approximately 300ms

Attenuation Operation

Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3

(Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the

command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and

approaches Y2. And, when the command X3 is sent before the audio output reaches Y2 (B or C in the

figure), the audio output approaches Y3 from the value (B or C in the figure) at that point.

0dB

400 (H)

–∞

000 (H)

23.2 [ms]

DAC Block Mute Operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

• When attenuation data of 000 (h) is set

• When $A5 command SMUT is set to "1"

• When a high signal is input to the SYSM pin

Soft mute off

Soft mute on

Soft mute off

0dB

–∞dB

23.2 [ms]

– 135 –

CXD3048R

Zero detection mute

Analog mute is applied to the respective channel when $AX command ZMUTA is set to "0" and zero data is

detected for the left or right channel. (See "Zero data detection".)

When $AX command ZMUTA is set to “0”, analog mute is applied even if the mute flag output condition is

met.

LRCK Synchronization

Synchronization is performed at the first rising edge of the LRCK input when reset.

After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must

be performed.

The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed

changes such as the following cases.

• When the XTSL pin switches between high and low

• When the $9 command DSPB setting changes

• When the $A4 command MCSL setting changes

• When operation switches between CLV mode and CAV mode

For resynchronization, set the $A5 command XWOC to "1", wait for one LRCK cycle or more, and then set

XWOC to "0".

Digital High and Bass Boost

High and bass boost without external parts is possible using the built-in digital filter.

Perform the following operations when turning boost off or when lowering the current boost level.

1. Set $A5X command BSTCL to "1".

2. Wait 20ms or more, set the boost level or turn boost off, then set $A5X command BSTCL to "0".

High-cut Filter

This filter lowers the high-frequency level by approximately 8dB.

The frequency response is shown in Fig. 4-14.

0.00

–2.00

–4.00

–6.00

–8.00

100

10k

Frequency [Hz]

Fig. 4-14. High-Cut Filter Frequency Response

– 136 –

CXD3048R

Compressor, Dynamic High and Bass Boost

1. Frequency Response and I/O Characteristics

Fig. 4-15 shows the frequency response for dynamic high boost and bass boost.

This figure shows the frequency response for a high boost turnover frequency of 5kHz and a bass boost

turnover frequency of 160Hz. The boost level and turnover frequency can be set independently for high

boost and bass boost. In addition, all frequencies are lowered by approximately 2dB in order to prevent

clipping, so the medium frequencies are –2dB output. The high boost and bass boost levels indicate the

relative values from this level.

Next, the compressor, high boost and bass boost I/O characteristics are shown in Fig. 4-17.

As shown in this figure, the compressor characteristics span all frequencies. In addition, the high boost and

bass boost characteristics are for when the input signal is sufficiently higher or lower than the turnover

frequency.

The boost levels can be set independently. Uth and Lth on the vertical axis are the gain control threshold

values, and the desired output value can be taken from the area enclosed by the parallelograms near these

levels. The Uth and Lth settings are described hereafter.

20.00

(1) HBSL1 = 0, HBSL0 = 0, BBSL1 = 0, BBSL0 = 0

(4)

18.00

16.00

(2) HBSL1 = 0, HBSL0 = 1, BBSL1 = 0, BBSL0 = 1

(3) HBSL1 = 1, HBSL0 = 0, BBSL1 = 1, BBSL0 = 0

(4) HBSL1 = 1, HBSL0 = 1, BBSL1 = 1, BBSL0 = 1

(3)

14.00

12.00

10.00

8.00

(2)

(1)

6.00

4.00

2.00

0.00

–2.00

100

10k

Frequency response [Hz]

Fig. 4-15. Digital Bass Boost Frequency Response

– 137 –

CXD3048R

2. Settings

When performing dynamic processing, the auditory volume and other characteristics change according to

the boost levels and various other settings. The values that can be set by the serial commands and the

resulting effects are described below.

2-1. Boost Level

The boost level can be set independently for the compressor, high boost and bass boost. Boost level here

refers to the maximum boost level when a low level signal is input. The boost level changes over time when

a high level signal is input in order to prevent clipping.

2-2. Gain Control Thresholds

The gain control thresholds are Uth and Lth. When the level exceeds Uth, the gain is reduced; when the

level falls below Lth, the gain is increased. If both Uth and Lth are set to large values, the volume increases

and the respective boost effects are emphasized. On the other hand, some sources may be clipped due to

the balance with the boost level. These values can be set independently for the compressor and high/bass

boost. The same values are shared for high and bass boost.

2-3. Attack Time, Release Time

The attack time represents the speed at which the gain is reduced after high level input, and the release

time represents the speed at which the gain is increased when the input level suddenly becomes smaller. If

these values are set to "fast", the boost effects increase. Like the gain control thresholds, these values can

be set independently for the compressor and high/bass boost.

2-4. Envelope Detection Release Time

This sets the output signal envelope coefficient used for gain control. When set to "fast", the boost effects

increase. This setting is shared by compressor and high/bass boost.

Attack time

Standard

Slow

Release time

Standard

Lch

High boost

Bass boost

+10dB

Uch

–12dB

–1.9dB

+14dB

Slow

+18dB

Slow

+22dB

Table 4-16. Recommended Dynamic Bass and High Boost Settings

– 138 –

CXD3048R

Input [dB]

Uth

Lth

Fig. 4-17. Dynamic Processing I/O Characteristics

Lth [dB]

–23

Uth [dB]

–8.0

Boost level [dB]

Compressor

High boost

Bass boost

–12/–4.4

–1.9/–0.9

4/6/8/10

10/14/18/22

– 139 –

CXD3048R

§4-12. LPF Block

The CXD3048R contains a secondary active LPF.

The LPF block application circuit is shown in Fig. 4-18.

100Ω

AOUT1 (2)

Analog out

2200pF

VREFL (R)

1µF

Fig. 4-18. LPF External Circuit

– 140 –

CXD3048R

§4-13. Description of Shock-proof Memory Controller Block Functions

§4-13-1. DRAM I/F

A 4M DRAM or 16M DRAM can be selected as the external buffer RAM. The 16M DRAM supports either row

address 2¹²and column address 2¹⁰or row address 2¹¹and column address 2¹¹.

Refresh is performed by data access, and the refresh cycle is approximately 11.6ms when 4M DRAM is

selected, or approximately 46.4ms (2¹⁰× 2¹²) or 23.2ms (2¹¹× 2¹¹) when 16M DRAM is selected.

In addition, XRAS-only-refresh is executed 14 times in order to initialize the RAM after the power is turned on

and the DRAM, which is to be used by the $A4X commands RSL1 and RSL0, is selected. Data access to the

DRAM is not possible during this period.

XRST

XRAS

Approximately 5.67µs

14 times

§4-13-2. Switching from Data Through Mode to Shock-proof

The CXD3048R performs refresh by data access.

When switching from (1) Shock-proof mode to (2) data through mode to (3) Shock-proof mode, be sure to

reset all of WA, VWA and RA before performing data access for (3).

– 141 –

CXD3048R

§4-13-3. CPU Serial Data Output (when $A7X STASEL = 1)

Data is read out by setting the XSOEO command low and inputting SQCK. The data contents at the falling

edge of the XSOEO command are output from the SQSO pin at the falling edge of SCK.

XSOEO

SQCK

Invalid

SQSO

D10

D11

D0: XWPHD

D1: QRCVD

Data write to DRAM prohibited signal (low for XFUL + ROF + WRNG)

Indicates whether XQOK was registered as a defined address after it was sent.

(High = registration OK)

D2: XEMP

D3: AM15

D4: AM16

D5: AM17

D6: AM18

D7: AM19

D8: AM20

D9: AM21

D10: XFUL

D11: ROF

Low when the DRAM is empty of valid data. (VWA = RA)

Address monitor; indicates the amount of valid data remaining.

Low when the DRAM is full and there is no write area.

High when the DSP RAM has overflowed.

Note) When GRSCOR is low, QRCVD is high when data write to the DRAM is enabled, even if a negative

pulse is input to XQOK.

– 142 –

CXD3048R

§4-13-4. Data Linking

In order to restart write after PCM data write to the DRAM has been interrupted due to sound skipping or other

factors, continuity must be maintained between the data written last and the subsequent data to be written.

Conventional systems fix an aim at the data linking point, compare the preceding DRAM reference data with

the data read from the disc, and then link the data when matching data is detected. However, when using

music software where a fixed pattern is repeated, this system may link the data at an incorrect point. In

addition, if pre-value hold or interpolation is performed at the point to be linked, data linking may not be

possible at all. In order to eliminate these data linking errors, the CXD3048R generates a crystal accuracy

SCOR (= GRSCOR) synchronized to the PCM data to allow data linking along the time axis, thus greatly

increasing the data linking accuracy.

§4-13-5. Data Processing

The CXD3048R accumulates PCM data from the CD-DSP block in an external buffer and then inputs the data

to the DAC block in sync with the internally generated Fs system clock. At this time, the PCM data is loaded

and read out at the same rate during normal playback, so data does not accumulate in the buffer RAM.

Therefore, the loading rate must be increased. This is accomplished by setting the CD-DSP block to double-

speed mode and doubling the loading rate until the RAM is full. When the RAM becomes full, data regeneration

from the disc stops temporarily and the RAM data is read out to create an empty area, at which point loading

is restarted. These operations are then repeated to effectively use the entire area inside the RAM.

Shock-proof

4M DRAM

CD-DSP

DAC

PCM Data Flow (Example for 4M × 1 mode)

§4-13-6. System Outline (when SLXQOK = 1 and SLXWRE = 1)

The addresses for accessing the buffer RAM data consist of a readout address (RA) and a write address (WA).

The data to be written is not always correct, and the subcodes, etc. must be constantly checked to make sure

the data is correct and there is no sound skipping. The CXD3048R checks subcode-Q using the CPU, and

defines the data by inputting a negative pulse to the XQOK pin. This defined address (VWA) is loaded to the

internal register and the data between VWA and RA is treated as valid data. WA advances at a speed twice

that of RA, and RA is written by WA and read out sequentially in the order registered by VWA. When RA

catches up to VWA, there is no more valid data and readout is prohibited (XEMP = low). In addition, when WA

catches up to RA, the buffer is full and write is prohibited (XWIH = low). In this manner, write to the RAM is

interrupted when the RAM becomes full and there is no write area or when sound skipping caused by

scratches, external disturbances or other factors is detected. Data

continuity must be ensured in order to restart write. Therefore, the

VWA

CXD3048R returns to the last defined address, and the CPU accesses

the defined address point it sent last (actually the data slightly before that

point) and reads the subcode-Q after the rising edge of SCOR. If the

subcode-Q matches the last defined address, XWRE is made to fall and

write is restarted when GRSCOR comes high within 7ms.

Note 1) If XWRE is made to fall when GRSCOR is low, XWIH goes

low and the write prohibited state results.

Valid data

Note 2) When GRSCOR is low, VWA is not updated even if a

negative pulse is input to XQOK. Therefore, set XQOK high

while GRSCOR is low.

– 143 –

CXD3048R

§4-13-7. Data Write (when SLXQOK = 1 and SLXWRE = 1)

The PCM data input from the DSP is loaded according to the Fs system clock inputs (BCKI, WDCI and LRCI),

and is written sequentially to the external DRAM according to WA when the XWRE pin input goes low and

internal write is enabled (XWIH pin output = high).

The written data must be checked by some means or other. The CXD3048R assumes data checking with

subcode-Q. In this case, the CPU reads subcode-Q triggered by the SCOR signal output from the DSP to

determine whether sound skipping occurred. If sound skipping is not detected, the CPU inputs a negative

pulse to the XQOK pin during the GRSCOR high interval which comes within 7ms, and the data written to WA

thus far is registered to VWA as data without sound skipping.

SCOR

No sound skipping = CRC OK

No sound skipping = CRC NG

SUBQ

GRSCOR

XQOK

WA → VWA

Write prohibition is determined by the internal status or by an external command. When prohibited by the

internal status, the XWIH pin goes low, and this status is established when any one of the following conditions

is met.

1. There is no empty area in the DRAM.

2. The DSP RAM has overflowed.

XFUL = low

ROF = high

3. XWRE was made to fall when GRSCOR is low.

4. The DRAM write speed exceeds the set value.

WRNG = high

SPOVER = high

(when $A7 command XWIH1 = 1)

5. Access to DRAM in the shock-proof memory controller block failed. NOWR = high

(when $A7 command XWIH2 = 1)

monC2PO = high

6. The number of C2PO errors exceeds the set value.

7. Write is prohibited by the external input (A11 pin).

($AE command WTC C2PO = 1)

(when $A7 command A11 SEL = 1

and $AE command WTC C2PO = 1)

When the XWIH pin goes low due to the above conditions, the CPU must set the XWRE pin high and then the

XWIH pin high.

After the CPU sends XQOK, it must check whether XQOK was registered as a defined address. This is

because if the above conditions arise at the same time XQOK is sent, XQOK becomes invalid and the

addresses defined by the CPU and the CXD3048R may not match. Therefore, the XWIH pin output is used as

the XQOK recognition signal (QRCVD) while XQOK is low. When QRCVD is high, this indicates that XQOK

was correctly registered as a defined address (VWA was updated). When QRCVD is low, this indicates one of

the following conditions.

1. Write is prohibited due to the above conditions.

2. XWRE is high.

Regarding condition 2, if XQOK is sent while the XWRE pin is high, WA, VWA and RA are all reset (when

GRSCOR is high).

– 144 –

CXD3048R

§4-13-8. Data Readout (when SLXQOK = 1 and SLXWRE = 1)

When data write starts, there is no valid data in the RAM so the XEMP pin is low. The XWRE pin goes from

high to low, and if there is no sound skipping or other problems with the CRC check at the next SCOR, XQOK

is sent during the GRSCOR high interval which comes within 7ms, and the defined address and valid data are

registered. At this point, the XEMP pin goes high for the first time and readout is enabled. Data readout follows

RA, and is performed in sync with the internally generated Fs system clocks. The readout data and the Fs

system clocks are output from the DATA and the BCK and LRCK pins, respectively.

RA is the address for reading out the written data that has been validated by VWA, and the area from VWA to

RA is the amount of valid data (|VWA – RA|). The upper 5 bits are output as AM21 to AM17. When RA catches

up to VWA and there is no more valid data (|VWA – RA| = 0), the XEMP pin goes low and readout is prohibited.

When this state occurs, the CPU must set the XRDE pin high to prohibit readout. To restart readout, valid data

must be registered as described above. The XEMP pin is held low until valid data is registered.

XWRE

XQOK

XEMP

XRDE

Note) After the XWRE pin goes from high to low, readout is enabled when valid data is registered by

the first XQOK. However, ensuring some difference between VWA and RA is recommended in

consideration of CRC NG, etc.

See also "Application Notes" for the control of the shock-proof memory controller block.

– 145 –

CXD3048R

§4-14. CPU to DRAM Access Function

The CXD3048R can establish a special area in the DRAM. This allows a microcomputer to read and write

optional 16-bit data to a portion of the DRAM area.

This function can be used to store and optionally read out demodulated CD TEXT data, etc.

The range of this special area is set by $A7, and can be selected in 8 steps from 32K to 2M bits.

Table 4-19 shows the addresses which can be specified according to the used DRAM capacity and the special

area setting value.

In addition, the address specification method can be selected from absolute and relative specification.

RSL

1 0

MSL

2 1 0

DRDR19 to DRDR0

specification range

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

— — — — — — —

00000 to 007FF

00000 to 00FFF

00000 to 01FFF

00000 to 03FFF

00000 to 07FFF

00000 to 0FFFF

00000 to 1FFFF

4M setting

0 0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

— — — — — — —

00000 to 007FF

00000 to 00FFF

00000 to 01FFF

00000 to 03FFF

00000 to 07FFF

00000 to 0FFFF

00000 to 1FFFF

16M setting 1 1

Table 4-19.

– 146 –

CXD3048R

Write and Read by Absolute Address Specification

WRITE

READ

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "1"

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "1"

Transfer an optical address

with the $A9F command

Transfer an optional address

with the $A9F command

L (Req NG)

Check SQSO

(A)

Check SQSO

(1)

H (Req OK)

Write optional data with the

$A9E command

(DRWR = 1, DRADR = 1)

Generate a readout request

with $A9E command

(DRWR = 0, DRADR = 1)

(B)

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "0"

Change $A8 command

XSOEO2 from "1" to "0"

L (NG)

END

Check SQSO

(2)

H (Data Ready)

Read 16-bit data from SQSO

and SQCK

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "0"

END

– 147 –

CXD3048R

Write Communication Timing

$A8

$A9F $A9E $A8

Command

XSOEO2

STDO OUT

SQSO

Readout Communication Timing

$A8

$A9F $A9E $A8

Command

XSOEO2

$A8

STDO OUT

SQCK

(1)

(2)

SQSO

D15

Readout Communication Operation

(1) Set STDO OUT to "1" to switch the serial communication line for special memory.

(2) Send the address command ($A9F), then check whether the DRAM related processing has completed

using the SQSO pin.

(3) The data read out from the DRAM is loaded to the communication block inside the LSI by sending the read

command ($A9E) and causing XSOEO2 to fall ($A8). However, the DRAM related processing requires a

check as to whether the data was loaded properly using the SQSO pin.

(4) The readout data is output from the SQSO pin by inputting 16 clocks from the SQCK pin.

– 148 –

CXD3048R

Write and Read by Relative Address Specification

READ

WRITE

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "1"

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "1"

Write the absolute address

(A) on page 147

Write the absolute address

(B) on page 147

PENDING

Write optional data with the

$A9E command

(DRWR = 1, DRADR = 0)

Generate a readout request

with $A9E command

(DRWR = 0, DRADR = 0)

L (Req NG)

Check SQSO

H (Req OK)

Check SQSO

H (Req OK)

Change $A8 command

XSOEO2 from "1" to "0"

and set SDTO OUT to "1"

END

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "0"

L (NG)

Check SQSO

H (Data Ready)

Read 16-bit data from SQSO

and SQCK

END

Set $A8 commands

XSOEO2 to "1" and

SDTO OUT to "0"

END

– 149 –

CXD3048R

§4-15. Asymmetry Correction

Fig. 4-20 shows the block diagram and circuit example.

ASYE command

ASYO

RFAC

–

ASYI

–

BIAS

Fig. 4-20. Asymmetry Correction Application Circuit

– 150 –

CXD3048R

§4-16. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to "1". While TXON is "1",

the CD TEXT demodulation circuit occupies the EXCK and SBSO pins, so connect EXCK to low and do not

use the data output from SBSO. Also, 26.7ms (max.) are required to demodulate the CD TEXT data correctly

after TXON is set to "1".

• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is

enabled by setting the command $8 Data 6 D2 TXOUT to "1". To read data, the readout clock should be input

to SQCK.

• The readable data are the CRC counting results for each pack and the CD TEXT data (16 bytes) except for

CRC data.

• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result,

although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Data which can be stored in the LSI is 1 packet (4 packs).

TXON

CD TEXT

Decoder

EXCK

SBSO

Subcode

Decoder

SQCK

SQSO

TXOUT

Fig. 4-21. Block Diagram of CD TEXT Demodulation Circuit

– 151 –

SCOR

SQSO

SQCK

16 Bytes

Pack4

4 bits

CRC

4 bits

16 Bytes

Pack1

16 Bytes

Pack2

16 Bytes

Pack3

Subcode Q Data

80 Clocks

CRCF

520 Clocks

TXOUT

(command)

CRC Data

ID1 (Pack1)

ID2 (Pack1)

ID3 (Pack1)

LSB

MSB LSB

MSB

LSB

CRC CRC CRC CRC

S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4

SQSO

SQCK

TXOUT

(command)

Fig. 4-22. CD TEXT Data Timing Chart

CXD3048R

[5] Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System (VDD: Supply voltage)

Focus servo

Sampling rate:

Input range:

Output format:

Other:

88.2kHz (when MCK = 128Fs)

1/4VDD to 3/4VDD

7-bit PWM

Offset cancel

Focus bias adjustment

Focus search

Gain-down

Defect countermeasure

Auto gain control

Tracking servo

Sampling rate:

Input range:

Output format:

Other:

88.2kHz (when MCK = 128Fs)

1/4V^DDto 3/4VDD

7-bit PWM

Offset cancel

E:F balance adjustment

Track jump

Gain-up

Defect countermeasure

Drive cancel

Auto gain control

Vibration countermeasure

Sled servo

Sampling rate:

Input range:

Output format:

Other:

345Hz (when MCK = 128Fs)

1/4VDD to 3/4VDD

7-bit PWM

Sled move

FOK, MIRR, DFCT signal generation

RF signal sampling rate: 1.4MHz (when MCK = 128Fs)

Input range:

Other:

1/4VDD to 3/4VDD

RF zero level automatic measurement

– 153 –

CXD3048R

§5-2. Digital Servo Block Master Clock (MCK)

The clock with 2/3 frequency of the crystal is supplied to the digital servo block.

XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default is "0" for each command)

The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.

Mode

XTAI

FSTO

256Fs

512Fs

XTSL

—

XT4D

—

XT2D

XT1D

Frequency division ratio

MCK

256Fs

128Fs

512Fs

256Fs

128Fs

384Fs

768Fs

—

1/2

—

1/2

1/4

Fs = 44.1kHz, —: don't care

Table 5-1.

– 154 –

CXD3048R

§5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)

The CXD3048R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the

measurement results to control the servo effectively. This AVRG measurement and compensation is necessary

to initialize the CXD3048R, and is able to cancel the DC offset.

AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of

256 samples, and then loads these values into each AVRG register.

The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38.

Measurement is on when the respective command is set to "1".

AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is

received.

The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.)

Monitoring requires that the upper 8 bits of the command register are 38 (h).

XLAT

2.9 to 5.8ms

SENS

(= XAVEBSY)

Max. 1µs

AVRG measurement completed

Timing Chart 5-2.

VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to

compensate the FE, TE and SE signals.

FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals.

TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals.

RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.

RFLC:

(RF signal Ð RF AVRG) is input to the RF In register.

"00" is input when the RF signal is lower than RF AVRG.

(TE signal Ð VC AVRG) is input to the TRK In register.

(TE signal Ð TE AVRG) is input to the TRK In register.

(FE signal Ð VC AVRG) is input to the FCS In register.

(FE signal Ð FE AVRG) is input to the FCS In register.

(FE signal Ð FE AVRG) is input to the FZC register.

TCL0:

TCL1:

VCLC:

FLC1:

FLC0:

Two methods of canceling the DC offset are assumed for the CXD3048R. These methods are shown in Figs. 5-

3a and 5-3b.

An example of AVRG measurement and compensation commands is shown below.

$38 08 00 (RF AVRG measurement)

$38 20 00 (FE AVRG measurement)

$38 00 10 (TE AVRG measurement)

$38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1]; corresponds to Fig. 5-3a.)

See the description of $38 for these commands.

– 155 –

CXD3048R

§5-4. E:F Balance Adjustment Function (See Fig. 5-3.)

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS search, the traverse

waveform appears in the TE signal due to disc eccentricity.

In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold

filter by setting D5 (TBLM) of $38 to "1".

The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC

Next, setting D2 (TLC2) of $38 to "1" compensates the values obtained from the TE and SE input pins with the

TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.)

§5-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to "1". (See

Fig. 5-3.)

When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9

to D1 (D9: MSB).

In addition, the RF jitter can be monitored by setting the $8 command SOCT to "1". (See "DSP Block Timing

Chart".)

The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to "1". The FBIAS register functions

as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.

The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.

When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to

FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this

time, SENS goes high and the counter stop can be monitored.

Here, assume the FBIAS setting value FB9

to FB1 and the FBIAS LIMIT value FBL9 to

FBL1 are set in status A. For example, if

command registers FBUP = 0, FBV1 = 0,

FBV0 = 0 and FBSS = 1 are set from this

status, down count starts from status A and

approaches the set LIMIT value. When the

LIMIT value is reached and the FBIAS value

matches FBL9 to FBL1, the counter stops

and the SENS pin goes high. Note that the

up/down counter counts at each sampling

cycle of the focus servo filter. The number of

steps by which the count value changes can

be selected from 1, 2, 4 or 8 steps by FBV1

and FBV0. When converted to FE input, 1

step corresponds to 1/512 × VDD/2.

FBIAS setting value (FB9 to FB1)

LIMIT value (FBL9 to FBL1)

SENS value

A: Register mode

B: Counter mode

C: Counter mode (when stopped)

– 156 –

CXD3048R

RFDC from A/D

to RF In register

–

RF AVRG

RFLC

SE from A/D

TE from A/D

to SLD In register

to TRK In register

–

TLC1 · TLD1

TLC2 · TLD2

–

TE AVRG

TRVSC

TLC1

TLC2

FE from A/D

to FCS In register

–

FE AVRG

FBIAS

FLC1

FLC0

FBON

to FZC register

–

Fig. 5-3a.

RFDC from A/D

to RF In register

–

RF AVRG

RFLC

SE from A/D

TE from A/D

to SLD In register

to TRK In register

–

TLC0 · TLD0

TLC2 · TLD2

–

TLC0

VC AVRG

TRVSC

TLC2

VCLC

FE from A/D

to FCS In register

–

FE AVRG

FBIAS

FLC0

FBON

to FZC register

–

Fig. 5-3b.

– 157 –

CXD3048R

§5-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop

gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also

obtains the optimal gain for each disc.

The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of

the command register are 38 (h), the completion of AGCNTL operation can be confirmed by monitoring the

SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".)

Setting D9 and D8 of $38 to "1" sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation.

Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described

hereafter) must be disabled.

XLAT

Max. 11.4µs

SENS

(= AGOK)

AGCNTL completion

Timing Chart 5-4.

Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking

AGCNTL) due to AGCNTL.

These coefficients change from 01 to 7F (h), and they must also be set within this range when written

externally.

After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from

the SENS pin with the serial readout function (described hereafter).

AGCNTL related settings

The following settings can be changed with $35, $36 and $37.

FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (h)

TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (h)

AGS;

Self-stop on/off

AGJ;

Convergence completion judgment time

Internally generated sine wave amplitude (AGF)

Internally generated sine wave amplitude (AGT)

AGCNTL sensitivity 1 (during rough adjustment)

AGCNTL sensitivity 2 (during fine adjustment)

Rough adjustment on/off

AGGF;

AGGT;

AGV1;

AGV2;

AGHS;

AGHT;

Fine adjustment time

Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting

values. In addition, these setting values must be within the effective setting range. The default settings

aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each

constituent element of the servo loop, FG and TG values should be set as necessary.

– 158 –

CXD3048R

AGCNTL default operation has two stages.

In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select

256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.

The sensitivity at this time can be selected from two types with AGV1.

In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach

the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the

second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops

changing, the CXD3048R confirms that the AGCNTL coefficient has not changed for a certain period of time

(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)

This self-stop mode can be canceled by setting AGS to "0".

In addition, the first stage is omitted for AGCNTL operation when AGHS is set to "0".

An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in

Fig. 5-5.

Initial value

Slope AGV1

AGCNTL coefficient value

Slope AGV2

Convergence value

AGHT

AGJ

AGCNTL

Start

AGCNTL

completion

SENS

Fig. 5-5.

Note) Fig. 5-5 shows the case where the AGCCNTL coefficient converges from the initial value to a smaller

value.

– 159 –

CXD3048R

§5-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)

Command D23 to D20 D19 to D16

name

1 0 — — FOCUS SERVO ON (FOCUS GAIN NORMAL)

1 1 — — FOCUS SERVO ON (FOCUS GAIN DOWN)

0 — 0 — FOCUS SERVO OFF, 0V OUT

FOCUS

CONTROL

0 0 0 0

0 — 0 — FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT

0 — 0 0 FOCUS SEARCH VOLTAGE DOWN

0 — 0 0 FOCUS SEARCH VOLTAGE UP

—: don't care

Table 5-6.

FCS Search

FCS search is required in the course of turning on the FCS servo.

Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation.

Fig. 5-8 shows the signals for sending $08 (FCS on) after that.

$00 $02 $03

$08

FCSDRV

FOK

FZC comparator level

FZC

Fig. 5-7.

Fig. 5-8.

– 160 –

CXD3048R

§5-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)

When the upper 4 bits of the serial data are 2 (h), TZC is output to the SENS pin.

Command D23 to D20 D19 to D16

name

0 0 — — TRACKING SERVO OFF

0 1 — — TRACKING SERVO ON

1 0 — — FORWARD TRACK JUMP

1 1 — — REVERSE TRACK JUMP

— — 0 0 SLED SERVO OFF

— — 0 1 SLED SERVO ON

TRACKING

MODE

0 0 1 0

— — 1 0 FORWARD SLED MOVE

— — 1 1 REVERSE SLED MOVE

—: don't care

Table 5-9.

TRK Servo

The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.

In addition, when the TRK servo is on and D17 of $1 is set to "1", the TRK servo filter switches to gain-up

mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected

with the anti-shock circuit (described hereafter) enabled.

The CXD3048R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting

D16 of $1. (See Table 5-17.)

SLD Servo

The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by

multiplying this value by 1×, 2×, 3×, or 4× set using D17 and D16 when D18 = D19 = 0 is set with $3. (See

Table 5-10.)

SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low

when the SLD servo is on, the SLD servo turns off.

Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned

off. These operations are disabled by setting D6 (LKSW) of $38 to "1".

Command D23 to D20 D19 to D16

name

0 0 0 0 SLED KICK LEVEL (basic value × ±1)

0 0 0 1 SLED KICK LEVEL (basic value × ±2)

SELECT

0 0 1 1

0 0 1 0 SLED KICK LEVEL (basic value × ±3)

0 0 1 1 SLED KICK LEVEL (basic value × ±4)

Table 5-10.

– 161 –

CXD3048R

§5-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and

loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits.

An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is

generated from the average of this envelope waveform.

The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value

from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)

The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and

D4, respectively, of $3C.

Peak Hold

Bottom Hold

Peak Hold

MIRR Comp

– Bottom Hold

(Mirror comparator level)

MIRR

Fig. 5-11.

DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is

generated by comparing the difference between these two peak hold waveforms with the DFCT comparator

level. (See Fig. 5-12.)

The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Peak Hold1

Peak Hold2

SDF

– Peak Hold1

(Defect comparator level)

DFCT

Fig. 5-12.

– 162 –

CXD3048R

§5-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become

easily dislocated due to scratches or defects on discs.

Specifically, this operation is achieved by detecting scratches and defects with the DFCT signal generation

circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT

went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)

In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to "1".

Hold filter

Error signal

Input register

Hold register EN

DFCT

Servo filter

Fig. 5-13.

§5-11. Anti-shock Circuit

When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the

servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.

Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is

increased. (See Fig. 5-14.)

The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator

level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.

This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See

Table 5-17.)

This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up

mode by inputting high level to the ATSK pin.

When the upper 4 bits of the command register are 1 (h), vibration detection can be monitored from the SENS

pin. It can also be monitored from the ATSK pin by setting $3F command ASOT to "1".

ATSK

Anti-shock

filter

SENS

Comparator

TRK gain-up

filter

TRK

PWM Gen.

TRK gain normal

filter

Fig. 5-14.

– 163 –

CXD3048R

§5-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to

turn on.

The brake circuit prevents these phenomenon.

In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing

the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator

traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15

and 5-16.)

Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by

loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.

The brake circuit can be turned on and off by D18 of $1. (See Table 5-17.)

In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1 and SFBK2 of

$34B)

Outer track → Inner track

Inner track → Outer track

REV FWD

JMP JMP

FWD REV

JMP JMP

Servo ON

TRK

DRV

TRK

DRV

Trace

MIRR

TZC

Edge

TZC

Edge

TRKCNCL

TRK DRV

(SFBK OFF)

TRK DRV

(SFBK OFF)

TRK DRV

(SFBK ON)

TRK DRV

(SFBK ON)

SENS

TZC out

SENS

TZC out

Fig. 5-15.

Fig. 5-16.

name

Command D23 to D20 D19 to D16

1 0 — — ANTI SHOCK ON

0 —— — ANTI SHOCK OFF

— 1 — — BRAKE ON

— 0 — — BRAKE OFF

TRACKING

CONTROL

0 0 0 1

— — 0 — TRACKING GAIN NORMAL

— — 1 — TRACKING GAIN UP

— —— 1 TRACKING GAIN UP FILTER SELECT 1

— —— 0 TRACKING GAIN UP FILTER SELECT 2

—: don't care

Fig. 5-17.

– 164 –

CXD3048R

§5-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by

loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among

three different phases according to the COUT signal application.

• HPTZC: For 1-track jumps

Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by

a cut-off 1kHz digital HPF; when MCK = 128Fs.)

• STZC: For COUT generation when MIRR is externally input and for applications other than COUT

generation.

This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)

• DTZC: For high-speed traverse

Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance

with the MIRR signal delay during high-speed traverse.

The COUT signal output method is switched with D15 and D14 of $3C.

When D15 = 1:

STZC

When D15 = 0 and D14 = 0: HPTZC

When D15 = 0 and D14 = 1: DTZC

When DTZC is selected, the delay can be selected from two values with D14 of $36.

§5-14. Serial Readout Circuit

The measurement and adjustment results specified beforehand by serial command $39 can be read out from

the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 5-18, Table 5-19 and "Description of

SENS Signals".)

Specified commands

See the table on page 180.

XLAT

tSPW

DLS

· · ·

SCLK

1/fSCLK

Serial Readout Data

(SENS pin)

MSB

LSB

Fig. 5-18.

Item

Symbol

Min.

Typ.

Max.

Unit

MHz

SCLK frequency

SCLK pulse width

Delay time

fSCLK

SPW

DLS

31.3

µs

Table 5-19.

During readout, the upper 8 bits of the command register must be 39 (h).

– 165 –

CXD3048R

§5-15. Writing to Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and

transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin

rises. (The coefficient RAM cannot be rewritten during this period.)

After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address

of the coefficient RAM.

The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and

D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is

received. When rewriting multiple coefficients continuously, be sure to wait 11.3µs (when MCK = 128Fs) before

sending the next rewrite command.

§5-16. PWM Output

FCS, TRK and SLD PWM format outputs are described below.

In particular, FCS and TRK use a double oversampling noise shaper.

Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.

MCK

(5.6448MHz) ↑

↑

Output value +A

Output value –A

64tMCK

Output value 0

64tMCK

SLD

64tMCK

SFDR

SRDR

AtMCK

FCS/TRK

32tMCK

FFDR/

TFDR

MCK

tMCK

FRDR/

TRDR

MCK

tMCK

MCK =

≈ 180ns

5.6448MHz

Timing Chart 5-20.

VCC

DRV

RDR

FDR

Fig. 5-21. Drive Circuit

– 166 –

CXD3048R

§5-17. Servo Status Changes Produced by LOCK Signal

When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off

in order to prevent SLD free-running.

Setting D6 (LKSW) of $38 to "1" deactivates this function.

In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.

This enables microcomputer control.

§5-18. Description of Commands and Data Sets

$34

D15 D14 D13 D12 D11 D10

KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

When D15 = 0.

KA6 to KA0: Coefficient address

KD7 to KD0: Coefficient data

$348 (preset: $348 000)

D15 D14 D13 D12 D11 D10

PGFS1PGFS0PFOK1PFOK0

MRS MRT1 MRT0

These commands set the GFS signal hold time. The hold time is inversely proportional to the playback speed.

PGFS1 PGFS0

Processing

High when the frame sync is at the correct timing, low when not the correct timing.

High when the frame sync is at the correct timing, low when continuously not the

correct timing for 2ms or longer.

High when the frame sync is at the correct timing, low when continuously not the

correct timing for 4ms or longer.

High when the frame sync is at the correct timing, low when continuously not the

correct timing for 8ms or longer.

These commands set the FOK signal hold time. See $3B for the FOK slice level.

These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.

PFOK1 PFOK0

Processing

High when the RFDC value is higher than the FOK slice level, low when lower than

the FOK slice level.

High when the RFDC value is higher than the FOK slice level, low when continuously

lower than the FOK slice level for 4.35ms or more.

High when the RFDC value is higher than the FOK slice level, low when continuously

lower than the FOK slice level for 10.16ms or more.

High when the RFDC value is higher than the FOK slice level, low when continuously

lower than the FOK slice level for 21.77ms or more.

– 167 –

CXD3048R

MRS:

This command switches the time constant for generating the MIRR comparator level of the

MIRR generation circuit.

When "0", the time constant is normal. (default)

When "1", the time constant is longer than normal.

The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc.,

can be suppressed by setting MRS = 1.

MRT1, MRT0:

These commands limit the time while MIRR = high.

MRT1

MRT0 MIRR maximum time [ms]

No time limit

1.10

2.20

4.00

: preset

$34A (preset: $34A 150)

D15 D14 D13 D12 D11 D10

A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT

SEL

EN1 DMUT WOD EN EN2

Processing

Command bit

A/DSEL = 0

A/DSEL = 1

Bit 1 of the channel status data is output as audio data.

Bit 1 of the channel status data is output as other than audio data.

Command bit

COPY EN = 0

COPY EN = 1

Processing

Bit 2 of the channel status data is output as digital copy prohibited.

Bit 2 of the channel status data is output as digital copy enabled.

Command bit

EMPH D = 0

EMPH D = 1

Processing

Bit 3 of the channel status data is output as without pre-emphasis.

Bit 3 of the channel status data is output as with pre-emphasis.

Command bit

CAT b8 = 0

CAT b8 = 1

Processing

Bit 8 of the channel status data is output as "0".

Bit 8 of the channel status data is output as "1".

Command bit

Processing

DOUT EN1 = 0 The DOUT signal, generated from the PCM data read out from the disc, is output.

DOUT EN1 = 1 The DOUT signal, generated from the DA interface input, is output.

– 168 –

CXD3048R

$34A commands cont.

Command bit

Processing

DOUT DMUT = 0 Digital Out output is normally output.

DOUT DMUT = 1 All the audio data portions are output in zero, with Digital Out output as it is.

Command bit

Processing

DOUT WOD = 0 The DOUT sync window is not open.

DOUT WOD = 1 The DOUT sync window is open.

Command bit

Processing

Automatic synchronization to the input LRCK to match the phase with the internal

processing is disabled.

WIN EN = 0

WIN EN = 1

Automatic synchronization to the input LRCK to match the phase with the internal

processing is disabled.

Command bit

Processing

DOUT EN2 = 0 Set to "0" when not generating Digital Out from the DA interface input.

DOUT EN2 = 1 Set to "1" when generating Digital Out from the DA interface input.

DOUT

EN1

DOUT

DMUT

Other mute

conditions

DOUT

Mute

DOUT

Mute F

$B MD2

DOUT output

OFF

—

0dB

The output from the PCM

data read out from a disc.

– ∞dB

The output from the PCM

data read out from a disc.

0dB

—

The output from the DA

interface input.

– ∞dB

The output from the DA

interface input.

—: don't care

See "Mute conditions" (1) and (3) to (5) of $AX commands for the other mute conditions.

See $8 commands for DOUT Mute and DOUT Mute F.

– 169 –

CXD3048R

$34B (preset: $34B 000)

D15 D14 D13 D12 D11 D10

SFBK1 SFBK2

LB1SN LB2SNLB2SM

The low frequency can be boosted for brake operation.

See §5-12 for brake operation.

SFBK1: When "1", brake operation is performed by setting the LowBooster-1 input to "0".

This is valid only when TLB1ON = 1. Preset is "0".

SFBK2: When "1", brake operation is performed by setting the LowBooster-2 input to "0".

This is valid only when TLB2ON = 1. Preset is "0".

See the $34C command booster setting for LB1SN, LB2SN and LB2SM.

$34C (preset: $34C 000)

D15 D14 D13 D12 D11 D10

THBON FHBON TLB1ON FLB1ON TLB2ON

HBST1HBST0 LB1S1 LB1S0 LB2S1 LB2S0

These bits turn on the boost function. (See §5-20. Filter Composition.)

There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off

independently.

THBON: When "1", the high frequency is boosted for the TRK filter. Preset is "0".

FHBON: When "1", the high frequency is boosted for the FCS filter. Preset is "0".

TLB1ON: When "1", the low frequency is boosted for the TRK filter. Preset is "0".

FLB1ON: When "1", the low frequency is boosted for the FCS filter. Preset is "0".

TLB2ON: When "1", the low frequency is boosted for the TRK filter. Preset is "0".

The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted.

For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump.

The following commands set the boosters. (See §5-20. Filter Composition.)

HBST1, HBST0: TRK and FCS HighBooster setting.

HighBooster has the configuration shown in Fig. 5-22a, and can select three different

combinations of coefficients BK1, BK2 and BK3. (See Table 5-23a.)

An example of characteristics is shown in Fig. 5-24a.

These characteristics are the same for both the TRK and FCS filters.

The sampling frequency is 88.2kHz (when MCK = 128Fs).

LB1S1, LB1S0, LB1SN:

TRK and FCS LowBooster-1 setting.

LowBooster-1 has the configuration shown in Fig. 5-22b, and can select six different

combinations of coefficients BK4, BK5 and BK6. (See Table 5-23b.)

An example of characteristics is shown in Fig. 5-24b.

These characteristics are the same for both the TRK and FCS filters.

The sampling frequency is 88.2kHz (when MCK = 128Fs).

LB2S1, LB2S0, LB2SN, LB2SM:

TRK LowBooster-2 setting.

LowBooster-2 has the configuration shown in Fig. 5-22c, and can select six different

combinations of coefficients BK7, BK8 and BK9. (See Table 5-23c.)

An example of characteristics is shown in Fig. 5-24c.

This booster is used exclusively for the TRK filter.

The sampling frequency is 88.2kHz (when MCK = 128Fs).

Note) Fs = 44.1kHz

– 170 –

CXD3048R

HighBooster setting

BK2

BK3

HBST0

HBST1

BK1

BK3

Z ^–1

—

–120/128

–124/128

–126/128

96/128

112/128

120/128

BK1

BK2

—: don't care

Fig. 5-22a.

Table. 5-23a.

LowBooster-1 setting

BK4

BK5

Characteristic

diagram

BK6

LB1S1 LB1S0 LB1SN

BK6

Z ^–1

—

–255/256

–511/512

–1023/1024 4095/4096 1/4

–127/128

–255/256

–511/512

1023/1024 1/4

2047/2048 1/4

BK4

BK5

255/256

511/512

Fig. 5-22b.

1023/1024

—: don't care

Table. 5-23b.

LowBooster-2 setting

Characteristic

diagram

BK9

LB2S1 LB2S0 LB2SN LB2SM

BK7

BK8

BK9

Z ^–1

—

–255/256

–511/512

–1023/1024

–31/32

1023/1024 1/4

2047/2048 1/4

4095/4096 1/4

BK7

BK8

127/128

255/256

–63/64

Fig. 5-22c.

–127/128

–255/256

–511/512

–1023/1024

511/512

1023/1024

2047/2048

4095/4096

—: don't care

Table. 5-23c.

correspond to

in Fig. 5-23b respectively.

in Fig. 5-23c respectively.

– 171 –

CXD3048R

–3

–6

–9

–12

–15

100

Frequency [Hz]

10k

+90

+72

+36

–36

–72

–90

100

Frequency [Hz]

10k

Fig. 5-24a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs)

HBST1 = 0

HBST1 = 1, HBST0 = 0

– 172 –

HBST1 = 1, HBST0 = 1

CXD3048R

–3

–6

–9

–12

–15

100

10k

Frequency [Hz]

–18

–36

–54

–72

–90

100

10k

Frequency [Hz]

Fig. 5-24b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs)

(

correspond to

in Table 5-23b respectively.)

– 173 –

CXD3048R

–3

–6

–9

–12

–15

100

10k

Frequency [Hz]

–18

–36

–54

–72

–90

100

10k

Frequency [Hz]

Fig. 5-24c. Servo LowBooster-2 characteristics [TRK] (MCK = 128Fs)

(

correspond to

in Table 5-23c respectively.)

– 174 –

CXD3048R

$34E (preset: $34E000)

D15 D14 D13 D12 D11 D10

IDFSL3 IDFSL2 IDFSL1 IDFSL0

DFSLS IDFT1 IDFT0

LPDF0 INVRFDC

IDFSL3:

New DFCT detection output setting.

When "0", only the DFCT signal described in §5-9 is detected and output from the DFCT

pin. (default)

When "1", the DFCT signal described in §5-9 and the new DFCT signal are switched and

output from the DFCT pin.

The switching timing is as follows.

When the §5-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin.

When the §5-9 DFCT signal is high, this DFCT signal is output from the DFCT pin.

In addition, the time at which the new DFCT signal can be output after the ¤5-9 DFCT signal

switches to low can also be set. (See IDFT1 and IDFT0 of $34E.)

IDFSL3

§5-9 DFCT

DFCT pin

§5-9 DFCT

New DFCT

§5-9 DFCT

IDFSL2:

New DFCT detection time setting.

DFCT = high is held for a certain time after new DFCT detection. This command sets that time.

When "0", a long hold time. (default)

When "1", a short hold time.

IDFSL1:

IDFSL0:

DFSLS:

New DFCT detection sensitivity setting.

When "0", a high detection sensitivity. (default)

When "1", a low detection sensitivity.

New DFCT release sensitivity setting.

When "0", a high release sensitivity. (default)

When "1", a low release sensitivity.

DFCT slice level setting mode switching.

When "0", the two bits of $3B commands SDF2 and SDF1 are used to set the DFCT slice

level as usual. (default)

When "1", the six bits of $3D commands SDF6 to SDF3 and $3B commands SDF2 and

SDF1 are used to set the DFCT slice level.

IDFT1, IDFT0:

These commands set the time at which the new DFCT signal can be output (output

prohibited time) after the §5-9 DFCT signal switches to low.

IDFT1

IDFT0

New DFCT signal output prohibited time

204.08µs

294.78µs

408.16µs

612.24µs

: preset

LPDF0:

DFCT signal generation mode switching.

When "0", the rise time constant of the DFCT generation circuit peak hold value is as

usual. (default)

When "1", the rise time constant of the DFCT generation circuit peak hold value is

weighed.

INVRFDC:

RFDC signal polarity inverted input setting.

When "0", the RFDC signal polarity is set to non-inverted. (default)

When "1", the RFDC signal polarity is set to inverted.

– 175 –

CXD3048R

$34F

D15 D14 D13 D12 D11 D10

FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1

—

When D15 = D14 = D13 = D12 = D11 = 1 ($34F)

D10 = 0

FBIAS LIMIT register write

FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB.

When using the FBIAS register in counter mode, counter operation stops when the value

of FB9 to FB1 matches with FBL9 to FBL1.

D15 D14 D13 D12 D11 D10

—

FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 1

FBIAS register write

FB9 to FB1: Data; two's complement data, FB9 = MSB.

For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/4

and FB9 to FB1 = 100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)

D15 D14 D13 D12 D11 D10

TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 0

TRVSC register write

TV9 to TV0: Data; two's complement data, TV9 = MSB.

For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/4

and TV9 to TV0 = 1100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)

Notes) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to

each bit TV8 to TV0 during external write are read out.

• When reading out internally measured values and then writing these values externally, set TV9 the

same as TV8.

– 176 –

CXD3048R

$35 (preset: $35 58 2D)

D15 D14 D13 D12 D11 D10

FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0

FT1, FT0, FTZ: Focus search-up speed

Default value: 010 (0.673 × VDDV/s)

Focus drive output conversion

FT1

FT0

FTZ

Focus search speed [V/s]

1.35 × VDD

0.673 × VDD

0.449 × VDD

0.336 × VDD

1.79 × VDD

1.08 × VDD

0.897 × VDD

0.769 × VDD

: preset, VDD: PWM driver supply voltage

FS5 to FS0:

FG6 to FG0:

Focus search limit voltage

Default value: 011000 ((1 ± 24/64) × V^DD/2, VDD: PWM driver supply voltage)

Focus drive output conversion

AGF convergence gain setting value

Default value: 0101101

$36 (preset: $36 0E 2E)

D15 D14 D13 D12 D11 D10

TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0

TDZC:

Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.

When "0", the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.

When "1", the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross,

whichever has the faster phase, is used. (See §5-12.)

DTZC delay (8.5/4.25µs, when MCK = 128Fs)

DTZC:

Default value: 0 (4.25µs)

TJ5 to TJ0:

Track jump voltage

Default value: 001110 ((1 ± 14/64) × VDD/2, VDD: PWM driver supply voltage)

Tracking drive output conversion

SFJP:

Surf jump mode on/off

The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5

to TJ0), by setting D7 to "1" (on)

TG6 to TG0:

AGT convergence gain setting value

Default value: 0101110

– 177 –

CXD3048R

$37 (preset: $37 50 BA)

D15 D14 D13 D12 D11 D10

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT

FZSH, FZSL:

FZC (Focus Zero Cross) slice level

Default value: 01 (1/8 × V^DD/2, VDD: supply voltage); FE input conversion

FZSH

FZSL

Slice level

1/4 × V^DD/2

1/8 × V^DD/2

1/16 × VDD/2

1/32 × V^DD/2

: preset

SM5 to SM0:

Sled move voltage

Default value: 010000 ((1 ± 16/64) × VDD/2, VDD: PWM driver supply voltage)

Sled drive output conversion

AGS:

AGJ:

AGCNTL self-stop on/off

Default value: 1 (on)

AGCNTL convergence completion judgment time during low sensitivity adjustment

(31/63ms, when MCK = 128Fs)

Default value: 0 (63ms)

AGGF:

AGGT:

Focus AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

Tracking AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

FE/TE input conversion

0 (small) 1/32 to V^DD/2

AGGF

1 (large) 1/16 to VDD/2

0 (small) 1/16 to VDD/2

AGGT

1 (large) 1/8 to VDD/2

: preset

AGV1:

AGV2:

AGHS:

AGHT:

AGCNTL convergence sensitivity during high sensitivity adjustment; high/low

Default value: 1 (high)

AGCNTL convergence sensitivity during low sensitivity adjustment; high/low

Default value: 0 (low)

AGCNTL high sensitivity adjustment on/off

Default value: 1 (on)

AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)

Default value: 0 (256ms)

– 178 –

CXD3048R

$38 (preset: $38 00 00)

D15 D14 D13 D12 D11 D10

VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0

DC offset cancel. See §5-3.

VCLM: VC level measurement (on/off)

VCLC: VC level compensation for FCS In register (on/off)

FLM:

Focus zero level measurement (on/off)

FLC0:

Focus zero level compensation for FZC register (on/off)

RFLM: RF zero level measurement (on/off)

RFLC: RF zero level compensation (on/off)

Automatic gain control. See §5-6.

AGF:

AGT:

Focus auto gain adjustment (on/off)

Tracking auto gain adjustment (on/off)

Misoperation prevention circuit

DFSW: Defect disable switch (on/off)

Setting this switch to "1" (on) disables the defect countermeasure circuit.

LKSW: Lock switch (on/off)

Setting this switch to "1" (on) disables the sled free-running prevention circuit.

DC offset cancel. See §5-3.

TBLM: Traverse center measurement (on/off)

TCLM: Tracking zero level measurement (on/off)

FLC1:

TLC2:

TLC1:

TLC0:

Focus zero level compensation for FCS In register (on/off)

Traverse center compensation (on/off)

Tracking zero level compensation (on/off)

VC level compensation for TRK/SLD In register (on/off)

Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs)

All commands are on when "1".

– 179 –

CXD3048R

$39 (preset: $390000)

D15 D14 D13 D12 D11 D10

DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0

When $3A command SVDA = 0

DAC:

Serial data readout DAC mode setting.

When "0", serial data cannot be read out. (default)

When "1", serial data can be read out.

These bits select the serial readout data.

SD6 to SD0:

D14 D13 D12 D11 D10

Readout data

length

Readout data

SD6 SD5 SD4 SD3 SD2 SD1 SD0

Coefficient RAM address

Data RAM address

Coefficient RAM data

Data RAM data

RF AVRG register

RFDC input signal

FCS Bias register

TRVSC register

DFCT count

8 bits

16 bits

8 bits

9 bits

8 bits

9 bits

8 bits

RFDC (Bottom)

RFDC (Peak)

RFDC (Peak – Bottom)

VC AVRG register

FE AVRG register

TE AVRG register

FE input signal

—

TE input signal

SE input signal

VC input signal

—: don't care

Note) When $3A SVDA is changed, select the readout data again.

– 180 –

CXD3048R

When $3A command SVDA = 1

DAC:

This command selects whether to set readout data for the left or right channel.

When "0", right channel readout data is selected. (default)

When "1", left channel readout data is selected.

SD6 to SD0:

These bits select the data to be output from the left or right channel.

D14 D13 D12 D11 D10

SD6 SD5 SD4 SD3 SD2 SD1 SD0

Data RAM address

Readout data

length

Readout data

Data RAM data

16 bits

RF AVRG register

RFDC input signal

FCS Bias register

TRVSC register

8 bits

9 bits

8 bits

9 bits

8 bits

FCS output signal

TRK output signal

VC AVRG register

FE AVRG register

FE (A-B): FCS in Reg

TE (E-F): TRK in Reg

TE AVRG register

FE input signal

TE input signal

SE input signal

VC input signal

Right channel preset

Left channel preset

Note) Coefficient RAM data cannot be output from the audio DAC side.

Do not output RFDC (peak, bottom, peak-bottom) or the DFCT count from the audio

DAC side.

When $3A SVDA is changed, select the readout data again.

The DFCT count counts the number of times the DFCT signal rises while $3994 is set.

Readout outputs the DFCT count at that time.

Memory Readout

The following three memories can be readout without waiting the memory access.

• M02 (Sled filter final memory)

• M12 (Focus hold filter final memory)

• M1A (Track hold filter final memory)

– 181 –

CXD3048R

$3A (D15 = 0) (preset: $3A0000)

D15 D14 D13 D12 D11 D10

FBON FBSS FBUP FBV1 FBV0 FIFZC TJD0 FPS1 FPS0 TPS1 TPS0 SVDA SJHD INBK MTI0

FBIAS (focus bias) register operation setting.

FBON:

FBSS

FBUP

FBON

FBSS

FBUP

Processing

—

FBIAS (focus bias) register addition off.

FBIAS (focus bias) register addition on.

FBIAS register acts as a down counter.

FBIAS register acts as an up counter.

—: don't care

FBV1, FBV0: FBIAS (focus bias) counter voltage switching.

The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.

The counter changes once for

each sampling cycle of the

focus servo filter. When MCK

is 128Fs, the sampling

frequency is 88.2kHz. When

converted to FE input, 1 step

is approximately 1/2⁹× VDD/2,

VDD = supply voltage.

FBV1

FBV0

Number of steps per cycle

: preset

FIFZC:

TJDO:

This selects the FZC slice level setting command.

When "0", the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default)

When "1", the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to

FIFZA0 setting values.

This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH

and FZSL setting.

This sets the tracking servo filter data RAM to "0" when switched from track jump to servo

on only when SFJP = 1 (during surf jump operation).

FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.

TPS1, TPS0:

Gain setting when transferring data from the tracking filter to the PWM block.

These are effective for increasing the overall gain in order to widen the servo band, etc.

Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,

6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the

relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.

FPS1

FPS0

Relative gain

0dB

TPS1

TPS0

Relative gain

0dB

+6dB

+12dB

+18dB

+12dB

+18dB

: preset

SVDA:

This allows the data set by the $39 command to be output through the audio DAC.

When "0", audio is output. (default)

When "1", the data set by the $39 command is output.

SJHD:

INBK:

This holds the tracking filter output at the value when surf jump starts during surf jump.

When INBK = 0 (off), the brake circuit masks the tracking drive signal with the TRKCNCL

signal which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on),

the tracking filter input is masked instead of the drive output.

The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).

– 182 –

MTI0:

CXD3048R

$3A8 (preset : $3A 80 00)

D15 D14 D13 D12 D11 D10

FPGS1 FPGS0 TPGS1 TPGS0

FPGS1, FPGS0: These increase +6dB, +12dB and +18dB immediately before FCS SRCH.

TPGS1, TPGS0: These increase +6dB, +12dB and +18dB immediately before TRK JMP.

FPGS1 FPGS0

Gain

0dB

TPGS1 TPGS0

Gain

0dB

+6dB

+12dB

+18dB

+6dB

+12dB

+18dB

: preset

$3A9 (preset : $3A 90 00)

D15 D14 D13 D12 D11 D10

UDFZC

UDFZC:

This detects FZC not depending on the search direction.

When "0", FZC is detected for UP search. (conventional system: default)

When "1", FZC is detected not depending on the search direction.

$3AFF (preset : $3A FF 00)

D15 D14 D13 D12 D11 D10

SRQ1 SRQ0

SRQ1, SRQ0: These bits select the ASYO output delay time.

SRQ1 SRQ0 ASYO output delay time

Approx. 0ns

Approx. 5ns

Approx. 10ns

Approx. 15ns

: preset

– 183 –

CXD3048R

$3B (preset: $3B E0 50)

D15 D14 D13 D12 D11 D10

SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT

SFOX, SFO2, SFO1: FOK slice level

Default value: 011 (28/256 × V^DD/2, VDD = supply voltage)

RFDC input conversion

SFOX SFO2 SFO1

Slice level

16/256 × V^DD/2

20/256 × VDD/2

24/256 × VDD/2

28/256 × V^DD/2

32/256 × VDD/2

40/256 × V^DD/2

48/256 × VDD/2

56/256 × VDD/2

: preset

SDF2, SDF1:

DFCT slice level

Default value: 10 (0.0313 × VDD)

RFDC input conversion

SFO2 SFO1

Slice level

0.0156 × VDD

0.0234 × VDD

0.0313 × VDD

0.0391 × VDD

: preset, V^DD: supply voltage

See the $34E command DFSLS and $3D commands SDF6 to SDF3.

MAX2, MAX1:

DFCT maximum time (MCK = 128Fs)

Default value: 00 (no timer limit)

MAX2 MAX1 DFCT maximum time

No timer limit

2.00ms

2.36ms

2.72ms

: preset

BTF:

Bottom hold double-speed count-up mode for MIRR signal generation

On/off (default: off)

On when "1".

– 184 –

CXD3048R

D2V2, D2V1:

D1V2, D1V1:

RINT:

Peak hold 2 for DFCT signal generation

Count-down speed setting

Default value: 01 (0.086 × VDD/ms, 44.1kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate

the operating frequency of the internal counter.

Count-down speed

D2V2

D2V1

[V/ms]

[kHz]

0.0431 × VDD

0.0861 × VDD

0.172 × VDD

0.344 × VDD

22.05

44.1

88.2

176.4

: preset, VDD: supply voltage

Peak hold 1 for DFCT signal generation

Count-down speed setting

Default value: 01 (0.688 × V^DD/ms, 352.8kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate

the operating frequency of the internal counter.

Count-down speed

D1V2

D1V1

[V/ms]

[kHz]

0.344 × V^DD

0.688 × VDD

1.38 × VDD

2.75 × VDD

176.4

352.8

705.6

1411.2

: preset, VDD: supply voltage

This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.

– 185 –

CXD3048R

$3C (preset: $3C 00 80)

D15 D14 D13 D12 D11 D10

COSS COTS CETZ CETF COT2 COT1 MOT2

BTS1 BTS0 MRC1 MRC0

COSS, COTS: These select the TZC signal used when generating the COUT signal.

COSS

COTS

TZC

—

STZC

HPTZC

DTZC

: preset, —: don't care

STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)

DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.)

HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.

See §5-13.

CETZ:

CETF:

Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC

signal. However, the input from the CE pin can also be used. This function is for the center

error servo.

When "0", the TZC signal is generated by using the signal input to the TE pin.

When "1", the TZC signal is generated by using the signal input to the CE pin.

When "0", the signal input to the TE pin is input to the TRK servo filter.

When "1", the signal input to the CE pin is input to the TRK servo filter.

These commands output the TZC signal.

COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from

the COUT pin and the TZC signal is used for auto sequence instead of the COUT signal.

COT2

COT1

COUT pin output

STZC

HPTZC

COUT

—

: preset, —: don't care

MOT2:

The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from

the MIRR pin and the STZC signal is used for generating the COUT signal instead of the

MIRR signal.

These commands set the MIRR signal generation circuit.

BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit.

The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1,

BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is "0".

MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.

As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by

subtracting the bottom hold value from the peak hold value with the MIRR comparator

level. Strictly speaking, however, for MIRR to become high, these levels must be compared

continuously for a certain time. These bits set that time.

The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R.

MRC1 MRC0 Setting time [µs]

BTS1 BTS0 Number of count-up steps per cycle

5.669

11.338

22.675

45.351

: preset (when MCK = 128Fs)

– 186 –

CXD3048R

$3D (preset: $3D 00 00)

D15 D14 D13 D12 D11 D10

SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SDF6 SDF5 SDF4 SDF3

SFID:

SFSK:

THID:

THSK:

SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the

TRK filter second-stage output.

When the low frequency component of the tracking error signal obtained from the RF

amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter.

Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally,

the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain

up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted

to M00 can be kept uniform by adjusting the K30 value even during the above switching.

TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK

filter second-stage output.

When signals other than the tracking error signal from the RF amplifier are input to the SE

input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.

Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally,

the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain

up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted

to M18 can be kept uniform by adjusting the K46 value even during the above switching.

See "§5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.

The focus error (FE) and tracking error (TE) can be generated internally.

When 0, the FE and TE signal input mode results. Input each error signal through the FE

and TE pins. (default)

ABEF:

When 1, the FE and TE signal generation mode results and the FE and TE signals are

generated internally.

TLD2 to TLD0: These turn on and off SLD filter correction independently of the TRK filter.

See $38 (TLC0 to TLC2) and Fig. 5-3.

Traverse center correction

TLC2

TLD2

TRK filter

OFF

SLD filter

OFF

—

OFF

Tracking zero level correction

TLC1

TLD1

TRK filter

OFF

SLD filter

OFF

—

OFF

VC level correction

TLC0

TLD0

TRK filter

OFF

SLD filter

OFF

—

OFF

: preset, —: don't care

– 187 –

CXD3048R

SDF6 to SDF3: These set the DEFECT slice level when the $34E command DFSLS = 1.

SDF6 to SDF1

111111

111110

111101

Slice level

63/256 × V^DD/2

62/256 × VDD/2

61/256 × VDD/2

000010

000001

000000

2/256 × V^DD/2

1/256 × V^DD/2

: preset

Note) Set SDF2 and SDF1 with the $3B command.

• Input coefficient sign inversion when SFID = 1 and THID = 1

The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3048R

outputs servo drives which have the reversed phase of input errors.

Negative input coefficient

K19

Positive output coefficient

K22

TRK filter

SLD filter

Negative input coefficient

K00

Positive output coefficient

K05

Positive input coefficient

K40

Positive output coefficient

K45

TRK Hold

TRK Hold filter

When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient

(K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0h results in 20h.)

For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted.

Negative input coefficient

K19

Positive output coefficient

K22

TRK filter

M0D

Positive input coefficient

K00

Positive output coefficient

K05

SLD filter

Negative input coefficient

K40

Positive output coefficient

K45

TRK Hold

TRK Hold filter

For TRK servo gain normal

See "§5-20. Filter Composition".

– 188 –

CXD3048R

$3E (preset: $3E 00 00)

D15 D14 D13 D12 D11 D10

F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD

LKIN COIN MDFI MIRI XT1D

F1NM, F1DM:

T1NM, T1UM:

F3NM, F3DM:

Quasi double accuracy setting for FCS servo filter first-stage

On when "1"; default is "0".

F1NM: Gain normal

F1DM: Gain down

Quasi double accuracy setting for TRK servo filter first-stage

On when "1"; default is "0".

T1NM: Gain normal

T1UM: Gain up

Quasi double accuracy setting for FCS servo filter third-stage

On when "1"; default is "0".

Generally, the advance amount of the phase increases by partially setting the FCS servo

third-stage filter which is used as the phase compensation filter to double accuracy.

F3NM: Gain normal

F3DM: Gain down

T3NM, T3UM:

Quasi double accuracy setting for TRK servo filter third-stage

On when "1"; default is "0".

Generally, the advance amount of the phase increases by partially setting the TRK servo

third-stage filter which is used as the phase compensation filter to double accuracy.

T3NM: Gain normal

T3UM: Gain up

Note) Filter first- and third-stage quasi double accuracy settings can be set individually.

See "§5-20 Filter Composition" at the end of this specification concerning quasi double accuracy.

DFIS:

FCS hold filter input extraction node selection

0: M05 (Data RAM address 05); default

1: M04 (Data RAM address 04)

TLCD:

LKIN:

COIN:

This command masks the TLC2 command set by D2 of $38 only when FOK is low.

On when "1"; default is "0".

When "0", the internally generated LOCK signal is output to the LOCK pin. (default)

When "1", the LOCK signal can be input from an external source to the LOCK pin.

When "0", the internally generated COUT signal is output to the COUT pin. (default)

When "1", the COUT signal can be input from an external source to the COUT pin.

The MIRR, DFCT and FOK signals can also be input from an external source.

MDFI:

When "0", the MIRR, DFCT and FOK signals are generated internally. (default)

When "1", the MIRR, DFCT and FOK signals can be input from an external source

through the MIRR, DFCT and FOK pins.

MIRI:

When "0", the MIRR signal is generated internally. (default)

When "1", the MIRR signal can be input from an external source through the MIRR pin.

MDFI

MIRI

MIRR, DFCT and FOK are all generated internally.

MIRR only is input from an external source.

MIRR, DFCT and FOK are all input from an external source.

: preset, —: don't care

—

XT1D:

The input to the servo master clock is used without being frequency-divided by setting

XT1D to "1". This command takes precedence over the XTSL pin, XT2D and XT4D. See

the description of $3F for XT2D and XT4D.

– 189 –

CXD3048R

$3F (preset: $3F 00 10)

D15 D14 D13 D12 D11 D10

AGG4 XT4D XT2D

DRR2 DRR1 DRR0

ASFG FTQ

SRO1

AGHF ASOT

AGG4:

This varies the amplitude of the internally generated sine wave using the AGGF and AGGT

commands during AGC.

When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.

Sine wave amplitude

AGG4 AGGF AGGT

FE input

TE input

See $37 for AGGF and AGGT.

The presets are AGG4 = 0,

AGGF = 1 and AGGT = 1.

conversion

—

1/32 × V^DD/2

—

1/16 × VDD/2

—

1/16 × VDD/2

1/8 × V^DD/2

1/64 × VDD/2

1/32 × V^DD/2

1/16 × VDD/2

1/8 × VDD/2

: preset, —: don't care

XT4D, XT2D:

MCK (digital servo master clock) frequency division ratio setting

This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is

generated. See the description of $3E for XT1D. Also, see "§5-2. Digital Servo Block

Master Clock (MCK)".

XT1D

XT2D

XT4D

Frequency division ratio

—

According to XTSL

1/1

1/2

1/4

: preset, —: don't care

DRR2 to DRR0: Partially clears the Data RAM values ("0" write).

The following values are cleared when "1" (on) respectively; default is "0".

DRR2: M08, M09, M0A

DRR1: M00, M01, M02

DRR0: M00, M01, M02 only when LOCK = low

Note) Set DRR1 and DRR0 on for 50µs or more.

When vibration detection is performed during anti-shock circuit operation, the FCS servo

filter is forcibly set to gain normal status.

ASFG:

FTQ:

On when "1"; default is "0".

The slope of the output during focus search is 1/4 the conventional output slope.

On when "1"; default is "0".

– 190 –

CXD3048R

SRO1:

This command is used to continuously externally output various data inside the digital

servo block which have been specified with the $39 command. (However, D15 (DAC) of

$39 must be set to "1".)

Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by

setting this command to "1".

SRO1 = 1

SOLK Output from XPCK pin.

XOLT Output from GFS pin.

SOUT Output from XUGF pin.

AGHF:

ASOT:

This halves the frequency of the internally generated sine wave during AGC.

The anti-shock signal, which is internally detected, is output from the ATSK pin.

Output when "1"; default is "0".

Vibration detection when a high signal is output for the anti-shock signal output.

– 191 –

CXD3048R

$3F8 (preset: $3F8800)

D15 D14 D13 D12 D11 D10

SYG3 SYG2 SYG1 SYG0 FIFZB3 FIFZB2 FIFZB1 FIFZB0 FIFZA3 FIFZA2 FIFZA1 FIFZA0

SYG3 to SYG0: These simultaneously set the focus drive, tracking drive and sled drive output gains. See

the $AF and $CX commands for the spindle drive output gain setting.

SYG3 SYG2 SYG1 SYG0

GAIN

0 (– ∞dB)

0.125 (–18.1dB)

0.250 (–12.0dB)

0.375 (–8.5dB)

0.500 (–6.0dB)

0.625 (–4.1dB)

0.750 (–2.5dB)

0.875 (–1.2dB)

1.000 (0.0dB)

1.125 (+1.0dB)

1.250 (+1.9dB)

1.375 (+2.8dB)

1.500 (+3.5dB)

1.625 (+4.2dB)

1.750 (+4.9dB)

1.875 (+5.5dB)

: preset

FIFZB3 to FIFZB0:

This sets the slice level at which FZC changes from high to low.

FIFZA3 to FIFZA0:

This sets the slice level at which FZC changes from low to high.

The FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values are valid only when $3A

FIFZC is "1".

Set so that the FIFZB3 to FIFZB0 ≤ FIFZA3 to FIFZA0.

Hysteresis can be added to the slice level by setting FIFZB3 to FIFZB0 < FIFZA3 to FIFZA0.

FIFZB3 to FIFZB0 or FIFZA3 to FIFZA0 setting value

FZC slice level =

× 0.5 × VDD [V]

– 192 –

CXD3048R

$3F9 (preset: $3F9000)

D15 D14 D13 D12 D11 D10

FSUD FFSUP

FFS5 FFS4 FFS3 FFS2 FFS1 FFS0

FSUD, FFSUP: These set the focus search type.

The focus search is started by the $47 command.

FSUD FFSUP

Focus search type

The usual focus search is performed.

UP search is performed, and the focus servo is turned on at the FZC

falling edge.

Do not set.

When the upper limit value is reached during the focus search, the

focus search stops. After that, when the lower limit value is reached

UP/DOWN search is performed.

These limit values should be set with the $35 FS5 to FS0.

When the lower limit value is reached during the focus search, the

focus search stops. After that, when the upper limit value is reached

UP/DOWN search is performed.

These limit values should be set with the $35 FS5 to FS0.

: preset

FFS5 to FFS0: These set the focus search amplitude voltage. Valid only when FSUD = 1.

FFS5 to FFS0 setting values

Focus search amplitude = (1 ±

) × 0.5 × V^DD[V]

– 193 –

CXD3048R

Description of Data Readout

SOCK

(5.6448MHz)

...

XOLT

(88.2kHz)

MSB

LSB

8-bit data

9-bit data

MSB

LSB

SOUT

LSB

16-bit data

16-bit register

for serial/parallel

conversion

16-bit register

for latch

SOUT

LSB

To the 7-segment LED

MSB

CLK

MSB

SOCK

XOLT

CLK

Data is connected to the 7-segment LED

by 4-bits at a time. This enables Hex

display using four 7-segment LEDs.

SOUT

Serial data input

D/A

Analog

output

To an oscilloscope, etc.

SOCK

XOLT

Clock input

Offset adjustment,

gain adjustment

Latch enable input

Waveforms can be monitored with an oscilloscope using a serial

input-type D/A converter as shown above.

– 194 –

CXD3048R

§5-19. List of Servo Filter Coefficients

ADDRESS

DATA

CONTENTS

K00

K01

K02

K03

K04

K05

K06

K07

K08

K09

K0A

K0B

K0C

K0D

K0E

K0F

SLED INPUT GAIN

SLED LOW BOOST FILTER A-H

SLED LOW BOOST FILTER A-L

SLED LOW BOOST FILTER B-H

SLED LOW BOOST FILTER B-L

SLED OUTPUT GAIN

FOCUS INPUT GAIN

SLED AUTO GAIN

FOCUS HIGH CUT FILTER A

FOCUS HIGH CUT FILTER B

FOCUS LOW BOOST FILTER A-H

FOCUS LOW BOOST FILTER A-L

FOCUS LOW BOOST FILTER B-H

FOCUS LOW BOOST FILTER B-L

FOCUS PHASE COMPENSATE FILTER A

FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K1A

K1B

K1C

K1D

K1E

K1F

FOCUS PHASE COMPENSATE FILTER B

FOCUS OUTPUT GAIN

ANTI SHOCK INPUT GAIN

FOCUS AUTO GAIN

HPTZC / Auto Gain HIGH PASS FILTER A

HPTZC / Auto Gain HIGH PASS FILTER B

ANTI SHOCK HIGH PASS FILTER A

HPTZC / Auto Gain LOW PASS FILTER B

Fix

TRACKING INPUT GAIN

TRACKING HIGH CUT FILTER A

TRACKING HIGH CUT FILTER B

TRACKING LOW BOOST FILTER A-H

TRACKING LOW BOOST FILTER A-L

TRACKING LOW BOOST FILTER B-H

TRACKING LOW BOOST FILTER B-L

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K2A

K2B

K2C

K2D

K2E

K2F

TRACKING PHASE COMPENSATE FILTER A

TRACKING PHASE COMPENSATE FILTER B

TRACKING OUTPUT GAIN

TRACKING AUTO GAIN

FOCUS GAIN DOWN HIGH CUT FILTER A

FOCUS GAIN DOWN HIGH CUT FILTER B

FOCUS GAIN DOWN LOW BOOST FILTER A-H

FOCUS GAIN DOWN LOW BOOST FILTER A-L

FOCUS GAIN DOWN LOW BOOST FILTER B-H

FOCUS GAIN DOWN LOW BOOST FILTER B-L

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

FOCUS GAIN DOWN DEFECT HOLD GAIN

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

FOCUS GAIN DOWN OUTPUT GAIN

Not used

Fix indicates that normal preset values should be used.

– 195 –

CXD3048R

ADDRESS

DATA

CONTENTS

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K3A

K3B

K3C

K3D

K3E

K3F

SLED INPUT GAIN (Only when TRK gain up2 is accessed with SFSK = 1.)

ANTI SHOCK LOW PASS FILTER B

Not used

ANTI SHOCK HIGH PASS FILTER B-H

ANTI SHOCK HIGH PASS FILTER B-L

ANTI SHOCK FILTER COMPARATE GAIN

TRACKING GAIN UP2 HIGH CUT FILTER A

TRACKING GAIN UP2 HIGH CUT FILTER B

TRACKING GAIN UP2 LOW BOOST FILTER A-H

TRACKING GAIN UP2 LOW BOOST FILTER A-L

TRACKING GAIN UP2 LOW BOOST FILTER B-H

TRACKING GAIN UP2 LOW BOOST FILTER B-L

TRACKING GAIN UP PHASE COMPENSATE FILTER A

TRACKING GAIN UP PHASE COMPENSATE FILTER B

TRACKING GAIN UP OUTPUT GAIN

Not used

K40

K41

K42

K43

K44

K45

K46

TRACKING HOLD FILTER INPUT GAIN

TRACKING HOLD FILTER A-H

TRACKING HOLD FILTER A-L

TRACKING HOLD FILTER B-H

TRACKING HOLD FILTER B-L

TRACKING HOLD FILTER OUTPUT GAIN

TRACKING HOLD FILTER INPUT GAIN

(Only when TRK gain up2 is accessed with THSK = 1.)

Not used

FOCUS HOLD FILTER INPUT GAIN

FOCUS HOLD FILTER A-H

FOCUS HOLD FILTER A-L

FOCUS HOLD FILTER B-H

FOCUS HOLD FILTER B-L

K47

K48

K49

K4A

K4B

K4C

K4D

K4E

K4F

FOCUS HOLD FILTER OUTPUT GAIN

Not used

– 196 –

§5-20. Filter Composition

The internal filter composition is shown below.

: Coefficient RAM address, M : Data RAM address

FCS Servo Gain Normal fs = 88.2kHz

M1F

M1E

FCS

AUTO Gain

To FCS

Hold

To FCS

Hold

K0F

M04

K0F

M05

FCS

DFCT

Hold Reg2

M03

Z ^–1

2^–1

M06

Z ^–1

M07

K06

K11

K13

FCS

In Reg

Z ^–1

K09

Z ^–1

AGFON

Sin ROM

K08

K0A

K0B

K0C

K0D

K0E

K10

2 ^–7

2⁷

Note) Set the MSB bit of the K0B and K0D coefficients to "0".

FCS Servo Gain Down fs = 88.2kHz

M1F

M1E

FSC

AUTO Gain

To FCS

Hold

To FCS

Hold

K2B

M04

K2B

M05

FCS

DFCT

Hold Reg2

2^–1

M06

Z ^–1

M07

M03

Z ^–1

K2D

K13

K06

FCS

In Reg

Z ^–1

K25

Z ^–1

K28

K29

K2A

K2C

K24

K26

K27

2^–7

2 ^–7

Note) Set the MSB bit of the K27 and K29 coefficients to "0".

FPGS1, 0

FPS1, 0

BK3

BK6

PWM

Z ^–1

BK2

Z ^–1

FCS SRCH

BK5

BK1

BK4

TRK Servo Gain Normal fs = 88.2kHz

TRK

AUTO Gain

To SLD Servo,

TRK Hold

TRK

Hold Reg

DFCT

2^–1

M0B

M0C

Z ^–1

M0D

Z ^–1

M0E

Z ^–1

M0F

K19

K22

K23

TRK

In Reg

Z ^–1

AGTON

Sin ROM

K1B

K1C

K1A

K1E

K1F

K19

K20

K21

2 ^–7

K1D

Note) Set the MSB bit of the K1D and K1F coefficients to "0".

TRK Servo Gain Up1 fs = 88.2kHz

TRK

AUTO Gain

TRK

Hold Reg

DFCT

2⁷

M0B

M0C

Z ^–1

K1B

M0E

Z ^–1

K3D

M0F

2 ^–1

K19

K23

K3E

TRK

In Reg

Z ^–1

K1A

K3C

TRK Servo Gain Up2 fs = 88.2kHz

TRK

AUTO Gain

TRK

Hold Reg

DFCT

2^–1

M0E

Z ^–1

M0F

M0B

Z ^–1

M0C

Z ^–1

M0D

Z ^–1

K19

K3E

K23

TRK

In Reg

K37

K38

K3A

K3C

K3D

K36

2 ^–7

K39

K3B

Note) Set the MSB bit of the K39 and K3B coefficients to "0".

TPS1, 0

TPGS1, 0

BK6

BK3

PWM

BK9

Z^–1

Z ^–1

Z^–1

BK5

Z ^–1

BK7

Z ^–1

BK8

TRK JMP

BK1

BK2

BK4

FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)

M1F

M1E

FCS

AUTO Gain

To FCS

Hold

To FCS

Hold

K0F

M05

K0F

M04

FCS

Hold Reg 2

DFCT

2^–1

M06

Z ^–1

M07

M03

Z ^–1

K13

K06

K11

FCS

In Reg

Z ^–1

AGFON

Sin ROM

K0A

K0B

7FH

K09

K0C

K0D

81H

K08

80H

K0E

K10

2^–7

2 ^–7

2^–7

2⁷

Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to "0".

FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)

M1F

M1E

FCS

AUTO Gain

To FCS

Hold

To FCS

Hold

K2B

M04

K2B

M05

FCS

Hold Reg 2

DFCT

2 ^–1

M03

Z ^–1

M06

Z ^–1

M07

K06

K13

K2D

FCS

In Reg

Z ^–1

K26

K27

K28

K29

80H

K2A

K2C

81H

K24

7FH

K25

2 ^–7

2^–7

2 ^–7

2^–7

Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to "0".

81H, 7FH and 80H are each Hex display 8-bit fixed values

when set to quasi double accuracy.

FPS1, 0

FPGS1, 0

BK3

BK6

PWM

Z ^–1

FCS SRCH

BK1

BK2

BK4

BK5

TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)

TRK

AUTO Gain

TRK

Hold Reg

DFCT

M0B

Z ^–1

M0C

Z^–1

M0D

Z ^–1

M0E

Z ^–1

M0F

2^–1

K22

K23

K19

TRK

In Reg

AGTON

Sin ROM

81H

K1A

7FH

K1C

K1D

K1E

K1F

80H

K21

2 ^–7

K1B

K20

Note) Set the MSB bit of the K1D and K1F coefficirnts during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to "0".

TRK Servo Gain Up1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)

TRK

AUTO Gain

TRK

DFCT

Hold Reg

2⁷

M0B

Z ^–1

M0C

Z ^–1

M0E

Z ^–1

M0F

2^–1

K19

K3E

K23

TRK

In Reg

81H

K1A

7FH

80H

K3C

K3D

2 ^–7

2^–7

2 ^–7

K1B

Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to "0".

TRK Servo Gain Up2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)

TRK

AUTO Gain

TRK

DFCT

Hold Reg

M0B

Z ^–1

M0C

Z ^–1

M0D

Z ^–1

M0E

Z ^–1

M0F

2^–1

K19

K3E

K23

TRK

In Reg

K3A

K3B

80H

81H

K36

7FH

K38

K39

K3D

2^–7

2 ^–7

2^–7

K37

K3C

Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to "0".

81H, 7FH and 80H are each Hex display 8-bit fixed values

when set to quasi double accuracy.

TPS1, 0

TPGS1, 0

BK3

BK6

BK9

PWM

Z ^–1

BK2

Z ^–1

BK5

Z ^–1

BK8

TRK JMP

BK1

BK4

BK7

CXD3048R

SLD Servo fs = 345Hz

TRK SERVO FILTER

Secont-stage output

TRK

K30

K00

SFSK (only when TGup2 is used.)

M00

AUTO Gain

M0D

SFID

2⁷

M01

Z ^–1

M02

K05

K07

2^–1

PWM

SLD

In Reg

Z ^–1

SLD MOV

K03

K04

K01

2^–7

K02

Note) Set the MSB bit of the K02 and K04 coefficients to "0".

HPTZC/Auto Gain fs = 88.2kHz

2^–1

FCS

In Reg

Slice

TZC Reg

AGFON

2^–1

M08

Z ^–1

M09

Z ^–1

M0A

Z ^–1

AUTO Gain

Reg

Slice

TRK

In Reg

AGTON

AGFON

Sin ROM

K15

K14

K17

– 201 –

CXD3048R

Anti Shock fs = 88.2kHz

2^–1

M08

Z ^–1

M09

Z ^–1

M0A

Z ^–1

TRK

In Reg

Anti Shock

Reg

K35

K12

Comp

K31

K16

K33

K34

2 ^–7

Note) Set the MSB bit of the K34 coefficient to "0".

The comparator level is 1/16 the maximum amplitude of the comparator input.

AVRG fs = 88.2kHz

2^–1

2 ^–7

M08

Z ^–1

VC, TE, FE,

RFDC

AVRG Reg

TRK Hold fs = 345Hz

TRK SERVO FILTER

Second-stage output

K46

THSK (only when TGup2 is used.)

M18

M0D

THID

M19

Z ^–1

TRK

Hold Reg

K45

2 ^–1

K40

SLD

In Reg

Z ^–1

K41

K43

K44

2 ^–7

K42

Note) Set the MSB bit of the K42 and K44 coefficients to "0".

FCS Hold fs = 345Hz

FCS SERVO FILTER

First-stage output

M1F

M1E

K2B when using the

FCS Gain Down filter

K2B

DFIS

($3E)

M04

M10

Z^–1

M11

Z^–1

M12

FCS

Hold Reg 2

K4D

K48

K0F

M05

FCS SERVO FILTER

Second-stage output

K49

K4B

K4C

2^–7

K4A

Note) Set the MSB bit of the K4A and K4C coefficients to "0".

– 202 –

CXD3048R

§5-21. TRACKING and FOCUS Frequency Response

Tracking frequency response

180˚

90˚

NORMAL

GAIN UP

0˚

–90˚

–10

–180˚

20k

2.1

100

f – Frequency [Hz]

When using the preset coefficients with the boost function off.

Focus frequency response

180˚

NORMAL

GAIN DOWN

90˚

0˚

–90˚

–180˚

–10

2.1

100

20k

f – Frequency [Hz]

When using the preset coefficients with the boost function off.

– 203 –

[6] Application Circuit

VCC

GND

RFO

FZC

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

SS1

TEST

TES1

AVDD

SS2

AOUT2

VREFR

FRDR

FFDR

TRDR

TFDR

SRDR

SFDR

SSTP

MDS

AVSS

Vcc

Driver setting

SSTP

SLED

SPDL

GND

VREFL

AOUT1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

AVDD

XVSS

XTAO

XTAI

MDS

C176

MDP

C176

XVDD

HVDD

HPR

DD2

CXD3048R

LRCK

LRCKI

PCMD

PCMDI

BCK

BCKI

DVDD

HPL

HVSS

XTSL

EXCK

SBSO

XWIH

XEMP

SQSO

SCLK

SQCK

SBSO

A10

SS0

A11

XRAS

XCAS

R4M

TEST3

TEST4

XWRE

XWE

XOE

A11 to A0

D3 to D0

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

4M DRAM or 16M DRAM

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot

assume responsibility for any problems arising out of the use of these circuits or for any infringement of

third party patent and other right due to same.

CXD3048R

Package Outline

Unit: mm

120PIN LQFP (PLASTIC)

18.0 ± 0.2

16.0 ± 0.1

1.7 MAX

SCT A'ssy

1.4 ± 0.1

0.1

120

0.5

0.22 ± 0.05

0.1

0.1 ± 0.05

0.22 ± 0.05

(0.2)

0.25

0˚ to 10˚

DETAIL

PACKAGE STRUCTURE

LEAD PLATING SPECIFICATIONS

EPOXY RESIN

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

ITEM

SPEC.

COPPER ALLOY

Sn-Bi Bi:1-4wt%

5-18µm

SOLDER PLATING

SONY CODE

EIAJ CODE

LQFP-120P-L01

LEAD MATERIAL

LQFP120-P-1616

COPPER ALLOY

0.8g

SOLDER COMPOSITION

PLATING THICKNESS

JEDEC CODE

PACKAGE MASS

120PIN LQFP (PLASTIC)

18.0 ± 0.2

16.0 ± 0.1

1.7MAX

1.4 ± 0.1

Renesas A'ssy

120

0.5

0.10

0.25

0.1 ± 0.05

b=0.22 ± 0.05

(0.2)

0˚ to 10˚

DETAIL B

PACKAGE STRUCTURE

LEAD PLATING SPECIFICATIONS

DETAIL A

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

ITEM

SPEC.

COPPER ALLOY

Sn-Bi Bi:1-4wt%

5-18µm

SONY CODE

EIAJ CODE

LQFP-120P-L051

P-LQFP120-16x16-0.5

SOLDER

LEAD MATERIAL

COPPER ALLOY

0.8g

SOLDER COMPOSITION

PLATING THICKNESS

JEDEC CODE

PACKAGE MASS

Sony Corporation

– 205 –

CXD3048R [SONY]

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