CXL1504M [SONY]
CMOS-CCD 1H Delay Line for NTSC; 对于NTSC CMOS ， CCD 1H延时线
| 型号： | CXL1504M |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD 1H Delay Line for NTSC |
| 文件： | 总9页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1504M
CMOS-CCD 1H Delay Line for NTSC
Description
20 pin SOP (Plastic)
The CXL1504M is a delay line used in conjunction
with an external low-pass filter. Through negative
phase input and positive phase output 1H delay time
is obtained for NTSC signals.
Features
• Single 5V power supply
• 14.3MHz driver
• Low power consumption at 160mW (Typ.)
• Built-in peripheral circuits
• Completely adjustment free
Functions
• 905.5-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
Structure
CMOS-CCD
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
Topr
Tstg
PD
6
V
• Operating temperature
• Storage temperature
• Allowable power dissipation
–10 to +60
–55 to +150
500
°C
°C
mW
Operating Voltage Range (Ta = 25°C)
Supply voltage
VDD
5 ± 5%
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
• Clock frequency
VCLK
0.3 to 1.0
Vp-p (0.5Vp-p typ.)
MHz
fCLK
14.318182
• Input clock waveform
sine wave
Input Signal Amplitude
VSIG
560
mVp-p (Max.)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E71217A78-PS
CXL1504M
Block Diagram and Pin Configuration (Top View)
13
19
18
17
16
15
14
12
20
11
Pulse generation
circuit
Autobias
circuit
Clock
driver
Bias circuit
(B)
φS/H
φ1
φ2
Output circuit,
S/H circuit
CCD (905.5bit)
Bias circuit
(A)
1
2
5
6
7
8
9
10
3
4
Pin Description
Pin No.
1
Symbol
I/O
Description
Impedance [Ω]
600 to 2k
IS
O
O
CCD bias DC output
Autobias DC output
2
AB
2k to 20k
3
NC
—
I
4
IN
Signal input (Negative phase signal)
5V power supply (For clock driver)
GND
> 100k (at no clamp)
5
VDD
VSS
VGGA
OUT
VSS
VGGB
VSS
NC
—
—
O
6
7
Gate bias (A) DC output
Signal output (Positive phase signal)
GND
2k to 10k
40 to 500
8
O
9
—
O
10
11
12
13
14
15
16
17
18
19
20
Gate bias (B) DC output
GND
2k to 10k
—
—
—
—
—
I
VDD
NC
5V power supply (For analog system)
VSS
CLK
VDD
NC
GND
Clock input
4k to 50k
—
—
—
—
5V power supply (For digital system)
NC
SUB
GND
– 2 –
CXL1504M
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, sine wave)
See the Electrical Characteristics Test Circuits.
(Note 1)
Bias conditions
4
VBIAS1 [V]
SW conditions
Item
Supply
Symbol
Test conditions
—
Min. Typ. Max. Unit Note
1
2
3
a
a —
—
20
mA
dB
2
3
IDD
a
32
42
current
200kHz,
500mVp-p,
sine wave
Low
frequency
gain
—
–5.0
GL
fr
a
a
a
a
b
b
b
–3.0
–1.0
200kHz ←→ 3.58MHz,
150mVp-p,
sine wave
b
c
Frequency
response
VIN – 0.2
–2.5
dB
4
–1.3
0
5-staircase wave
(See Note 5)
Differential
gain
%
5
5
6
DG
DP
CP
d
d
a
a
b
a
a
b
c
c
a
—
—
0
0
3
3
7
7
5-staircase wave
(See Note 5)
Differential
phase
degree
mVp-p
S/H pulse
coupling
VIN
—
No signal input
—
200
350
50% white video
signal
S/N
e
a
a
d
—
54
56
dB
7
—
S/N ratio
(See Note 7)
Notes
1) VIN is defined as follows.
VIN is the input signal clamp level, it clamps the video signal sync tip level.
CXL1504
4
Input
(IN)
Clamp level VIN
Negative phase
signal input
VIN is the pin voltage for Pin 4 at no-input signal. Testing is executed with a voltmeter under the follwing SW
conditions.
SW conditions
Test point
V1
Item
3
a
4
2
b
1
VIN
—
—
As VIN varies with each IC, they are all subject to testing.
2) IDD is the IC supply current value during clock and signal input.
3) GL is the OUT pin output gain when a 500mVp-p, 200kHz sine wave is input to IN pin.
OUT pin output voltage [mVp-p]
GL = 20 log
[dB]
– 3 –
500 [mVp-p]
CXL1504M
4) Indicates the dissipation at 3.58MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.58MHz sine wave is fed to same, calculation is made
according to the following formula. The input part bias is tested at VIN – 0.2V.
OUT pin output voltage (3.58MHz) [mVp-p]
fr = 20 log
[dB]
OUT pin output voltage (200kHz) [mVp-p]
5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure. below is
input are tested at the vector scope.
143mV
357mV
500mV
143mV
1H 63.56µs
IN pin input waveform is the inverted waveform in the figure above
6) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input part bias is tested at VINV.
Test value
(mVp-p)
7) S/N ratio during 50% white video signal input shown in figure. below is tested at a video noise meter, in
BPF 100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
IN pin input waveform is the inverted waveform in the figure above
Clock
4fsc (14.318182MHz) sine wave
0.3Vp-p to 1.0Vp-p
(0.5Vp-p typ.)
– 4 –
CXL1504M
S S V
C N
B G G V
S S V
T U O
A G G V
S S V
D D V
N I
D D V
C N
S S V
K L C
D D V
C N
C N
C N
B A
B U S
S I
– 5 –
CXL1504M
– 6 –
CXL1504M
Example of Representative Characteristics
Frequency response vs. Supply voltage
Low frequency gain vs. Supply voltage
–1
0
–1
–2
–3
–2
–3
–4
–5
4.75
5.0
5.25
4.75
5.0
5.25
Supply voltage [V]
Supply voltage [V]
Differential gain vs. Supply voltage
Supply current vs. Supply voltage
40
10
8
6
4
2
30
20
0
4.75
5.0
5.25
4.75
5.0
5.25
Supply voltage [V]
Supply voltage [V]
Low frequency gain vs. Ambient temperature
Frequency response vs. Ambient temperature
–1
0
–1
–2
–3
–2
–3
–4
–5
0
20
40
60
0
20
40
60
Ambient temperature [°C]
Ambient temperature [°C]
– 7 –
CXL1504M
Supply current vs. Ambient temperature
40
Differentical gain vs. Ambient temperature
10
8
6
4
3
0
30
20
0
20
40
60
0
20
40
60
Ambient temperature [°C]
Ambient temperature [°C]
Frequency response
0
–2
–4
–6
–8
10k
100k
1M
10M
Frequency [Hz]
– 8 –
CXL1504M
Package Outline
Unit: mm
20PIN SOP (PLASTIC)
+ 0.4
12.45 – 0.1
+ 0.4
1.85 – 0.15
20
11
0.15
+ 0.2
0.1 – 0.05
1
0.45 ± 0.1
10
+ 0.1
0.2 – 0.05
1.27
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.3g
SONY CODE
EIAJ CODE
SOP-20P-L01
SOP020-P-0300
JEDEC CODE
PACKAGE MASS
– 9 –
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