CXL5502N [SONY]

CMOS-CCD 1H Delay Line for NTSC; 对于NTSC CMOS ， CCD 1H延时线


型号：	CXL5502N
厂家：	SONY CORPORATION
描述：	CMOS-CCD 1H Delay Line for NTSC 对于NTSC CMOS ， CCD 1H延时线 CD
文件：	总13页 (文件大小：188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXL5502M/N/P

CMOS-CCD 1H Delay Line for NTSC

For the availability of this product, please contact the sales office.

Description

CXL5502M

CXL5502N

The CXL5502M/N/P are CMOS-CCD delay line ICs

that provide 1H delay time for NTSC signals including

the external low-pass filter.

14 pin SOP (Plastic)

16 pin SSOP (Plastic)

The ICs contain a PLL circuit (quadruple progression).

Features

• Single power supply (5V)

• Low power consumption 95mW (Typ.)

• Built-in peripheral circuits

• Clamp level of I/O signal can be selected

• Built-in quadruple PLL circuit

CXL5502P

14 pin DIP (Plastic)

Functions

• 905-bit CCD register

• Clock driver

• Autobias circuit

• Input clamp circuit

• Sample and hold circuit

• PLL circuit (quadruple progression)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

VDD

• Operating temperature Topr

• Storage temperature Tstg

• Allowable power dissipation

–10 to +60

°C

Structure

–55 to +150 °C

CMOS-CCD

CXL5502M

400

260

800

CXL5502N

CXL5502P

Recommended Operating Condition (Ta = 25°C)

Supply voltage 5 ± 5%

VDD

Recommended Clock Conditions (Ta = 25°C)

• Input clock amplitude VCLK 0.3 to 1.0

Vp-p

(0.5Vp-p typ.)

3.579545 MHz

• Clock frequency

fCLK

• Input clock waveform Sine wave

Input Signal Amplitude

VSIG 500mVp-p (Typ.), 572mVp-p (Max.)

(at internal clamp condition)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E89930E79-PS

CXL5502M/N/P

Block Diagram and Pin Configuration (Top View)

CXL5502M/P

VCO

OUT

VSS

VDD

CLK

PLL

Autobias circuit

Clock driver

Timing circuit

Bias circuit (A)

Bias circuit (B)

CCD

(905bit)

Output circuit

(S/H 1bit)

Clamp circuit

I/O control

I/O1

VCO

OUT

I/O2

OUT

VSS

CXL5502N

OUT

VCO

OUT

VSS

(N.C)

VDD

CLK

PLL

Autobias circuit

Clock driver

Timing circuit

CCD

(905bit)

Bias circuit (A)

Bias circuit (B)

Output circuit

(S/H 1bit)

Clamp circuit

I/O control

I/O2

OUT

(N.C)

VSS

I/O1

VSS

VCO

OUT

– 2 –

CXL5502M/N/P

Pin Description

CXL5502M/P

Pin No.

Symbol

I/O

Description

Signal input

Impedance

> 10kΩ at no clamp

I/O1

I/O control 1

I/O control 2

Signal output

GND

I/O2

OUT

VSS

—

40 to 500Ω

> 100kΩ

VSS

GND

VCO OUT

CLK

VCO output

Clock input

VDD

—

Power supply (5V)

Phase comparator output

VCO input

PC OUT

VCO IN

VDD

—

Power supply (5V)

Autobias DC output

GND (SUB)

600 to 200kΩ

VSS

CXL5502N

Pin No.

Symbol

I/O

Description

Signal input

I/O contorl 1

I/O contorl 2

Signal output

GND

Impedance

> 10kΩ at no clamp

I/O1

I/O2

OUT

VSS

—

40 to 500Ω

(N.C)

VSS

—

GND

VCO OUT

CLK

VCO output

Clock input

> 100kΩ

VDD

—

Power supply (5V)

—

(N.C)

PC OUT

VCO IN

VDD

Phase comparator output

VCO input

—

Power supply (5V)

Autobias DC output

GND (SUB)

600 to 200kΩ

VSS

– 3 –

CXL5502M/N/P

Description of Function

In the CXL5502M/N/P, the condition of I/O control pins (Pins 2 and 3) control the input signal clamp condition

and the mode of the output signal with relation to its input signal.

There are 2 modes for the I/O signal.

Input waveform

Output waveform

(1) PN mode

(Low level clamp/reverse phase output mode)

Clamp

level

(2) NP mode

(High level clamp/positive phase output mode)

Clamp

level

I/O Control Pin

(1) I/O1 (Pin 2)

Control of the I/O signal condition

DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input

signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling

capacitor of around 1000pF is necessary.

GND ............. Input signal is high level clamped and the output signal turns into an inverted signal.

(2) I/O2 (Pin 3)

Control of the input signal clamp condition

0V ................. Internal clamp condition

5V ................. Non internal clamp condition

Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ).

Usage in this mode is limited to APL 50% signals and in this mode, the maximum input

signal amplitude is 200mVp-p.

– 4 –

CXL5502M/N/P

Electrical Characteristics

(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p, Sine wave)

See "Electrical Characteristics Test Circuit"

Bias condition

SW condition

Vbias1 (V)

(Note 1)

Item

Symbol

Test condition

—

Min. Typ. Max. Unit Note

1 2

3 4 5 6 7

b b

IDDPN

IDDNP

Supply

current

—

— c b

a —

a a

b b

a a

b b

a a

b b

a a

b b

a a

b b

a a

b b

a a

Low

GLPN 200kHz,

frequency

gain

—

2.1

—

–2

–1

500mVp-p,

a a b

a b

b b

a c

b a

a d

GLNP

fPN

sine wave

200kHz ←→ 3.57MHz,

150mVp-p,

sine wave

Frequency

response

a a

fNP

DGPN

DGNP

DPPN

DPNP

CPPN

CPNP

SNPN

SNNP

5-staircase wave

(See Note 5)

Differential

gain

5-staircase wave

(See Note 5)

Differential

phase

—

degree

VINPN + 0.5

VINNP

S/H pulse

coupling

No signal input

—

350 mVp-p

— c a

50% white

video signal

(See Note 7)

—

S/N ratio

Notes

(1) VINPN and VINNP are defined as follows.

VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync

tip level.

CXL5502

Input

(IN)

VINPN

VINNP

Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions.

SW condition

Test

point

Item

VINPN

VINNP

—

– 5 –

CXL5502M/N/P

(2) This is the IC supply current value during clock and signal input.

(3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.

(Example of calculation)

OUT pin output voltage (PN mode) [mVp-p]

GLPN = 20 log

[dB]

500 [mVp-p]

(4) Indicates the dissipation at 3.57MHz in relation to 200kHz.

From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the

output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made

according to the following formula. The input part bias is tested at 2.1V.

(Example of calculation)

OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p]

fPN = 20 log

[dB]

OUT pin output voltage (PN mode, 200kHz) [mVp-p]

(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is

input are tested at the vector scope.

143mV

357mV

500mV

143mV

1H 63.56µs

Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)

(6) The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP

modes respectively.

Test value

(mVp-p)

– 6 –

CXL5502M/N/P

(7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in

BPF 100kHz to 4MHz, Sub Carrier Trap mode.

178mV

321mV

143mV

1H 63.56µs

Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)

Clock

fsc (3.579545MHz) sine wave

0.3Vp-p to 1.0Vp-p

(0.5Vp-p typ.)

– 7 –

CXL5502M/N/P

– 8 –

CXL5502M/N/P

– 9 –

CXL5502M/N/P

Example of Representative Characteristics

Supply current vs. Ambient temperature

Low frequency gain vs. Ambient temperature

–1

–2

–3

–20

Ambient temperature [°C]

Differential gain vs. Ambient temperature

Frequency response vs. Ambient temperature

–1

–2

–3

–20

Ambient temperature [°C]

Low frequency gain vs. Supply voltage

Supply current vs. Supply voltage

–1

–2

–3

4.75

5.25

4.75

5.25

Supply voltage [V]

– 10 –

CXL5502M/N/P

Differential gain vs. Supply voltage

Frequency response vs. Supply voltage

–1

–2

–3

4.75

5.25

4.75

5.25

Supply voltage [V]

Frequency response

–2

–4

–6

10k

100k

10M

Frequency [Hz]

– 11 –

CXL5502M/N/P

Package Outline

CXL5502M

Unit: mm

14PIN SOP (PLASTIC)

+ 0.4

1.85 – 0.15

+ 0.4

9.9 – 0.1

0.15

+ 0.2

0.1 – 0.05

+ 0.1

0.2 – 0.05

0.45 ± 0.1

1.27

0.24

PACKAGE STRUCTURE

EPOXY RESIN

SOLDER PLATING

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

SONY CODE

EIAJ CODE

SOP-14P-L01

SOP014-P-0300

42/COPPER ALLOY

0.2g

PACKAGE MASS

JEDEC CODE

14PIN SOP (Plastic) 300mil

10.2 ± 0.3

0.15

1.44 MAX

1.27

0.4 ± 0.1

0.05 MIN

0.13

10° MAX

DETAIL

PACKAGE STRUCTURE

EPOXY RESIN

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

SOLDER PLATING

COPPER / 42 ALLOY

0.2g

SONY CODE

EIAJ CODE

SOP-14P-L121

SOP014-P-0300-AX

PACKAGE WEIGHT

JEDEC CODE

– 12 –

CXL5502M/N/P

CXL5502N

16PIN SSOP (PLASTIC)

+ 0.2

1.25 – 0.1

5.0 ± 0.1

0.1

+ 0.05

0.15 – 0.02

0.65

+ 0.1

0.22 – 0.05

0.13

0.1 ± 0.1

0° to 10°

DETAIL

NOTE: Dimension “ ” does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER / PALLADIUM

PLATING

SONY CODE

EIAJ CODE

SSOP-16P-L01

SSOP016-P-0044

42/COPPER ALLOY

0.1g

JEDEC CODE

PACKAGE MASS

CXL5502P

14PIN DIP (PLASTIC)

+ 0.4

19.2 – 0.1

0° to 15°

2.54

0.5 ± 0.1

1.2 ± 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

SONY CODE

EIAJ CODE

DIP-14P-01

DIP014-P-0300

42/COPPER ALLOY

0.9g

JEDEC CODE

Similar to MO-001-AH

PACKAGE MASS

– 13 –

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