CXL5508P [SONY]

CMOS-CCD 1H Delay Line for PAL; 对于PAL CMOS ， CCD 1H延时线


型号：	CXL5508P
厂家：	SONY CORPORATION
描述：	CMOS-CCD 1H Delay Line for PAL 对于PAL CMOS ， CCD 1H延时线 CD
文件：	总9页 (文件大小：106K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXL5508M/P

CMOS-CCD 1H Delay Line for PAL

Description

CXL5508M

8 pin SOP (Plastic)

CXL5508P

8 pin DIP (Plastic)

The CXL5508M/P are CMOS-CCD delay line ICs

that provide 1H delay time for PAL signals, including

the external low-pass filter.

Features

• Single 5V power supply

• Low power consumption 60mW (Typ.)

• Built-in peripheral circuits

Functions

• 565-bit CCD register

• Clock driver

• Auto-bias circuit

• Input clamp circuit

• Sample-and-hold circuit

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

V^DD

°C

• Operating temperature Topr

• Storage temperature Tstg

• Allowable power dissipation

P^D

–10 to +60

–55 to +150 °C

Structure

CMOS-CCD

CXL5508M

CXL5508P

350

480

Recommended Operating Condition (Ta = 25°C)

Supply voltage V^DD5 ± 5%

Recommended Clock Conditions (Ta = 25°C)

• Input clock amplitude VCLK 0.3 to 1.0

Vp-p

(0.5Vp-p typ.)

8.867238 MHz

• Input clock waveform Sine wave

• Clock frequency

f^CLK

Input Signal Amplitude

V^SIG500mVp-p (Typ.), 527mVp-p (Max.)

Blook Diagram and Pin Configuration (Top View)

(at internal clamp condition)

Auto-bias circuit

Bias circuit

Timing circuit

Clock driver

Bias circuit (A)

Bias circuit (B)

CCD

(565bit)

Output circuit

(S/H 1bit)

Clamp circuit

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E91101A7X-PS

CXL5508M/P

Pin Description

Pin No. Symbol

Description

Signal input

Impedance

I/O

> 10kΩ at no clamp

VGB

OUT

VSS

CLK

VGA

VDD

Gate control B

Signal output

GND

40 to 500Ω

> 100kΩ

—

Clock input

—

Gate control A

Power supply (5V)

Auto-bias DC output

600 to 200kΩ

Description of I/O Signals

Input signals are low level clamped and output signals are

inverted in relation to the input signals. Also, the clamp

condition of input signals are controlled by VGB (Pin 2)

conditions.

Input waveform

Output waveform

0V ........ Internal clamp condition

5V ........ Non internal clamp condition

Clamp

level

Center biased to approx. 2.1V by means of

the IC internal resistance (approx. 10kΩ).

In this mode, the input signal is limited to

APL 50% and the maximum input signal

amplitude is 200mVp-p.

Electrical Characteristics

(Ta = 25°C, VDD = 5V, fCLK = 8.867238MHz, VCLK = 500mVp-p, sine wave)

See "Electrical Characteristics Test Circuit"

Bias

condition

V1 (V)

SW condition

Item

Symbol

Test condition

—

Min. Typ. Max. Unit Note

—

Supply current

IDD

200kHz,

500mVp-p, sine wave

Low frequency

gain

–2

200kHz ←→ 2MHz,

150mVp-p, sine wave

Frequency

response

2.1

–1.8

—

–1.8

—

S/H pulse

coupling

350 mVp-p

No signal input

—

S/N ratio

LIS

LIL

LIC

—

5-staircase wave

(For luminance

signals only)

—

Linearity

– 2 –

CXL5508M/P

Notes

(1) This is the IC supply current value during clock and signal input.

(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.

OUT pin output voltage [mVp-p]

GL = 20 log

[dB]

500 [mVp-p]

(3) Indicates the dissipation at 2MHz in relation to 200kHz.

From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the

output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, cal culation is made

according to the following formula. Input bias is tested at 2.1V.

OUT pin otuput voltage (2MHz) [mVp-p]

fg = 20 log

[dB]

OUT pin output voltage (200kHz) [mVp-p]

(4) The internal clock component to the output signal during no-signal input and the leakage of that high

harmonic component are tested. Input bias is tested at 2.1V.

Test value

(mVp-p)

(5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is

calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following

formula.

Noise (mVrms)

0.5 • 10 ^GL/20

S/N = –20 • Iog

[dB]

(6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance

signals only) and calculated according to the formula below.

(However, output signals become inverted with regards to input.)

LIS =

× 100 [%]

100 IRE

40 IRE

500mV

LIL =

LIC =

× 100 [%]

– 3 –

CXL5508M/P

Clock

2fsc (8.867238MHz) sine wave

0.3 to 1.0Vp-p

(0.5Vp-p typ.)

– 4 –

CXL5508M/P

– 5 –

CXL5508M/P

– 6 –

CXL5508M/P

Example of Representative Characteristics

Supply current vs. Supply voltage

Low frequency gain vs. Supply voltage

0.5

–0.5

–1

–1.5

4.75

5.25

4.75

5.25

Supply voltage [V]

Frequency response vs. Supply voltage

Linearity (LIS) vs. Supply voltage

0.5

–0.5

–1

–1.5

4.75

5.25

4.75

Supply voltage [V]

Linearity (LIL) vs. Supply voltage

Linearity (LIC) vs. Supply voltage

4.75

5.25

4.75

Supply voltage [V]

– 7 –

CXL5508M/P

Supply current vs. Ambient temperature

Low frequency gain vs. Ambient temperature

0.5

–0.5

–1

–1.5

–20 –10

10 20 30 40 50 60 70

Ambient temperature [°C]

–20 –10

10 20 30 40 50 60 70

Ambient temperature [°C]

Frequency response vs. Ambient temperature

Linearity (LIS) vs. Ambient temperature

0.5

–0.5

–1

–1.5

–20 –10

10 20 30 40 50 60 70

Ambient temperature [°C]

–20 –10

10 20 30 40 50 60 70

Ambient temperature [°C]

Linearity (LIL) vs. Ambient temperature

Linearity (LIC) vs. Ambient temperature

–20 –10

10 20 30 40 50 60 70

–20 –10

10 20 30 40 50 60 70

Ambient temperature [°C]

– 8 –

CXL5508M/P

Package Outline

CXL5508M

Unit: mm

8PIN SOP (PLASTIC)

+ 0.4

1.85 – 0.15

+ 0.4

6.1– 0.1

0.15

+ 0.2

0.1– 0.05

+ 0.1

0.2 – 0.05

0.45 ± 0.1

1.27

0.24

PACKAGE STRUCTURE

EPOXY RESIN

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

SOLDER PLATING

SONY CODE

EIAJ CODE

SOP-8P-L01

SOP008-P-0300

42/COPPER ALLOY

0.1g

PACKAGE MASS

JEDEC CODE

CXL5508P

8PIN DIP (PLASTIC)

+ 0.4

9.4 – 0.1

0° to 15°

2.54

0.5 ± 0.1

1.2 ± 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

SONY CODE

DIP-8P-01

EIAJ CODE

DIP008-P-0300

COPPER ALLOY

0.5g

PACKAGE MASS

JEDEC CODE

– 9 –

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