CXP-82220 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP-82220 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总21页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP82220/82224
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82220/82224 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, fluorescent display tube
controller/driver, remote control reception circuit, CTL
duty detection circuit, 14-bit PWM output, high-speed
output circuit and other servo systems besides the
basic configurations of 8-bit CPU, PROM, RAM, and
I/O port.
100 pin QFP (Plastic)
The CXP82220/82224 also provides power-on reset
function and sleep/stop function that enables lower
power consumption.
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity
20K bytes (CXP82220)
24K bytes (CXP82224)
• Incorporated RAM capacity
• Peripheral functions
— A/D converter
704 bytes (including fluorescent display area)
8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
— Timer
SIO with 8-bit, 8-stage FIFO incorporated for data use
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit standard SIO, 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display tube controller/driver Maximum of 384 segment display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
Hardware key scan function
Maximum of 16 × 8 key matrix compatible
— Remote control reception circuit
Incorporated noise elimination circuit
Incorporated 8-bit, 6-stage FIFO for measurement data
14 bits, 1 channel
— PWM output circuit
— CTL duty detection circuit
— High-speed output circuit
• Interruption
Precision of 800ns at 10MHz, 4 outputs
19 factors, 15 vectors, multi-interruption possible
Sleep/stop
• Standby mode
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP82200 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E92235A81-PS
CXP82220/82224
A T R O P B T R O P C T R O P D T R O P E T R O P F T R O P G T R O P H T R O P I T R O P
S S V
D D V
T S R
L A T X
L A T X E
X T
X E T
3 O T R / 3 G P
o t
0 O T R / 0 G P
I M N / 3 T N I / 3 E P
2 T N I / 2 E P
1 T N I / 1 C E / 1 E P
0 T N I / 0 C E / 0 E P
R E L L O R T N O C T P U R R E T N I
F E R V A
S S V A
– 2 –
CXP82220/82224
Pin Assignment (Top View)
100
99 98
96 95 94 93 92
91 90 89 88 87 86 85 84 83 82 81
97
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/CTL
PE6/PWM
PE7/TO/DDO/ADJ
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
1
2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
T7
T8/S31
T9/S30
T10/S29
T11/S28
T12/S27
T13/S26
T14/S25
T15/S24
PI7/S23
PI6/S22
PI5/S21
PI4/S20
PI3/S19
PI2/S18
PI1/S17
PI0/S16
PF7/S15
PF6/S14
PF5/S13
PF4/S12
PF3/S11
PF2/S10
PF1/S9
PF0/S8
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
31
32 33
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
34
Note) NC (Pin 90) must be connected to VDD.
– 3 –
CXP82220/82224
Pin Description
Symbol
I/O
Functions
(Port A)
PA0/AN0
to
PA7/AN7
8-bit I/O port. I/O can be
set in a unit of single bit .
(8 pins)
I/O/
Analog input
Analog inputs to A/D converter.
(8 pins)
I/O/Input
I/O/Input
I/O/I/O
External capture input to 16bittimer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
(Port B)
8-bit I/O port. I/O for lower
7 bits can be set in a unit
of single bit. Uppermost
bit (PB7) is for output only.
(8 pins)
I/O/Input
I/O/Output
I/O/I/O
Serial data input (CH0).
Serial data output (CH0).
PB4/SO0
PB5/SCK1
PB6/SI1
Serial clock I/O (CH1).
I/O/Input
Output/Output
Serial data input (CH1).
Serial data output (CH1).
PB7/SO1
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Capable of driving 12mA
synk current. (8 pins)
PC0/KR0
to
PC7/KR7
Serves as key return inputs when operating
key scan with FDP segment signal.
I/O/Input
(Port D)
8-bit output port.
(8 pins)
PD0/S0
to
PD7/S7
Output/Output
FDP segment signal outputs.
External event inputs for
Input/Input/Input
Input/Input/Input
Input/Input
PE0/INT0/EC0
PE1/INT1/EC1
PE2/INT2
Inputs for
external
timer/counter.
(2 pins)
interruption
request.
(4 pins)
Non-maskable
(Port E)
Input/Input/Input
PE3/INT3/NMI
interruption request input.
8-bit port. Lower 6 bits are
for inputs; upper 2 bits are
for outputs.
Input/Input
Remote control reception circuit input.
Input for CTL duty ditection circuit.
14-bit PWM output.
PE4/RMC
PE5/CTL
PE6/PWM
Input/Input
(8 pins)
Output/Output
Output for the 16-bit timer/counter
rectangular waves, CTU duty detection,
and 32kHz oscillation frequuency
demultiplication.
Output/Output/
Output/Output
PE7/TO/DDO/
ADJ
(Port F)
8-bit output port.
(8 pins)
PF0/S8
to
PF7/S15
FDP segment signal
outputs.
Output/Output
(Port G)
Outputs for real-time pulse generator (RTG).
Functions as high-precision, real-time pulse
output port.
8-bit I/O port. I/O can be
set in a unit of single bit.
Data for the lower 4 bits
are gated with the contents
of RTO or OR-gate output.
(8 pins)
PG0/RTO0
to
PG3/RTO3
I/O/Output
I/O
(4 pins)
PG4 to PG7
– 4 –
CXP82220/82224
Symbol
I/O
Functions
(Port H)
I/O
PH0 to PH7
8-bit I/O port. I/O can be set in a unit of single bit.
(8 pins)
PI0/S16
to
PI7/S23
(Port I)
8-bit output ports.
(8 bits)
Output/Output
FDP segment signal outputs.
T8/S31
to
T15/S24
Output/Output
Output
Outputs for FDP timing (digit) signals/segment signals.
FDP timing signal outputs.
T0 to T7
VFDP
FDP voltage supply when incorporated resistor is set by mask option.
Input
EXTAL
XTAL
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
Output
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
Input
TEX
Output
Input
TX
RST
Low-level active, system reset.
NC.
NC
Under normal operation, connect to VDD.
Input
AVREF
AVSS
VDD
Reference voltage input for A/D converter.
A/D converter GND.
Positive power supply.
GND.
VSS
– 5 –
CXP82220/82224
Input/Output Circuit Formats for Pins
Circuit format
When reset
Pin
Port A
Port A data
PA0/AN0
to
Port A direction
"0" when reset
IP Input protection circuit
PA7/AN7
Hi-Z
Hi-Z
Hi-Z
Data bus
RD (Port A)
Port A input selection
"0" when reset
Input multiplexer
A/D converter
8 pins
Port B
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
"0" when reset
IP
Schmitt input
Data bus
RD (Port B)
CINT
CS0
SI0
4 pins
SI1
Port B
SCK out
Output enable
Port B output selection
"0" when reset
Port B data
IP
PB2/SCK0
PB5/SCK1
Port B direction
"0" when reset
Data bus
Schmitt input
RD (Port B)
SCK in
2 pins
– 6 –
CXP82220/82224
Circuit format
Pin
When reset
Port B
SO
Output enable
Port B output selection
"0" when reset
Port B data
PB4/SO0
IP
Hi-Z
Port B direction
"0" when reset
Data bus
1 pin
RD (Port B)
Port B
Internal reset signal
SO
Output enable
Port B output selection
"1" when reset
PB7/SO1
High level
Port B data
"1" when reset
Data bus
Pull-up transistor approx.
10kΩ
1 pin
RD (Port B)
Port C
Port C data
PC0/KR0
to
PC7/KR7
Port C direction
IP
"0" when reset
Hi-Z
Data bus
RD (Port C)
Key input signal
Large current drive of 12mA possible
8 pins
Port E
EC0/INT0
EC1/INT1
INT2
INT3/NMI
RMC
PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
Schmitt input
IP
Hi-Z
CTL
PE5/CTL
Data bus
6 pins
RD (Port E)
– 7 –
CXP82220/82224
Circuit format
Pin
PE6/PWM
1 pin
When reset
Port E
PWM
Port E output selection
"0" when reset
Port E data
High level
"1" when reset
Data bus
RD (Port E)
Port E
Output enable
TO
DDO
ADJ16K
ADJ2K
0
1
2
3
MPX
Port E output selection
PE7/TO/
DDO/ADJ
Port E output selection
"00" when reset
High level
Port E output selection
"0" when reset
Port E data
"1" when reset
ADJ signal is a frequency demultiplication
Data bus
output for 32kHz oscillation frequency
adjustment.
ADJ2K can be used for buzzer output.
1 pin
RD (Port E)
Port G
RTO data
"0" when reset
Port G data
PG0/RTO0
to
PG3/RTO3
Hi-Z
Port G direction
"0" when reset
IP
Data bus
4 pins
RD (Port G)
– 8 –
CXP82220/82224
Pin
Circuit format
When reset
Port G
Port H
Port G or Port H data
PG4 to PG7
PH0 to PH7
Port G or Port H
direction
Hi-Z
IP
"0" when reset
Data bus
RD (Port G or Port H)
12 pins
PD0/S0
to
PD7/S7
Port D
Port F
Port I
Segment output data
Hi-Z or Low
level
PF0/S8
to
PF7/S15
Output selection control signal
("0" when reset)
(when PD
resistance is
added)
Port D, F, or I data
"0" when reset
Mask option
VFDP
OP
PI0/S16
to
PI7/S23
Pull-down
resistor
Data bus
RD (Port D, F, or I)
24 pins
High voltage drive transistor
Segment output data
Output selection control signal
("0" when reset)
T15/S24
to
T8/S31
Hi-Z or Low
level
(when PD
resistance is
added)
Mask option
OP
T0 to T7
16 pins
Pull-down
resistor
VFDP
High voltage drive transistor
• Diagram shows circuit
composition during
oscillation.
EXTAL
XTAL
EXTAL
IP
IP
• Feedback resistor is
Oscillation
removed during stop.
XTAL
2 pins
– 9 –
CXP82220/82224
Pin
When reset
Circuit format
• Diagram shows circuit
composition during
oscillation.
TEX
TX
TEX
TX
IP
IP
Oscillation
• When the operation of the oscillation
circuit is stopped by the software,
the feedback resistor is removed,
and TEX and TX become "Low" level
and "High" level respectively.
2 pins
Pull-up resistor
RST
1 pin
Mask option
OP
Low level
IP
Schmitt input
– 10 –
CXP82220/82224
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
VDD
Rating
Unit
V
Remarks
–0.3 to +7.0
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
Supply voltage
AVSS
VIN
V
1
1
Input voltage
V
Output voltage
VOUT
V
As P channel transistor is open drain,
VDD is reference.
Display output voltage
VDD – 40 to VDD + 0.3
VOD
V
2
All pins excluding display outputs
(value per pin)
–5
IOH
mA
mA
–15
IODH1
Display outputs S0 to S23 (value per pin)
High level output current
Display outputs T0 to T7, and T8/S31 to
T15/S24 (value per pin)
–35
IODH2
mA
–40
–100
∑IOH
∑IODH
IOL
mA
mA
mA
mA
mA
°C
Total for all pins excluding display outputs
Total for all display outputs
Port 1
High level total output current
Low level output current
15
3
20
IOLC
∑IOL
Topr
Tstg
PD
Large current Port 1
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
1
100
Total for all output pins
–20 to +75
–55 to +150
600
°C
mW
VIN and VOUT must not exceed VDD + 0.3V.
2
3
Specifies output current of general-purpose l/O ports.
The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSl.
– 11 –
CXP82220/82224
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
High-speed mode
Guaranteed operation range
Low-speed mode
Guaranteed operation range
5.5
3.5
VDD
Supply voltage
5.5
5.5
Guaranteed operation range with TEX clock
2.7
2.5
Guaranteed data hold range during stop
1
VDD
VDD
VIH
0.7VDD
0.8VDD
V
V
2
Hysteresis input
VIHS
VIHEX
VIL
High level input voltage
3
EXTAL
VDD – 0.4 VDD + 0.3
V
1
0
0
0.3VDD
0.2VDD
0.4
V
2
Low level input voltage
Operating temperature
Hysteresis input
VILS
VILEX
Topr
V
3
EXTAL
–0.3
–20
V
+75
°C
1
Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PG, PH).
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC, CTL.
Specifies only during external clock input.
2
3
– 12 –
CXP82220/82224
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min. Typ. Max. Unit
4.0
3.5
V
V
V
V
V
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
High level
output voltage
VOH
VOL
PA, PB, PC,PE6,
PE7, PG, PH
0.4
0.6
1.5
Low level
output voltage
PC
0.5
–0.5
0.1
40 µA
–40 µA
10 µA
–10 µA
–400 µA
mA
IIHE
IILE
IIHT
IILT
IILR
EXTAL
Input current
TEX
–0.1
–1.5
–8
VDD = 5.5V,
VIL = 0.4V
1
RST
S0 to S23
Display output
current
VDD = 4.5V,
VOH = VDD – 2.5V
IOH
S24/T15 to S31/T8
T0 to T7
–20
60
mA
Open drain output
leakage current
(P-CH Tr in off state)
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
S0 to S23
S24/T15 to S31/T8
T0 to T7
ILOL
–20 µA
S0 to S23
S24/T15 to S31/T8
T0 to T7
Pull-down
resistance
VDD = 5V
VFDP = VDD – 35V
RL
IIZ
100
20
270 kΩ
±10 µA
2
PA to PC, PE, PG,
VDD = 5.5V
VI = 0, 5.5V
I/O leakage current
1
PH, RST
High-speed mode operation
(1/2 frequency demultiplier clock)
IDD1
40 mA
100 µA
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDD2
35
1.2
9
Sleep mode
3
Supply current
VDD
IDDS1
8
mA
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
IDDS2
IDDS3
30 µA
10 µA
Stop mode
VDD = 5.5V, termination of 10MHz and
32kHz crystal oscillation
Pins other than
Clock 1MHz
S0 to S31, T0 to T7,
PB7, PE6,PE7,AVREF,
Input capacity
CIN
10
20
pF
0V for all pins excluding
measured pins
AVSS, VFDP, VDD, VSS
1
RST specifies the input current when pull-up resistance has been selected; leakage current when no
resisance has been selected.
When incorporated pull-down resistance has been selected through mask option.
2
3
When all pins are open.
– 13 –
CXP82220/82224
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Fig. 1, Fig. 2
Min.
1
Typ.
Max. Unit
XTAL
EXTAL
MHz
ns
10
200
20
System clock frequency
fC
Fig. 1, Fig. 2
External clock drive
t
t
XL,
XH
37.5
System clock input pulse width
EXTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
System clock input rise time,
fall time
t
t
CR,
CF
ns
Event count input clock
pulse width
EC0
EC1
t
t
EH,
EL
1
Fig. 3
Fig. 3
ns
tsys
+
50
Event count input clock
rise time, fall time
EC0
EC1
t
t
ER,
EF
ms
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
TX
kHz
32.768
System clock frequency
fC
Event count input clock input
pulse width
t
t
TL,
TH
Fig. 3
Fig. 3
µs
10
TEX
TEX
Event count input clock rise
time,fall time
t
t
TR,
TF
ms
20
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation
Ceramic oscillation
32kHz clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
C1
C2
74HC04
Fig. 2. Clock applied conditions
– 14 –
CXP82220/82224
0.8VDD
0.2VDD
TEX
EC0
EC1
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
Fig. 3. Event count clock timing
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss=0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
ns
Chip select transfer mode
(SCK0 = output mode)
CS0 ↓ → SCK0
t
t
t
DCSK
SCK0
tsys + 200
delay time
Chip select transfer mode
(SCK0 = output mode)
CS0 ↑ → SCK0
float delay time
ns
ns
ns
DCSKF SCK0
DCSO SO0
tsys + 200
tsys + 200
tsys + 200
CS0 ↓ → SO0
Chip select transfer mode
Chip select transfer mode
delay time
CS0 ↑ → SO0
float delay time
t
DCSOF SO0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WHCS CS0
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
Chip select transfer mode
Input mode
CS0 High level width
SCK0
cycle time
tKCY
SCK0
SCK0
SI0
Output mode
Input mode
t
KH,
KL
SCK0
High, Low level width
t
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input setup time
(for SCK0 ↑)
t
t
t
SIK
200
tsys + 200
100
SI0 input hold time
(for SCK0 ↑)
KSI
SI0
tsys + 200
100
SCK0 ↓ → SO0
delay time
KSO
SO0
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits
= "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
CXP82220/82224
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK
tKSI
0.8VDD
Input
data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
SO0
Output data
Fig. 4. Serial transfer CH0 timing
– 16 –
CXP82220/82224
Serial transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
t
KCY
SCK1
Output mode
16000/fc
400
Input mode
t
t
KH,
KL
SCK1
SI1
SCK1 High, Low level width
Output mode
8000/fc – 50
100
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SI1 input setup time
(for SCK1 ↑)
t
t
t
SIK
200
200
SI1 input hold time
(for SCK1 ↑)
KSI
SI1
100
200
100
SCK1 ↓ → SO1
KSO
SO1
delay time
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
SI1
Input data
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 17 –
CXP82220/82224
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference)
Item
Resolution
Symbol
Pin
Max. Unit
Typ.
Condition
Min.
Bits
8
LSB
±5
Linearity error
Ta = 25°C
VDD = AVDD = 5.0V
VDD = AVss = 0V
1
mV
VZT
Zero transition voltage
–10
70
150
Full-scale
transition voltage
2
mV
VFT
4930
5050
5120
3
µs
µs
t
t
CONV
SAMP
Conversion time
160/fADC
12/fADC
3
Sampling time
V
VREF
VIAN
IREF
Reference input voltage
Analog input voltage
AVREF
VDD – 0.5
0
VDD
V
AN0 to AN7
AVREF
mA
1.0
Operation mode
0.6
Sleep mode
Stop mode
AVREF
AVREF current
IREFS
µA
10
32kHz operation mode
FFH
FEH
1 VZT : Value at which the digital conversion value
changes from 00H to 01H and vice versa.
2 VFT : Value at which the digital conversion value
changes from FEH to FFH and vice versa.
3 fADC indicates the below values due to ADC operation
clock selection (ADCS: Bit 6 of address 00F9H).
During PS2 selection, fADC = fc/2
Linearity error
Analog input
01H
00H
During PS1 selection, fADC = fc
VZT
VFT
Fig. 6. Definitions of A/D converter terms
– 18 –
CXP82220/82224
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
INT0
Condition Min.
Max.
Unit
External interruption
High, Low level width
t
t
IH
IL
INT1
INT2
NMI/INT3
µs
1
µs
Reset input Low level width
8/fc
t
RSL
RST
tIH
tIL
0.8VDD
INT0
0.2VDD
INT1
INT2
tIL
tIH
NMI/INT3
(NMI specifies only for
the falling edge)
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
(5) Others
(Ta = –20 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V reference)
Item
CLK input
Symbol
Pin
CTL
Max.
Unit
ns
Condition
tsys = 2000/fc
Min.
tCTH,
CTL
tsys + 200
High, Low level width
t
tCTH
tCTL
0.8VDD
CTL
0.2VDD
Fig. 9. Other timing
– 19 –
CXP82220/82224
Appendix
(i) Main clock
(ii) Main clock
EXTAL
(iii) Sub clock
EXTAL
XTAL
XTAL
TEX
TX
Rd
C2
C1
C2
C1
C2
C1
Fig. 10. Recommended oscillation circuit
Circuit
example
Manufacturer
Model
fc (MHz)
C1 (pF)
C2 (pF)
CSA4.19MG
CSA8.00MG
CSA10.0MT
4.19
8.00
(i)
MURATA
MFG
CO., LTD
10.00
4.19
30
30
CST4.19MGW
CST8.00MTW
CST10.00MTW
(ii)
(i)
8.00
10.00
4.19
RIVER
ELETEC
CORPORATION
HC-49/U03
8.00
15
27
15
27
10.00
4.19
KINSEKI
LTD.
HC-49/U (-S)
8.00
10.00
Those marked with an asterisk ( ) signify types with built-in ground capacitance (C1, C2).
Mask option table
Item
Contents
Reset pin pull-up resistor
Non-existent
Non-existent
Existent
Existent
High voltage drive output port pull-down
– 20 –
CXP82220/82224
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.3 – 0.1
0.65
+ 0.35
2.75 – 0.15
0.13
0.15
M
+ 0.2
0.1 – 0.05
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
– 21 –
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明