CXP-85232A [SONY]
CMOS 8-bit Single-chip Microcomputer; CMOS 8位单片机
| 型号： | CXP-85232A |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single-chip Microcomputer |
| 文件： | 总20页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP85112B/85116B
CXP85220A/85224A/85228A/85232A
CMOS 8-bit Single-chip Microcomputer
Description
The CXP85112B/85116B, CXP85220A/85224A/
85228A/85232A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, vector interruption, on-screen display function,
I2C bus interface, PWM generator, remote control
reception circuit, HSYNC counter, power source
frequency counter and watch dog timer besides the
basic configurations of 8-bit CPU, ROM, RAM, and
l/O port.
64 pin SDIP (Plastic)
64 pin QFP (Plastic)
The CXP85112B/85116B, CXP85220A/85224A/
85228A/85232A also provides a power-on reset
function and a sleep function that enables lower
power consumption.
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
• Incorporated ROM capacity
1µs at 4MHz operation
12K bytes (CXP85112B)
16K bytes (CXP85116B)
20K bytes (CXP85220A)
24K bytes (CXP85224A)
28K bytes (CXP85228A)
32K bytes (CXP85232A)
• Incorporated RAM capacity
352 bytes (CXP85112B/85116B)
448 bytes (CXP85220A/85224A/85228A/85232A)
• Peripheral functions
— On-screen display function
12 × 16 dots, 128 types
21 words × 4 Iines (more than 4 Iines possible)
Double scan mode compatible, jitter elimination circuit
— I2C bus interface
— PWM output
14 bits, 1 channel
6 bits, 8 channels
— Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO
— A/D converter
4 bits, 4channels, successive approximation method
(Conversion time of 40µs/4MHz)
— HSYNC counter
— Power supply frequency counter
— Watch dog timer
— Serial I/O
8-bit clock synchronization
— Timer
• Interruption
• Standby mode
8-bit timer, 8-bit timer/counter, 19-bit time base timer
14 factors, 14 vectors, multi-interruption possible
Sleep
• Package
64-pin plastic SDIP/QFP
• Piggyback/evaluation chip
CXP85100A, CXP85190 (Custom font compatible)
CXP85200A, CXP85290 (Custom font compatible)
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93Z17B86
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
A T R O P
B T R O P
C T R O P
D T R O P
E T R O P
F T R O P
S S V
D D V
P M
T S R
L A T X
L A T X E
7 M W P / 7 F P
o t
0 M W P / 0 F P
M W P / 6 E P
2 T N I / 0 D P
1 T N I / 1 E P
0 T N I / 0 E P
R E L L O R T N O C T P U R R E T N I
– 2 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 1 (Top View) 64 pin SDIP Package
1
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA7
PA6
VDD
NC
PA5
3
VSS
4
PA4
MP
5
PA3
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
BLK
6
PA2
PA1
7
8
PA0
9
PB7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB6
PB5
PB4
PB3
R
PB2
G
PB1
B
PB0
PC7
VSYNC
HSYNC
EXLC
PC6
PC5
PC4
XLC
PC3
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3
PE6/PWM
PE7/TO
RST
PC2
PC1
PC0
PD7/EC
PD6/RMC
PD5/ACI
PD4/HSI
PD3/SI
PD2/SO
PD1/SCK
VSS
EXTAL
XTAL
PD0/INT2
Note) 1. NC (Pin 63) must be connected to VDD.
2. Vss for both Pins 32 and 62 must be grounded.
3. MP (Pin 61) must be connected to GND.
– 3 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 2 (Top View) 64 pin QFP Package
64 63 62 61 60 59 58 57 56 55 54 53 52
1
2
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA1
PA0
PF3/PWM3
PF4/PWM4/SCL0
PF5/PWM5/SCL1
PF6/PWM6/SDA0
PF7/PWM7/SDA1
BLK
PB7
3
4
PB6
5
PB5
6
PB4
R
PB3
7
G
8
PB2
9
PB1
B
10
11
12
13
14
15
16
17
18
19
PB0
VSYNC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7/EC
HSYNC
EXLC
XLC
PE0/INT0
PE1/INT1
PE2/AN0
PE3/AN1
PE4/AN2
PE5/AN3
32
20 21 22 23 24 25 26 27 28 29 30 31
Note) 1. NC (Pin 56) must be connected to VDD.
2. Vss for both Pins 26 and 58 must be grounded.
3. MP (Pin 55) must be connected to GND.
– 4 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Description
Symbol
I/O
Description
(Port A)
PA0 to PA7
PB0 to PB7
I/O
I/O
I/O
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port C)
PC0 to PC7
PD0/INT2
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
External interruption request input.
Active at falling edge.
I/O/Input
Serial clock I/O.
(Port D)
PD1/SCK
PD2/SO
PD3/SI
I/O/I/O
Serial data output.
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
8-bit I/O port.
I/O can be set ina a
unit of single bits.
Capable of driving
12mA sink current.
(8 pins)
Serial data input.
HSYNC counter input.
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC
Input for power supply frequency counter.
Input for remote control reception circuit.
External event input for timer/counter.
External interruption request inputs.
Active at falling edge.
(2 pins)
PE0/INT0
PE1/INT1
Input/Input
Input/Input
PE2/AN0
to
PE5/AN3
(Port E)
Analog inputs for A/D converter.
(4 pins)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.
14-bit PWM output.
(CMOS output)
PE6/PWM
PE7/TO
Output/Output
Output/Output
Rectangular waveform output for Timer 1.
(Duty output 50%)
PF0/PWM0
to
PF3/PWM3
(Port F)
6-bit PWM outputs.
(8 pins)
Output/Output
8-bit output port,
operating as N-ch
open drain output
for high current
(12mA).
Lower 4 bits are
medium voltage
drive outputs (12V),
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
Transfer clock I/Os for I2C bus
interface.
Output/Output/
I/O
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
Output/Output/ upper 4bits are 5V
Transfer data I/Os for I2C data bus.
I/O
drive outputs.
(8 pins)
R, G, B, BLK
HSYNC
Output
Input
4-bit outputs for CRT display.
Horizontal synchronizing signal input for CRT display.
Vertical synchronizing signal input for CRT display.
VSYNC
Input
– 5 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Symbol
EXLC
I/O
Description
Input
Clock oscillation I/Os for CRT display.
Oscillation frequency is set using the external L and C.
XLC
Output
Input
Crystai connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
XTAL
Output
Low-level active, system reset. RST is an I/O, from whlch Low level is
output when the built-in power-on reset function is activated at the rise
of power on. (Mask option)
RST
I/O
MP
VDD
Vss
Input
Microprocessor mode input. For this device, this pin must be grounded.
Vcc supply.
GND. Both Vss must be grounded.
– 6 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Input/Output Circuit Formats for Pins
Pin
Circuit format
When reset
Port A
Port B
Data for Ports
A, B, and C
Port C
PA0 to PA7
PB0 to PB7
PC0 to PC7
Direction for
Ports A, B, and C
Hi-Z
Input protection
circuit
IP
Data bus
RD (Ports A, B, and C)
24 pins
Port D
Port D data
PD0/INT2
PD3/SI
Port D direction
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC
High current
12mA
Hi-Z
IP
Data bus
RD (Port D)
INT2, SI, HSI, ACI, RMC, EC
Schmitt input
6 pins
Port D
SCK or SO
Output eneble
High current
12mA
PD1/SCK
PD2/SO
Hi-Z
Port D data
IP
Port D direction
Schmitt input
Data bus
RD (Port D)
SCK only
2 pins
– 7 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin
Circuit format
When reset
Hi-Z
Port E
Port E
Schmitt input
PE0/INT0
PE1/INT1
(To interruption circuit)
Data bus
IP
2 pins
RD (Port E)
Input multiplexer
PE2/AN0
to
PE5/AN3
IP
To A/D converter
Hi-Z
Data bus
RD (Port E)
4 pins
Port E
TO, PWM
PE6/PWM
PE7/TO
High level
Port E data
Port selection
2 pins
Port F
PWM
PF0/PWM0
to
Middle tension proof 12V
PF3/PWM3
Port F data
Hi-Z
High current
12mA
Port selection
4 pins
Port F
SCL, SDA
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
PF6/PWM6/
SDA0
I2C output enable
PWM
Hi-Z
PF7/PWM7/
SDA1
Port F data
IP
Port selection
BUS SW
Schmitt input
SCL, SDA
(To I2C circuit)
To other I2C pins
4 pins
– 8 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin
Circuit format
When reset
Hi-Z
BLK
R
G
BLK, R, G, B
Output polarity
B
Hi-Z → output active
by writing into the output polarity register.
4 pins
Schmitt input
IP
HSYNC
VSYNC
HSYNC
VSYNC
Hi-Z
Input polarity
2 pins
EXLC
XLC
IP
Oscillation control
EXLC
XLC
Oscillation
terminated
CRT display clock
IP
2 pins
• Diagram shows
circuit composition
during oscillation.
EXTAL
XTAL
EXTAL
XTAL
IP
Oscillation
• Feedback resistor
is removed during
stop.
2 pins
Pull-up resistance
Schmitt input
RST
1 pin
Mask option
OP
Low level
From power-on reset circuit
(Mask option)
MP
CPU mode
Hi-Z
IP
1 pin
– 9 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Supply voltage
Symbol
Rating
Unit
V
Remarks
VDD
VIN
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
1
1
Input voltage
V
Output voltage
VOUT
VOUTP
IOH
V
Pins PF0 to PF3
Medium voltage drive output voltage
High level output current
High level total output current
–0.3 to +15.0
V
–5
–50
mA
mA
mA
mA
mA
°C
Total for all output pins
∑IOH
IOL
Excludes high current outputs
15
Low level output current
2
High current outputs
IOLC
∑IOL
Topr
Tstg
20
Total for all output pins
Low level total output current
Operating temperature
Storage temperature
130
–20 to +75
–55 to +150
1000
°C
SDIP
QFP
mW
mW
Allowable power dissipation
PD
600
1
VIN and VOUT must not exceed VDD + 0.3V.
2
The high current operation transistor is the N-ch transistor of PD and PF0 to PF3.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions.
Exceeding these conditions may adversely affect the reliability of the LSI.
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
Min.
4.5
Max. Unit
Remarks
5.5
5.5
V
V
Guaranteed operation range
Low-speed mode guaranteed
3.5
2.5
1
Supply voltage
VDD
operation range
Guaranteed data hold range
during stop
5.5
V
2
Includes I2C Schmitt input
VIH
0.7VDD
0.8VDD
VDD
VDD
V
V
3
High level input voltage
Low level input voltage
VIHS
VIHEX
VIL
CMOS Schmitt input
4
VDD – 0.4 VDD + 0.3
V
EXTAL
2
Includes I2C Schmitt input
0
0
0.3VDD
0.2VDD
0.4
V
3
VILS
VILEX
Topr
V
CMOS Schmitt input
4
–0.3
–20
V
EXTAL
Operating temperature
+75
°C
1
Specifies only for 1/16 frequency demultiplication mode and sleep mode.
2
3
Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP.
Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC,
PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST.
4
Specifies only during external clock input.
– 10 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min. Typ. Max. Unit
V
V
4.0
3.5
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
High level output
current
PA to PD, PE6, PE7,
R, G, B, BLK
VOH
PA to PD, PE6, PE7,
R, G, B, BLK,
PF0 to PF3, RST
0.4
V
VDD = 4.5V, IOL = 1.8mA
1
0.6
1.5
0.4
V
V
V
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 4.5V, IOL = 3.0mA
Low level output
current
PD, PF0 to PF3
VOL
PF4 to PF7
(SCL0, SCL1,
SDA0, SDA1)
0.6
V
VDD = 4.5V, IOL = 4.0mA
IIHE
IIHL
IILR
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
0.5
40
µA
µA
EXTAL
Input current
–0.5
–1.5
–40
2
RST
–400 µA
PA to PE, HSYNC,
VSYNC, R, G, B,
BLK, RST , MP
VDD = 5.5V
VI = 0, 5.5V
I/O leakage current IIZ
Open drain output
±10
µA
2
PF0 to PF3
PF4 to PF7
50
10
µA
µA
VDD = 5.5V, VOH = 12.0V
VDD = 5.5V, VOH = 5.5V
ILOH
leakage current
(N-ch Tr in off state)
Impedance connected
to I2C bus switch
(output Tr in off state)
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
SCL0: SCL1
SDA0: SDA1
RBS
IDD
120
Ω
3
Operation mode
(1/2 frequency
demultiplier clock)
4MHz crystal oscillation
(C1 = C2 = 22pF)
All outputs open
8
20
mA
3
Power supply current
VDD
mA
µA
2
IDDSL
IDDST
0.5
—
Sleep mode
4
—
—
Stop mode
Pins other than
VDD and Vss
Clock 1MHz
0V for all pins excluding
pF
20
Input capacity
CIN
10
1
RST specifies only when the power-on reset circuit has been selected througn mask option.
2
RST specifies input current when the pull-up resistance has been selected; Ieakage current when no
resistance has been selected.
3
4
Specifies only when the oscillatlon of OSD has been terminated.
This device does not enter the stop mode.
– 11 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
fC
Pins
Conditions
Fig. 1, Fig. 2
Min.
3.5
Max.
4.5
Unit
XTAL
EXTAL
MHz
System clock frequency
System clock input
pulse width
Fig. 1, Fig. 2
External clock drive
t
XL,
XH
100
ns
ns
ns
ms
EXTAL
EXTAL
EC
t
System clock input rise
time, fall time
Fig. 1, Fig. 2
External clock drive
t
CR,
CF
200
20
t
Event clock input clock
pulse width
t
EH,
EL
1
tsys + 50
Fig. 3
Fig. 3
t
Event count input clock
rise time, fall time
t
ER,
EF
EC
t
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation
Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 2. Clock applying condition
0.8VDD
0.2VDD
EC
tEH
tEF
tEL
tER
Fig. 3. Event count clock timing
– 12 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(2) Serial transfer
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SCK
SI
t
KCY
SCK cycle time
8000/fc
400
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
t
KH
KL
SCK High and Low level
widths
t
4000/fc – 50
100
SI input setup time
(for SCK ↑)
t
t
t
SIK
200
200
SI input hold time
(for SCK ↑)
SI
KSI
100
200
100
SO
KSO
SCK ↓ → SO delay time
Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
0.8VDD
0.2VDD
SCK
tSIK
tKSI
0.8VDD
0.2VDD
SI
Input data
tKSO
0.8VDD
SO
Output data
0.2VDD
Fig. 4. Serial transfer timing
– 13 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(3) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions Min.
Max.
Unit
µs
External interruption High and
Low level widths
tIH
IL
INT0 to
INT2
1
t
8/fc
µs
Reset input Low level width
tRSL
RST
tIH
tIL
0.8VDD
INT0 to INT2
(Falling edge)
0.2VDD
Fig. 5. Interruption input timing
tRSL
RST
0.2VDD
Fig. 6. RST input timing
(4) Power on reset
Power on reset
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Power-on reset
Repetitive power-on reset
Min.
0.05
1
Max. Unit
Power supply rise time
Power supply cut-off time
50
ms
ms
tR
VDD
tOFF
Specifies only when the power-on reset function has been selected.
4.5V
VDD
0.2V
0.2V
tR
tOFF
The power supply should be raised smoothly.
Fig. 7. Power-on reset
– 14 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(5) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Resolution
Symbol
Pin
Condition
Min.
Typ.
Max.
4
Unit
Bits
LSB
Linearity error
±1
Ta = 25°C
VDD = 5.0V
Vss = 0V
Zero transition
voltage
1
VZT
–10
160
320
mV
mV
Full-scale transition
voltage
2
VFT
4370
4530
4690
Conversion time
Sampling time
t
t
CONV
SAMP
160/fc
12/fc
0
µs
µs
V
Analog input voltage VIAN
AN0 to AN3
VDD
FH
EH
1
VZT: Value at which the digital conversion value changes
from 0H to 1H and vice versa.
2
VFT: Value at which the digital conversion value changes
from EH to FH and vice versa.
Linearity error
1H
0H
VZT
VFT
Analog input
Fig. 8. Definition of A/D converter terms
Note) The 4-bit conversion specifies values based on the upper 5 bits of the A/D data register (ADD: Address
00F5H), compensated into 4-bit data. A program example is shown below:
(A/D converter program example)
MOV
LSR
LSR
LSR
LSR
ADC
CMP
BNE
MOV
A, ADD
; ACC ← conversion data
A
; Shift to the right (4 times)
A
;
A
;
A
;
A, #00H
A, #10H
ADC_SKIP ;
; Addition with carry (data increment if AD3 = 1)
;
A, #0FH
;
ADC_SKIP:
– 15 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(6) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
SCL
Conditions
Min.
0
Max.
100
Unit
kHz
µs
SCL clock frequency
Bus free time prior to transfer start
Transfer start hold time
Clock Low level width
Clock High level width
Setup time during repetitive transfer
Data hold time
fSLC
BUF
t
t
t
t
t
t
t
t
t
t
SDA, SCL
SDA, SCL
SCL
4.7
4.0
4.7
4.0
4.7
HD; STA
LOW
µs
µs
HIGH
SCL
µs
SU; STA
HD; DAT
SU; DAT
R
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
µs
1
0
µs
Data setup time
250
ns
SDA, SCL rise time
1
µs
SDA, SCL fall time
F
300
ns
Transfer end setup time
SU; STO
4.7
µs
1
The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold
time exceeds 300ns.
SDA
tBUF
tR
tF
tHD; STA
SCL
tHD; STA
tSU; STO
tSU; STA
P
S
St
P
tLOW
tHD; DAT
tHIGH
tSU; DAT
Fig. 9. I2C bus transfer timing
I2C device
I2C device
RS
RS RS
RS
RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
Fig. 10. Recommended circuit example for I2C device
• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise
caused by CRT flashover.
– 16 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(7) OSD (On-Screen Display) timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
fOSC
Pins Condition
Unit
Min.
4
Max.
13
EXLC
OSD clock frequency
Fig. 12
MHz
XLC
HSYNC pulse width
VSYNC pulse width
µs
H*
Fig. 11
Fig. 11
HSYNC
VSYNC
1.2
1.0
t
t
HWD
VWD
HSYNC after-edge
rise time/fall time
ns
µs
Fig. 11
Fig. 11
HSYNC
VSYNC
200
1.0
t
t
HCG
VCG
VSYNC after-edge
rise time/fall time
* H indicates 1HSYNC period.
tHCG
tHWD
0.8VDD
HSYNC
when Bit 5 of OPOL register
(01FBH) is set to "0"
0.2VDD
tVCG
tVWD
0.8VDD
0.2VDD
VSYNC
when Bit 4 of OPOL register
(01FBH) is set to "0"
Fig. 11. OSC timing
EXLC
XLC
L
C1
C2
Fig. 12. LC oscillation circuit example
– 17 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Supplement
(i)
(ii)
EXTAL
XTAL
Rd
EXTAL
XTAL
Rd
C1
C2
C1 C2
Fig. 13. Recommended Oscillation circuit
Circuit
example
Model
Rd (Ω)
Manufacturer
fc (MHz)
C1 (pF)
30
C2 (pF)
30
CSA4.00MG
CSA4.19MG
CST4.00MGW
CST4.19MGW
4.00
4.19
4.00
4.19
4.00
4.19
4.00
4.19
(i)
MURATA
MFG
CO., LTD.
0
(ii)
RIVER ELETEC
CORPORATION
10
18
0
0
HC-49/U03
10
18
(i)
KINSEKI
LTD.
HC-49/U (-S)
Indicates types with on-chip grounding capacitance (C1 and C2).
Mask option table
Content
Item
Existent
Existent
Non-existent
Non-existent
Reset pin pull-up resistance
Power-on reset circuit
– 18 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
IDD vs. VDD
(fc = 4MHz, Ta = 25°C typical)
IDD vs. fc
(VDD = 5V, Ta = 25°C typical)
12
15
10
1/2 frequency
demultiplication mode
1/2 frequency
demultiplication mode
11
10
9
1/4 frequency
demultiplication mode
8
1/16 frequency
demultiplication mode
7
1/4 frequency
demultiplication mode
1
6
5
Sleep mode
4
3
1/16 frequency
demultiplication mode
2
1
0.1
Sleep mode
0
1
2
3
4
5
6
2
3
4
5
6
VDD – Supply voltage [V]
fc – System clock [MHz]
OSD oscillation vs. C
Calculated curves
(reference value by theoretical calculation)
100
5.0MHz
6.5MHz
10
13.0MHz
1
fosc =
C = C1//C2
2π LC
1
0
50
100
C1, C2 – Capacitance [pF]
Fig. 14. Characteristics curves
– 19 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
+ 0.4
57.6 – 0.1
64
33
0° to 15°
1
32
1.778
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 ALLOY
8.6g
SONY CODE
EIAJ CODE
SDIP-64P-01
SDIP064-P-0750
JEDEC CODE
PACKAGE MASS
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
51
33
52
32
64
20
+ 0.2
0.1 – 0.05
1
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
0° to10°
M
0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
EIAJ CODE
QFP-64P-L01
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.5g
QFP064-P-1420
JEDEC CODE
– 20 –
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