CXP82940 [SONY]
CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机
| 型号： | CXP82940 |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS 8-bit Single Chip Microcomputer |
| 文件： | 总24页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP82940/82948/82952/82960
CMOS 8-bit Single Chip Microcomputer
Description
80 pin QFP (Plastic)
The CXP82940/82948/82952/82960 is a CMOS 8-bit
single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, fluorescent display panel
controller/driver, I2C bus interface, remote control
transmission circuit, remote control reception circuit,
and 32kHz timer/counter besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.
Structure
Silicon gate CMOS IC
Features1
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
• Incorporated ROM capacity
250ns at 16MHz operation
(122µs at 32kHz operation)
40K bytes (CXP82940)
48K bytes (CXP82948)
52K bytes (CXP82952)
60K bytes (CXP82960)
• Incorporated RAM capacity
• Periphera; functions
— A/D converter
2048 bytes (including fluorescent display area)
8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)
— Serial interface
— Timers
Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit timer, 8-bit timer/counter, 19-bit time base timer
32kHz timer/counter
—
Fluorescent display panel controller/driver Maximum of 196 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (Mask option)
Hardware key scan function
Maximum of 12 × 8 key matrix supportable
— I2C bus interface
— Remote control transmission circuit
Auto transmission for 1 to 32 bytes,
restart function, carrier output function
8-bit pulse measurement counter, 6-stage FIFO
16 factors, 15 vectors, multi-interruption possible
SLEEP/STOP
— Remote control reception circuit
• Interruption
• Standby mode
• Package
80-pin plastic QFP
• Piggyback/evaluation chip
CXP82900 80-pin ceramic QFP
Perchase of Sony’s I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95130-PK
CXP82940/82948/82952/82960
P O R T A P O R T B P O R T C P O R T D P O R T E P O R T F P O R T G
S S V
D D V
R S T
X T A L
E X T A
T X
T E X
I N T 3 / N M I
I N T 2
I N T 1
I N T E R R U P T C O N T R O L L E R
I N T 0
D D A V
R E F A V
S S A V
– 2 –
CXP82940/82948/82952/82960
Pin Assignment (Top View)
80 79 78 77 76 75 74 73 72 71
70 69 68 67
66 65
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
1
2
64
T7
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
T8/S19
T9/S18
T10/S17
T11/S16
T12/S15
T13/S14
T14/S13
T15/S12
S11
3
4
5
PE6/RMCO
PE7/TO/ADJ
PB0
6
7
8
PB1/CS0
PB2/SCK0
PB3/SI0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S10
PB4/SO0
PB5/SCK1
PB6/SI1
S9
S8
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
VFDP
PB7/SO1
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AVDD
PC7/KR7
PC6/KR6
35
36 37 38
40
39
25 26 27 28 29 30
31
32 33
34
Note) NC (Pin 75) must be connected to VDD.
– 3 –
CXP82940/82948/82952/82960
Pin Description
Pin code
Functions
I/O
(Port A)
8-bit I/O port. I/O can
be set in a unit of
single bits.
PA0/AN0
to
PA7/AN7
I/O/
Analog input
Incorporation of pull-up Analog inputs to A/D converter. (8 pins)
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
I/O
PB0
(Port B)
I/O/Input
I/O/I/O
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
8-bit I/O port. I/O can
be set in a unit of
single bits.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
(8 pins)
I/O/Input
I/O/Output
I/O/I/O
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
I/O/Input
I/O/Output
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can
be set in a unit of single
bits. Capable of driving
12mA sync current.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
Serves as key return inputs when operating
key scan with fluorescent display panel (FDP)
segment signal (8 pins).
PC0/KR0
to
PC7/KR7
I/O/Input
(8 pins)
External event inputs for
timer/counter.
Input/Input/Input
PE0/INT0/EC
Inputs for
external
interruption
request.
(4 pins)
Input/Input
Input/Input
PE1/INT1
PE2/INT2
(Port E)
Non-maskable interruption
request input.
PE3/INT3/
NMI
Input/Input/Input
8-bit port. Lower 6 bits
are for inputs; upper
2 bits are for outputs.
(8 pins)
Remote control reception circuit input.
Input/Input
Input
PE4/RMC
PE5
Carrier output of remote control transmission
circuit.
Output/Output
PE6/RMCO
PE7/TO/ADJ
Output for the timer/counter rectangular waves,
and 32kHz oscillation dividing frequency.
Output/Output/
Output
(Port F)
PF0/SCL0
PF1/SCL1
Transfer clock I/Os for I2C bus interface.
Transfer data I/Os for I2C bus interface.
Output/I/O
Output/I/O
4-bit output port,
operating as N-ch open
drain output for large
current (12mA).
(4 pins)
PF2/SDA0
PF3/SDA1
– 4 –
CXP82940/82948/82952/82960
Pin code
I/O
Functions
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits.
PG0 to PG3
I/O
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits.
(4 pins)
(Port D)
PD0/S0
to
PD7/S7
FDP segment signal outputs.
8-bit output ports.
(8 pins)
Output/Output
Output
(8 pins)
S8 to S11
FDP segment signal outputs. (4 pins)
T8/S12
to
T15/S19
Outputs for FDP timing signals/segment signals.
(8 pins)
Output/Output
Output
T0 to T7
FDP timing signal outputs.
VFDP
FDP voltage supply when incorporated resistor is set by mask option.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
EXTAL
XTAL
TEX
Input
Output
Input
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
TX
Output
Input
Low-level active, system reset.
NC. Under normal operation, connect to VDD.
Positive power supply for A/D converter.
Reference voltage input for A/D converter.
A/D converter GND.
RST
NC
AVDD
AVREF
AVSS
VDD
Input
Positive power supply.
GND.
VSS
– 5 –
CXP82940/82948/82952/82960
I/O Circuit Format for Pins
Circuit format
Pin
When reset
Port A
Pull-up resistor
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
"0" when reset
Input
protection
circuit
IP
Hi-Z
Data bus
RD (Port A)
Port A input
selection
Input multiplexer
"0" when reset
A/D converter
Pull-up transistor approx. 100kΩ
8 pins
Port B
Pull-up resistor
"0" when reset
Port B data
PB1/CS0
PB3/SI0
PB6/SI1
Port B direction
"0" when reset
IP
Hi-Z
Schmitt input
Data bus
RD (Port B)
CS0
SI0
SI1
Pull-up transistor approx. 100kΩ
3 pins
Not Schmitt input for SI0 and SI1.
Port B
Pull-up resistor
"0" when reset
SCK OUT
Output enable
Port B output
selection
PB2/SCK0
PB5/SCK1
"0" when reset
IP
Port B data
Hi-Z
Port B direction
"0" when reset
Schmitt input
Data bus
RD (Port B)
2 pins
Pull-up transistor approx. 100kΩ
SCK in
– 6 –
CXP82940/82948/82952/82960
Pin
Circuit format
When reset
Port B
Pull-up resistor
"0" when reset
SO
Output enable
Port B output
selection
PB4/SO0
PB7/SO1
"0" when reset
IP
Hi-Z
Port B data
Port B direction
“0” when reset
Data bus
RD (Port B)
2 pins
Pull-up transistor approx. 100kΩ
Port C
2
Pull-up resistor
"0" when reset
Port C data
PC0/KR0
to
PC7/KR7
1
Hi-Z
Port C direction
"0" when reset
IP
Data bus
RD (Port C)
Key input signal
1 Large current 12mA
2 Pull-up transistor approx. 100kΩ
8 pins
Port E
PE0/EC/INT0
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
EC/INT0
INT1
INT2
INT3/NMI
RMC
Schmitt input
IP
Hi-Z
Hi-Z
Data bus
5 pins
RD (Port E)
Port E
Port E
PE5
Data bus
IP
1 pin
RD (Port E)
Remote control
transmission circuit
Port E output selection
"0" when reset
PE6/RMCO
1 pin
High level
Reset E data
Output enable
"1" when reset
Data bus
RD (Port E)
– 7 –
CXP82940/82948/82952/82960
Circuit format
Pin
When reset
Port E
Internal reset signal
00
Port E data
"1" when reset
01
10
11
TO
MPX
1
ADJ16K
2
High level
with approx.
1
ADJ2K
PE7/TO/ADJ
(
150kΩ
resistor when
reset)
Port E output selection (upper)
Port E output selection (lower)
"00" when reset
1
ADJ signal is a frequency dividing output for
32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.
TO output enable
2
Pull-up transistor approx. 150kΩ.
1 pin
Port F
SCL, SDA
I2C output enable
("0" when reset)
Large current
12mA
PF0/SCL0
PF1/SCL1
PF2/SDA0
PF3/SDA1
Hi-Z
Port F data
"1" when reset
IP
Schmitt input
SCL, SDA
(I2C circuit)
BUS SW
To internal I2C pin
(to SCL1 for SCL0)
4 pins
Port B
Port G
Pull-up resistor
"0" when reset
Port B data or
Port G data
PB0
PG0 to PG3
Port B direction or
Port G direction
Hi-Z
IP
"0" when reset
Data bus
RD (Port B or Port G)
Pull-up transistor approx. 100kΩ
5 pins
– 8 –
CXP82940/82948/82952/82960
Circuit format
When reset
Pin
Port D
High voltage drive transistor
Segment output data
Output selection
control signal
("0" when reset)
PD0/S0
to
PD7/S7
Hi-Z or
Low level
(when PD
resistor is
connected)
Mask option
OP
Port D data
Pull-down
transistor
VFDP
Data bus
RD (Port D)
8 pins
High voltage drive transistor
Segment output data
Timing output data
S8 to S11
T15/S12
to
Hi-Z or
Output selection
control signal
Low level
(when PD
resistor is
connected)
T8/S19
T0 to T7
("0" when reset)
OP
Mask option
Pull-down
resistor
VFDP
20 pins
• Diagram shows circuit
composition during oscillation.
EXTAL
XTAL
IP
IP
EXTAL
• Feedback resistor is removed
during stop, and XTAL
becomes High.
Oscillation
XTAL
2 pins
• Diagram shows circuit
composition during oscillation.
TEX
TX
IP
IP
TEX
TX
Oscillation
• When the operation of the oscillation
circuit is stopped by the software,
the feedback resistor is removed,
and TEX becomes Low level and TX
becomes High level.
2 pins
Pull-up resistor
RST
1 pin
OP
Mask option
IP
Low level
Schmitt input
– 9 –
CXP82940/82948/82952/82960
Absolute Maximum Ratings
(Vss = 0V reference)
Remarks
Item
Supply voltage
Input voltage
Symbol
Rating
Unit
V
VDD
VIN
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
1
1
V
V
Output voltage
VOUT
As P channel transistor is open drain,
VDD is reference.
V
Display output voltage
VOD
VDD – 40 to VDD + 0.3
mA All pins excluding outputs 2 (value per pin)
mA Display outputs S0 to S11 (value per pin)
IOH
–5
IODH1
–15
High level output current
Display outputs T0 to T7, and T8/S19 to
T15/S12 (value per pin)
mA
IODH2
–35
mA Total for all pins excluding display outputs
mA Total for all display outputs
mA Port (value per pin)
∑IOH
∑IODH
IOL
–40
–100
High level total output
current
15
Low level output current
3
mA Large current Port (value per pin)
IOLC
20
mA Total for all output pins
Low level total output current ∑IOL
100
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
–20 to +75
–55 to +150
600
mW
Allowable power dissipation PD
1
VIN and VOUT must not exceed VDD + 0.3V.
2
3
Specifies output current of general-purpose I/O ports.
The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.
– 10 –
CXP82940/82948/82952/82960
Recommended Operating Conditions
(Vss = 0V reference)
Remarks
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Guaranteed operation range for high-speed
mode (1/2, 1/4 frequency dividing clock)
Guaranteed operation range for low-speed
mode (1/16 frequency dividing clock) or
SLEEP mode
3.5
2.7
5.5
5.5
V
V
Supply voltage
VDD
Guaranteed operation range with TEX
clock
5.5
VDD
VDD
V
V
Guaranteed data hold range during STOP
2.5
1
0.7VDD
0.8VDD
VIH
High level input
voltage
2
V
Hysteresis input
VIHS
VIHEX
VIL
3
V
EXTAL
VDD – 0.4 VDD + 0.3
1
0
0
0.3VDD
0.2VDD
0.4
V
Low level input
voltage
2
V
Hysteresis input
VILS
VILEX
Topr
3
V
EXTAL
–0.3
–20
Operating temperature
+75
°C
1
Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG).
Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1,
SDA0, SDA1.
2
3
Specifies only during external clock input.
– 11 –
CXP82940/82948/82952/82960
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
4.0
Typ.
Max.
Unit
V
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
High level
output current
VOH
PA, PB,
PC, PE6,
PE7, PG
3.5
V
0.4
0.6
1.5
V
V
Low level
output current
PC, PF
V
VOL
PF
0.4
0.6
V
V
VDD = 4.5V, IOL = 3.0mA
VDD = 4.5V, IOL = 4.0mA
(SCL0, SCL1,
SDA0, SDA1)
0.5
–0.5
0.1
40
–40
10
µA
µA
µA
µA
µA
µA
µA
mA
IIHE
IILE
IIHT
IILT
IILR
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V
EXTAL
TEX
Input current
–0.1
–1.5
–10
–400
–50
1
RST
VDD = 5.5V, VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
2
PA to PC ,
IIL
2
PG
–3.3
–8
S0 to S11
VDD = 4.5V
VOH = VDD – 2.5V
Display output
current
S12/T15 to
S19/T8,
IOH
–20
mA
µA
T0 to T7
S0 to S11,
S12/T15 to
S19/T8,
Open drain output
leakage current
(P-CH Tr off state)
VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V
ILOL
–20
T0 to T7
S0 to S11,
S12/T15 to
S19/T8,
Pull-down
resistance
VDD = 5V
VOD – VFDP = 30V
RL
60
100
270
±10
10
kΩ
µA
µA
3
T0 to T7
2
PA to PC ,
I/O
VDD = 5.5V
VI = 0, 5.5V
2
IIZ
PG ,
leakage current
1
RST
Open drain
output leakage
current (N-ch Tr
off state)
PF
VDD = 5.5V, VOH = 5.5V
ILOH
I2C bus switch
connection
impedance
(Output Tr off
state)
VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V
SCL0: SCL1
SDA0: SDA1
120
Ω
RBS
– 12 –
CXP82940/82948/82952/82960
Symbol
Pins
Conditions
Min.
Typ.
31
Max. Unit
Item
High speed mode operation
(1/2 frequency dividing clock)
50
mA
IDD1
VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32MHz crystal
oscillation (C1 = C2 = 47pF)
40
2.5
8
100
10
µA
IDD2
Power supply
SLEEP mode
VDD
4
current
mA
IDDS1
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)
30
10
µA
µA
IDDS2
IDDS3
STOP mode
VDD = 5.5V, termination of 16MHz
and 32kHz crystal oscillation
PA to PC,
PE0 to PE5,
PF, PG,
EXTAL,
XTAL, TEX,
TX, RST
Clock 1MHz
0V for all pins excluding
measured pins
Input
capacity
10
20
pF
CIN
1
RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
2
PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current
when no resistance has been selected.
3
4
When incorporated pull-down resistance has been selected through mask option.
When all pins are open.
– 13 –
CXP82940/82948/82952/82960
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
Item
Pin
Conditions
Fig. 1, Fig. 2
Min.
1
Typ.
Max.
16
Unit
XTAL
EXTAL
System clock frequency
fC
MHz
t
XL
Fig. 1, Fig. 2
External clock drive
System clock input pulse width
EXTAL
EXTAL
EC
ns
ns
ns
ms
28
tXH
System clock input rise time,
fall time
t
CR
CF
Fig. 1, Fig. 2
External clock drive
200
20
t
Event count input clock
pulse width
t
EH
EL
Fig. 3
Fig. 3
4tsys
t
Event count input clock
rise time, fall time
t
ER
EF
EC
t
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
TX
System clock frequency
fC
kHz
32.768
Event count input
pulse width
t
TL
TEX
TEX
Fig. 3
Fig. 3
µs
10
tTH
Event count input rise time,
fall time
tTR
TF
ms
20
t
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
0.4V
EXTAL
tXH
tCF
tXL
tCR
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
32kHz clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
0.8VDD
0.2VDD
TEX
EC
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
– 14 –
CXP82940/82948/82952/82960
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Min.
Condition
Max.
Unit
ns
Chip select transfer mode
(SCK = output mode)
CS ↓ → SCK
delay time
t
t
t
DCSK
DCSKF
DCSO
SCK0
1.5tsys + 200
Chip select transfer mode
(SCK = output mode)
CS ↑ → SCK
float delay time
ns
ns
ns
SCK0
SO0
1.5tsys + 200
1.5tsys + 200
1.5tsys + 200
CS ↓ → SO
delay time
Chip select transfer mode
Chip select transfer mode
CS ↑ → SO
float delay time
t
t
DCSOF
WHCS
SO0
CS0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select transfer mode
Input mode
CS High level width
tsys + 200
2tsys + 200
8000/fc
SCK cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
tsys + 100
8000/fc – 100
–tsys + 100
200
SCK
t
t
KH
KL
High, Low level width
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input setup time
(for SCK ↑)
t
t
t
SIK
2tsys + 100
100
SI input hold time
(for SCK ↑)
KSI
SI0
2tsys + 200
100
SCK ↓ → SO
delay time
KSO
SO0
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) CS, SCK, SI and SO correspond to each pin of CS0, SCK0, SI0 and SO0.
Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
– 15 –
CXP82940/82948/82952/82960
Fig. 4. Serial transfer CH0 timing (CH0)
tWHCS
CSO
0.8VDD
0.2VDD
tKCY
tDCSKF
tDCSK
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tSIK
tKSI
0.8VDD
0.2VDD
SI0
Input data
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
Output data
SO0
– 16 –
CXP82940/82948/82952/82960
Serial transfer (CH1) (SIO mode)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Input mode
Min.
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
SCK1
tKCY
Ouput mode
Input mode
SCK1
t
KH
KL
SCK1
SI1
High, Low level width
t
Ouput mode
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
SCK1 input mode
SCK1 ouput mode
SI1 input setup time
(for SCK1 ↑)
t
t
t
SIK
200
tsys + 200
100
SI1 input hold time
(for SCK1 ↑)
KSI
SI1
tsys + 200
100
SCK1 ↓ → SO1 delay time
KSO
SO1
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock registor (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI1
tKSO
0.8VDD
SO1
Output data
0.2VDD
– 17 –
CXP82940/82948/82952/82960
Serial transfer (CH1) (Special mode)
Item Symbol
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Pin
Condition
Min.
Typ.
104
Max.
Unit
µs
SO1
SI1
SO1 cycle time
t
LCY
SI1 data setup time
SI1 data hold time
t
t
LSU
LHD
SI1
SI1
2
2
µs
µs
t
LCY is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1) (SIOM1:
address 01E2H) is set to 104µs.
Note) The load condition for SO1 is 50pF + 1TTL.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY
tLCY
SO1
Start bit
Output data bit
0.5VDD
tLCY/2
tLSU
tLHD
0.8VDD
0.2VDD
Input
data bit
SI1
– 18 –
CXP82940/82948/82952/82960
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Resolution
Symbol
Pin
Condition
Min.
Typ. Max. Unit
8
Bits
Linearity error
±3
LSB
Ta = 25°C
Zero transition
voltage
1
VZT
–10
10
70
mV
V
DD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Full-scale
transition voltage
2
VFT
4910
4970 5030 mV
3
Conversion time
160/fADC
12/fADC
µs
µs
t
CONV
SAMP
3
Sampling time
t
AVREF
Reference input voltage
Analog input voltage
VDD = AVDD = 4.5 to 5.5V
Operation mode
AVDD – 0.5
0
AVDD
AVREF
1.0
V
V
VREF
VIAN
IREF
AN0 to AN7
0.6
mA
SLEEP mode
STOP mode
AVREF current
AVREF
IREFS
10
µA
32kHz operation mode
Fig. 7. Definition of A/D converter terms
FFH
FEH
1
2
3
VZT: Value at which the digital conversion value change
from 00H to 01H and vice versa.
VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
fADC indicates the below values due to the contents of bit 6
(CKS) of the A/D control register (address: 00F9H) and bits 7
(PCK1) and 6 (PCK0) of the clock control register (address:
00FEH).
Linearity error
01H
00H
CKS
0 (φ /2 selection)
1 (φ selection)
PCK1, PCK0
VZT
VFT
Analog input
00 (φ = fEX/2)
fADC = fC/2
fADC = fC/4
fADC = fC/16
fADC = fC
01 (φ = fEX/4)
11 (φ = fEX/16)
fADC = fC/2
fADC = fC/8
– 19 –
CXP82940/82948/82952/82960
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Min.
Max.
Item
Symbol
Pin
INT0
Condition
Unit
INT1
INT2
INT3
NMI
External interruption
High, Low level width
t
t
IH
IL
1
µs
Reset input Low level width
32/fc
µs
t
RSL
RST
Fig. 8. Interruption input timing
tIH
tIL
0.8VDD
INT0
0.2VDD
INT1
INT2
tIL
tIH
INT3
NMI
(NMI specifies only the
falling edge.)
Fig. 9. RST input timing
tRSL
RST
0.2VDD
– 20 –
CXP82940/82948/82952/82960
(5) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
SCL
Condition
Min.
0
Max.
100
Unit
kHz
µs
SCL clock frequency
fSLC
BUF
Bus-free time before starting transfer
Hold time for starting transfer
Clock Low level width
t
t
t
t
t
t
t
t
t
t
SDA, SCL
SDA, SCL
SCL
4.7
4.0
4.7
4.0
4.7
0
µs
HD; STA
LOW
µs
µs
Clock High level width
Setup time for repetitive transfers
Data hold time
HIGH
SCL
µs
SU; STA
HD; DAT
SU; DAT
R
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
µs
ns
Data setup time
250
µs
SDA, SCL rise time
1
ns
SDA, SCL fall time
F
300
µs
Setup time for transfer completion
SU; STO
4.7
The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.
Fig.10. I2C bus transfer timing
SDA
tBUF
tR
tF
tHD ; STA
SCL
tHD ; STA
tSU ; STO
tSU ; STA
P
S
St
P
tLOW
tHD ; DAT
tHIGH
tSU ; DAT
Fig.11. Recommended circuit example for I2C device
I2C
device
I2C
device
RS
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by
CRT flash-over.
– 21 –
CXP82940/82948/82952/82960
Appendix
Fig. 12. Recommended oscillation circuit
(i)
(ii)
EXTAL
XTAL
Rd
TEX
TX
Rd
C2
C1
C2
C1
Circuit
example
Model
fc (MHz)
C1 (pF)
10
C2 (pF)
10
Rd (Ω)
Manufacturer
8.00
RIVER
ELETEC
CO., LTD.
10.00
(i)
0
HC-49/U03
5
12.00
16.00
8.00
5
16 (12)
16 (12)
12
16 (12)
16 (12)
12
0
10.00
(i)
HC-49/U (-S)
P3
KINSEKI
LTD.
12.00
16.00
0
0
12
12
30
18
(ii)
32.768kHz
470k
Mask Option Table
Content
Item
Reset pin pull-up resistance
High voltage drive output port pull-down resistance
Existent
Existent (Selectable for each pin)
Non-existent
Non-existent
– 22 –
CXP82940/82948/82952/82960
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
50
1/2 dividing mode
30
20
1/4 dividing mode
30
20
10
1/2 dividing mode
10
5
1/16 dividing mode
SLEEP mode
1
1/4 dividing mode
0.5
(500µA)
32kHz mode
(instruction)
0.1
(100µA)
0.05
(50µA)
32kHz
SLEEP mode
1/16 dividing mode
SLEEP mode
0.01
(10µA)
0
1
2
3
4
5
6
7
0
5
10
15
VDD – Supply voltage [ V ]
Frequency [MHz]
– 23 –
CXP82940/82948/82952/82960
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
64
41
65
40
A
+ 0.2
0.1 – 0.05
80
25
1
24
+ 0.15
+ 0.35
2.75 – 0.15
0.8
0.35 – 0.1
0.12
M
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
EIAJ CODE
QFP-80P-L01
QFP080-P-1420-A
COPPER / 42 ALLOY
1.6g
JEDEC CODE
PACKAGE WEIGHT
– 24 –
相关型号：
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