CXP83120A [SONY]

CMOS 8-bit Single Chip Microcomputer; CMOS 8位单片机


型号：	CXP83120A
厂家：	SONY CORPORATION
描述：	CMOS 8-bit Single Chip Microcomputer CMOS 8位单片机微控制器和处理器外围集成电路 ISM频段时钟
文件：	总24页 (文件大小：558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXP83120A/83124A

CMOS 8-bit Single Chip Microcomputer

Description

100 pin QFP (Plastic)

100 pin LQFP (Plastic)

The CXP83120A/83124A is a CMOS 8-bit single

chip microcomputer integrating on a single chip an

A/D converter, serial interface, timer/counter, time

base timer, 32kHz timer/counter, capture timer

counter, LCD controller/driver, remote control

reception circuit and 14-bit PWM output besides the

basic configurations of 8-bit CPU, ROM, RAM, and

I/O port.

The CXP83120A/83124A also provides a sleep/stop

function that enables lower power consumption.

Features

• Wide-range instruction system (213 instructions) to cover various types of data.

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle

• Incorporated ROM capacity

400ns at 10MHz operation

8µs at 500kHz

122µs at 32kHz operation

20Kbytes (CXP83120A)

24Kbytes (CXP83124A)

644bytes (includes LCD display data area)

• Incorporated RAM capacity

• Peripheral functions

— A/D converter

8-bit, 8-channel, successive approximation method

(Conversion time of 32µs/10MHz)

— Serial interface

8-bit, 8-stage FIFO incorporated

(Auto transfer for 1 to 8 bytes), 1 channel

8-bit clock synchronized type, 1 channel

8-bit timer, 8-bit timer/counter, 19-bit time base timer,

16-bit capture timer/counter, 32kHz timer/counter

Maximum 160 segment display possible (during 1/4 duty)

4 common output, 40 segment output

Display method static, 1/2, 1/3, 1/4 duty

Bias method 1/2, 1/3 bias

— Timer

— LCD controller/driver

— Remote control reception circuit

— PWM output circuit

• Interruption

8-bit pulse measuring counter, 6-stage FIFO

14 bits, 1 channel

15 factors, 15 vectors, multi-interruption possible

SLEEP/STOP

• Standby mode

• Package

100-pin plastic QFP/LQFP

• Piggyback/evaluation chip

CXP83200A 100-pin ceramic QFP/LQFP

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94843-PK

CXP83120A/83124A

A T R P O B T R P O C T R P O D T R P O E T R P O F T R P O G T R P O H T R P O

S S V

D D V

R S

1 A L X T

1 A L E X T

2 A L X T

2 A L E X T

T X

X T E

3 T I / I N M N

2 T I N

1 T I N

0 T I N

R E L L R O N T C T O

R E R T U N P I

R E A V

S S A V

– 2 –

CXP83120A/83124A

Pin Assignment (Top View) (QFP package)

99 98

96 95 94 93 92 91

90 89 88 87 86 85 84 83 82 81

100

PE3/INT2

PE3/INT3/NMI

PE4/RMC

SEG26/PF2

SEG25/PF1

SEG24/PF0

SEG23/PD7

SEG22/PD6

SEG21/PD5

SEG20/PD4

SEG19/PD3

SEG18/PD2

SEG17/PD1

SEG16/PD0

SEG15

PE5/PWM

PE6/TO/ADJ

PB0/CINT

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1

PB7/SO1

PC0

SEG14

SEG13

PC1

SEG12

PC2

SEG11

PC3

SEG10

PC4

SEG9

PC5

SEG8

PC6

SEG7

PC7

SEG6

PH0

SEG5

PH1

SEG4

PH2

SEG3

PH3

SEG2

PH4

SEG1

PH5

SEG0

PH6

COM3

PH7

COM2

PA0/AN0

COM1

32 33

36 37 38 39 40 41 42

43 44 45 46

48 49 50

Note) 1. NC (Pin 90) is always connected to VDD.

2. VSS (Pin 41 and 91) are both connected to GND.

– 3 –

CXP83120A/83124A

Pin Assignment (Top View) (LQFP package)

99 98

96 95 94 93 92 91

90 89 88 87 86 85 84 83 82 81 80 79

100

78 77 76

SEG23/PD7

SEG22/PD6

SEG21/PD5

SEG20/PD4

SEG19/PD3

SEG18/PD2

SEG17/PD1

SEG16/PD0

SEG15

PE4/RMC

PE5/PWM

PE6/TO/ADJ

PB0/CINT

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

SEG14

PB6/SI1

PB7/SO1

SEG13

PC0

PC1

PC2

PC3

PC4

PC5

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

PC6

PC7

PH0

PH1

PH2

PH3

PH4

PH5

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

COM3

26 27 28 29 30

32 33

36 37

38 39 40

43 44 45 46

48 49 50

Note) 1. NC (Pin 88) is always connected to VDD.

2. VSS (Pin 39 and 89) are both connected to GND.

– 4 –

CXP83120A/83124A

Pin Description

Symbol

I/O

Functions

(Port A)

8-bit I/O port. I/O can

be set in a single bit

unit.

Incorporation of pull-up

resistor can be set

through the software in

a unit of 4 bits. (8 pins)

PA0/AN0

PA7/AN7

Analog inputs to A/D converter.

(8 pins)

I/O/Analog input

I/O/Input

I/O/I/O

External capture input to 16-bit timer/counter.

Chip select input for serial interface (CH0).

Serial clock I/O (CH0).

PB0/CINT

PB1/CS0

PB2/SCK0

PB3/SI0

(Port B)

8-bit I/O port. I/O can

be set in a single bit

unit.

Incorporation of pull-up

resistor can be set

through the software in

a unit of 4 bits.

(8 pins)

I/O/Input

I/O/Output

I/O/I/O

Serial data input (CH0).

Serial data output (CH0).

PB4/SO0

PB5/SCK1

PB6/SI1

Serial clock I/O (CH1).

I/O/input

I/O/Output

Serial data input (CH1).

Serial data output (CH1).

PB7/SO1

(Port C)

8-bit I/O port. I/O can be set in a single bit unit. Capable of driving 12mA

sync current. Incorporation of pull-up resistor can be set through the

software in a unit of 4 bits.

I/O

PC0 to PC7

(8 pins)

PE0/INT0/

EC0

Input/Input/Input

External event inputs for

timer/counter.

(2 pins)

PE1/INT1/

EC1

Input/Input/Input

Input/Input

External interruption request inputs.

(Port E)

PE2/INT2

(4 pins)

7-bit port. lower 5 bits

are for inputs; upper 2

bits are for outputs.

(7 pins)

Non-maskable interruption request

input.

PE3/INT3/

NMI

Input/Input/Input

Remote control reception circuit input.

14-bit PWM output.

Input/Input

PE4/RMC

PE5/PWM

Output/Output

Rectangular wave output

for 16-bit timer/counter

(duty output 50%).

Output for 32kHz

oscillation

frequency division.

Output/Output/

Output

PE6/TO/

ADJ

(Port H)

8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up

resistor can be set through the software in a unit of 4 bits.

(8 pins)

I/O

PH0 to PH7

– 5 –

CXP83120A/83124A

Symbol

I/O

Functions

PD0/SEG16

PD7/SEG23

(Port D)

8-bit output port.

(8 pins)

Output/Output

PF0/SEG24

PF7/SEG31

(Port F)

8-bit output port.

(8 pins)

LCD segment signal output.

Output/Output

PG0/SEG32

PG7/SEG39

(port G)

8-bit output port.

(8 pins)

SEG0 to SEG15 Output

COM0 to COM3 Output

VLC1 to VLC3

LCD segment signal output.

LCD common signal output.

LCD bias power supply.

Control pin to cut off the current flowing to external LCD bias resistor

during standby.

Output

Input

Crystal connectors for system clock oscillation. When the clock is supplied

externally, input to EXTAL1; opposite phase clock should be input to XTAL1.

System clock oscillation of EXTAL1 and XTAL1 is used for normal operation

mode (Max. 10MHz).

EXTAL1

XTAL1

EXTAL2

XTAL2

Crystal connectors for system clock oscillation. When the clock is supplied

externally, input to EXTAL2; opposite phase clock should be input to XTAL2.

System clock oscillation of EXTAL2 and XTAL2 is used for sub clock mode

(Typ. 500kHz).

Input

Crystal connectors for 32kHz timer/counter clock generation circuit.

Connect a 32.768kHz crystal oscillator between TEX and TX. For usage

as event input, connect clock oscillation source to TEX, and leave TX

open.

TEX

Output

Input

RST

Low-level active system reset.

NC. Under normal operating conditions, connect to VDD.

Reference voltage input for A/D converter.

A/D converter GND.

AVREF

AVSS

VDD

Input

Positive power supply.

VSS

GND. Two VSS are connected to GND.

– 6 –

CXP83120A/83124A

I/O Circuit Format for Pins

When reset

Circuit format

Port A

Pull-up resistor

"0" when reset

Port A data

PA0/AN0

PA7/AN7

Port A direction

"0" when reset

IP Input protection

circuit

Hi-Z

Data bus

RD (Port A)

Port A input selection

"0" when reset

Input multiplexer

A/D converter

Pull-up transistors

approx. 100kΩ

8 pins

Port B

Pull-up resistor

"0" when reset

Port B data

PB0/CINT

PB1/CS0

PB3/SI0

PB6/SI1

Port B direction

"0" when reset

Hi-Z

Schmitt input

Data bus

RD (Port B)

CINT

CS0

SI0

SI1

Pull-up transistors

approx. 100kΩ

4 pins

Port B

Pull-up resistor

"0" when reset

SCK OUT

Output enable

Port B output selection

"0" when reset

Port B data

PB2/SCK0

PB5/SCK1

Hi-Z

Port B direction

"0" when reset

Data

bus

Schmitt input

RD (Port B)

Pull-up transistors

approx. 100kΩ

SCK in

2 pins

– 7 –

CXP83120A/83124A

When reset

Circuit format

Port B

Pull-up resistor

"0" when reset

Output enable

Port B output selection

"0" when reset

Port B data

PB4/SO0

PB7/SO1

Hi-Z

Port B direction

"0" when reset

Data

bus

RD (Port B)

Pull-up transistors

approx. 100kΩ

2 pins

Port C

Pull-up resistor

"0" when reset

Port C data

PC0 to PC7

Port C direction

"0" when reset

Hi-Z

Data bus

RD (Port C)

High current drive

of 12mA possible

Pull-up transistors

approx. 100kΩ

8 pins

Port E

PE0/INT0/EC0

PE1/INT1/EC1

PE2/INT2

PE3/INT3/NMI

PE4/RMC

INT0/EC0

INT1/EC1

INT2

INT3/NMI

RMC

Schmitt input

Hi-Z

Data bus

RD (Port E)

5 pins

– 8 –

CXP83120A/83124A

P in

When reset

Circuit format

Port E

PWM

Port E output selection

"0" when reset

Reset E data

PE5/PWM

High level

"1" when reset

Data bus

RD (Port E)

1 pin

Port E

Internal reset signal

Port E data

"1" when reset

MPX

High level

ADJ16K

PE6/TO/ADJ

(High level

with 150kΩ

resistor when

reset)

ADJ2K

Port E output selection

"00" when reset

Pull-up transistors approx. 150kΩ.

ADJ signals are frequency divider outputs

for 32kHz oscillation frequency adjustment.

ADJ2K provides usage as buzzer output.

TO Output enable

1 pin

Port H

Pull-up resistor

"0" when reset

Port H data

PH0 to PH7

Hi-Z

Port H direction

"0" when reset

Data bus

RD (Port H)

Pull-up transistors approx. 100kΩ

8 pins

– 9 –

CXP83120A/83124A

When reset

Circuit format

Port D

Port F

Port G

Port data

PD0 to PD7

PF0 to PF7

PG0 to PG7

by a single bit unit

by 4-bit unit

PD7 to PD4

Segment

output

(VDD level)

Port/segment output

selection

PD3 to PD0

PF7 to PF0

PG7 to PG0

by 8-bit unit

"0" when reset

Segment

driver

Segment data

24 pins

Segment

VCH

VCL

SEG0 to

SEG15

VDD level

16 pins

Common

VDD

VLC1

VLC2

VLC3

COM0 to

COM3

VDD level

4 pins

LCD control

(DSP bit)

Hi-Z

"0" when reset

1 pin

– 10 –

CXP83120A/83124A

When reset

Circuit format

• Diagram shows circuit

composition during

oscillation.

EXTAL1

XTAL1

EXTAL1

XTAL1

Oscillation

• Feedback resistor is

removed during stop.

XTAL1 becomes "High"

level.

2 pins

• Diagram shows circuit

composition during

oscillation.

EXTAL2

Hi-Z

EXTAL2

XTAL2

EXTAL2

XTAL2

• Feedback resistor is

removed during stop.

XTAL2 becomes "High"

level.

XTAL2

High level

2 pins

• Diagram shows circuit

composition during

oscillation.

TEX

Oscillation

• When the operation of the oscillation

circuit is stopped by the software, the

feedback resistor is removed and TEX

and TX become "Low" level and "High"

level respectively.

2 pins

Pull-up resistor

RST

1 pin

Low level

Mask option

Schmitt input

– 11 –

CXP83120A/83124A

Absolute Maximum Ratings

(Vss = 0V)

Item

Symbol

Rating

–0.3 to +7.0

–0.3 to +0.3

–0.3 to +7.0

–5

Unit

Remarks

VDD

AVSS

Supply voltage

LCD bias voltage

Input voltage

VLC1, VLC2, VLC3

VIN

Output voltage

VOUT

IOH

High level output current

Output per pin

°C

High level total output current ∑IOH

–50

Total for all output pins

IOL

Low level output current

IOLC

Value per pin, excluding high current outputs

Value per pin ²for high current outputs

Total for all output pins

Low level total output current ∑IOL

100

Operating temperature

Storage temperature

Topr

Tstg

–20 to +75

–55 to +150

600

QFP package

LQFP package

Allowable power dissipation PD

380

VIN and VOUT must not exceed VDD + 0.3V.

The high current drive transistor is the N-ch transistor of Port C (PC)

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely

affect the reliability of the LSI.

– 12 –

CXP83120A/83124A

Recommended Operating Conditions

(Vss = 0V)

Item

Symbol

Min.

4.5

Max.

5.5

Unit

Remarks

High-speed mode guaranteed operation range

Low-speed mode guaranteed operation range

3.5

5.5

Guaranteed operation range during

EXTAL2 clock (sub clock mode)

Supply voltage

VDD

3.0

5.5

2.7

2.5

5.5

Guaranteed operation range with TEX clock

Guaranteed data hold range during STOP

VLC1

VLC2

VLC3

VIH

LCD power supply range

LCD bias voltage

VDD

Vss

0.7VDD

0.8VDD

VDD

High level

input voltage

VIHS

VIHEX

VIL

Hysteresis input

EXTAL

VDD – 0.4 VDD + 0.3

0.3VDD

0.2VDD

0.4

Low level

input voltage

VILS

VILEX

Topr

Hysteresis input

EXTAL

–0.3

–20

°C

Operating temperature

+75

During EXTAL1 clock (main clock mode), high-speed mode is 1/2 frequency division clock selection; low-

speed mode is 1/16 frequency division clock selection.

Value for each pin of normal input ports (PA, PB4, PB7, PC and PH).

Value of the following pins; RST, CINT CS0, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, NMI/INT3,

and RMC.

Specifies only during external clock input.

Optimal values are determined by LCD used.

– 13 –

CXP83120A/83124A

Electrical Characteristics

DC Characteristics

(Ta = –20 to +75°C, Vss = 0V)

Item

Symbol

Pins

Conditions

VDD = 4.5V, IOH = –0.5mA

VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA

VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 12.0mA

VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V

V^DD= 5.5V, VIL = 0.4V

VDD = 4.5V, VIH = 4.0V

VDD = 5.5V, VIL = 0.4V

Min.

4.0

Typ.

Max.

Unit

High level

output voltage

PA, PB, PC,

VOH

PD , PE5,

3.5

PE6

PF to PG

VL (only VOL)

0.4

0.6

1.5

Low level

output voltage

VOL

0.5

–0.5

0.3

IIHE1

IILE1

IIHE2

IILE2

IIHT

IILT

µA

EXTAL1

EXTAL2

TEX

–40

–0.3

0.1

–30

Input current

–0.1

–1.5

–3.33

–10

–400

IILR

IIH

RST

PA to PC ,

IIL

–50

±10

PE0 to PE4,

VDD = 5.5V,

VI = 0, 5.5V

I/O leakage

current

IIZ

µA

RST

Common

output

impedance

COM0 to

COM3

RCOM

kΩ

VDD = 5V,

VLC1 = 3.75V

VLC2 = 2.5V

VLC3 = 1.25

SEG0 to

SEG15

SEG16 to

Segment

output

impedance

kΩ

RSEG

IDD1

SEG39

High-speed mode operation

(1/2 frequency division clock)

VDD = 5.5V, 10MHz crystal oscillation

(C1 = C2 = 15pF)

VDD = 3.5V, 500kHz crystal oscillation

(C1 = C2 = 22pF)

0.8

µA

IDD2

IDD3

VDD = 3V, 32kHz crystal oscillation

(C1 = C2 = 47pF)

100

SLEEP mode

Supply

current

VDD

1.1

IDDS1

VDD = 5.5V, 10MHz crystal oscillation

(C1 = C2 = 15pF)

VDD = 3.5V, 500kHz crystal oscillation

(C1 = C2 = 22pF)

400

800

µA

I^DDS2

VDD = 3V, 32kHz crystal oscillation

(C1 = C2 = 47pF)

IDDS3

STOP mode

VDD = 5.5V, 10MHz, 500kHz crystal

oscillation and termination of 32kHz

oscillation

µA

IDDSS

– 14 –

CXP83120A/83124A

Item

Symbol

Pins

Conditions

Min.

Typ.

Max.

Unit

Pins other than

PB7, PE5, PE6

VLC1 to VLC3

COM0 to COM3

SEG0 to SEG15

PD0/SEG16 to

Clock 1MHz

Input capacity

CIN

PD7/SEG23 0V for all pins excluding

PF0/SEG24 to

PF7/SEG31

PG0/SEG32 to

PG7/SEG39

AVREF, AVSS,

VDD, VSS

measured pins

Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PG0/SEG32 to PG7/SEG39,

PD, PF and PG is the case when the common pin is selected as port; SEG16 to SEG39 is when the

common pin is selected as segment output.

RST specifies the input current when pull-up resitor has been selected; leakage current when no resistor

has been selected.

Pins PA to PC, and PH specifies the input current when pull-up resistor has been selected; leakage current

when no resistor has been selected. (PE0 to PE4 specifies the leakage current.)

When all output pins are left open.

– 15 –

CXP83120A/83124A

AC Characteristics

(1) Clock timing

(Ta = –20 to +75°C, V^DD= 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

XTAL1

EXTAL1

System clock frequency

Fig. 1, Fig. 2

MHz

System clock input

pulse width

Fig. 1, Fig. 2

external clock drive

XL,

37.5

EXTAL1

System clock input rise and

fall time

Fig. 1, Fig. 2

external clock drive

CR,

200

0.7

VDD = 3.0 to 5.5V

Fig. 1, Fig. 2

XTAL2

EXTAL2

System clock frequency

MHz

0.3

0.5

VDD = 3.0 to 5.5V

Fig. 1, Fig. 2

external clock drive

XL,

System clock input pulse width

450

EXTAL2

tXH

VDD = 3.0 to 5.5V

Fig. 1, Fig. 2

external clock drive

System clock input rise and

fall time

CR,

200

Event count input clock pulse

width

EH,

EC0

EC1

Fig. 3

tsys +50

Event count input clock rise

and fall time

ER,

EC0

EC1

VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock

applied condition)

TEX

System clock frequency

kHz

32.768

Event count input clock input

pulse width

TL,

Fig. 3

µs

TEX

tTH

Event count input clock rise

and fall time

tTR,

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (address: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11").

Fig. 1. Clock timing

1/fc

VDD – 0.4V

0.4V

EXTAL1

EXTAL2

tXH

tCF

tXL

tCR

Fig. 2. Clock applied conditions

Crystal oscillation

Ceramic oscillation

32kHz clock applied condition

Crystal oscillation

External clock

EXTAL

XTAL

EXTAL

XTAL

TEX

74HC04

– 16 –

CXP83120A/83124A

Fig. 3. Event count clock timing

0.8VDD

0.2VDD

TEX

EC0

EC1

tEH

tTH

tEF

tTF

tEL

tTL

tER

tTR

(2) Serial transfer (CH0)

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS0 ↓ → SCK0

Symbol

Conditions

Min.

Max.

Unit

Chip select transfer mode

(SCK0 = output mode)

tsys + 200

tDCSK

tDCSKF

DCSO

SCK0

delay time

CS0 ↑ → SCK0

float delay time

Chip select transfer mode

(SCK0 = output mode)

tsys + 200

SCK0

SO0

CS0 ↓ → SO0

delay time

Chip select transfer mode

CS0 ↑ → SO0

float delay time

DCSOF

WHCS

SO0

CS0

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100

CS0 high level width

Chip select transfer mode

Input mode

tKCY

SCK0

SI0

SCK0 cycle time

Output mode

Input mode

SCK0 high and low level

widths

Output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SCK0 input mode

SCK0 output mode

SI0 input setup time

(for SCK0 ↑)

SIK

200

tsys + 200

100

SI0 input hold time

(for SCK0 ↑)

KSI

SI0

tsys + 200

100

SCK0 ↓ → SO0

delay time

KSO

SO0

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the

clock control register (address: 00FEH).

tsys ( ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.

– 17 –

CXP83120A/83124A

Fig. 4. Serial transfer CH0 timing

tWHCS

CS0

0.8VDD

0.2VDD

tKCY

tDCSK

tDCSKF

tKL

tKH

0.8VDD

0.2VDD

SCK0

tSIK

tKSI

0.8VDD

0.2VDD

SI0

Input data

tDCSO

tKSO

tDCSOF

0.8VDD

SO0

Output data

0.2VDD

– 18 –

CXP83120A/83124A

Serial Transfer (CH1)

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

Symbol

Conditions

Input mode

Min.

1000

Max.

Unit

SCK1 cycle time

SCK1

tKCY

Output mode

16000/fc

400

input mode

SCK1 high and low level

widths

SCK1

SI1

Output mode

8000/fc – 50

100

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SCK1 input mode

SCK1 output mode

SI1 input setup time

(for SCK1 ↑)

SIK

200

SI1 input hold time

(for SCK1 ↑)

SI1

KSI

100

200

100

SCK1 ↓ → SO1 delay time

SO1

KSO

Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing

tKCY

tKL

tKH

0.8VDD

0.2VDD

SCK1

tSIK

tKSI

0.8VDD

0.2VDD

SI1

Input data

tKSO

0.8VDD

SO1

Output data

0.2VDD

– 19 –

CXP83120A/83124A

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = AVSS = 0V)

Item

Resolution

Symbol

Conditions

Min.

Typ.

Max.

Unit

Bits

LSB

Linearity error

±3

Ta = 25°C

V^DD= AVREF = 5.0V

VSS = AVSS = 0V

Zero transition

voltage

VZT

–10

Full-scale transition

voltage

VFT

4910

4970

5030

160/fADC

12/fADC

µs

Conversion time

Sampling time

CONV

SAMP

VDD – 0.5

Reference input voltage

Analog input voltage

VREF

VIAN

IREF

AVREF

VDD

AVREF

1.0

AN0 to AN7

0.6

Operation mode

SLEEP mode

STOP mode

AVREF current

AVREF

IREFS

µA

32kHz operation mode

Fig. 6. Definition of A/D converter terms

FFH

FEH

VZT: Value at which the digital conversion value changes

from 00H to 01H and vice versa.

VFT: Value at which the digital conversion value changes

from FEH to FFH and vice versa.

fADC indicates the below values due to the Bit 6 (CKS) of

A/D control register (address: 00F9H )and the Bit 7 (PCK1)

and Bit 6 (PCK0) of clock control register (address: 00FFH).

Linearity error

01H

00H

CKS

VZT

VFT

0 (φ/2 selection)

1 (φ selection)

Analog input

PCK1, PCK0

fADC = fC/2

fADC = fC/4

fADC = fC/16

00 (φ = fEX/2)

fADC = fC

01 (φ = fEX/4)

11 (φ = fEX/16)

fADC = fC/2

fADC = fC/8

– 20 –

CXP83120A/83124A

(4) Interruption, reset input

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

Symbol

INT0

INT1

INT2

Conditions Min.

Max.

Unit

External interruption

high and low level widths

µs

NMI/INT3

µs

Reset input low level width

RST

32/fc

tRSL

Fig. 7. Interruption input timing

tIH

tIL

0.8VDD

INT0

0.2VDD

INT1

INT2

tIL

tIH

NMI / INT3

(NMI specifies only

for the falling edge)

Fig. 8. RST input timing

tRSL

RST

0.2VDD

– 21 –

CXP83120A/83124A

Appendix

Fig. 9. SPC700 series recommended oscillation circuit

(iii) 32kHz sub clock

(i) Main clock

(ii) Main clock

500kHz sub clock

EXTAL

XTAL

EXTAL

XTAL

ETXETXAL

XTXAL

C1 C2

Circuit

example

Manufacturer

Model

fc (MHz)

C¹(pF)

C2 (pF)

Rd (Ω)

CSA4.19MG

CSA8.00MG

CSA10.0MT

4.19

8.00

(i)

10.00

MURATA MFG

CO., LTD.

CST4.19MGW

CST8.00MTW

CST10.00MTW

4.19

8.00

(ii)

(i)

10.00

4.19

RIVER

ELETEC

CO., LTD.

2.2k

HC-49/U03

8.00

470

560

10.00

4.19

HC-49/U (-S)

8.00

KINSEKI LTD.

10.00

Those marked with an asterisk ( ) signify types with built-in ground capacitance (C¹, C2).

Mask Option Table

Item

Content

Reset pin pull-up resistor

Non-existent

Existent

– 22 –

CXP83120A/83124A

Characteristics Curves

IDD vs. fc

(VDD = 5V, Ta = 25°C, typical)

IDD vs. VDD

(fc = 10MHz main clock, Ta = 25°C, typical)

1/2 frequency dividing

mode

20.0

10.0

5.0

Main clock

1/2 frequency

dividing mode

fc = 500kHz sub clock

1/2 frequency dividing mode

fc = 10MHz main clock

SLEEP mode

1.0

0.5

fc = 500kHz sub clock

SLEEP mode

32kHz mode

(Instruction)

0.1

(100µA)

0.05

(50µA)

32kHz

SLEEP mode

Main clock

SLEEP mode

0.01

(10µA)

VDD – Supply voltage [ V ]

fc – System clock [MHz]

– 23 –

CXP83120A/83124A

Package Outline

Unit: mm

100PIN QFP (PLASTIC)

+ 0.1

0.15 – 0.05

23.9 ± 0.4

+ 0.4

20.0 – 0.1

0.65

+ 0.35

2.75 – 0.15

±0.12

0.15

0° to 15°

DETAIL

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

EPOXY RESIN

SOLDER PLATING

QFP-100P-L01

SONY CODE

EIAJ CODE

QFP100-P-1420-A

LEAD MATERIAL

COPPER / 42 ALLOY

1.4g

PACKAGE WEIGHT

JEDEC CODE

100PIN LQFP (PLASTIC)

16.0 ± 0.2

14.0 ± 0.1

100

(0.22)

+ 0.08

0.18 – 0.03

+ 0.05

0.127 – 0.02

0.5 ± 0.08

+ 0.2

1.5 – 0.1

0.1

0.1 ± 0.1

NOTE: Dimension “ ” does not include mold protrusion.

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL

EPOXY/PHENOL RESIN

SOLDER PLATING

LQFP-100P-L01

LEAD TREATMENT

LEAD MATERIAL

SONY CODE

EIAJ CODE

QFP100-P-1414-A

42 ALLOY

JEDEC CODE

PACKAGE WEIGHT

– 24 –

CXP83120A [SONY]

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