CXP972032Q [SONY]
Microcontroller, 16-Bit, MROM, SPC970 CPU, 40.5MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100;
| 型号： | CXP972032Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | Microcontroller, 16-Bit, MROM, SPC970 CPU, 40.5MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100 PC 微控制器 |
| 文件： | 总44页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP972032/973032/973064
CMOS 16-bit Single Chip Microcomputer
Description
The CXP972032/973032/973064 is a CMOS 16-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, I2C bus interface, timer,
PWM output circuit, programmable pattern
generator, remote control receive circuit, parallel
interface, as well as basic configurations like a 16-bit
CPU, ROM, RAM, and I/O port.
100 pin QFP (Plastic)
100 pin LQFP (Plastic)
This LSI also provides the sleep/stop functions that
enable lower power consumption.
Features
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system,
general-purpose register of 16-bit × 8-pin × 16-bank
configuration
104 pin LFLGA (Plastic)
• Minimum instruction cycle
50ns at 40MHz operation (2.7 to 3.6V)
• Incorporated ROM capacity
128K bytes (CXP972032/973032)
256K bytes (CXP973064)
• Incorporated RAM capacity
7.5K bytes (CXP972032)
11.5K bytes (CXP973032/973064)
• Peripheral functions
— A/D converter
— Serial interface
— I2C bus interface
— Timers
8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55µs at 40MHz)
Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels
64-byte buffer RAM
(supports master/slave and automatic transfer mode)
8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels, watchdog timer
14-bit PWM, 4 channels
— PWM output circuit
(2 channels of binary output switch function by PPG)
— Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel
— Remote control receive circuit
— Parallel interface
8-bit pulse measurement counter, 10-stage FIFO
External register interface (8-bit parallel bus), 4-chip select
• Interruption
• Standby mode
• Package
33 factors, 33 vectors, multi-interruption and priority selection possible
Sleep/stop
100-pin plastic QFP (CXP972032/973032/973064)
100-pin plastic LQFP (CXP972032/973032/973064)
104-pin plastic LFLGA (CXP973064)
CXP971000
• Piggy/evaluation chip
•
FLASH EEPROM incorporated version CXP973F064
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99930A14-PS
CXP972032/973032/973064
A T
P O R B T
P O R C T
P O R D T
P O R E T
P O R F T
P O G T
P O R R T O P H I T
P O R J T
P O R K T
P O R
X W R
X R D
D 0 t o D
S S V
D D V
R S T
A 1 5 A 0 t o
A L X T
A L E X T
X C S 0
X C S 1
X C S 2
X C S 3
1
t o A N 1
A N 0
D D A V
R E F A V
S S A V
A D T R G
A D T E N
t o K S 1 9
K S 0
t o P P O
P P O 0
t o I N T 7
I N T 0
C O N T R O L L I E N R T E R R U P T
N M I
– 2 –
CXP972032/973032/973064
Pin Assignment 1 (Top View) 100-pin QFP package
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PH0/SDA
PK6
PB2/PPO02/A10
PB3/PPO03/A11
PB4/PPO04/A12
PB5/PPO05/A13
PB6/PPO06/A14
PB7/PPO07/A15
PC0/PPO08
2
3
PK5
4
PK4/ADTRG
PK3/ADTEN
PK2
5
6
PK1
7
PK0
8
PC1/PPO09
AVDD
PC2/PPO10
9
AVREF
PC3/PPO11
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AVSS
PC4/PPO12/XCS3
PC5/PPO13/XCS2
PC6/PPO14/XCS1
PC7/PPO15/XCS0
VSS
PJ7/AN11/KS11
PJ6/AN10/KS10
PJ5/AN9/KS9
PJ4/AN8/KS8
PJ3/AN7/KS7
PJ2/AN6/KS6
PJ1/AN5/KS5
PJ0/AN4/KS4
PI7/AN3/KS3
PI6/AN2/KS2
PI5/AN1/KS1
PI4/AN0/KS0
Vss
PD0/D0/KS12
PD1/D1/KS13
PD2/D2/KS14
PD3/D3/KS15
PD4/D4/KS16
PD5/D5/KS17
PD6/D6/KS18
PD7/D7/KS19
PE0/INT0
PI3/SCK2
PI2/SO2
PE1/INT1
PE2/INT2
PI1/SI2
PE3/INT3
PI0/SCS2
PG7/SCK0
PG6/SO0
PE4/INT4
PE5/INT5
PE6/INT6
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 88) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND.
3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD.
– 3 –
CXP972032/973032/973064
Pin Assignment 2 (Top View) 100-pin LQFP package
76
78 77
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79
PK4/ADTRG
PK3/ADTEN
PK2
1
2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PB4/PPO04/A12
PB5/PPO05/A13
PB6/PPO06/A14
PB7/PPO07/A15
PC0/PPO08
3
PK1
4
PK0
5
AVDD
6
PC1/PPO09
AVREF
7
PC2/PPO10
AVSS
8
PC3/PPO11
PJ7/AN11/KS11
PJ6/AN10/KS10
PJ5/AN9/KS9
PJ4/AN8/KS8
PJ3/AN7/KS7
PJ2/AN6/KS6
PJ1/AN5/KS5
PJ0/AN4/KS4
PI7/AN3/KS3
PI6/AN2/KS2
PI5/AN1/KS1
PI4/AN0/KS0
Vss
9
PC4/PPO12/XCS3
PC5/PPO13/XCS2
PC6/PPO14/XCS1
PC7/PPO15/XCS0
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PD0/D0/KS12
PD1/D1/KS13
PD2/D2/KS14
PD3/D3/KS15
PD4/D4/KS16
PD5/D5/KS17
PD6/D6/KS18
PD7/D7/KS19
PE0/INT0
PI3/SCK2
PI2/SO2
PE1/INT1
PI1/SI2
PE2/INT2
PI0/SCS2
PE3/INT3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 86) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND.
3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD.
– 4 –
CXP972032/973032/973064
Pin Assignment 3 (Top View) 104-pin LFLGA package
1
2
2
3
4
5
6
7
8
9
10
80
11
77
12
74
13
72
A
B
C
D
E
F
97
95
92
90
87
84
82
PB0 PA6 PA3 PA1 VDD PH6 PH4 PH2 PK6
99 96 93 91 88 85 81 76 75
PB2 PA7 PA4 PA2 VSS PH7 PH3 PK5 PK4
98 94 89 86 83 79 78
PB1 PA5 PA0 NC PH5 PH1 PH0
100
PB5 PB3
PK3 PK1
70 69
PK2 AVDD AVREF
71 68 67
PK0 AVSS PJ7
66 65 64
PJ6 PJ5 PJ4
63 61 62
PJ3 PJ1 PJ2
5
1
3
73
PC0 PB4 PB6
7
6
4
PC2 PC1 PB7
10
PC5 PC4 PC3
9
8
G
H
J
12
PC7 VSS PC6
15 16 14
PD1 PD2 PD0
17 18 19
PD3 PD4 PD5
13
11
58
PI6 PJ0
54 56
PI3 PI4
53 51
60
59
PI7
57
PI5
55
K
L
20
PD6 PD7 PE1
22 24
PE0 PE2
21
23
PI2 PI0
50
VSS
28
PE6 PF0 PF3 PF6 EXTAL PG3 PG5
26 32 35 38 40 43 45
PE3 PE4 PF2 PF5 RST XTAL PG0 PG2 PG6
30
33
36
41
46
48
52
PG7 PI1
M
25
49
N
27
29
31
34
37
39
42
44
47
PE5 PE7 PF1 PF4
VSS
VDD PG1 PG4
PF7
Note) 1. NC (Pin C7) must be left open. However, use this pin for FLASH EEPROM
incorporated version.
2. Vss and AVss (Pins B7, E12, G2, K13 and N8) must be connected to GND.
3. VDD and AVDD (Pins A7, D12 and N9) must be connected to VDD.
– 5 –
CXP972032/973032/973064
Pin Functions
Symbol
I/O
Functions
(Port A)
External register interface address bus port
output data value and OR output.
(8 pins)
PA0/A0
to PA7/A7
Output / Output 8-bit output port.
(8 pins)
External register interface address bus.
Address width can be extended in 1-bit
PB0/PPO00/
A8
(Port B)
8-bit output port. PPO
Output /
units.
(8 pins)
to PB7/PPO07/
A15
Output / Output value and OR output.
(8 pins)
PC0/PPO08
to PC3/PPO11
Programmable pattern generator outputs.
(16 pins)
(Port C)
8-bit I/O port. I/O can
be specified in 1-bit
I/O / Output
PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0
External register interface chip select
signal. Chip select signal output function
can be selected in 1-bit units.
(4 pins)
units. PPO value and
I/O / Output /
OR output.
Output
(8 pins)
(Port D)
8-bit I/O port. I/O can
I/O / I/O / Input be specified in 1-bit
units.
PD0/D0/
KS12
to PD7/D7/
KS19
Standby release input
External register
function can be
interface data bus.
specified in 1-bit units.
(8 pins)
(8 pins)
(8 pins)
PE0/INT0
to PE6/INT6
External interrupt inputs.
(8 pins)
(Port E)
8-bit I/O port. I/O can
I/O / Input
be specified in 1-bit
units. (8 pins)
Input
External capture input for 16-bit capture
timer/counter.
PE7/INT7/
CINT
I/O / Input /
PF0/EC0
PF1/EC2
External event inputs for 8-bit timer/counter.
(2 pins)
Input / Input
Non-maskable external
Serial chip select
PF2/SCS1/
NMI
Input / Input /
Input
(Port F)
interrupt input.
(CH1) input.
8-bit port. Lower 6 bits
are for input; upper 2
bits are for output.
(8 pins)
PF3/SI1
PF4/SO1
PF5/SCK1
PF6/T1
Input / Input
Serial data (CH1) input.
Input / Output
Serial data (CH1) output.
Input / I/O
Serial clock (CH1) I/O.
Output / Output
Output / Output
8-bit timer/counter output.
16-bit capture timer/counter timing output.
PF7/T2
14-bit PWM output with output value switch
control by programmable pattern generator.
(2 pins)
PG0/PWM0
to PG1/PWM1
Output / Output
(Port G)
8-bit port. Lower 4 bits
PG2/PWM2
PG3/PWM3
14-bit PWM output.
(2 pins)
Output / Output
are for output; upper 4
bits are for I/O. Upper
4 bits can be specified
in 1-bit units.
PG4/SCS0
PG5/SI0
I/O / Input
I/O / Input
I/O / Output
I/O / I/O
Serial chip select (CH0) input.
Serial data (CH0) input.
Serial data (CH0) output.
Serial clock (CH0) I/O.
(8 pins)
PG6/SO0
PG7/SCK0
– 6 –
CXP972032/973032/973064
Symbol
PH0/SDA
PH1/SCL
PH2/RxD
PH3/TxD
PH4/RMC
PH5
I/O
Output / I/O
Output / I/O
I/O / Input
I/O / Output
I/O / Input
I/O
Functions
I2C bus interface data I/O.
I2C bus interface clock I/O.
UART reception data input.
(Port H)
8-bit port. Lower 2 bits
are for large current
N-ch open drain
outputs; medium 4 bits
are for I/O; upper 2 bits
are for output. Medium
4 bits can be specified
in 1-bit units.
UART transmission data output.
Remote control receive circuit input.
Output / Output
Output / Output
I/O / Input
I/O / Input
I/O / Output
I/O / I/O
External register interface write signal.
External register interface read signal.
Serial chip select (CH2) input.
Serial data (CH2) input.
PH6/XWR
PH7/XRD
PI0/SCS2
PI1/SI2
(8 pins)
(Port I)
Serial data (CH2) output.
PI2/SO2
PI3/SCK2
8-bit I/O port. I/O can
be specified in 1-bit
units.
Serial clock (CH2) I/O.
PI4/AN0/
KS0
to PI7/AN3/
KS3
(8 pins)
I/O / Input /
Input
Standby release input
Analog input for
A/D converter.
(12 pins)
function can be
specified in 1-bit units.
(12 pins)
(Port J)
PJ0/AN4/
KS4
to PJ7/AN11/
KS11
8-bit I/O port. I/O can
be specified in 1-bit
units.
I/O / Input /
Input
(8 pins)
I/O
PK0 to PK2
PK3/ADTEN
PK4/ADTRG
(Port K)
7-bit port. Lower 5 bits
are for I/O; upper 2 bits
are for output. Lower
5 bits can be specified
in 1-bit units.
A/D converter operation enable input by external
trigger.
I/O / Input
I/O / Input
Output
Input
External trigger input for A/D converter.
PK5
PK6
(7 pins)
EXTAL
XTAL
RST
Connects a crystal for main clock oscillation. (When the clock is supplied
externally, input it to EXTAL and input an opposite phase clock to XTAL.)
Input
Input
System reset. Active at "L" level.
Positive power supply for A/D converter. (Must be the same voltage with
VDD)
AVDD
Reference voltage input for A/D converter. (Must be the same voltage with
VDD)
AVREF
AVss
VDD
GND for A/D converter.
Positive power supply.
(Connect both VDD pins to positive power supply.)
GND. (Connect all four Vss pins to GND.)
Vss
NC
NC. (NC is used for FLASH EEPROM incorporated version.)
– 7 –
CXP972032/973032/973064
I/O Circuit Format for Pins
Pin
Circuit format
After a reset
A0 to A7
PA register
PA0/A0
to PA7/A7
(Undefined after a reset)
Hi-Z
Internal
data bus
RD
S
R
Q
PA register write
Reset
Address width
setting
("0" after a reset)
A8 to A15
1
MPX
0
PB0/PPO00/A8
to PB7/PPO07/
A15
PPO00 to PPO07
PB register
Hi-Z
(Undefined after a reset)
Internal
data bus
PB register write
Reset
S
R
Q
RD
PPO08 to PPO11
PC register
("0" after a reset)
Input
protection
circuit
PC0/PPO08
to PC3/PPO11
PCD register
Hi-Z
IP
("0" after a reset)
Internal
data bus
RD
– 8 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
XCS output setting
("0" after a reset)
XCS3 to XCS0
1
MPX
0
PPO12 to PPO15
PC4/PPO12/
XCS3
to PC7/PPO15/
XCS0
PC register
Hi-Z
("0" after a reset)
PCD register
IP
("0" after a reset)
Internal
data bus
RD
WR (external register area)
External register
I/F
Internal data bus
External register operation enable
CLR
∗
PD register
("0" after a reset)
CLR
PDD register
IP
PD0/D0/KS12
to PD7/D7/
KS19
("0" after a reset)
Hi-Z
Internal data bus
RD
Standby release
Internal data bus
External register
I/F
External register operation enable
RD (external register area)
∗ Large current drive
5mA (VDD = 2.7 to 3.6V)
PE register
(Undefined after a reset)
PE0/INT0
to PE7/INT7/
CINT
PED register
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
INT0 to INT7/CINT
CMOS Schmitt input
– 9 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
IP
EC0, EC2
PF0/EC0
PF1/EC2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CMOS Schmitt input
Internal data bus
RD
Internal data bus
IP
CMOS Schmitt input
RD
PF2/SCS1/
NMI
SCS1
NMI
PFSL register
("0" after a reset)
NMI input enable
("0" after a reset)
Internal data bus
SI1
IP
CMOS Schmitt input
RD
PF3/SI1
PFSL register
("0" after a reset)
SO1
SO1 output enable
PF4/SO1
PFSL register
IP
("0" after a reset)
Internal data bus
RD
SCK1
SCK1 output enable
PF5/SCK1
Hi-Z
PFSL register
IP
("0" after a reset)
Internal data bus
CMOS Schmitt input
RD
SCK1
– 10 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
1
T1
PF register
MPX
0
("1" after a reset)
PFSL register
"H" level
PF6/T1
("0" after a reset)
Internal data bus
RD
∗
1
T2
PF register
MPX
0
"H" level
("H" level at ON
resistance of
pull-up transistor
by a reset.)
("1" after a reset)
PFSL register
PF7/T2
("0" after a reset)
Internal data bus
RD
PF register write
S
Q
∗ Pull-up transistor
approximately 150kΩ (VDD = 2.7 to 3.6V)
Reset
R
1
PWM0 to PWM3
MPX
0
PG register
(Undefined after a reset)
PGSL register
PG0/PWM0
to PG3/PWM3
Hi-Z
("0" after a reset)
Internal data bus
RD
PG register write
Reset
S
R
Q
– 11 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
PG register
(Undefined after a reset)
PGD register
("0" after a reset)
PGSL register
Hi-Z
PG4/SCS0
IP
("0" after a reset)
SCS0
Internal data bus
CMOS Schmitt input
RD
PG register
(Undefined after a reset)
PGD register
("0" after a reset)
PGSL register
Hi-Z
PG5/SI0
IP
("0" after a reset)
SI0
Internal data bus
CMOS Schmitt input
RD
SO0
PG register
1
MPX
0
(Undefined after a reset)
PGSL register
("0" after a reset)
SO0 output enable
IP
1
Hi-Z
PG6/SO0
MPX
PGD register
0
("0" after a reset)
Internal
data bus
RD
– 12 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
SCK0
PG register
1
MPX
0
(Undefined after a reset)
PGSL register
("0" after a reset)
IP
1
SCK0 output enable
Hi-Z
PG7/SCK0
MPX
PGD register
0
("0" after a reset)
Internal
data bus
RD
SCK0
CMOS Schmitt input
SDA, SCL
1
MPX
PH register
("1" after a reset)
PHSL register
0
∗
PH0/SDA
PH1/SCL
("0" after a reset)
Internal data bus
Hi-Z
IP
RD
SDA, SCL
CMOS Schmitt input
∗ Large current drive
5mA (VDD = 2.7 to 3.6V)
PHL register
(Undefined after a reset)
PHD register
IP
Hi-Z
PH2/RxD
("0" after a reset)
Internal data bus
RxD
RD
CMOS Schmitt input
– 13 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
TxD
PH register
1
MPX
0
(Undefined after a reset)
TxD output enable
Hi-Z
PH3/TxD
PHD register
IP
("0" after a reset)
Internal
data bus
RD
PH register
(Undefined after a reset)
PHD register
IP
Hi-Z
PH4/RMC
("0" after a reset)
Internal data bus
RMC
RD
CMOS Schmitt input
PH register
(Undefined after a reset)
PHD register
PH5
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
PHSL register
("0" after a reset)
1
XWR, XRD
MPX
PH register
0
PH6/XWR
PH7/XRD
Hi-Z
(Undefined after a reset)
Internal
data bus
PH register write
Reset
RD
S
R
Q
– 14 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
Hi-Z
PI0/SCS2
IP
("0" after a reset)
SCS2
Internal data bus
CMOS Schmitt input
RD
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
Hi-Z
PI1/SI2
IP
("0" after a reset)
SI2
Internal data bus
CMOS Schmitt input
RD
SO2
PI register
1
MPX
0
(Undefined after a reset)
PISL register
("0" after a reset)
SO2 output enable
IP
1
Hi-Z
PI2/SO2
MPX
PID register
0
("0" after a reset)
Internal
data bus
RD
– 15 –
CXP972032/973032/973064
Pin
After a reset
Circuit format
1
SCK2
PI register
MPX
0
(Undefined after a reset)
PISL register
("0" after a reset)
SCK2 output enable
IP
1
Hi-Z
PI3/SCK2
MPX
PID register
0
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
SCK2
PI register
(Undefined after a reset)
PID register
("0" after a reset)
PISL register
PI4/AN0/KS0
to PI7/AN3/
KS3
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
Standby release
A/D converter
Input multiplexer
PJ register
(Undefined after a reset)
PJD register
("0" after a reset)
PJSL register
PJ0/AN4/KS4
to PJ7/AN11/
KS11
IP
Hi-Z
("0" after a reset)
Internal data bus
RD
Standby release
A/D converter
Input multiplexer
– 16 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
PK register
(Undefined after a reset)
Hi-Z
PK0 to PK2
PKD register
IP
("0" after a reset)
Internal data bus
RD
PK register
(Undefined after a reset)
PKD register
PK3/ADTEN
PK4/ADTRG
IP
Hi-Z
("0" after a reset)
Internal data bus
ADTEN, ADTRG
RD
CMOS Schmitt input
PK register
"H" level
("1" after a reset)
PK5
Internal data bus
RD
∗
PK register
"H" level
("H" level at ON
resistance of
pull-up transistor
by a reset.)
("1" after a reset)
Internal data bus
PK6
RD
PK register write
Reset
S
R
Q
∗ Pull-up transistor
approximately 150kΩ (VDD = 2.7 to 3.6V)
– 17 –
CXP972032/973032/973064
Pin
Circuit format
After a reset
EXTAL
IP
Timing
generator
Oscillation
stop control
XTAL
EXTAL
Oscillation
XTAL
• Diagram shows circuit configuration during oscillation.
• Feedback resistor is removed during standby stop mode,
and XTAL is driven at "H" level.
∗
Mask option
OP
"L" level
(during a reset)
RST
Internal reset circuit
IP
RST
CMOS Schmitt input
∗ Pull-up transistor
approximately 30kΩ (VDD = 2.7 to 3.6V)
– 18 –
CXP972032/973032/973064
Absolute Maximum Ratings
(Vss = 0V reference)
Remarks
Item
Symbol
VDD
Rating
Unit
V
–0.3 to +4.6
∗1
AVDD
AVREF
AVSS
VIN
AVSS to +4.6
AVSS to +4.6
V
Supply voltage
∗1
V
–0.3 to +0.3
V
∗2
Input voltage
–0.3 to +4.6
–0.3 to +4.6
–5.0
V
∗2
Output voltage
VOUT
IOH
V
High level output current
mA
mA
Output (value per pin)
High level total output current ΣIOH
–50
Total for all output pins
All pins excluding large
current output pins
(value per pin)
IOL
15.0
mA
mA
Low level output current
∗3
Large current output pins
(value per pin)
IOLC
20.0
130
Low level total output current
Operating temperature
Storage temperature
ΣIOL
Topr
Tstg
mA
°C
Total for all output pins
–30 to +85
–55 to +150
600
°C
QFP-100P-L01
Allowable power dissipation
PD
380
mW LQFP-100P-L01
LFLGA-104P-01
500
∗1
AVDD and AVREF must be the same voltage with VDD.
∗2
∗3
VIN and VOUT excluding PH0 and PH1 must not exceed VDD + 0.3V.
The large current drive transistor is N-ch transistor of PD and PH0, PH1.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 19 –
CXP972032/973032/973064
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
VDD
Min.
2.7
Max.
3.6
Unit
V
Remarks
2.0
3.6
Guaranteed data hold range during stop mode
Supply voltage
∗1
AVDD
AVREF
VIH
2.7
3.6
V
V
V
V
V
V
V
V
∗1
∗2
2.7
3.6
0.7VDD
0.8VDD
VDD
VDD
High level input
voltage
∗3
VIHS
VIHEX
VIL
CMOS Schmitt input
∗4
VDD – 0.4 VDD + 0.2
EXTAL
∗2
0
0
0.2VDD
0.2VDD
0.4
Low level input
voltage
∗3
VILS
CMOS Schmitt input
∗4
–0.3
VILEX
EXTAL
Operating
temperature
–30
+85
°C
Topr
∗1
AVDD and AVREF must be the same voltage with VDD.
∗2
∗3
∗4
PC, PD, PF4, PG6, PH3, PI2, PI4 to PI7, PJ, PK0 to PK2 for normal input port.
RST, PE, PF0 to PF3, PF5, PG4, PG5, PG7, PH0 to PH2, PH4, PH5, PI0, PI1,PI3, PK3 and PK4.
Specified only during self-oscillation.
– 20 –
CXP972032/973032/973064
Electrical Characteristics
DC Characteristics 1
(Topr = –30 to +85°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
2.70
2.40
2.30
2.00
Typ.
Max.
Unit
V
VDD = 3.0V, IOH = –0.15mA
VDD = 2.7V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 2.7V, IOH = –0.5mA
PD to PE, PF6,
PF7, PG0 to PG5,
PH2, PH4, PH5,
PI to PJ,
High level
output
voltage
V
V
PK0 to PK6
VOH
PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3
2.30
2.00
VDD = 3.0V, IOH = –1.5mA
VDD = 2.7V, IOH = –1.5mA
PE, PF6, PF7,
PG0 to PG5,
PH2, PH4, PH5,
PI0, PI1, PI4 to PI7,
PJ, PK0 to PK6
IOL = 1.2mA
IOL = 1.6mA
0.30
0.50
0.30
0.50
V
V
V
V
Low level
output
VOL
PA to PC, PF4,
PF5, PG6, PG7,
PH3, PH6, PH7,
PI2, PI3
IOL = 2.0mA
IOL = 3.0mA
voltage
1.00
61
V
PD, PH0, PH1
IOL = 5.0mA
0.3
µA
µA
µA
IIHE
IILE
IILR
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 0.3V
EXTAL
Input
current
–0.3
–0.9
–61
–250
∗1
RST
I/O leakage
current
PA to PJ, PK0 to PK6,
RST
31
µA
IIZ
VDD = 3.6V, VI = 0, 3.6V
∗1
Open drain
output
leakage
current
31
µA
ILOH
PH0, PH1
VDD = 3.6V, VIH = 3.6V
(N-ch Tr.
off state)
∗1
RST specifies the input current when pull-up resistor has been selected; the leakage current when no
resistor has been selected.
– 21 –
CXP972032/973032/973064
DC Characteristics 2 (CXP972032)
(Topr = –30 to +85°C, Vss = 0V reference)
Min. Typ. Max. Unit
Item
Symbol
Pins
Conditions
VDD = 3.3 0.3V,
∗2
VDD, VSS
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state
32
40
10
mA
mA
IDD1
VDD = 3.3 0.3V,
∗2
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state,
sleep mode
VDD, VSS
VDD, VSS
Supply
current
8.0
IDDS2
∗1
25
13
5
85°C or less
IDDS3
VDD = 3.6V, stop mode
75°C or less
µA
50°C or less
∗1
When all output pins are open.
∗2
When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the
LSI is operated in high-speed mode (2 frequency dividing clock).
DC Characteristics 2 (CXP973032/973064)
(Topr = –30 to +85°C, Vss = 0V reference)
Min. Typ. Max. Unit
Item
Symbol
Pins
Conditions
VDD = 3.3 0.3V,
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state
∗2
VDD, VSS
35
44
11
mA
mA
IDD1
VDD = 3.3 0.3V,
∗2
fEX = fsrc = 40MHz, External clock operation
A/D off state, PLL off state,
sleep mode
VDD, VSS
VDD, VSS
Supply
current
8.8
IDDS2
∗1
25
13
5
85°C or less
IDDS3
VDD = 3.6V, stop mode
75°C or less
µA
50°C or less
∗1
When all output pins are open.
∗2
When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the
LSI is operated in high-speed mode (2 frequency dividing clock).
– 22 –
CXP972032/973032/973064
I/O Capacitance
Item Symbol
Input
Pins
Conditions
Clock 1MHz,
0V for all pins excluding
measured pins
Min.
Typ.
10
Max.
20
Unit
pF
PF0 to PF3,
EXTAL, RST
CIN
capacitance
PA to PB, PF6, PF7,
PG0 to PG3,
PH6, PH7, PK5, PK6,
XTAL
Clock 1MHz,
0V for all pins excluding
measured pins
Output
capacitance
10
10
20
20
pF
pF
COUT
PC to PE, PF4, PF5,
PG4 to PG7,
PH0 to PH5,
Clock 1MHz,
0V for all pins excluding
measured pins
I/O
CI/O
capacitance
PI to PJ, PK0 to PK4
– 23 –
CXP972032/973032/973064
AC Characteristics
(1) Clock timing
(Topr = –30 to +85°C, VDD = 2.7 to 3.6 V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min. Typ. Max. Unit
4.76 33.86 40.5 MHz
Fig.1, Fig.2
Mask option
Selection less than 40MHz
EXTAL,
XTAL
Main clock base
oscillation frequency
fEX
Fig.1, Fig.2
4.76 20.0 20.5 MHz
Mask option
Selection less than 20MHz
fEX = 40.0MHz
Fig.1, Fig.2
External clock drive
t
t
t
t
XH
XL
XH
XL
4.0
4.0
11
ns
ns
Main clock base
oscillation input pulse
width
fEX = 33.86MHz
Fig.1, Fig.2
External clock drive
EXTAL,
XTAL
fEX = 20.0MHz
Fig.1, Fig.2
External clock drive
t
XH
ns
tXL
fEX = 40.0MHz
Fig.1, Fig.2
External clock drive
t
t
t
XR
XF
XR
8.5 ns
10.5 ns
Main clock base
oscillation input
rise time, fall time
fEX = 33.86MHz
Fig.1, Fig.2
External clock drive
EXTAL,
XTAL
t
XF
XR
XF
fEX = 20.0MHz
Fig.1, Fig.2
External clock drive
t
14
60
ns
%
t
Fig.1, Fig.2
1/2 VDD point
duty
40
50
Main clock duty
XTAL
Note) tsys indicates the four values below according to the upper two bits (PCK1, PCK0) of the clock control
register (CLC: 0002FEh).
tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10),
16/fEX (PCK1, PCK0 = 11)
(2) Main clock multiplier circuit
(Topr = –30 to +85°C, VDD = 2.7 to 3.6 V, Vss = 0V reference)
Item
Symbol
fSRC
Conditions
Min.
22.0
19.9
Typ.
Max.
40.5
40.5
5
Unit
MHz
ms
Main clock multiplier
frequency
∗1
–20 to +85°C
1
Lock-up time
tLOCK
∗1
When the degree of input frequency of the main clock base oscillation frequency fEX is 10.0 0.1MHz,
quadruple setting is 40.0 0.4MHz.
Note) Main clock multiplier frequency fSRC generates the value set from 1.5 times to 4 times of the main clock
base oscillation frequency fEX internally according to the Bits 10 to 8 (CMN2 to CMN0) of PLL setting
register (PLL: 0002FCh).
– 24 –
CXP972032/973032/973064
1/fEX
VDD – 0.4V
0.4V
EXTAL
XTAL
tXH
tXF
tEX
tXL
tXR
XTAL
1/2VDD
tX
duty = tx/tEX; tEX = 1/fEX
Fig. 1. Clock timing
Oscillator connection example
of main oscillation circuit
Connection example (1)
of external clock
Connection example (2)
of external clock
EXTAL
XTAL
EXTAL
XTAL
EXTAL
XTAL
(i)
(ii)
(iii)
Fig. 2. Oscillator connection and clock applied conditions
– 25 –
CXP972032/973032/973064
(3) Event count input
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol
Pins
EC0,
Conditions
Min.
Max.
Unit
ns
Event count input clock
pulse width
tEH,
EL
Fig. 3
tsys + 100
t
EC2
0.8VDD
0.2VDD
EC0
EC2
tEH
tEL
Fig. 3. Event count input timing
(4) Interruption and reset input
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Main mode
INT0 to INT7, Sleep mode
Min.
Max.
Unit
NMI,
tsys + 100
KS0 to KS19
Fig. 4
External interruption
high, low level width
t
IH,
IL
ns
φ
2tsys + 100
32/fEX + 100
t
Noise filter
selected
Fig. 4
INT4 to INT7
PS4
PS6 128/fEX + 100
50/fEX
Reset input low level
width
ns
RST
Fig. 5
tRST
tIH
tIL
0.8VDD
NMI
0.2VDD
INT0 to INT7
KS0 to KS19
Fig. 4. Interruption input timing
tRST
RST
0.2VDD
Fig. 5. Reset input timing
– 26 –
CXP972032/973032/973064
(5) A/D converter characteristics
(Topr = –30 to +85°C, VDD = AVDD = AVREF = 2.7 to 3.6V, Vss = AVss = 0V reference)
Item
Resolution
Symbol
Pins
Conditions
Min.
Typ. Max. Unit
8
Bits
LSB
LSB
ns
Linearity error
Absolute error
1
VDD = AVDD = AVREF = 3.0V
3
34tsys
62tsys
10tsys
20tsys
2.7
Conversion time
Sampling time
t
CONV
SAMP
∗1
ns
ns
t
∗1
ns
AVREF
3.6
Reference input voltage
Analog input voltage
V
VREF
VDD = AVDD = AVREF
AN0 to AN11
AVREF
V
0
VDD = 3.3 0.3V
fSRC = 40MHz
1.5
1.2
2.1
1.7
12
mA
mA
µA
Main
mode
IREF
VDD = 3.3 0.3V
fSRC = 20MHz
AVREF current
AVREF
∗
2
ADC off state
Stop mode
IREFS
∗1
∗2
When Bit 6 (ADCK) of A/D control status register (ADCS: 000132h) is specified to "1".
When Bit 5 (ADPC) of A/D control status register (ADCS: 000132h) is specified to "1".
Note) AVDD and AVREF must be the same voltage with VDD.
(100h)
FFh
FEh
FFh
FEh
Linearity error
Absolute error
Analog input
01h
00h
01h
00h
VZT∗1
VFT∗2
AVREF
Analog input
Absolute error
∗1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Fig. 6. Definition of A/D converter terms
– 27 –
CXP972032/973032/973064
(6) Serial transfer (CH0, CH1, CH2)
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Min.
Max.
Unit
ns
VDD = 3.3 0.3V
SCK0,
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
t
t
t
t
t
t
t
t
sys + 200
CS ↓ → SCK
delay time
t
t
t
t
t
DCSK
SCK1,
SCK2
External start
transfer mode
(SCK = output
mode)
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
ns
ns
ns
ns
ns
ns
ns
ns
ns
sys + 210
sys + 200
sys + 210
sys + 200
sys + 210
sys + 200
sys + 210
SCK0,
SCK1,
SCK2
CS ↑ → SCK
float delay time
DSKF
SO0,
SO1,
SO2
CS ↓ → SO
delay time
DCSO
DCSOF
WHCS
SCS0,
SCS1,
SCS2
CS ↑ → SO
float delay time
External start
transfer mode
SCS0,
SCS1,
SCS2
tsys + 100
tsys + 110
CS high level
width
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
VDD = 3.3 0.3V
VDD = 3.0 0.3V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
2tsys + 210
16/fEX
Input mode
SCK0,
SCK1,
SCK2
t
KCY
SCK cycle time
Output mode
16/fEX
tsys + 100
tsys + 110
8/fEX – 100
8/fEX – 110
100
Input mode
SCK
high, low pulse
width
SCK0,
SCK1,
SCK2
t
KH,
KL
t
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SI input data
setup time
(for SCK ↑)
SI0,
SI1,
SI2
110
tSIK
tKSI
tKSO
t
INT
200
210
2tsys + 100
2tsys + 110
100
SI input data
hold time
(for SCK ↑)
SI0,
SI1,
SI2
110
2tsys + 150
2tsys + 160
100
SO0,
SO1,
SO2
SCK ↓ → SO
delay time
110
3tsys + 100
3tsys + 110
8/fEX – 100
8/fEX – 110
SCK0,
SCK1,
SCK2
Minimum interval
time
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
– 28 –
CXP972032/973032/973064
tWHCS
0.8VDD
SCS0
SCS1
SCS2
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.2VDD
SCK0
SCK1
SCK2
tSIK tKSI
0.8VDD
0.2VDD
SI0
SI1
SI2
Input data
tDCSOF
tDCSO
tKSO
0.8VDD
0.2VDD
SO0
SO1
SO2
Output data
tINT
0.8VDD
SCK0
SCK1
SCK2
Fig. 7. Serial transfer CH0, CH1, CH2 timing
– 29 –
CXP972032/973032/973064
(7) I2C bus
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Standard mode
High-speed mode
Item
Symbol
Pins
SCL
Unit
Min.
Max.
100
Min.
Max.
400
SCK clock frequency
kHz
µs
t
SCL
BUF
Bus free time between stop
and start conditions
4.7
4.0
4.7
4.0
4.7
0
1.3
0.6
SDA
t
Hold time under (resend)
start condition
SDA,
SCL
µs
µs
µs
µs
µs
ns
ns
ns
µs
t
t
t
t
t
t
HD;STA
Hold time in SCL clock low
state
1.3
SCL
SCL
Low
Hold time in SCL clock high
state
0.6
High
Setup time under (resend)
start condition
SDA,
SCL
0.6
SU;STA
HD;DAT
SU;DAT
SDA,
SCL
Data hold time
Data setup time
0.9
0
SDA,
SCL
250
100
20 + α
20 + α
0.6
SCL, SDA signal output
rise time
SDA,
SCL
t
Rd,
Rc
∗1
1000
300
300
300
t
SCL, SDA signal output
fall time
SDA,
SCL
t
Fd,
Fc
∗1
t
Setup time under stop
condition
SDA,
SCL
4.0
tSU;STO
∗
1
Due to the total capacitance of the bus.
tSU;DAT
tBUF
SDA
tHD;STA
tRd
tFd
tSCL
tRc
tFc
tLow
SCL
tHD;STA
tHD;DAT
tHigh
tSU;STA
tSU;STO
Fig. 8. I2C bus timing
– 30 –
CXP972032/973032/973064
(8) Remote control reception
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol Pins
Conditions
PS5 selected
Typ.
Max.
Unit
128/fEX + 100
512/fEX + 100
2048/fEX + 100
Remote control receive
high, low level width
ns
RMC
Main mode
tRMC
PS7 selected
PS9 selected
0.8VDD
RMC
0.2VDD
tRMC
tRMC
Fig. 9. Remote control signal input timing
– 31 –
CXP972032/973032/973064
(9) External register interface
(Vss = 0V reference)
3.0 0.3V
3.3 0.3V
3.3 0.3V
Topr = –20 to +75°C Topr = –30 to +85°C Topr = –30 to +85°C
Item
Symbol
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Chip select
pulse width 1
1.5tsys
–20
1.5tsys
–20
1.5tsys
–30
t
t
t
t
t
t
t
t
t
t
CS1
CS2
CS3
CS4
CS5
CS6
CS7
RW1
RW2
RW3
1.5tsys
1.5tsys
1.5tsys
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select
pulse width 2
2.5tsys
–20
2.5tsys
–20
2.5tsys
–30
16.5tsys
32.5tsys
33.5tsys
17.5tsys
18.5tsys
34.5tsys
tsys
16.5tsys
32.5tsys
33.5tsys
17.5tsys
18.5tsys
34.5tsys
tsys
16.5tsys
32.5tsys
33.5tsys
17.5tsys
18.5tsys
34.5tsys
tsys
Chip select
pulse width 3
2.5tsys
–20
2.5tsys
–20
2.5tsys
–30
Chip select
pulse width 4
3.5tsys
–20
3.5tsys
–20
3.5tsys
–30
Chip select
pulse width 5
2.5tsys
–20
2.5tsys
–20
2.5tsys
–30
Chip select
pulse width 6
3.5tsys
–20
3.5tsys
–20
3.5tsys
–30
Chip select
pulse width 7
4.5tsys
–20
4.5tsys
–20
4.5tsys
–30
Read/write strobe
pulse width 1
tsys – 25
2tsys – 25
2tsys – 25
tsys – 25
2tsys – 25
2tsys – 25
tsys – 35
2tsys – 35
2tsys – 35
Read/write strobe
pulse width 2
16tsys
32tsys
tsys/2
1.5tsys
—
16tsys
32tsys
tsys/2
1.5tsys
—
16tsys
32tsys
tsys/2
1.5tsys
—
Read/write strobe
pulse width 3
tsys/2
–25
tsys/2
–25
tsys/2
–35
Address setting time 1 tAS1
Address setting time 2 tAS2
1.5tsys
–25
1.5tsys
–25
1.5tsys
–35
tsys/2
–25
tsys/2
–25
tsys/2
–35
Address hold time
t
t
t
t
t
t
AH
Read data setting
request time
DS1
DH1
DS2
DS3
DH2
—
—
—
15
0
15
0
20
0
Read data hold
request time
—
—
—
Write data
setting time 1
1.5tsys
–25
1.5tsys
–25
1.5tsys
–35
1.5tsys
16.5tsys
1.5tsys
16.5tsys
1.5tsys
16.5tsys
Write data
setting time 2
2.5tsys
–25
2.5tsys
–25
2.5tsys
–35
tsys/2
+30
tsys/2
+30
tsys/2
+30
tsys/2
–25
tsys/2
–25
tsys/2
–35
Write data hold time
– 32 –
CXP972032/973032/973064
Read Timing
t1
t2
A15 to A0
tCS1
tAH
XCS3 to XCS0
tAS1
tRW1
XRD
tDS1
tDH1
D7 to D0
Fig. 10. Byte read (without programmable wait)
t1
t2 or tw
t3 or tW + 1
A15 to A0
tCS2
tAH
XCS3 to XCS0
tAS1
tRW2
XRD
tDS1
tDH1
D7 to D0
Fig. 11. Byte read (with programmable wait)
– 33 –
CXP972032/973032/973064
t1
t2
t3
EVEN ADD.
ODD ADD.
A15 to A0
tCS3
tAH
XCS3 to XCS0
tAS1
tRW3
XRD
tDS1
tDS1
tDH1
D7 to D0
Fig. 12. Word read (no strobe mode, without programmable wait)
t1
t2
t3
t4
EVEN ADD.
ODD ADD.
A15 to A0
tCS4
tAH
tAH
XCS3 to XCS0
tAS1
tRW1
tAS1
tRW1
XRD
tDS1
tDH1
tDS1
tDH1
D7 to D0
Fig. 13. Word read (strobe mode, without programmable wait)
– 34 –
CXP972032/973032/973064
Write Timing
t1
t2
t3
A15 to A0
tCS5
tAH
XCS3 to XCS0
tAS2
tRW1
XWR
tDS2
tDH2
D7 to D0
Fig. 14. Byte write (without programmable wait)
t1
t2
t3 or tw
t4 or tW + 1
A15 to A0
tCS6
tAH
XCS3 to XCS0
tAS2
tRW2
XWR
tDS3
tDH2
D7 to D0
Fig. 15. Byte write (with programmable wait)
– 35 –
CXP972032/973032/973064
t1
t2
t3
t4
t5
EVEN ADD.
ODD ADD.
A15 to A0
tCS7
tAH
XCS3 to XCS0
tRW1
tAH
tAS1
tRW1
XWR
tDS2
tDH2
tDS2
tDH2
D7 to D0
Fig. 16. Word write (without programmable wait)
– 36 –
CXP972032/973032/973064
Appendix
SPC970 Series recommended oscillation circuit and oscillator
(i) Main oscillation circuit
(ii) Main oscillation circuit
(iii) Main oscillation circuit
EXTAL
XTAL
Rd
EXTAL
XTAL
Rd
EXTAL
XTAL
Rd
C1
C2
C1
C2
C2
C1
L
C3
Fig. 17. Recommended oscillation circuit
Circuit
example
Manufacturer
Model
fEX (MHz)
C1 (pF)
C2 (pF)
Rd (Ω)
Remarks
CSA6.00MG040
CSA8.00MTZ
6.0
8.0
100
30
30
30
15
10
7
100
30
30
30
15
10
7
0
0
CSA10.0MTZ
10.0
12.0
16.0
20.0
24.0
6.0
0
(i)
CSA12.0MTZ
0
CSA16.00MXZ040
CSA20.00MXZ040
CSA24.00MXZ040
0
0
MURATA MFG
CO., LTD.
0
∗
CST6.00MGW040
100
30
30
30
15
18
15
10
10
100
30
30
30
15
18
15
10
10
0
∗
∗
∗
CST8.00MTW
CST10.0MTW
CST12.0MTW
8.0
0
(ii)
(i)
10.0
12.0
16.0
6.0
0
0
∗
CST16.00MXW0C3
0
CL = 13.5pF
CL = 12pF
CL = 9.5pF
CL = 10pF
560
330
330
220
8.0
RIVER ELETEC
CO., LTD.
HC-49/U03
10.0
12.0
∗
Indicates types with on-chip grounding capacitor (C1, C2).
CL: Load capacitor
– 37 –
CXP972032/973032/973064
Circuit
example
Manufacturer
Model
fEX (MHz)
C1 (pF)
C2 (pF)
Rd (Ω)
Remarks
6.0
15
15
10
12
12
12
12
1
15
15
10
12
12
12
12
1
5.6k
3.0k
1.8k
1.0k
470
390
200
100
CL = 16pF
8.0
10.0
12.0
16.0
20.0
24.0
28.0
HC-49/U-S
(i)
CL = 12pF
KINSEKI LTD.
C3 = 10pF,
L = 2.7µH
32.0
36.0
40.0
3
3
1
0.01µF
0.01µF
0.01µF
0
0
0
C3 = 5pF,
L = 2.7µH
(iii)
HC-49/U
C3 = 3pF,
L = 3.3µH
∗
6.0
36 ( 20%) 36 ( 20%)
20 ( 20%) 20 ( 20%)
10 ( 20%) 10 ( 20%)
10 ( 20%) 10 ( 20%)
0
0
0
0
0
CCR6.0MC5
∗
∗
∗
12.0
16.0
28.0
40.0
CCR12.0MSC5
CCR16.0MSC6
CCR28.0MSC6
CCR40.0MS6
(ii)
(i)
TDK
Corporation
5
5
∗
∗∗∗
Indicates types with on-chip grounding capacitor (C1, C2).
CCR
CL:
: Surface mounted type ceramic
oscillator
Load capacitor
Product List
Type
Mask ROM
Product name
ROM capacitance
RAM capacitance
CXP973064
256K byte
11.5K byte
CXP973032
128K byte
11.5K byte
CXP972032
128K byte
7.5K byte
100-pin plastic QFP,
100-pin plastic LQFP,
104-pin plastic LFLGA
100-pin plastic QFP,
100-pin plastic LQFP
Package
Main clock base
oscillation frequency
Less than 40MHz,
Less than 20MHz
∗1
Reset pin pull-up
resistor
Existent/Non-existent
∗1
When the main clock base oscillation frequency is specified below 20MHZ, operation is not performed even
though higher external oscillation and higher external input frequency than the upper limit of clock timing
specification are applied.
– 38 –
CXP972032/973032/973064
Notes on PK6 Usage
FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings:
1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150kΩ),
and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load
impedance.
2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output
prior to software reset execution or connecting pull-up resistor is recommended.
RST
Normal operation
PK6
Flash mode
Keep PK6 above 0.7VDD
during this period.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that FLASH
EEPROM incorporated version is used, above countermeasure should be performed.
– 39 –
CXP972032/973032/973064
Characteristics Curve (CXP973032/973064)
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
40
40
36
32
28
24
20
16
12
8
36
32
2 frequency
28
dividing mode
24
20
Sleep mode
4 frequency
dividing mode
16
12
8
(2 frequency dividing mode)
Sleep mode
(4 frequency dividing mode)
Sleep mode
(8 frequency dividing mode)
Sleep mode
(16 frequency dividing mode)
8 frequency
dividing mode
16 frequency
dividing mode
4
4
0
0
2.1
2.4
2.7
3
3.3
3.6
3.9
2.1
2.4
2.7
3
3.3
3.6
3.9
VDD – Supply voltage [V]
VDD – Supply voltage [V]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
40
40
36
32
28
24
20
16
12
8
36
32
28
24
20
16
12
8
2 frequency
dividing mode
4 frequency
dividing mode
Sleep mode
(2 frequency dividing mode)
Sleep mode
(4 frequency dividing mode)
Sleep mode
(8 frequency dividing mode)
Sleep mode
(16 frequency dividing mode)
8 frequency
dividing mode
16 frequency
dividing mode
4
4
0
0
0
10
20
30
40
10
20
30
40
0
fEX – Main clock base oscillation frequency [MHz]
fEX – Main clock base oscillation frequency [MHz]
– 40 –
CXP972032/973032/973064
Characteristics Curve (CXP972032)
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
40
40
36
32
28
24
20
16
12
8
36
32
28
2 frequency
24 dividing mode
20
Sleep mode
16 4 frequency
dividing mode
12
(2 frequency dividing mode)
Sleep mode
(4 frequency dividing mode)
8 frequency
dividing mode
8
Sleep mode
(8 frequency dividing mode)
Sleep mode
(16 frequency dividing mode)
16 frequency
dividing mode
4
4
0
0
2.1
2.4
2.7
3
3.3
3.6
3.9
2.1
2.4
2.7
3
3.3
3.6
3.9
VDD – Supply voltage [V]
VDD – Supply voltage [V]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
40
40
36
32
28
24
20
16
12
8
36
32
28
24
20
16
12
8
2 frequency
dividing mode
4 frequency
dividing mode
Sleep mode
(2 frequency dividing mode)
Sleep mode
(4 frequency dividing mode)
Sleep mode
(8 frequency dividing mode)
Sleep mode
(16 frequency dividing mode)
8 frequency
dividing mode
16 frequency
dividing mode
4
4
0
0
0
10
20
30
40
10
20
30
40
0
fEX – Main clock base oscillation frequency [MHz]
fEX – Main clock base oscillation frequency [MHz]
– 41 –
CXP972032/973032/973064
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
100PIN QFP (PLASTIC)
23.9 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
LEAD TREATMENT
SPEC.
ALLOY 42
Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18μm
– 42 –
CXP972032/973032/973064
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 0.2
∗
14.0 0.1
75
51
76
50
B
A
26
M
100
(0.22)
1
25
0.13
0.5
b
+ 0.2
1.5 – 0.1
0.1
0.1 0.1
+ 0.08
b = 0.18 – 0.03
( 0.18 )
DETAIL B
0˚ to 10˚
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LQFP-100P-L01
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 / COPPER ALLOY
0.7g
SONY CODE
EIAJ CODE
P-LQFP100-14x14-0.5
JEDEC CODE
PACKAGE MASS
100PIN LQFP (PLASTIC)
16.0 0.2
∗
14.0 0.1
75
51
76
50
B
A
26
M
100
(0.22)
1
25
0.13
0.5
b
+ 0.2
1.5 – 0.1
0.1
0.1 0.1
+ 0.08
b = 0.18 – 0.03
( 0.18 )
DETAIL B
0˚ to 10˚
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LQFP-100P-L01
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 / COPPER ALLOY
0.7g
SONY CODE
EIAJ CODE
P-LQFP100-14x14-0.5
JEDEC CODE
PACKAGE MASS
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
LEAD TREATMENT
SPEC.
ALLOY 42
Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18μm
– 43 –
CXP972032/973032/973064
Package Outline
Unit: mm
104PIN LFLGA
0.2
S
A
11.0
1.4MAX
0.01
X
PIN 1 INDEX
x4
0.15
S
DETAIL X
0.8
A
103 – φ0.40 0.05
φ0.08 M
N
M
L
S
A B
K
J
B
H
G
F
E
D
C
B
A
2
1
3 4 5 6 7 8 9 10111213
0.7
0.4
1.6
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
LFLGA-104P-01
GOLD PLATING
NICKEL PLATING
0.3g
P-LFLGA104-11x11-0.8
EIAJ CODE
JEDEC CODE
Sony Corporation
– 44 –
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