ICX409ALB_技术文档

ICX409AK

Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Cameras

Description

16 pin DIP (Plastic)

The ICX409AK is an interline CCD solid-state

image sensor suitable for PAL color video cameras

with a diagonal 6mm (Type 1/3) system. Compared

with the conventional product ICX059CK, basic

characteristics such as sensitivity, smear, dynamic

range and S/N are improved drastically.

This chip features a field period readout system and

an electronic shutter with variable charge-storage

time.

This chip is suitable for applications such as surveillance

cameras, automotive cameras, etc.

Features

• High sensitivity (+6dB compared with the ICX059CK)

• Low smear (–15dB compared with the ICX059CK)

• High D range (+5dB compared with the ICX059CK)

• High S/N

Pin 1

2

• High resolution and low dark current

• Excellent antiblooming characteristics

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

• Continuous variable-speed shutter

• No voltage adjustment

V

12

3

40

H

Pin 9

(Reset gate and substrate bias are not adjusted.)

• Reset gate:

• Horizontal register: 5V drive

5V drive

Optical black position

(Top View)

Device Structure

• Interline CCD image sensor

• Image size:

Diagonal 6mm (Type 1/3)

• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels

• Total number of pixels:

• Chip size:

795 (H) × 596 (V) approx. 470K pixels

5.59mm (H) × 4.68mm (V)

• Unit cell size:

6.50µm (H) × 6.25µm (V)

• Optical black:

Horizontal (H) direction : Front 3 pixels, rear 40 pixels

Vertical (V) direction

Horizontal 22

Vertical 1 (even fields only)

Silicon

: Front 12 pixels, rear 2 pixels

• Number of dummy bits:

• Substrate material:

Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-

Accumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by Sony

Corporation.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E00611B28

ICX409AK

Block Diagram and

Pin Configuration

(Top View)

8

7

6

5

4

3

2

1

Cy

G

Cy

Ye

Mg

G

Cy

G

Ye

Mg

Ye

G

Cy

G

Ye

Mg

Cy

Mg

Cy

Mg

Ye

G

Note)

Horizontal Register

Note)

: Photo sensor

13

9

10

11

12

14

15

16

Pin Description

Pin No. Symbol

Description

Pin No.

9

Description

Symbol

VDD

1

2

3

4

5

6

7

8

Vφ⁴

Vφ3

Vφ2

Vφ1

GND

NC

Vertical register transfer clock

GND

Supply voltage

GND

10

GND

φSUB

VL

11

Substrate clock

Protective transistor bias

Reset gate clock

12

13

φRG

NC

14

NC

15

Hφ1

Horizontal register transfer clock

VOUT

Signal output

16

Hφ2

Absolute Maximum Ratings

Item

Ratings

–40 to +8

–50 to +15

–50 to +0.3

–40 to +0.3

–0.3 to +20

–10 to +18

–10 to +6

–0.3 to +28

–0.3 to +15

to +15

Unit Remarks

V^DD, VOUT, φRG – φSUB

Vφ1, Vφ3 – φSUB

V

Against φSUB

Vφ2, Vφ4, VL – φSUB

Hφ1, Hφ2, GND – φSUB

VDD, VOUT, φRG – GND

Vφ1, Vφ2, Vφ3, Vφ4 – GND

Hφ1, Hφ2 – GND

Against GND

Against VL

Vφ1, Vφ3 – VL

Vφ2, Vφ4, Hφ1, Hφ2, GND – VL

1

Voltage difference between vertical clock input pins

V

Between input clock

pins

Hφ1 – Hφ2

–6 to +6

V

Hφ1, Hφ2 – Vφ4

–14 to +14

–30 to +80

–10 to +60

Storage temperature

Operating temperature

°C

1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

– 2 –

ICX409AK

Bias Conditions

Item

Symbol Min.

Typ.

Max.

Unit Remarks

V

Supply voltage

V^DD

VL

14.55

15.45

15.0

1

Protective transistor bias

Substrate clock

2

φSUB

1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL

power supply for the V driver should be used.

2

Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

DC Characteristics

Item

Symbol Min.

I^DD

Typ.

4

Max.

6

Unit Remarks

mA

Supply current

Clock Voltage Conditions

Waveform

diagram

Symbol

Min.

Unit

Remarks

Item

Typ. Max.

Readout clock voltage

V^VT

14.55 15.0 15.45

V

1

2

VVH1, VVH2

VVH3, VVH4

–0.05

–0.2

0

0.05

VVH = (VVH1 + VVH2)/2

VVL1, VVL2,

VVL3, VVL4

–8.0 –7.0 –6.5

V

2

VVL = (VVL3 + VVL4)/2

VφV

6.3

7.0

8.05

0.1

V

2

3

VφV = VVHn – VVLn (n = 1 to 4)

Vertical transfer clock

voltage

VVH3 – VVH

VVH4 – VVH

VVHH

–0.25

0.1

0.3

High-level coupling

Low-level coupling

VVHL

0.3

VVLH

0.3

VVLL

0.3

VφH

4.75

5.0

0

5.25

0.05

Horizontal transfer

clock voltage

VHL

–0.05

Input through 0.1µF

capacitance

VφRG

4.5

5.0

5.5

V

4

VRGLH – VRGLL

VRGL – VRGLm

0.4

0.5

V

4

Low-level coupling

Reset gate clock

voltage

VDD

VRGH

V

4

5

+0.3 +0.6 +0.9

Substrate clock voltage

VφSUB

21.0 22.0 23.5

– 3 –

ICX409AK

Clock Equivalent Circuit Constant

Item

Symbol

Cφ^V1, CφV3

CφV2, CφV4

CφV12, CφV34

CφV23, CφV41

CφV13

Min.

Typ.

1500

1000

820

Max.

Unit Remarks

pF

Capacitance between vertical transfer

clock and GND

330

Capacitance between vertical transfer

clocks

120

CφV24

100

Capacitance between horizontal

transfer clock and GND

CφH1, CφH2

CφHH

75

22

5

pF

Capacitance between horizontal

transfer clocks

Capacitance between reset gate clock

and GND

CφRG

Capacitance between substrate clock

and GND

CφSUB

270

R1, R3

R2, R4

RGND

RφH

100

150

68

Ω

Vertical transfer clock series resistor

Vertical transfer clock ground resistor

Horizontal transfer clock series resistor

Reset gate clock series resistor

15

RφRG

50

Vφ1

Vφ2

CφV12

R1

R2

RφH

Hφ2

Hφ1

CφHH

CφV1

CφV2

CφV41

CφV23

CφV13

R3

CφH1

CφH2

CφV24

R4

CφV4 ^RGNDCφV3

CφV34

Vφ4

Vφ3

Vertical transfer clock equivalent circuit

Horizontal transfer clock equivalent circuit

RφRG

RGφ

CφRG

Reset gate clock equivalent circuit

– 4 –

ICX409AK

Drive Clock Waveform Conditions

(1) Readout clock waveform

100%

90%

II

φM

VVT

φM

2

10%

0%

0V

tr

twh

tf

(2) Vertical transfer clock waveform

Vφ1

Vφ3

VVHH

VVH1

VVH

VVHH

VVHL

VVH3

VVHL

VVL1

VVL3

VVLH

VVLL

VVL

Vφ2

Vφ4

VVHH

VVH4

VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVL4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

VφV = VVHn – VVLn (n = 1 to 4)

– 5 –

ICX409AK

(3) Horizontal transfer clock waveform

tr

twh

tf

90%

VφH

twl

10%

VHL

(4) Reset gate clock waveform

tr

twh

tf

VRGH

twl

Point A

VφRG

RG waveform

VRGLH

VRGL

VRGLL

VRGLm

Hφ1 waveform

VφH/2 [V]

V^RGLHis the maximum value and VRGLL is the minimum value of the coupling waveform during the period from

Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and

VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

100%

90%

φM

VφSUB

φM

2

10%

0%

(A bias generated within the CCD)

VSUB

tr

twh

tf

– 6 –

ICX409AK

Clock Switching Characteristics

twh

twl

tr

tf

Item

Symbol

Unit Remarks

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

During

µs

Readout clock

V^T

2.3 2.5

0.5

readout

Vertical transfer

clock

Vφ1, Vφ2,

Vφ3, Vφ4

1

15

250 ns

Hφ1

Hφ2

Hφ1

Hφ2

26 28.5

5.38

26 28.5

6.5 9.5

0.01

6.5 9.5

0.01

During

imaging

2

ns

During

parallel-serial

conversion

µs

ns

5.38

51

0.01

Reset gate clock

φRG

11 13

1.5 1.8

3

During drain

charge

Substrate clock

µs

φSUB

0.5

1

When vertical transfer clock driver CXD1267AN is used.

2

tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be

at least VφH/2 [V].

two

Item

Symbol

Unit Remarks

Min.

22

Typ.

26

Max.

3

Horizontal transfer clock Hφ¹, Hφ2

ns

3

The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

– 7 –

ICX409AK

Image Sensor Characteristics

(Ta = 25°C)

Item

Symbol Min. Typ. Max. Unit

Measurement method

Remarks

Sensitivity

S

760

0.93

1.15

1000

950

mV

1

2

R^MgG

RYeCy

Ysat

Sm

1.35

1.48

Sensitivity ratio

2

Saturation signal

Smear

mV

dB

%

3

Ta = 60°C

–110 –93

4

20

25

10

2

5

Zone 0 and I

Zone 0 to II'

Video signal shading

SHy

%

5

∆Sr

∆Sb

Ydt

∆Ydt

Fy

%

6

Uniformity between video

signal channels

%

6

Dark signal

Dark signal shading

Flicker Y

mV

%

7

Ta = 60°C

1

8

2

9

Flicker R-Y

Flicker B-Y

Line crawl R

Line crawl G

Line crawl B

Line crawl W

Lag

Fcr

5

%

9

Fcb

Lcr

5

%

9

3

%

10

11

Lcg

Lcb

Lcw

Lag

3

%

3

%

3

%

0.5

%

Zone Definition of Video Signal Shading

752 (H)

12

8

V

10

H

8

H

8

582(V)

Zone 0, I

Zone II, II'

Ignored region

6

V

10

Effective pixel region

Measurement System

[ Y]

[ A]

Y signal output

CCD signal output

LPF1

(3dB down 6.3MHz)

CCD

C.D.S

AMP

S

[ C]

H

Chroma signal output

LPF2

(3dB down 1MHz)

Note) Adjust the amplifier gain so that the gain between [ A] and [ Y] , and between [ A] and [ C] equals 1.

– 8 –

ICX409AK

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the bias and clock

voltage conditions.

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical

black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output

or chroma signal output of the measurement system.

Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals

As shown in the left figure, fields are read out. The charge is

Cy

G

Ye

Cy

G

Ye

A1

A2

mixed by pairs such as A1 and A2 in the A field. (pairs such

as B in the B field)

Mg

B

As a result, the sequence of charges output as signals from

the horizontal shift register (Hreg) is, for line A1, (G + Cy),

(Mg + Ye), (G + Cy), and (Mg + Ye).

Cy

Mg

Ye

G

Cy

Mg

Ye

G

Hreg

Color Coding Diagram

These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed

by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,

the approximation:

Y = {(G + Cy) + (Mg + Ye)} × 1/2

= 1/2 {2B + 3G + 2R}

is used for the Y signal, and the approximation:

R – Y = {(Mg + Ye) – (G + Cy)}

= {2R – G}

is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are

(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).

The Y signal is formed from these signals as follows:

Y = {(G + Ye) + (Mg + Cy)} × 1/2

= 1/2 {2B + 3G + 2R}

This is balanced since it is formed in the same way as for line A1.

In a like manner, the chroma (color difference) signal is approximated as follows:

– (B – Y) = {(G + Ye) – (Mg + Cy)}

= – {2B – G}

In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)

in alternation. This is also true for the B field.

– 9 –

ICX409AK

Definition of standard imaging conditions

1) Standard imaging condition I:

Use a pattern box (luminance 706cd/m², color temperature of 3200K halogen source) as a subject. (Pattern

for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and

image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard

sensitivity testing luminous intensity.

2) Standard imaging condition II:

Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.

Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted

to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity

Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of

1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following

formula.

250

50

S = Ys ×

[mV]

2. Sensitivity ratio

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal

output is 200mV, and then measure the Mg signal output (SMg [mV]) and G signal output (SG [mV]), and Ye

signal output (SYe [mV]) and Cy signal output (SCy [mV]) at the center of the screen with frame readout

method. Substitute the values into the following formula.

RMgG = SMg/SG

RYeCy = SYe/SCy

3. Saturation signal

Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with

average value of the Y signal output, 200mV, measure the minimum value of the Y signal.

4. Smear

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to

500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is

stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure

the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.

1

10

YSm

200

1

500

Sm = 20 × log

×

[dB] (1/10V method conversion value)

5. Video signal shading

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so

that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and

minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.

SHy = (Ymax – Ymin)/200 × 100 [%]

6. Uniformity between video signal channels

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal

output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin

[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the

following formula.

∆Sr = | (Crmax – Crmin)/200 | × 100 [%]

∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]

– 10 –

ICX409AK

7. Dark signal

Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and

the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

8. Dark signal shading

After measuring 7, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal

output and substitute the values into the following formula.

∆Ydt = Ydmax – Ydmin [mV]

9. Flicker

1) Fy

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal

output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then

substitute the value into the following formula.

Fy = (∆Yf/200) × 100 [%]

2) Fcr, Fcb

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal

output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between

fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).

Substitute the values into the following formula.

Fci = (∆Ci/CAi) × 100 [%] (i = r, b)

10. Line crawls

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal

output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference

between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the

following formula.

Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)

11. Lag

Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it

strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following

formula.

Lag = (Ylag/200) × 100 [%]

FLD

V1

Light

Strobe light

timing

Y signal output 200mV

Ylag (lag)

Output

– 11 –

ICX409AK

D D V

O U V T

N C

G N D

S φ U B

L V

R φ G

N C

G N D

1 φ V

2 φ V

3 φ V

4 φ V

1 φ H

2 φ H

– 12 –

ICX409AK

Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Ye

Cy

G

Mg

450

550

Wave Length [nm]

700

500

600

650

400

Sensor Readout Clock Timing Chart

V1

V2

2.6

Odd Field

V3

V4

1.5

2.6 2.6 2.6

33.6

0.2

V1

V2

Even Field

V3

V4

Unit : µs

– 13 –

ICX409AK

3 4 0

3 3 5

3 3 0

3 2 5

3 2 0

3 1 5

3 1 0

2 5

2 0

1 5

1 0

5

4

3

2

1

6 2 5

6 2 0

– 14 –

ICX409AK

2 0

1 0

3

2

1

3

2

1

2 2

2 0

1 0

5

3

2

1

4 0

3 0

2 0

1 0

5

3

1

7 5 2

7 5 0

7 4 5

– 15 –

ICX409AK

Notes on Handling

1) Static charge prevention

CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following

protective measures.

a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes.

b) When handling directly use an earth band.

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.

d) Ionized air is recommended for discharge when handling CCD image sensor.

e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering

a) Make sure the package temperature does not exceed 80°C.

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection

Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and

dirt. Clean glass plates with the following operation as required, and use them.

a) Perform all assembly operations in a clean room (class 1000 or less).

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized

air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Installing (attaching)

a) Remain within the following limits when applying a static load to the package. Do not apply any load more

than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited

portions. (This may cause cracks in the package.)

Cover glass

50N

1.2Nm

Torsional strength

Plastic package

Compressive strength

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for

installation, use either an elastic load, such as a spring plate, or an adhesive.

– 16 –

ICX409AK

c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated

voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,

and indicated values should be transferred to the other locations as a precaution.

d) The notch of the package is used for directional index, and that can not be used for reference of fixing.

In addition, the cover glass and seal resin may overlap with the notch of the package.

e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be

generated by the fragments of resin.

f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-

acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)

5) Others

a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high

luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the

image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a

case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off

mode should be properly arranged. For continuous using under cruel condition exceeding the normal

using condition, consult our company.

b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or

usage in such conditions.

c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD

characteristics.

d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength

are the same.

Structure A

Structure B

Package

Chip

Metal plate

(lead frame)

Cross section of

lead frame

The cross section of lead frame can be seen on the side of the package for structure A.

– 17 –

ICX409AK

2 . 5

0 . 2 5

t o 0 9 ˚ ˚

1 1 . 4 3

0 ± . 1 5 3 . 3 5

0 ± . 3 3 . 5

1 . 2 7

0 ± . 1 1 1 . 4

3 . 1

9 . 5

1 . 2

5 . 7

8 . 4

2 . 5

0 . 5

2 . 5

~

Sony Corporation

– 18 –


型号：	ICX409ALB
厂家：	SONY CORPORATION
描述：	CCD Sensor, 752 Horiz pixels, 582 Vert pixels, Square, Through Hole Mount, 0.200 INCH, CERAMIC, DIP-14 传感器换能器图像传感器 CD 摄像机
文件：	总18页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICX409ALB [SONY]

相关型号：

ICX411AQ

ICX412

ICX412AQ

ICX412AQF

ICX413AQ

ICX414AL

ICX414AQ

ICX415AL

ICX415AQ

ICX418AKB

ICX418AKL

ICX418ALB