LCX020BK [SONY]
1.8cm (0.7-inch) Color LCD Panel; 1.8厘米（ 0.7英寸）彩色液晶显示屏
| 型号： | LCX020BK |
| 厂家： | 
SONY CORPORATION |
| 描述： | 1.8cm (0.7-inch) Color LCD Panel |
| 文件： | 总24页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX020BK
1.8cm (0.7-inch) Color LCD Panel
Description
The LCX020BK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel provides full-color representation.
RGB dots are arranged in a striped pattern optimum
for data applications and capable of displaying fine
text and vertical lines.
The adoption of an advanced on-chip black matrix
realizes a high luminance screen, and high picture
quality is possible with built-in cross talk free and
ghost free circuits.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. In addition, the
built-in 5V interface circuit leads to lower voltage of
timing and control signals.
The panel contains a display area varying circuit
1
2
which supports Macintosh16 /SVGA/VGA/PC98
data signals by changing the display area according
to the type of input signal. In addition, double-speed
processed NTSC/PAL/WIDE can also be supported.
1
"Macintosh" is a trademark of Apple Company Inc.
"PC98" is a trademark of NEC.
2
Features
• Number of active dots: 1,557,000, 1.8cm (0.7-inch) in diagonal
• Supports Macintosh16 (832 × 624), SVGA (800 × 600), VGA (640 × 480) and PC98 (640 × 400) display
• Supports NTSC (640 × 480), PAL (762 × 572) and WIDE (832 × 480) display by processing the video signal
at double speed
• High optical transmittance: 1% (typ.)
• Built-in cross talk free circuit
• High contrast ratio with normally white mode: 70 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
Element Structure
• Dots: 2496 (H) × 624 (V) = 1,557,504
• Built-in peripheral driving circuit using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal EVFs for personal PCs/DVDs
• Small monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99210-PS
LCX020BK
M O C
6 B G I S
5 B G I S
4 B G I S
3 B G I S
2 B G I S
1 B G I S
6 G G I S
5 G G I S
4 G G I S
3 G G I S
2 G G I S
1 G G I S
6 R G I S
5 R G I S
4 R G I S
3 R G I S
2 R G I S
1 R G I S
) g n i n n a c S l a n o i t c e r i d i B ( r e t s i g e R t f i h S V
t i u c r i C l o r t n o C e m a r F k c a l B
S S V
D D V V
D D V H
3 E D O M
2 E D O M
1 E D O M
B N E
N W D
G C P
K C V
T S V
t i u c r i C l o r t n o C
e g r a h c e r P
T G R
t i u c r i C l o r t n o C e m a r F k c a l B
K L B
) g n i n n a c S l a n o i t c e r i d i B ( r e t s i g e R t f i h S V
2 K C H
1 K C H
T S H
t i u c r i C l o r t n o C n o i s r e v n I
t f e L / t h g i R r o / d n a n w o D / p U
B G I S P
G G I S P
R G I S P
– 2 –
LCX020BK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage
• V driver supply voltage
• Common pad voltage
HVDD
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
VVDD
COM
• H shift register input pin voltage
HST, HCK1, HCK2,
RGT
• V shift register input pin voltage
• Video signal input pin voltage
VST, VCK, PCG,
BLK, ENB, DWN
MODE1, MODE2, MODE3
SIGR1 to SIGR6,
SIGG1 to SIGG6,
SIGB1 to SIGB6,
PSIGR, PSIGG, PSIGB
Topr
–1.0 to +17
–1.0 to +15
V
V
• Operating temperature
• Storage temperature
–10 to +70
–30 to +85
°C
°C
Tstg
Operating Conditions (Vss = 0V)
• Supply voltage
HVDD
15.5 ± 0.3V
15.5 ± 0.3V
VVDD
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin
5.0 ± 0.5V
Pin Description
Pin
Symbol
No.
Description
1
2
COM
Common voltage of panel
PSIGR
PSIGG
PSIGB
SIGR1
SIGR2
SIGR3
SIGR4
SIGR5
SIGR6
SIGG1
SIGG2
SIGG3
SIGG4
Uniformity improvement signal input (R)
Uniformity improvement signal input (G)
Uniformity improvement signal input (B)
Video signal input to panel (R-1)
Video signal input to panel (R-2)
Video signal input to panel (R-3)
Video signal input to panel (R-4)
Video signal input to panel (R-5)
Video signal input to panel (R-6)
Video signal input to panel (G-1)
Video signal input to panel (G-2)
Video signal input to panel (G-3)
Video signal input to panel (G-4)
3
4
5
6
7
8
9
10
11
12
13
14
– 3 –
LCX020BK
Pin
No.
Symbol
Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
SIGG5
SIGG6
SIGB1
SIGB2
SIGB3
SIGB4
SIGB5
SIGB6
HVDD
RGT
Video signal input to panel (G-5)
Video signal input to panel (G-6)
Video signal input to panel (B-1)
Video signal input to panel (B-2)
Video signal input to panel (B-3)
Video signal input to panel (B-4)
Video signal input to panel (B-5)
Video signal input to panel (B-6)
Power supply input for H driver
Drive direction input for H shift register (H: normal, L: reverse)
Display area switching 3 input
MODE3
MODE2
MODE1
HST
Display area switching 2 input
Display area switching 1 input
Start pulse input for H shift register drive
Clock pulse input for H shift register drive
Clock pulse input for H shift register drive
GND (H, V drivers)
HCK1
HCK2
VSS
BLK
Black frame display pulse input
ENB
Gate selection pulse enable input
VCK
Clock pulse input for V shift register drive
Start pulse input for V shift register drive
Drive direction input for V shift register (H: normal, L: reverse)
Uniformity improvement pulse input
VST
DWN
PCG
VVDD
Power supply input for V driver
SOUT
H and V shift register drive checking (Test pin; no connection.)
– 4 –
LCX020BK
Input Equivalent Circuits
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except video signal inputs. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) SIGR1 to SIGR6, SIGG1 to SIGG6, SIGB1 to SIGB6, PSIGR, PSIGG, PSIGB
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
250Ω
Level conversion circuit
(2-phase input)
250Ω
1MΩ
Input
1MΩ
(3) RGT, MODE1, MODE2, MODE3
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
Input
Input
1MΩ
HVDD
250Ω
(4) HST
250Ω
Level conversion circuit
(single-phase input)
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
1MW
(6) VST, BLK, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(7) COM
VVDD
Input
LC
1MΩ
– 5 –
LCX020BK
Input Signals
1. Input signal voltage conditions (Vss = 0V)
Item
Symbol
VHIL
Min.
–0.5
4.5
Typ.
0.0
Max.
0.4
Unit
V
(Low)
(High)
H shift register input voltage
HST, HCK1, HCK2, RGT
VHIH
5.0
5.5
V
V shift register input voltage
MODE1, MODE2, MODE3,
BLK, VST, VCK, PCG,
ENB, DWN
(Low)
(High)
VVIL
VVIH
–0.5
4.5
0.0
5.0
0.4
5.5
V
V
Video signal center voltage
VVC
6.9
7.0
7.0
7.1
V
V
V
V
V
1
Video signal input range
Vsig
VVC – 4.5
VVC + 4.5
2
Common pad voltage of panel
Vcom
Vpsig1
Vpsig2
VVC – 0.5 VVC – 0.4 VVC – 0.3
VVC ± 2.0 VVC ± 3.0 VVC ± 4.0
VVC ± 4.0 VVC ± 4.5 VVC ± 4.6
Uniformity improvement signal input
voltage (PSIGR, PSIGG, PSIGB)
3
1
Video input signal shall be symmetrical to VVC.
2
The optimum typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.
Input a uniformity improvement signals PSIGR, PSIGG and PSIGB in the same polarity with video signals
SIGR1 to 6, SIGG1 to 6 and SIGB1 to 6 and which is symmetrical to VVC. PSIGR, PSIGG and PSIGB have
two steps as shown by the waveform in the figure below, and in the table above, the upper value indicates
the signal level of the first step, and the lower value, the signal level of the second step.
Here, the rising and falling of PSIGR, PSIGG and PSIGB are synchronized with the rising of PCG pulse,
and the rise and fall times trPSIGR, trPSIGG, trPSIGB, tfPSIGR, tfPSIGG and tfPSIGB are suppressed
within 800ns.
3
Input waveform of uniformity improvement signal PSIG
PRG
90%
Vpsig2
PSIGR,
PSIGG,
PSIGB
VVC
Vpsig1
10%
trPSIGR,
trPSIGG,
trPSIGB
tfPSIGR,
tfPSIGG,
tfPSIGB
LCX020BK level conversion circuit
The LCX020BK has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The Vcc of external ICs are applicable to 5 ± 0.5V.
– 6 –
LCX020BK
2. Clock timing conditions (Ta = 25°C)
(Macintosh16 mode: fHckn = 4.8MHz, fVck = 24.9kHz)
Item
Symbol
trHst
Min.
—
Typ.
—
Max.
30
Unit
Hst rise time
tfHst
—
—
30
Hst fall time
HST
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
70
15
—
80
90
Hst data setup time
25
35
Hst data hold time
4
—
30
Hckn rise time
ns
4
—
—
30
Hckn fall time
HCK
–15
–15
—
0
15
Hck1 fall to Hck2 rise time
0
15
Hck1 rise to Hck2 fall time
Vst rise time
—
100
100
15
tfVst
—
—
Vst fall time
VST
tdVst
thVst
trVck
tfVck
5
10
Vst data setup time
µs
Vst data hold time
5
10
15
Vck rise time
VCK
—
—
100
100
100
100
—
Vck fall time
—
—
Enb rise time
Enb fall time
trEnb
tfEnb
toEnb
tdEnb
toPcg
trPcg
tfPcg
toPrgr
toPrgf
toVck
twPcg
trBlk
—
—
—
—
ENB
Vck rise/fall to Enb rise time
Horizontal video period end to Enb fall time
Enb fall to Pcg rise time
Pcg rise time
400
900
900
—
500
1000
1000
—
—
—
ns
30
Pcg fall time
—
—
30
Pcg rise to Prg rise time
Pcg fall to Prg fall time
Pcg rise to Vck rise/fall time
Pcg pulse width
0
—
—
PCG
200
0
250
1000
1200
—
—
1100
1300
100
100
2
1100
—
Blk rise time
Blk fall time
tfBlk
—
—
5
BLK
Blk fall to Vst rise time
Blk pulse width
toVst
twBlk
1
—
line
1
—
—
4
5
Hckn means Hck1 and Hck2.
Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz).
This pulse is positive polarity other than in Macintosh16 mode. Set to L level in Macintosh16 mode.
– 7 –
LCX020BK
<Horizontal Shift Register Driving Waveform>
Item
Symbol
trHst
Waveform
Conditions
90%
90%
3
• Hckn
Hst rise time
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
50%
10%
tfHst
Hst fall time
tfHst
trHst
6
HST
50%
Hst data setup time
tdHst
Hst
3
• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hck1
50%
50%
thHst
Hst data hold time
thHst
tdHst
90%
10%
90%
10%
3
3
Hckn rise time
trHckn
tfHckn
• Hckn
3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hckn
3
Hckn fall time
trHckn
tfHckn
HCK
6
50%
50%
Hck1 fall
to Hck2 rise time
Hck1
to1Hck
to2Hck
50%
50%
Hck2
Hck1 rise
to Hck2 fall time
to2Hck
to1Hck
6
Definitions:
The right-pointing arrow (
The left-pointing arrow (
The black dot at an arrow (
) means +.
) means –.
) indicates the start of measurement.
– 8 –
LCX020BK
<Vertical Shift Register Driving Waveform>
Item
Symbol
trVst
Waveform
90%
90%
Vst rise time
Vst
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
6
VST
Vst
Vst data setup time
tdVst
50%
50%
Vck
Vck
thVst
Vst data hold time
tdVst
thVst
90%
10%
90%
10%
Vck rise time
Vck fall time
trVck
tfVck
VCK
trVckn
tfVckn
90%
90%
Enb rise time
Enb fall time
trEnb
tfEnb
10% 10%
Enb
tfEn
trEn
Horizontal blanking period
50%
Horizontal video period
Vck
Vck rise/fall
to Enb rise time
toEnb
tdEnb
ENB
Horizontal video period end
to Enb fall time
50%
50%
Enb
toEnb
toPcg
tdEnb
50%
Enb fall to Pcg rise time
toPcg
Pcg
6
Pcg rise time
Pcg fall time
trPcg
tfPcg
50%
Vck
toVck
50%
7
Pcg rise
to Vck rise/fall time
PCG
toVck
trPcg
50%
twPcg
Pcg
Pcg pulse width
6
Blk rise time
Blk fall time
twBlk
tfBlk
Vst
50%
BLK
toVst
twBlk
Blk fall to Vst rise time
Blk pulse width
Blk
50%
50%
toVst
6
twBlk
7
Input the pulse obtained by taking the OR of the above pulses and BLK to the PCG input pin.
– 9 –
LCX020BK
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance HCKn
HST
Symbol Min. Typ. Max. Unit
Condition
CHckn
CHst
—
—
8
8
13
13
—
—
—
—
pF
pF
Input pin current
HCK1
HCK2
HST
–500 –110
–1000 –350
–500 –180
–150 –30
µA HCK1 = GND
µA HCK2 = GND
µA HST = GND
µA RGT = GND
RGT
Video signal input pin capacitance
Current consumption
Csig
IH
—
—
150 270 pF
16.0 30.0 mA HCKn: HCK1, HCK2 (4.8MHz)
2. Vertical drivers
Item
Input pin capacitance VCK
VST
Symbol Min. Typ. Max. Unit
Condition
CVck
CVst
—
—
8
8
13
13
—
pF
pF
µA
Input pin current
VCK
–1000 –160
–150 –30
VCK = GND
PCG, VST, ENB, DWN, BLK,
MODE1, MODE2, MODE3
PCG, VST, ENB, DWN, BLK,
MODE1, MODE2, MODE3 = GND
—
µA
Current consumption
IV
—
3.0
5.0 mA
VCK: (24.9kHz)
3. Total power consumption of the panel
Item
Symbol Min. Typ. Max. Unit
Total power consumption of the panel
(MAC16)
PWR
—
300 600 mW
4. Pin input resistance
Item
Symbol Min. Typ. Max. Unit
Rpin 0.4 MΩ
Pin – Vss input resistance
1
—
5. Uniformity improvement signal input capacitance
Item
Symbol Min. Typ. Max. Unit
Uniformity improvement signal input
capacitance
—
CPSIGon
7
16
nF
– 10 –
LCX020BK
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Item
Symbol Measurement method
Min.
40
Typ. Max.
Unit
—
25°C
60°C
CR25
70
70
—
—
—
Contrast ratio
1
CR60
40
Optical transmittance
R
2
3
%
T
0.85
1.0
X
Rx
0.560 0.600 0.670
0.300 0.360 0.410
0.260 0.300 0.350
0.541 0.595 0.650
0.120 0.148 0.187
0.040 0.148 0.187
Y
Ry
X
Gx
CIE
standards
Chromaticity
G
B
Y
Gy
X
Bx
Y
By
25°C
60°C
25°C
60°C
25°C
60°C
R-G
B-G
0°C
25°C
0°C
25°C
60°C
V90-25
V90-60
V50-25
V50-60
V10-25
V10-60
V50RG
V50BG
ton0
ton25
toff0
toff25
F
0.9
1.0
1.2
1.3
1.9
1.8
—
1.4
1.6
1.8
1.9
2.4
2.3
2.0
2.2
2.4
2.5
3.0
3.0
V90
V50
V10
V-T
characteristics
4
V
–0.10 0.25
Half tone color reproduction
range
5
6
V
—
0.05
20
14
45
35
—
0.45
100
40
—
ON time
Response time
—
ms
—
150
70
OFF time
—
Flicker
7
8
—
–40
20
dB
s
Image retention time
60 min. YT60
—
—
– 11 –
LCX020BK
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V] (VAC = signal amplitude)
Measurement system I
Measurement
Equipment
Luminance
Meter
3.5mm
Back light: color temperature 6800K ± 700K (25°C)
Back light spectrum (reference) is listed on another page.
LCD panel
Measurement system II
Optical fiber
Measurement
Equipment
Light receptor lens
Light Detector
LCD panel
Drive Circuit
Light Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
L (Black)
CR =
... (1)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V.
Both luminosities are measured by System I.
– 12 –
LCX020BK
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
L (White)
Luminance of Back Light
T =
× 100 [%] ... (2)
L (White) is the same expression as defined in the "Contrast Ratio" section.
Optical transmittance is measured by System I.
3. Chromaticity
Chromaticity of the panel is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses x and y of
the CIE standards as the chromaticity here.
Signal amplitudes (VAC) supplied to each input
R input
0.5
G input
4.5
B input
4.5
R
G
B
0.5
4.5
4.5
4.5
4.5
0.5
(Unit: V)
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to each voltage which defines 90%, 50%,
and 10% of transmittance respectively.
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of the LCD
panel is characterized by the differences between the
V-T characteristics of R, G and B. The differences of
these V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B respectively. V50RG and V50BG
represent the differences between V50R and V50G and
between V50B and V50G, and are given by the following
formulas (3) and (4) respectively.
100
50
0
V50RG
V50BG
G raster
B raster
R raster
V50R V50B
V50G
V50RG = V50R – V50G ... (3)
V50BG = V50B – V50G ... (4)
VAC – Signal amplitude [V]
– 13 –
LCX020BK
6. Response Time
Input signal voltage (Waveform applied to the measured pixels)
Response time ton and toff are defined
by formulas (5) and (6) respectively.
ton = t1 – tON ... (5)
4.5V
0.5V
7.0V
toff = t2 – tOFF ... (6)
t1: time which gives 10% transmittance
of the panel.
0V
t2: time which gives 90% transmittance
of the panel.
Optical transmittance output waveform
The relationships between t1, t2, tON
and tOFF are shown in the right figure.
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
7. Flicker
Flicker (F) is given by the formula (7). DC and AC (MAC16/SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL:
25Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter
and a spectrum analyzer in System II.
AC component
DC component
F [dB] = 20log {
} ... (7)
R, G, B input signal voltage for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply a monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of
Vsig = 7.0 ± VAC [V] (VAC: 3 to 4V) so as to give the maximum image retention. Hold input signal VAC. The
time for the residual image to disappear gives the image retention time.
Monoscope signal conditions
Black level
Vsig = 7.0 ± 4.5 or 7.0 ± 2.0 [V]
4.5V
(shown in the right figure)
Vcom = 6.6V
White level
2.0V
7.0V
0V
2.0V
4.5V
Vsig waveform
– 14 –
LCX020BK
Example of Back Light Spectrum (Reference)
Spectral distribution data
5.000E – 01
A.U.
0.000E + 00
300.00
800.00
Wavelength [nm]
– 15 –
LCX020BK
s t o d 8 2 6
s t o d 2
s t o d 2
)
m m 1 6 . 0 1 e v i t c e f f e ( s t o d 4 2 6
– 16 –
LCX020BK
2. LCD Panel Operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 624 gate lines sequentially in every single horizontal scanning period. (in Macintosh16 mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 2496 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs for
one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 2496 × 832 dots to
display a picture in a single vertical scanning period.
• The data and video signals shall be input with polarity-inverted system in every horizontal cycle.
[Description of operating mode]
The LCD panel can change the angle of view by displaying a black frame to support various signal systems.
The angle of view is switched by MODE1, 2 and 3. However, the picture center does not change. The angle of
view mode settings are shown below.
MODE1
MODE2
MODE3
Display mode
Macintosh16: 832 × 624
SVGA: 800 × 600
PAL: 762 × 572
L
L
L
L
L
H
L
L
H
H
L
L
H
L
VGA/NTSC: 640 × 480
PC98: 640 × 400
H
H
L
H
WIDE: 832 × 480
The LCD panel has the following functions to easily apply to various uses, as well as various signal systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and up/down mode settings are
shown in the tables below.
RGT
H
Mode
Right scan
Left scan
DWN
Mode
Down scan
Up scan
H
L
L
Right/left and up/down mean the direction when the Pin 1 marking is located at the right side with the pin block
facing upward.
Since the display area is located in the center of the panel in each mode, the start pulse, clock phase and
polarity for both the H and V systems must be varied. The phase relationship between the start pulse and the
clock for each mode is shown on the following pages.
– 17 –
LCX020BK
(1) Vertical direction display cycle
(1.1) Macintosh 16
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
621 622 623 624
Vertical display cycle 624H
(1.2) SVGA
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
597 598 599 600
Vertical display cycle 600H
(1.3) PAL
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
569 570 571 572
Vertical display cycle 572H
(1.4) VGA/NTSC, WIDE
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
477 478 479 480
Vertical display cycle 480H
(1.5) PC98
VD
VST (DWN = H)
VST (DWN = L)
VCK
1
2
3
4
397 398 399 400
Vertical display cycle 400H
– 18 –
LCX020BK
(2) Horizontal direction display cycle
(2.1.1) Macintosh 16, WIDE, RGT = H
HD
HST
1
2
3
4
137 138 139 140
HCK1
HCK2
Horizontal display cycle
(2.1.2) Macintosh 16, WIDE, RGT = L
HD
HST
HCK1
HCK2
1
2
3
4
137 138 139 140
Horizontal display cycle
(2.2.1) SVGA, RGT = H
HD
HST
HCK1
1
2
3
4
131 132 133 134
HCK2
Horizontal display cycle
(2.2.2) SVGA, RGT = L
HD
HST
HCK1
1
2
3
4
131 132 133 134
HCK2
Horizontal display cycle
– 19 –
LCX020BK
(2.3.1) PAL, RGT = H
HD
HST
1
2
3
4
125 126 127 128
HCK1
HCK2
Horizontal display cycle
(2.3.2) PAL, RGT = L
HD
HST
HCK1
1
2
3
4
125 126 127 128
HCK2
Horizontal display cycle
(2.4.1) VGA/NTSC/PC98, RGT = H
HD
HST
HCK1
1
2
3
4
105 106 107 108
HCK2
Horizontal display cycle
(2.4.2) VGA/NTSC/PC98, RGT = L
HD
HST
1
2
3
4
105 106 107 108
HCK1
HCK2
Horizontal display cycle
– 20 –
LCX020BK
3. 18-dot Simultaneous Sampling
The horizontal shift register performs SIGR1 to SIGR6, SIGG1 to SIGG6 and SIGB1 to SIGB6 signal sampling
simultaneously, which requires phase matching between each signal to prevent the horizontal resolution from
deteriorating. Phase matching by an external signal delaying circuit is needed before applying video signals to
the LCD panel.
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right-direction scanning (RGT = High level). For left-
direction scanning (RGT = Low level), the phase settings should be inverted for the SIGR1 to SIGR6, SIGG1 to
SIGG6 and SIGB1 to SIGB6 signals.
SIGR1, SIGG1, SIGB1
SIGR2, SIGG2, SIGB2
S/H
S/H
S/H
SIGR1, SIGG1, SIGB1
SIGR2, SIGG2, SIGB2
CK1
S/H
CK2
S/H
SIGR3, SIGG3, SIGB3
SIGR4, SIGG4, SIGB4
S/H
S/H
SIGR3, SIGG3, SIGB3
SIGR4, SIGG4, SIGB4
CK3
S/H
CK4
S/H
S/H
SIGR5, SIGG5, SIGB5
SIGR6, SIGG6, SIGB6
SIGR5, SIGG5, SIGB5
SIGR6, SIGG6, SIGB6
CK5
S/H
CK6
<Phase relationship of delaying sample-and-hold pulses> (right-direction scanning)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
– 21 –
LCX020BK
Display System Block Diagram
An example display system configuration is shown below.
R
CXA2112R
R
G
B
G
CXA2111R
CXA2112R
LCX020BK
B
CXA2112R
MCK
HSYNC
PLL
FRP
CXD3500R
TIMING PULSE
VSYNC
– 22 –
LCX020BK
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dust
a) Operate in a clean environment.
b) When delivered, panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet
carefully so as not to damage the panel.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the polarizer.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
– 23 –
LCX020BK
Package Outline
Unit: mm
Thickness of the connector
18.0 ± 0.3
0.2 ± 0.03
12.0 ± 0.05
2
electrode
1
3
Polarizing Axis
Incident
light
Active Area
4
4
0.8 ± 0.1
1.9 ± 0.3
2.33 ± 0.4
(14.227)
17.6 ± 0.3
2.761 ± 0.1
1.075 ± 0.3
0.05 ± 0.3
19.65 ± 0.15
19.75 ± 0.15
0.3 ± 0.3
No
1
Description
F P C
P 0.6 ± 0.02 × 19 = 11.4 ± 0.03
P 0.6 ± 0.02 × 18 = 10.8 ± 0.03
0.3 ± 0.07
0.6 ± 0.07
2
Reinforcing board
PIN 39
PIN1
3
Reinforcing material
Polarizing film
4
weight 2g
electrode (enlarged)
– 24 –
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