LCX029CRT [SONY]
2.3cm (0.9 Type) Black-and-White LCD Panel; 2.3厘米（ 0.9型）黑白LCD面板
| 型号： | LCX029CRT |
| 厂家： | 
SONY CORPORATION |
| 描述： | 2.3cm (0.9 Type) Black-and-White LCD Panel |
| 文件： | 总27页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX029CRT
2.3cm (0.9 Type) Black-and-White LCD Panel
Description
The LCX029CRT is a 2.3cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX029CRT panels
provides a full-color representation. The striped
arrangement suitable for data projectors is capable
of displaying fine text and vertical lines.
1
The adoption of DMS structure and high light
resistance structure realize a high luminance screen.
And cross talk free circuit and ghost free circuit
contribute to high picture quality.
This panel has a polysilicon TFT high-speed scanner
and built-in function to display images up/down and/or
right/left inverse. The built-in 5V interface circuit leads
to lower voltage of timing and control signals.
The panel contains an active area variable circuit
which supports S-XGA 5:4 and PC-98 8:5 data signals
by changing the active area according to the type of
input signal.
1
Dual Metal Shield
Features
• Number of active dots: 786,432 (0.9 Type, 2.3cm in diagonal)
• XGA, SVGA, VGA, NTSC, PAL display
• SXGA display with simple display
• High optical transmittance: 26% (typ.)
• Built-in cross talk free circuit and ghost free circuit
• High contrast ratio with normally white mode: 400 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• Antidust glass package
• Right twist liquid crystal
Element Structure
• Dots: 1024 (H) × 768 (V) = 786,432
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal multimedia projectors
• Liquid crystal rear-projector TVs, etc.
The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00458D18
LCX029CRT
Block Diagram
13 14 31
9 10 11 12
3
4
5
6
7
8
21
2
17
19
18 22 16
25
1
24
29 26 23 27 28
15 30 20
H Shift Register (Bidirectional Scanning)
Side-Black Control Circuit
Input Signal
Level Shifter
Circuit
COM
PAD
– 2 –
LCX029CRT
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
• V driver supply voltage
• Common pad voltage
HVDD
VVDD
COM
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
• H shift register input pin voltage HST, HCK1, HCK2,
RGT
• V shift register input pin voltage VST, VCK, PCG,
BLK, ENB, DWN
–1.0 to +17
V
HB, VB
• Video signal input pin voltage
• Operating temperature
• Storage temperature
VSIG1 to 12, PSIG
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Topr
Tstg
Panel temperature inside the antidust glass
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD
VVDD
13.5 ± 0.5V
15.5 ± 0.5V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
Vin 5.0 ± 0.5V
– 3 –
LCX029CRT
Pin Description
Pin
Symbol
No.
Description
1
PSIG
VSSGR
VSIG1
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
VSIG8
VSIG9
VSIG10
VSIG11
VSIG12
HVDD
RGT
Uniformity improvement signal
GND for right V gate
2
3
Video signal 1 to panel
Video signal 2 to panel
Video signal 3 to panel
Video signal 4 to panel
Video signal 5 to panel
Video signal 6 to panel
Video signal 7 to panel
Video signal 8 to panel
Video signal 9 to panel
Video signal 10 to panel
Video signal 11 to panel
Video signal 12 to panel
Power supply for H driver
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Drive direction pulse for H shift register (H: normal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive 2
Clock pulse for H shift register drive 1
GND (H, V drivers)
HST
HCK2
HCK1
VSS
VSSGL
BLK
GND for left V gate
Input for PC98 mode
ENB
Enable pulse for gate selection
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: normal, L: reverse)
Display switch for S-XGA
VCK
VST
DWN
HB
VB
Display switch for PC98 mode
Improvement pulse for uniformity
Power supply for V driver
PCG
VVDD
COM
TEST
Common voltage of panel
Test pin, leave this pin open
– 4 –
LCX029CRT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
(1) VSIG1 to VSIG12, PSIG
HVDD
Input
1MΩ
Signal line
HVDD
(2) HCK1, HCK2
250Ω
250Ω
Level conversion circuit
(2-phase input)
250Ω
1MΩ
Input
1MΩ
250Ω
(3) RGT
(4) HST
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
HVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
VVDD
2.5kΩ
(6) VST, BLK, ENB, HB, DWN
2.5kΩ
1MΩ
Level conversion circuit
(single-phase input)
Input
(7) VB
VVDD
Input
LC
400kΩ
(8) COM
VVDD
Input
LC
1MΩ
are all Vss.
– 5 –
LCX029CRT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
Symbol
VHIL
Min.
–0.5
4.5
Typ.
0.0
Max.
0.4
Unit
V
(Low)
(High)
H shift register input voltage
HST, HCK1, HCK2, RGT
5.0
5.5
V
VHIH
(Low)
(High)
VVIL
VVIH
–0.5
0.0
5.0
0.4
5.5
V
V
V shift register input voltage
HB, VB, BLK, VST, VCK,
PCG, ENB, DWN
4.5
Video signal center voltage
7.4
7.5
7.5
7.6
V
V
V
VVC
1
Video signal input range
VVC – 5.0
VVC + 5.0
Vsig
2
Common voltage of panel
VVC – 0.5 VVC – 0.4 VVC – 0.3
VVC ± 4.9 VVC ± 5.0 VVC ± 5.1
VVC ± 1.8 VVC ± 1.9 VVC ± 2.0
Vcom
VpsigB
VpsigG
Uniformity improvement signal
V
3
input voltage (PSIG)
1
Input video signal shall be symmetrical to VVC.
2
3
The typical value of the common pad voltage may lower its suitable voltage according to the set construction
to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.
Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and
which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal
level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are
synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed
within 450ns (as shown in a diagram below).
The optimum input voltage of PSIG may be changed according as drive conditions of the drive side.
Input waveform of uniformity improvement signal PSIG
90%
PsigB
PsigG
VVC
PSIG
10%
trPSIG
tfPSIG
PCG
4
PRG
4
PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.
Level Conversion Circuit
The LCX029CRT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
– 6 –
LCX029CRT
2. Clock timing conditions (Ta = 25°C)
(XGA mode: fHckn = 3.9MHz, fVck = 34.3kHz)
Item
Symbol
trHst
Min.
Typ.
—
Max.
Unit
Hst rise time
—
—
30
30
tfHst
—
Hst fall time
HST
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
65
65
—
Hst data set-up time
55
75
Hst data hold time
55
75
5
Hckn rise time
—
30
ns
5
—
Hckn fall time
—
30
HCK
0
Hck1 fall to Hck2 rise time
–15
–15
—
15
0
Hck1 rise to Hck2 fall time
Vst rise time
15
—
100
100
12
tfVst
—
Vst fall time
VST
—
tdVst
thVst
trVck
tfVck
7
Vst data set-up time
2
µs
ns
µs
Vst data hold time
2
7
12
Vck rise time
VCK
—
—
100
100
100
100
—
Vck fall time
Enb rise time
Enb fall time
—
—
trEnb
tfEnb
—
—
—
—
Horizontal video period completed to Enb fall time tdEnb
760
110
830
1650
—
800
120
1000
—
ENB
Enb rise to PRG 4 fall time
Enb fall to Pcg rise time
Enb pulse width
toPRG
toPcg
twEnb
trPcg
tfPcg
130
—
4
—
Pcg rise time
—
30
Pcg fall time
—
—
30
PCG
Pcg rise to Vck rise/fall time
Pcg fall to horizontal video period start time
Pcg pulse width
toVck
–100
170
1400
–10
570
830
—
0
100
—
toVideo
twPcg
toPcgr
toPcgf
200
1700
0
—
PRG 4 rise to Pcg rise time
PRG 4 fall to Pcg fall time
PRG 4 pulse width
10
4
PRG
BLK
700
1000
—
—
4
twPRG
trBlk
—
Blk rise time
100
100
0
Blk fall time
tfBlk
—
—
6
Blk rise to Enb fall time
Blk fall to Pcg rise time
toEnb
toPcg
2
1
–1
0
1
5 Hckn means Hck1 and Hck2.
6 Blk is the timing during PC98 mode, which keeps "H" level in other modes.
– 7 –
LCX029CRT
<Horizontal Shift Register Driving Waveform>
Item
Symbol
trHst
Waveform
Conditions
90%
90%
5
• Hckn
Hst rise time
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
trHst
10%
tfHst
Hst fall time
tfHst
7
HST
50%
50%
Hst data set-up time
tdHst
5
Hst
• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hck1
50%
50%
thHst
Hst data hold time
thHst
tdHst
90%
10%
90%
10%
5
5
Hckn rise time
trHckn
tfHckn
• Hckn
5
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hckn
5
Hckn fall time
trHckn
tfHckn
7
HCK
50%
50%
Hck1 fall to Hck2 rise time to1Hck
Hck1 rise to Hck2 fall time to2Hck
Hck1
50%
50%
Hck2
to2Hck
to1Hck
7
Definitions: The right-pointing arrow (
The left-pointing arrow (
) means +.
) means –.
The black dot at an arrow (
) indicates the start of measurement.
– 8 –
LCX029CRT
<Vertical Shift Register Driving Waveform>
Item
Symbol
trVst
Waveform
Conditions
90%
90%
Vst rise time
Vst
10%
50%
10%
50%
Vst fall time
tfVst
trVst
tfVst
7
VST
Vst data set-up time
tdVst
Vst
50%
50%
Vck
Vst data hold time
thVst
tdVst
thVst
90%
10%
90%
10%
Vck rise time
Vck fall time
Enb rise time
Enb fall time
trVck
tfVck
trEnb
tfEnb
tdEnb
VCK
Vck
trVck
tfVck
90%
90%
10% 10%
Enb
tfEnb
trEnb
Horizontal video period
completed to Enb fall time
H. Video period H. Blanking period
7
twEnb
ENB
Enb rise to PRG 4 fall time toPRG
4
50% 50%
Enb
50%
tdEnb
50%
4
PRG
PCG
Enb fall to Pcg rise time
Enb pulse width
toPcg
4
toPRG
toPcg
50%
twEnb
– 9 –
LCX029CRT
Item
Symbol
trPcg
Waveform
Conditions
90%
90%
Pcg rise time
Pcg 10%
trpcg
10%
tfpcg
Pcg fall time
tfPcg
toVck
H. blanking period
twPcg
H. video period
toVideo
Pcg rise to Vck rise/fall
time
8
7
PCG
Pcg
50% 50%
toVck
Pcg fall to horizontal
video period start time
toVideo
twPcg
toPcgr
toPcgf
50%
Vck
Pcg pulse width
PRG 4 rise to Pcg rise
time
4
twPRG
7
toPcgf
50%
4
PRG
50% 50%
toPcgr
8
PRG 4 fall to Pcg fall time
PRG 4 pulse width
4
PRG
Pcg
50%
4
twPRG
tfBlk
trBlk
90%
Blk rise time
Blk fall time
trBlk
tfBlk
90%
10%
10%
toPcg
toEnb
BLK
7
toEnb
toPcg
Blk rise to Enb fall time
Blk fall to Pcg rise time
50%
50%
Blk
Pcg
50%
50%
Enb
8
PCG input pin and PRG 4 should be "H" level during the horizontal 1H period, where the above BLK is low
more than 10ns.
– 10 –
LCX029CRT
Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Symbol Min.
Typ. Max. Unit
Condition
pF
pF
µA
µA
µA
µA
pF
mA
Input pin capacitance
HCKn
HST
CHckn
CHst
—
—
15
15
20
20
—
Input pin current
HCK1
HCK2
HST
–500 –200
–1000 –300
–500 –150
HCK1 = GND
—
HCK2 = GND
HST = GND
RGT = GND
—
RGT
–150
—
–40
—
Video signal input pin capacitance
Current consumption
Csig
IH
50
200
—
10.0 15.0
HCKn: HCK1, HCK2 (3.9MHz)
2. Vertical drivers
Item
Symbol Min. Typ. Max. Unit
Condition
Input pin capacitance
VCK
CVck
CVst
—
—
15
15
20
20
—
pF
pF
µA
VST
Input pin current
VCK,PCG
–1000 –150
–150 –30
VCK = GND, PCG = GND
VST, ENB, DWN, BLK, HB,
VB
VST, ENB, DWN,BLK, HB
VB = GND
—
µA
Current consumption
IV
—
3.0
6.0
mA
VCK: (34.3kHz)
3. Total power consumption of the panel
Item Symbol Min. Typ. Max. Unit
Total power consumption of the panel PWR
—
200
350
mW
4. Pin input resistance
Item
Symbol Min. Typ. Max. Unit
Rpin 0.4 MΩ
Pin – VSS input resistance
1
—
5. Uniformity improvement signal
Item
Symbol Min. Typ. Max. Unit
Input pin capacitance for uniformity
improvement signal
—
CPSIGo
11
16
nF
6. COM pin capacitance
Item
Symbol Min. Typ. Max. Unit
COM 17 25 nF
COM pin capacitance
—
– 11 –
LCX029CRT
Electro-optical Characteristics
Item
(XGA mode)
Symbol Measurement method Min. Typ. Max. Unit
—
Contrast ratio
25°C
25°C
1
1
CR
300
23
400
26
—
Optical transmittance
%
T
—
RV90-25
GV90-25
BV90-25
RV90-60
GV90-60
BV90-60
RV50-25
GV50-25
BV50-25
RV50-60
GV50-60
BV50-60
RV10-25
GV10-25
BV10-25
RV10-60
GV10-60
BV10-60
ton0
0.9
1.0
1.1
0.8
0.9
1.0
1.2
1.3
1.4
1.2
1.3
1.4
1.6
1.7
1.8
1.6
1.7
1.8
—
1.2
1.3
1.4
1.1
1.2
1.3
1.5
1.6
1.7
1.5
1.6
1.7
1.9
2.0
2.1
1.9
2.0
2.1
1.5
1.6
1.7
1.4
1.5
1.6
1.8
1.9
2.0
1.8
1.9
2.0
2.2
2.3
2.4
2.2
2.3
2.4
25°C
60°C
25°C
60°C
25°C
60°C
V90
V-T
characteristics
V50
3
V
V10
0°C
25°C
0°C
28.0 80.0
14.0 40.0
72.0 200.0
34.0 70.0
–67.0 –40.0
ON time
Response time
ton25
toff0
—
4
ms
—
OFF time
25°C
60°C
25°C
25°C
toff25
F
—
Flicker
5
6
7
dB
s
—
Image retention time
Cross talk
YT60
—
0
—
%
CTK
—
—
5
Reflection Preventive Processing
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
– 12 –
LCX029CRT
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 13.5V, VVDD = 15.5V
VVC = 7.5V, Vcom = 7.1V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.5 ± VAC [V]
(VAC = signal amplitude)
• Measurement system I
Approx. 2000mm
LCD Projector
Projection size: 101.6cm (40 in)
Projection lens: F1.7
Light source: 120W UHP lamp
Incidence illumination system: F#2.5
Polarzer: Side of incidence light-Polatechno's SHC-128U
Side of output light-Polatechno's SKN-18243
• Measurement system II
Optical fiber
Measurement
Equipment
Light receptor lens
Light Detector
Drive Circuit
LCD panel
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
L (Black)
CR =
... (1)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 5.0V.
Both luminosities are measured by System I.
– 13 –
LCX029CRT
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
White luminance
T =
× 100 [%] ... (2)
Luminance of light source
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.
3. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
90
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
50
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
10
V90 V50 V10
VAC – Signal amplitude [V]
4. Response Time
Response time ton and toff are defined by
Input signal voltage (Waveform applied to the measured pixels)
formulas (3) and (4) respectively.
ton = t1 – tON ...(3)
toff = t2 – tOFF ...(4)
5.0V
7.5V
0.5V
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
0V
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Optical transmittance output waveform
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
– 14 –
LCX029CRT
5. Flicker
Flicker (F) is given by formula (5). DC and AC (XGA/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
AC component
DC component
Each input signal voltage for gray raster mode
is given by Vsig = 7.5 ± V50 [V]
F [dB] = 20 log
...(5)
{
}
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
6. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.5 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
Black level
Monoscope signal conditions:
Vsig = 7.5 ± 5.0 or ± 2.0 [V]
(shown in the right figure)
Vcom = 7.1V
5.0V
White level
2.0V
7.5V
0V
2.0V
5.0V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 5.0V/1V).
Wi' – Wi
Cross talk value CTK =
× 100 [%]
Wi
W1 W1'
W3 W3'
W2
W4
W2'
W4'
– 15 –
LCX029CRT
Viewing angle characteristics (Typical value)
90
100
Phi
160
220
280
340
400
0
180
10
30
50
70 Theta
270
θ0°
Z
θ
φ90°
Y
φ
φ180°
φ0°
X
φ270°
Measurement method
– 16 –
LCX029CRT
Optical transmittance of LCD panel (Typical value)
30
20
10
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 17 –
LCX029CRT
7 7 2 d o t s
7 6 8 d o t s ( E f f e c t i v e 1 3 . 8 2 m m ) 2 d o t s
2 d o t s
– 18 –
LCX029CRT
2. LCD Panel Operations
[Description of basic operations]
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 768 gate lines sequentially in a single horizontal scanning period. (XGA mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1024 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 1024 × 768 dots to display a
picture in a single vertical scanning period.
• The data and video signals shall be input with the 1H-inverted system.
[Description of operating mode]
This LCD panel can change the active area by displaying a black frame to support various computer or video
signals. The active area is switched by HB, VB and BLK. However, the center of the screen is not changed.
The active area setting modes are shown below.
HB
H
VB
H
BLK
H
Screen aspect ratio
4:3
1024 × 768
2
5:4
L
H
L
H
960 × 768
8:5
1024 × 640
1
H
1
2
Input BLK pulse (refer to drive waveform and vertical blanking period of PC98 made).
For only aspect ratio 5:4 mode, set Psig and COM voltage as shown below. The value of PsigG and COM
voltage is typical value. It is necessary to optimize the voltage for each set construction.
VVC + 5.0 [V]
VVC + 1.0 [V]
VVC
Psig
Psig G
Psig B
VVC – 1.0 [V]
VVC – 5.0 [V]
3
PRG
COM
VCOM + 2.0
VCOM
VCOM – 2.0
3
PRG shows the time of the 1st step of Psig signal, and it is not input to the panel.
– 19 –
LCX029CRT
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.
RGT
H
Mode
Right scan
Left scan
DWN
Mode
Down scan
Up scan
H
L
L
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
both the H and V systems must be varied. The phase relationship between the start pulse and the clock for
each mode is shown below.
(1) Vertical direction display cycle
(1.1) XGA, SXGA
(DWN = H, L)
VD
VST
1
2
3
765
766 767 768
VCK
Vertical display cycle 768H
(1.2) PC98
VD
VST
1
2
3
637
638 639 640
VCK
Vertical display cycle 640H
– 20 –
LCX029CRT
(2) Horizontal direction display cycle
(2.1.1) XGA, PC98 (RGT = H)
HD
HST
HCK1
1
2
3
4
83 84 85 86
HCK2
Horizontal display cycle
(2.1.2) XGA, PC98 (RGT = L)
HD
HST
1
2
3
4
83 84 85 86
HCK1
HCK2
Horizontal display cycle
(2.2.1) SXGA (RGT = H)
HD
HST
1
2
3
4
77 78 79 80
HCK1
Horizontal display cycle
HCK2
(2.2.2) SXGA (RGT = L)
HD
HST
HCK1
1
2
3
4
77 78 79 80
HCK2
Horizontal display cycle
– 21 –
LCX029CRT
(3) Vertical blanking cycle of PC98 mode
The input waveforms of PCG, PRG 1 and PSIG should be changed as shown below when BLK pulse is input.
Vertical blanking cycle
BLK
VCK
ENB
PCG
1
PRG
PSIG
1
PRG shows the period of PSIG black level, it is not input to the panel.
– 22 –
LCX029CRT
3. 12-dot Simultaneous Sampling
The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase
matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus,
phase matching between each signal is required using an external signal delaying circuit before applying
the video signal to the LCD panel.
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =
Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed.
VSIG1
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
S/H
VSIG1
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
VSIG8
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
3
4
CK1
S/H
CK2
S/H
5
6
7
CK3
S/H
CK4
S/H
CK5
S/H
8
9
CK6
S/H
CK7
10
S/H
VSIG8
VSIG9
CK8
S/H
11 VSIG9
CK9
S/H
12
13
14
VSIG10
VSIG11
VSIG12
VSIG10
VSIG11
VSIG12
CK10
S/H
CK11
S/H
CK12
– 23 –
LCX029CRT
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
CK7
CK8
CK9
CK10
CK11
CK12
– 24 –
LCX029CRT
Display System Block Diagram
An example of display system is shown below.
6
6
S/H Driver
CXA3512R
LCX029
LCX029
LCX029
S/H Driver
CXA3512R
6
6
S/H Driver
CXA3512R
R
G
B
Gamma
CXA2111R
S/H Driver
CXA3512R
PRG, CLP
VST
L.P.F.
Color Shading
Correction
CXA3503R
6
6
S/H Driver
CXA3512R
S/H Driver
CXA3512R
PLL
CXA3106AQ
HSYNC
MCLK/2
ENB, PRG, FRP
Timing Pulses
DSYNC
Timing
Generator
CXA3500R
VSYNC
– 25 –
LCX029CRT
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the glass panel.
c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a clean-
room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the glass panel.
(3) Light resistance
Orientation film and organic matter such as liquid crystal used inside of the LCD panel deteriorate by the
light chemical reaction. As a result, its indication characteristics may irreversible change. The progress of
its chemical reaction is influenced by short wavelength side's light (characteristics of UV cut filter) and
temperature when quantitiy of light is constant. To control its progress, attach suitable UV cut filter between
light source and LCD panel. (Sharp characteristic's filter of λ > 425nm is recommended.) Also, use suitable
IR cut filter to lower the temperature of LCD panel and cool the panel carefully.
(4) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 0.245N · m (measurement screw : JCIS Type 1,
M2.6 flat head screw) or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).
– 26 –
LCX029CRT
Package Outline
Unit: mm
4.9 ± 0.2
0.3 ± 0.05
2.2 ± 0.1
Thickness of the connector
16.5 ± 0.05
3
1
2
4
6
8
4-φ2.7 ± 0.08
5
Incident light
Polarizing Axis
Incident
light
Output light
Polarizing Axis
Active Area
7
(18.5)
14.1 ± 0.25
2.5 ± 0.1
No
1
Description
F P C
23.2 ± 0.1
28.2 ± 0.15
Outside frame
2
P0.5 × 31 = 15.5 ± 0.1
0.5 ± 0.1
3
Reinforcing board
0.35 ± 0.03
PIN32
PIN1
4 Reinforcing material
Glass 1
Glass 2
Cover 1
Cover 2
5
6
7
8
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
– 27 –
Mass
6.9g
Sony Corporation
相关型号：
LCX037BL
High Picture Quality 3.4 cm (1.35-Type) 1.05M-dot Wide XGA HDTV Projector LCD for the Coming Digital Age
SONY
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