AM27C512-255DC [SPANSION]

UVPROM, 64KX8, 250ns, CMOS, CDIP28, CERAMIC, DIP-28;


型号：	AM27C512-255DC
厂家：	SPANSION
描述：	UVPROM, 64KX8, 250ns, CMOS, CDIP28, CERAMIC, DIP-28 可编程只读存储器电动程控只读存储器 CD 内存集成电路
文件：	总12页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FINAL

Am27C512

512 Kilobit (64 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

n Fast access time

n Latch-up protected to 100 mA from –1 V to

V_CC+ 1 V

— Speed options as fast as 55 ns

n Low power consumption

n High noise immunity

n Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

— 20 µA typical CMOS standby current

n JEDEC-approved pinout

n Single +5 V power supply

n Standard 28-pin DIP, PDIP, and 32-pin PLCC

n ±10% power supply tolerance standard

n 100% Flashrite™ programming

— Typical programming time of 8 seconds

packages

GENERAL DESCRIPTION

The Am27C512 is a 512-Kbit, ultraviolet erasable pro-

grammable read-only memory. It is organized as 64K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast

single address location programming. Products are

available in windowed ceramic DIP packages, as well

as plastic one time programmable (OTP) PDIP and

PLCC packages.

thus eliminating bus contention in a multiple bus micro-

processor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 80 mW in active mode, and

100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses), re-

sulting in a typical programming time of 8 seconds.

Data can be typically accessed in less than 55 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

BLOCK DIAGRAM

Data Outputs

DQ0–DQ7

Output Enable

Chip Enable

and

OE#/V

Output

Buffers

CE#

Prog Logic

Gating

Decoder

A0–A15

Address

Inputs

524,288

Bit Cell

Matrix

Decoder

08140J-1

Publication# 08140 Rev: J Amendment/+2

Issue Date: June 1, 1999

PRODUCT SELECTOR GUIDE

Family Part Number

Am27C512

= 5.0 V ± 5%

= 5.0 V ± 10%

-55

-255

Speed Options

-70

-90

-120

120

-150

150

-200

200

Max Access Time (ns)

CE# (E#) Access (ns)

OE# (G#) Access (ns)

250

CONNECTION DIAGRAMS

Top View

DIP

PLCC

V_CC

A15

A12

1 32 31 30

A14

A13

A11

OE# (G#)/V_PP

A10

OE# (G#)/V_PP

A10

CE# (E#)

DQ7

CE# (E#)

DQ7

DQ0

DQ6

DQ0

DQ6

16 17

19 20

DQ1

DQ2

V_SS

DQ5

DQ4

DQ3

08140J-3

08140J-2

Notes:

1. JEDEC nomenclature is in parenthesis.

2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS

LOGIC SYMBOL

A0–A15

= Address Inputs

CE# (E#)

DQ0–DQ7

= Chip Enable Input

= Data Input/Outputs

A0–A15

OE# (G#)/V_PP= Output Enable Input

Program Voltage Input

DQ0–DQ7

CE# (E#)

V_CC

V_SS

= V_CCSupply Voltage

= Ground

OE# (G#)/V_PP

= No Internal Connection

08140J-4

Am27C512

ORDERING INFORMATION

UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the following:

AM27C512

-55

OPTIONAL PROCESSING

Blank = Standard Processing

= Burn-In

VOLTAGE TOLERANCE

= V ±5%

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

= Commercial (0°C to +70°C)

= Industrial (–40°C to +85°C)

= Extended (–55°C to +125°C)

PACKAGE TYPE

= 28-Pin Ceramic DIP (CDV028)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am27C512

512 Kilobit (64 K x 8-Bit) CMOS UV EPROM

Valid Combinations

AM27C512-55

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DC5

= 5.0 V ± 5%

AM27C512-55

= 5.0 V ± 10%

DC, DCB

AM27C512-70

AM27C512-90

DC, DCB, DI, DIB

AM27C512-120

AM27C512-150

AM27C512-200

AM27C512-255

DC, DCB, DI, DIB, DE, DEB

DC, DCB, DI, DIB

= 5.0 V ± 5%

Am27C512

ORDERING INFORMATION

OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the following:

AM27C512

-55

OPTIONAL PROCESSING

Blank = Standard Processing

VOLTAGE TOLERANCE

= V ±5%

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

= Commercial (0°C to +70°C)

= Industrial (–40°C to +85°C)

= Extended (–55°C to +125°C)

PACKAGE TYPE

= 28-Pin Plastic DIP (PD 028)

= 32-Pin Plastic Leaded Chip Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am27C512

512 Kilobit (64 K x 8-Bit) CMOS OTP EPROM

Valid Combinations

AM27C512-55

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

JC5, PC5

= 5.0 V ± 5%

AM27C512-55

= 5.0 V ± 10%

JC, PC

AM27C512-70

AM27C512-90

AM27C512-120

AM27C512-150

AM27C512-200

AM27C512-255

JC, PC, JI, PI

= 5.0 V ± 5%

Am27C512

FUNCTIONAL DESCRIPTION

Device Erasure

OE#/V_PP= 12.75 V ± 0.25 V, will program that particu-

lar device. A high-level CE# input inhibits the other de-

vices from being programmed.

In order to clear all locations of their programmed con-

tents, the device must be exposed to an ultraviolet light

source. A dosage of 15 W seconds/cm²is required to

completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp—wavelength

of 2537 Å—with intensity of 12,000 µW/cm²for 15 to 20

minutes. The device should be directly under and

about one inch from the source, and all filters should be

removed from the UV light source prior to erasure.

Program Verify

A verification should be performed on the programmed

bits to determine that they were correctly programmed.

The verify should be performed with OE#/V_PPand CE#

at V_IL, and V_PPbetween 12.5 V and 13.0 V.

Autoselect Mode

Note that all UV erasable devices will erase with light

sources having wavelengths shorter than 4000 Å, such

as fluorescent light and sunlight. Although the erasure

process happens over a much longer time period, ex-

posure to any light source should be prevented for

maximum system reliability. Simply cover the package

window with an opaque label or substance.

The autoselect mode provides manufacturer and de-

vice identification through identifier codes on DQ0–

DQ7. This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional in the 25°C ± 5°C

ambient temperature range that is required when pro-

gramming the device.

Device Programming

To activate this mode, the programming equipment

must force V_Hon address line A9. Two identifier bytes

may then be sequenced from the device outputs by

toggling address line A0 from V_ILto V_IH(that is, chang-

ing the address from 00h to 01h). All other address

lines must be held at V_ILduring the autoselect mode.

Upon delivery, or after each erasure, the device has

all of its bits in the “ONE”, or HIGH state. “ZEROs” are

loaded into the device through the programming pro-

cedure.

The device enters the programming mode when 12.75

V ± 0.25 V is applied to the OE#/V_PPpin, and CE# is at

V_IL.

Byte 0 (A0 = V_IL) represents the manufacturer code,

and Byte 1 (A0 = V_IH), the device identifier code. Both

codes have odd parity, with DQ7 as the parity bit.

For programming, the data to be programmed is ap-

plied 8 bits in parallel to the data pins.

Read Mode

The flowchart in the Programming section of the

EPROM Products Data Book (Section 5, Figure 5-1)

shows AMD’s Flashrite algorithm. The Flashrite algo-

rithm reduces programming time by using a 100 µs pro-

gramming pulse and by giving each address only as

many pulses to reliably program the data. After each

pulse is applied to a given address, the data in that ad-

dress is verified. If the data does not verify, additional

pulses are given until it verifies or the maximum pulses

allowed is reached. This process is repeated while se-

quencing through each address of the device. This part

of the algorithm is done at V_CC= 6.25 V to assure that

each EPROM bit is programmed to a sufficiently high

threshold voltage. After the final address is completed,

To obtain data at the device outputs, Chip Enable

(CE#) and Output Enable (OE#/V_PP) must be driven

low. CE# controls the power to the device and is typi-

cally used to select the device. OE#/V_PPenables the

device to output data, independent of device selection.

Addresses must be stable for at least t_ACC–t_OE. Refer

to the Switching Waveforms section for the timing dia-

gram.

Standby Mode

The device enters the CMOS standby mode when CE#

is at V_CC± 0.3 V. Maximum V_CCcurrent is reduced to

100 µA. The device enters the TTL-standby mode

when CE# is at V_IH. Maximum V_CCcurrent is reduced

to 1.0 mA. When in either standby mode, the device

places its outputs in a high-impedance state, indepen-

dent of the OE# input.

the entire EPROM memory is verified at V_CC= V_PP

5.25 V.

Please refer to Section 5 of the EPROM Products Data

Book for additional programming information and spec-

ifications.

Output OR-Tieing

To accommodate multiple memory connections, a

two-line control function provides:

Program Inhibit

Programming different data to multiple devices in par-

allel is easily accomplished. Except for CE#, all like in-

puts of the devices may be common. A TTL low-level

program pulse applied to one device’s CE# input with

n Low memory power dissipation, and

n Assurance that output bus contention will not occur.

Am27C512

CE# should be decoded and used as the primary de-

vice-selecting function, while OE#/V_PPbe made a com-

mon connection to all devices in the array and

connected to the READ line from the system control

bus. This assures that all deselected memory devices

are in their low-power standby mode and that the out-

put pins are only active when data is desired from a

particular memory device.

ing and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1 µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

V_CCand V_SSto minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

rays, a 4.7 µF bulk electrolytic capacitor should be

used between V_CCand V_SSfor each eight devices. The

location of the capacitor should be close to where the

power supply is connected to the array.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the ris-

MODE SELECT TABLE

Mode

CE#

OE#/V

Outputs

Read

OUT

Output Disable

Standby (TTL)

Standby (CMOS)

Program

High Z

± 0.3 V

Program Verify

Program Inhibit

OUT

High Z

01h

Manufacturer Code

Device Code

Autoselect

(Note 3)

91h

Notes:

1. V = 12.0 V ± 0.5 V.

2. X = Either V or V .

3. A1–A8 and A10–15 = V

4. See DC Programming Characteristics for V voltage during programming.

Am27C512

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature

Commercial (C) Devices

OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C

All Other Products . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature (T_A) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Ambient Temperature (T_A) . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Voltage with Respect to V_SS(Note 1)

Ambient Temperature (T_A) . . . . . . . .–55°C to +125°C

Supply Read Voltages

All pins except A9, V_PP, V_CC. . –0.6 V to V_CC+ 0.6 V

A9 and V_PP(Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V

_CCfor ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V

V_CCfor ± 10% devices . . . . . . . . . +4.50 V to +5.50 V

Notes:

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

1. Minimum DC voltage on input or I/O pins –0.5 V. During

voltage transitions, the input may overshoot V to –2.0

V for periods of up to 20 ns. Maximum DC voltage on

input and I/O pins is V +0.5 V. During voltage transi-

tions, input and I/O pins may overshoot to V + 2.0 V for

periods up to 20 ns.

2. Minimum DC input voltage on A9 is –0.5 V. During voltage

transitions, A9 and V may overshoot V to –2.0 V for

periods of up to 20 ns. A9 and V must not exceed +13.5

V at any time.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum ratings for extended periods

may affect device reliability.

Am27C512

DC CHARACTERISTICS over operating range (unless otherwise specified)

Parameter

Symbol

Parameter Description

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Test Conditions

Min

Max

Unit

= –400 µA

= 2.1 mA

2.4

0.45

2.0

+ 0.5

–0.5

+0.8

1.0

Input Load Current

= 0 V to V

µA

C/I Devices

E Devices

1.0

Output Leakage Current

= 0 V to V

µA

OUT

5.0

Active Current (Note 2)

CE# = V , f = 10 MHz,

CC1

= 0 mA

OUT

TTL Standby Current

CE# = V

1.0

µA

CC2

CMOS Standby Current

CE# = V ± 0.3 V

100

CC3

Caution: The device must not be removed from (or inserted into) a socket when V or V is applied.

Notes:

1. V must be applied simultaneously or before V , and removed simultaneously or after V .

2. I

is tested with OE# = V to simulate open outputs.

CC1

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods less than 20 ns.

–75 –50 –55

25 50 75 100 125 150

Temperature in °C

Frequency in MHz

08140J-5

08140J-6

Figure 1. Typical Supply Current vs. Frequency

_CC= 5.5 V, T = 25°C

Figure 2. Typical Supply Current vs. Temperature

_CC= 5.5 V, f = 10 MHz

Am27C512

TEST CONDITIONS

5.0 V

Table 1. Test Specifications

All

2.7 kΩ

Test Condition

-55

others

Unit

Device

Under

Test

Output Load

1 TTL gate

Output Load Capacitance, C

(including jig capacitance)

100

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

≤ 20

0.0–3.0 0.45–2.4

Input timing measurement

reference levels

1.5

0.8, 2.0

Note:

Diodes are IN3064 or equivalents.

Output timing measurement

reference levels

08140J-7

Figure 3. Test Setup

SWITCHING TEST WAVEFORM

3 V

2.4 V

2.0 V

0.8 V

2.0 V

Test Points

1.5 V

Test Points

1.5 V

0.8 V

0 V

0.45 V

Input

Output

Input

Output

Note: For C = 30 pF.

Note: For C = 100 pF.

08140J-8

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

Am27C512

AC CHARACTERISTICS

Parameter Symbols

Am27C512

JEDEC Standard

Description

Test Setup

-55 -70 -90 -120 -150 -200 -255 Unit

CE#,

OE# = V

Address to Output Delay

Max

90 120 150 200 250

AVQV

ACC

Chip Enable to Output Delay

OE# = V

Max

ELQV

GLQV

Output Enable to Output Delay CE# = V

Chip Enable High or Output

Enable High to Output High Z,

Whichever Occurs First

EHQZ

GHQZ

Max

Min

(Note 2)

Output Hold Time from

Addresses, CE# or OE#,

Whichever Occurs First

AXQX

Caution: Do not remove the device from (or insert it into) a socket or board that has V or V applied.

Notes:

1. V must be applied simultaneously or before V , and removed simultaneously or after V .

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

2.4

2.0

0.8

2.0

0.8

Addresses

0.45

Addresses Valid

CE#

OE#

(Note 2)

ACC

(Note 1)

High Z

Output

Valid Output

08140J-9

Notes:

1. OE# may be delayed up to t

– t after the falling edge of the addresses without impact on t .

ACC

2. t is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE

CDV028

PL 032

Typ Max

PD 028

Parameter

Parameter Symbol

Description

Input Capacitance

Output Capacitance

Test Conditions

Typ

Max

Typ

Max

Unit

= 0

OUT

= 0

OUT

Notes:

1. This parameter is only sampled and not 100% tested.

2. T = +25°C, f = 1 MHz.

Am27C512

PHYSICAL DIMENSIONS*

CDV028—28-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

DATUM D

CENTER PLANE

UV Lens

.565

.605

INDEX AND

TERMINAL NO. 1

I.D. AREA

TOP VIEW

DATUM D

CENTER PLANE

.700

MAX

1.435

1.490

.160

.220

BASE PLANE

SEATING PLANE

94°

105°

.125

.200

.015

.060

.300 BSC

.005 MIN

.600

BSC

.045

.065

.008

.018

.100 BSC

.014

.026

END VIEW

SIDE VIEW

16-000038H-3

CDV028

DF10

3-30-95 ae

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 028—28-Pin Plastic Dual In-Line Package (measured in inches)

1.440

1.480

.600

.625

.530

.580

.008

.015

Pin 1 I.D.

.630

.700

.045

.065

0°

10°

.005 MIN

.140

.225

16-038-SB-AG

PD 028

DG75

SEATING PLANE

.015

.060

.014

.022

7-13-95 ae

.120

.160

.090

.110

Am27C512

PHYSICAL DIMENSIONS

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

.485

.495

.447

.453

.009

.015

.042

.056

.125

.140

.585

.595

Pin 1 I.D.

.080

.095

.547

.553

SEATING

PLANE

.400

REF.

.490

.530

.013

.021

.050 REF.

16-038FPO-5

PL 032

DA79

.026

.032

TOP VIEW

SIDE VIEW

6-28-94 ae

REVISION SUMMARY FOR AM27C512

Revision I (May 1998)

Global

Revision J (January 1999)

Ordering Information

Changed formatting to match current data sheets.

Added the 5% voltage tolerance information for order-

ing part numbers.

Product Selector Guide

Revision J+1 (March 5, 1999)

Added the -55 speed option for V_CC= 5.0 V ± 10%.

Ordering Information

Ordering Information—UV EPROM Products

UV EPROM Products: Corrected the first row valid

combination to DC5.

Valid Combinations: -55 speed option added. Combi-

nations DI and DIB added for -70 and -90 speed op-

tions.

Revision J+2 (June 1, 1999)

Ordering Information

Ordering Information—OTP EPROM Products

Valid Combinations: Added speed options for -55 with

Corrected device organization to 64K x 8-Bit.

V_CC= 5.0 V ± 5% and -55 with V_CC= 5.0 V ± 10%.

Absolute Maximum Ratings

Changed Note 1 reference to indicate that it pertains

voltage on all pins. Corrected Note 1 to indicate that

maximum input voltage is V_CC+0.5 V.

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Flashrite is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am27C512

AM27C512-255DC [SPANSION]

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