AM29F017D-90E4C [SPANSION]
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory; 16兆位（2M ×8位） CMOS 5.0伏只，统一部门快闪记忆体
| 型号： | AM29F017D-90E4C |
| 厂家： | 
SPANSION |
| 描述： | 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 文件： | 总44页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Am29F017D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 21195 Revision E Amendment +2 Issue Date March 23, 2001
Am29F017D
16 Megabit (2 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Optimized for memory card applications
■ Unlock Bypass Program Command
— Backwards-compatible with Am29F016C and
Am29F017B
— Reduces overall programming time when
issuing multiple program command sequences
■ 5.0 V ± 10%, single power supply operation
■ Minimum 1,000,000 program/erase cycles per
sector guaranteed
— Minimizes system level power requirements
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package options
■ Manufactured on 0.23 µm process technology
■ High performance
— Access times as fast as 70 ns
— 40-pin TSOP
■ Low power consumption
— 48-pin TSOP
— 25 mA typical active read current
— 30 mA typical program/erase current
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— 1 µA typical standby current (standard access
time to active mode)
— Superior inadvertent write protection
■ Flexible sector architecture
— 32 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
■ Ready/Busy# output (RY/BY#)
— Group sector protection:
— Provides a hardware method for detecting
program or erase cycle completion
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
■ Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■ Embedded Algorithms
■ Hardware reset pin (RESET#)
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Resets internal state machine to the read mode
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
Publication# 21195 Rev: E Amendment/+2
Issue Date: March 23, 2001
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
GENERAL DESCRIPTION
The Am29F017D is a 16 Mbit, 5.0 volt-only Flash mem-
ory organized as 2,097,152 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F017D is offered in a
40-pin or 48-pin TSOP package. This device is de-
signed to be programmed in-system with the standard
system 5.0 volt VCC supply. A 12.0 volt VPP is not re-
quired for program or erase operations. The device can
also be programmed in standard EPROM program-
mers.
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
This device is manufactured using AMD’s 0.23 µm
process technology, and offers all the features and ben-
efits of the 0.32 µm Am29F017B and the 0.5 µm
Am29F016C.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#), write
enable (WE#), and output enable (OE#) controls.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
2
Am29F017D
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F017D Device Bus Operations .................................. 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status ...................................... 9
Standby Mode ........................................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode.............................................................. 10
Table 2. Sector Address Table........................................................ 11
Autoselect Mode..................................................................... 12
Table 3. Am29F017D Autoselect Codes (High Voltage Method).... 12
Sector Group Protection/Unprotection.................................... 12
Table 4. Sector Group Addresses................................................... 12
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Temporary Sector Group Unprotect Operation................ 13
Hardware Data Protection ...................................................... 13
DQ3: Sector Erase Timer ....................................................... 23
Figure 5. Toggle Bit Algorithm........................................................ 23
Table 10. Write Operation Status................................................... 24
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 6. Maximum Negative Overshoot Waveform ...................... 25
Figure 7. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
TTL/NMOS Compatible .......................................................... 26
CMOS Compatible.................................................................. 26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Test Setup...................................................................... 27
Table 11. Test Specifications......................................................... 27
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read-only Operations............................................................. 28
Figure 9. Read Operation Timings................................................. 28
Hardware Reset (RESET#) .................................................... 29
Figure 10. RESET# Timings .......................................................... 29
Erase/Program Operations..................................................... 30
Figure 11. Program Operation Timings.......................................... 31
Figure 12. Chip/Sector Erase Operation Timings .......................... 32
Figure 13. Data# Polling Timings (During Embedded Algorithms). 33
Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 33
Figure 15. DQ2 vs. DQ6................................................................. 34
Temporary Sector Unprotect .................................................. 34
Figure 16. Temporary Sector Group Unprotect Timing Diagram ... 34
Erase and Program Operations.............................................. 35
Alternate CE# Controlled Writes .................................................... 35
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 36
Erase and Programming Performance . . . . . . . . 37
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
TS 040—40-Pin Standard Thin Small Outline Package ......... 38
TSR040—40-Pin Reverse Thin Small Outline Package......... 39
TS 048—48-Pin Standard Thin Small Outline Package ......... 40
TSR048—48-Pin Reverse Thin Small Outline Package......... 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (July 1997)............................................................ 42
Revision B (January 1998) ..................................................... 42
Revision B+1 (January 1998) ................................................. 42
Revision B+2 (April 1998)....................................................... 42
Revision B+3 (August 1998)................................................... 42
Revision C (January 1999) ..................................................... 42
Revision C+1 (March 23, 1999).............................................. 42
Revision C+2 (May 17, 1999)................................................. 42
Revision D (November 16, 1999) ........................................... 42
Revision E (May 19, 2000) ..................................................... 43
Revision E+1 (December 5, 2000) ......................................... 43
Revision E+2 (March 23, 2001).............................................. 43
Low V Write Inhibit...................................................................... 13
CC
Write Pulse “Glitch” Protection........................................................ 13
Logical Inhibit .................................................................................. 13
Power-Up Write Inhibit .................................................................... 13
Common Flash Memory Interface (CFI) . . . . . . . 14
Table 5. CFI Query Identification String.......................................... 14
Table 6. System Interface String..................................................... 14
Table 7. Device Geometry Definition .............................................. 15
Table 8. Primary Vendor-Specific Extended Query ........................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data................................................................ 16
Reset Command..................................................................... 16
Autoselect Command Sequence............................................ 16
Byte Program Command Sequence....................................... 16
Unlock Bypass Command Sequence.............................................. 17
Figure 2. Program Operation .......................................................... 17
Chip Erase Command Sequence........................................... 17
Sector Erase Command Sequence........................................ 18
Erase Suspend/Erase Resume Commands........................... 18
Figure 3. Erase Operation............................................................... 19
Command Definitions ............................................................. 20
Table 9. Am29F017D Command Definitions................................... 20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling................................................................. 21
Figure 4. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I.................................................................... 22
DQ2: Toggle Bit II................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
DQ5: Exceeded Timing Limits................................................ 23
Am29F017D
3
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F017D
-120
Speed Options (V = 5.0 V ± 10%)
-70
70
70
40
-90
90
90
40
-150
150
150
75
CC
Max Access Time (ns)
120
120
50
CE# Access (ns)
OE# Access (ns)
Note: See the AC Characteristics section for more information.
BLOCK DIAGRAM
DQ0–DQ7
Sector Switches
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RY/BY#
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
A0–A20
4
Am29F017D
CONNECTION DIAGRAMS
NC
NC
1
2
3
4
5
6
7
8
9
48 NC
47 NC
46 A20
45 NC
A19
A18
A17
A16
A15
A14
A13
A12 10
CE# 11
VCC 12
NC 13
44 WE#
43 OE#
42 RY/BY#
41 DQ7
40 DQ6
39 DQ5
38 DQ4
37 VCC
36 VSS
35 VSS
34 DQ3
33 DQ2
32 DQ1
31 DQ0
30 A0
48-Pin Standard TSOP
RESET# 14
A11 15
A10 16
A9 17
A8 18
A7 19
A6 20
29 A1
28 A2
27 A3
A5 21
A4 22
NC 23
26 NC
24
25 NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
48 NC
47 NC
46 A19
45 A18
44 A17
43 A16
42 A15
41 A14
40 A13
39 A12
38 CE#
37 VCC
36 NC
35 RESET#
34 A11
33 A10
32 A9
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5 10
DQ4 11
VCC 12
VSS 13
VSS 14
DQ3 15
DQ2 16
DQ1 17
DQ0 18
A0 19
48-Pin Reverse TSOP
31 A8
30 A7
A1 20
29 A6
A2 21
28 A5
A3 22
27 A4
NC 23
26 NC
24
25 NC
NC
Am29F017D
5
CONNECTION DIAGRAMS
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
NC
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
VSS
5
6
7
8
9
40-Pin Standard TSOP
10
11
12
13
14
15
16
17
18
19
20
RESET#
A11
A10
A9
VSS
DQ3
DQ2
DQ1
DQ0
A0
A8
A7
A6
A5
A4
A1
A2
A3
A20
NC
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A19
A18
A17
A16
A15
A14
A13
A12
CE#
VCC
NC
RESET#
A11
A10
A9
A8
A7
A6
WE#
OE#
RY/BY#
DQ7
DQ6
DQ5
DQ4
VCC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Reverse TSOP
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A5
A4
6
Am29F017D
PIN CONFIGURATION
LOGIC SYMBOL
A0–A20
=
21 Addresses
21
DQ0–DQ7 = 8 Data Inputs/Outputs
A0–A20
8
CE#
=
=
=
=
=
=
Chip Enable
DQ0–DQ7
WE#
Write Enable
OE#
Output Enable
CE#
OE#
RESET#
RY/BY#
VCC
Hardware Reset Pin, Active Low
Ready/Busy Output
WE#
+5.0 V single power supply see
Product Selector Guide for device
speed ratings and voltage supply
tolerances)
RESET#
RY/BY#
VSS
NC
=
=
Device Ground
Pin Not Connected Internally
Am29F017D
7
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29F017D
-70
E
I
TEMPERATURE RANGE
C
I
=
=
=
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Extended (–55°C to +125°C)
E
PACKAGE TYPE
E
=
=
=
=
48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)
40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040)
40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040)
F
E4
F4
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F017D
16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
EC, EI, FC, FI, E4C, E4I,
AM29F017D-70
F4C, F4I
AM29F017D-90
AM29F017D-120
AM29F017D-150
EC, EI, EE,
FC, FI, FE,
E4C, E4I, E4E,
F4C, F4I, F4E
8
Am29F017D
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F017D Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
A0–A20
DQ0–DQ7
Read
Write
H
H
A
A
D
OUT
IN
IN
L
H
L
D
IN
CMOS Standby
TTL Standby
V
± 0.5 V
X
X
V
± 0.5 V
CC
X
High-Z
High-Z
High-Z
High-Z
CC
H
L
X
X
H
H
L
X
X
X
Output Disable
Hardware Reset
H
H
X
X
X
Temporary Sector Unprotect
(See Note)
X
X
X
V
A
D
IN
ID
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, D = Data In, D
= Data Out, A = Address In
IN
IL
IH
ID
IN
OUT
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
table represents the active current specification for
reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Am29F017D
9
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS
0.5 V, the device enters the CMOS standby mode.
±
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
RESET#: Hardware Reset Pin
Output Disable Mode
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
10
Am29F017D
Table 2. Sector Address Table
Sector
SA0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
Note: All sectors are 64 Kbytes in size.
Am29F017D
11
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-
Table 3. Am29F017D Autoselect Codes (High Voltage Method)
CE# OE# WE# A20-A18 A17-A10 A9 A8-A7 A6 A5-A2 A1 A0
Description
DQ7-DQ0
Manufacturer ID:
AMD
L
L
L
L
H
H
X
X
X
X
V
V
X
X
V
X
X
V
V
01h
ID
ID
IL
IL
IL
IL
IL
Device ID:
Am29F017D
V
V
V
3Dh
IH
Sector Group
Protection
Verification
Sector
Group
Address
01h (protected)
L
L
H
X
V
X
V
X
V
V
IL
ID
IL
IH
00h (unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
It is possible to determine whether a sector group is
protected or unprotected. See “Autoselect Mode” for
details.
Sector Group Protection/Unprotection
The hardware sector group protection feature dis-
ables both program and erase operations in any sec-
tor. Each sector group consists of four adjacent
sectors. Table 4 shows how the sectors are goruped,
and the address range that each sector group con-
tains. The hardware sector group unprotection fea-
ture re-enables both program and erase operations in
previously protected sectors.
Table 4. Sector Group Addresses
Sector
Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
A20
A19
A18
Sectors
0
0
0
SA0–SA3
0
0
1
SA4–SA7
0
1
0
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
Sector group protection/unprotection must be imple-
mented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 23923. Contact an
AMD representative to obtain a copy of the appropriate
document. Note that the sector group protection and
unprotection scheme differs from that used with the
previous versions of this device, the Am29F017B.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Temporary Sector Group Unprotect
The device is shipped with all sector groups unpro-
tected. AMD offers the option of programming and pro-
tecting sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
This feature allows temporary unprotection of previ-
ously protected sectors groups to change data in-sys-
tem. The Sector Group Unprotect mode is activated
by setting the RESET# pin to VID. During this mode,
formerly protected sector groups can be programmed
or erased by selecting the sector group addresses.
Once VID is removed from the RESET# pin, all the
12
Am29F017D
previously protected sector groups are
protected again. Figure 1 shows the algorithm, and
the Temporary Sector/Sector Group Unprotect dia-
gram shows the timing waveforms, for this feature.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
START
RESET# = V
(Note 1)
ID
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
Perform Erase or
Program Operations
RESET# = V
IH
tional writes when VCC is greater than VLKO
.
Temporary Sector Group
Unprotect
Write Pulse “Glitch” Protection
Completed (Note 2)
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
once again.
Power-Up Write Inhibit
Figure 1. Temporary Sector Group Unprotect
Operation
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Am29F017D
13
data. The system can read CFI information at the ad-
dresses given in Tables 5–8. To terminate reading CFI
data, the system must write the reset command.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of de-
vices. Software support can then be device-indepen-
dent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The sys-
tem must write the reset command to return the device
to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to any ad-
dress (XXh), any time the device is ready to read array
Table 5. CFI Query Identification String
Description
Addresses
Data
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
Primary OEM Command Set
13h
14h
02h
00h
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
00h
00h
Table 6. System Interface String
Description
Addresses
Data
V
Min. (write/erase)
CC
1Bh
45h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
1Ch
55h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
00h
00h
03h
00h
0Ah
00h
05h
00h
04h
00h
V
V
Min. voltage (00h = no V pin present)
PP
PP
PP
Max. voltage (00h = no V pin present)
PP
N
Typical timeout per single byte/word write 2 µs
N
Typical timeout for Min. size buffer write 2 µs (00h = not supported)
N
Typical timeout per individual block erase 2 ms
N
Typical timeout for full chip erase 2 ms (00h = not supported)
N
Max. timeout for byte/word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2 times typical
N
Max. timeout for full chip erase 2 times typical (00h = not supported)
14
Am29F017D
Table 7. Device Geometry Definition
Description
Addresses
Data
N
27h
15h
Device Size = 2 byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
N
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
1Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Table 8. Primary Vendor-Specific Extended Query
Data Description
Addresses
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
44h
31h
31h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
01h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
47h
48h
04h
01h
Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
04h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
4Bh
00h
00h
Simultaneous Operation: 00 = Not Supported, 01 = Supported
Burst Mode Type: 00 = Not Supported, 01 = Supported
Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
4Ch
00h
4Dh
4Eh
00h
00h
ACC supply minimum
ACC supply maximum
Top/bottom boot sector flag
2 = bottom, 3 = top. If address 2Ch = 01h, ignore this field
4Fh
00h
Am29F017D
15
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/
Erase Resume Commands” for more information on
this mode.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in returns 01h if that sector
is protected, or 00h if it is unprotected. Refer to the
Sector Address tables for valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
16
Am29F017D
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The program command sequence
should be reinitiated once the device has reset to read-
ing array data, to ensure data integrity.
START
Write Program
Command Sequence
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Data Poll
from System
Embedded
Program
algorithm
in progress
Unlock Bypass Command Sequence
Verify Data?
Yes
No
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the com-
mand sequence.
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
Am29F017D
17
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
18
Am29F017D
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
Am29F017D
19
Command Definitions
Table 9. Am29F017D Command Definitions
Bus Cycles (Notes 2–4)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
4
RA
RD
F0
XXX
XXX
XXX
XXX
XXX
XX
AA
AA
XXX
XXX
XXX
XXX
55
55
XXX
XXX
XXX
XXX
90
90
X00
X01
01
Autoselect
Device ID
(Note 7)
3D
XX00
XX01
Sector Group Protect
Verify (Note 8)
SGA
X02
4
AA
55
90
CFI Query (Note 9)
Program
1
4
3
2
2
6
6
1
1
98
AA
AA
A0
90
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
PA
55
55
PD
00
55
55
XXX
XXX
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
Chip Erase
XXX
XXX
XXX
AA
AA
B0
30
XXX
XXX
80
80
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
SA
10
30
Sector Erase
Erase Suspend (Note 9)
Erase Resume (Note 10)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on
the rising edge of WE# or CE# pulse, whichever happens
first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode)
or erased. Address bits A20–A16 select a unique sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
SGA = Address of the sector group to be verified. Address
bits A20–A18 select a unique sector group.
Notes:
8. The data is 00h for an unprotected sector group and 01h
for a protected sector group.See “Autoselect Command
Sequence” for more information.
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
4. Address bits A20–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the unlock
bypass mode.
5. No unlock or command cycles required when reading
array data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5
goes high (while the device is providing status data).
12. The system may read and program in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.
7. The fourth cycle of the autoselect command sequence is
a read cycle.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
20
Am29F017D
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
Yes
DQ7 = Data?
No
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
Am29F017D
21
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 10 shows the outputs for RY/BY#. The timing di-
agrams for read, reset, program, and erase shows the
relationship of RY/BY# to other signals.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 10 to compare out-
puts for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the following
read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
22
Am29F017D
the system must write the reset command to return to
reading array data.
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 10 shows the outputs for DQ3.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Read DQ7–DQ0
(Note 1)
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
No
Toggle Bit
= Toggle?
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command Se-
quence” section.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
Am29F017D
23
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 1)
DQ6
(Note 2)
DQ3
N/A
1
(Note 1)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
24
Am29F017D
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
V
CC
+2.0 V
Voltage with Respect to Ground
V
CC
VCC (Note 1) . . . . . . . . . . . . . . . . .–2.0 V to 7.0 V
A9, OE#, RESET# (Note 2). . . . .–2.0 V to 12.5 V
All other pins (Note 1) . . . . . . . . . .–2.0 V to 7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
+0.5 V
2.0 V
20 ns
20 ns
Notes:
Figure 6. Maximum Negative
Overshoot Waveform
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshoot V to –2.0 V
SS
for periods of up to 20 ns. See Figure 6. Maximum DC
voltage on output and I/O pins is V + 0.5 V. During
CC
voltage transitions, outputs may overshoot to V + 2.0 V
CC
for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on A9, OE#, RESET# pins is
–0.5V. During voltage transitions, A9, OE#, RESET# pins
20 ns
20 ns
+0.8 V
may overshoot V to –2.0 V for periods of up to 20 ns.
SS
See Figure 6. Maximum DC input voltage on A9, OE#,
and RESET# is 12.5 V which may overshoot to 13.5 V for
periods up to 20 ns.
–0.5 V
–2.0 V
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
20 ns
Stresses greater than those listed in this section may cause
permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections
of this specification is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods
may affect device reliability.
Figure 7. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TC) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TC) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
V
Supply Voltages
CC
VCC for ± 10% all devices . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Am29F017D
25
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
= V to V , V = V Max
Min
Typ
Max
±1.0
50
Unit
µA
µA
µA
mA
mA
mA
mA
V
I
Input Load Current
V
V
V
LI
IN
SS
CC CC
CC
I
A9 Input Load Current
Output Leakage Current
= V Max, A9 = 12.5 V
LIT
CC
OUT
CC
I
= V to V , V = V Max
±1.0
40
LO
SS
CC CC
CC
I
I
I
I
V
V
V
V
Read Current (Note 1)
Write Current (Notes 3, 4)
Standby Current (Note 2)
Standby Current (Note 2)
CE# = V , OE# = V
25
40
CC1
CC2
CC3
CC4
CC
CC
CC
CC
IL
IH
IH
CE# = V , OE# = V
60
IL
CE# = V , RESET# = V
0.4
0.4
1.0
1.0
0.8
IH
IH
RESET# = V
IL
V
Input Low Level
Input High Level
–0.5
2.0
IL
V
V
+ 0.5
V
IH
CC
Voltage for Autoselect and Sector
Protect
V
V
= 5.0 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
Output High Level
I
I
= 12 mA, V = V Min
V
V
V
OL
OL
CC
CC
V
= –2.5 mA, V = V Min
2.4
3.2
OH
OH
CC
CC
V
Low V Lock-out Voltage
4.2
LKO
CC
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
= V to V , V = V Max
Min
Typ
Max
±1.0
50
Unit
µA
I
Input Load Current
V
V
V
LI
IN
SS
CC CC
CC
I
A9 Input Load Current
Output Leakage Current
= V Max, A9 = 12.5 V
µA
LIT
CC
OUT
CC
I
= V to V , V = V Max
±1.0
40
µA
LO
SS
CC CC
CC
I
I
V
V
Read Current (Note 1)
CE# = V , OE# = V
25
30
mA
mA
CC1
CC2
CC
CC
IL
IH
IH
Write Current (Notes 3, 4)
CE# = V , OE# = V
40
IL
CE# = V
RESET# = V
± 0.5 V,
CC
I
I
V
V
Standby Current (Notes 2, 5)
1
1
5
µA
CC3
CC
± 0.5 V
CC
Standby Current (Notes 2, 5) RESET# = V
± 0.5 V
5
µA
V
CC4
CC
SS
V
Input Low Level
Input High Level
–0.5
0.8
IL
V
0.7x V
V + 0.3
CC
V
IH
CC
Voltage for Autoselect
and Sector Protect
V
V
= 5.0 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 12 mA, V = V Min
V
V
V
V
OL
OL
OH
OH
CC
CC
V
= –2.5 mA, V = V Min
0.85 V
CC
OH1
OH2
CC
CC
Output High Voltage
V
= –100 µA, V = V Min
V
– 0.4
CC
CC
CC
V
Low V Lock-out Voltage
3.2
4.2
LKO
CC
Notes for DC Characteristics (both tables):
1. The I current is typically less than 1 mA/MHz, with OE# at V .
CC
IH
2. Maximum I specifications are tested with V = V max.
CC
CC
CC
3. I active while Embedded Program or Embedded Erase algorithm is in progress.
CC
4. Not 100% tested.
5. For CMOS mode only I
, I
= 20 µA at extended temperature (>+85°C).
CC3 CC4
26
Am29F017D
TEST CONDITIONS
Table 11. Test Specifications
All speed
5.0 V
Test Condition
options
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
20
ns
0.45–2.4
V
Input timing measurement
reference levels
0.8
2.0
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
Am29F017D
27
AC CHARACTERISTICS
Read-only Operations
Parameter Symbol
Speed Options
Test
JEDEC
Std
Parameter Description
Read Cycle Time (Note 1)
Setup
-70
-90
-120
-150
Unit
t
t
Min
70
90
120
150
ns
AVAV
RC
CE# = V
OE# = V
IL
t
t
Address to Output Delay
Max
70
90
120
150
ns
AVQV
ACC
IL
t
t
t
Chip Enable to Output Delay
Output Enable to Output Delay
OE# = V
Max
Max
Min
70
40
0
90
40
0
120
50
0
150
55
0
ns
ns
ns
ELQV
GLQV
CE
IL
t
t
OE
Read
Output Enable Hold
t
OEH
Toggle and
Data# Polling
Time (Note 1)
Min
10
10
10
10
ns
t
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Max
Max
20
20
20
20
30
30
35
35
ns
ns
EHQZ
GHQZ
DF
t
DF
Output Hold Time From Addresses CE#
or OE# Whichever Occurs First
t
t
Min
0
0
0
0
ns
AXQX
OH
RESET# Pin Low to Read Mode
(Note 1)
t
Max
20
20
20
20
µs
Ready
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 11for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 9. Read Operation Timings
28
Am29F017D
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std Description
RESET# Pin Low (During Embedded
Test Setup
All Speed Options
Unit
t
Max
20
µs
READY
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
Max
500
ns
READY
t
t
t
RESET# Pulse Width
Min
Min
Min
500
50
0
ns
ns
ns
RP
RH
RB
RESET# High Time Before Read (See Note)
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 10. RESET# Timings
Am29F017D
29
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Parameter Description
Write Cycle Time (Note 1)
-70
-90
-120
-150
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
70
90
120
150
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
0
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
40
40
45
45
50
50
50
50
ns
t
t
ns
t
t
t
t
Data Hold Time
0
0
ns
t
Output Enable Setup Time
ns
OES
Read Recover Time Before Write
(OE# high to WE# low)
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Max
Min
Min
0
0
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
CE# Hold Time
t
t
Write Pulse Width
40
45
50
50
ns
t
t
Write Pulse Width High
Byte Programming Operation (Note 2)
20
7
ns
WPH
t
t
µs
WHWH1
WHWH2
WHWH1
1
sec
sec
µs
t
t
Sector Erase Operation (Note 2)
WHWH2
8
t
V
Set Up Time (Note 1)
50
VCS
CC
t
WE# to RY/BY# Valid
40
40
50
60
ns
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
30
Am29F017D
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
Figure 11. Program Operation Timings
Am29F017D
31
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note:
SA = Sector Address. VA = Valid Address for reading status data.
Figure 12. Chip/Sector Erase Operation Timings
32
Am29F017D
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 14. Toggle Bit Timings (During Embedded Algorithms)
Am29F017D
33
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
Figure 15. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
Rise and Fall Time (See Note)
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
ID
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 16. Temporary Sector Group Unprotect Timing Diagram
34
Am29F017D
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Parameter Symbol
Speed Options
JEDEC
Std
Parameter Description
Write Cycle Time (Note 1)
-70
-90
-120
-150
Unit
ns
t
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Max
70
90
120
150
AVAV
AVEL
ELAX
DVEH
EHDX
GHEL
WLEL
WC
t
Address Setup Time
Address Hold Time
0
ns
AS
AH
DS
DH
t
t
40
40
45
45
50
50
50
50
ns
t
t
t
Data Setup Time
ns
t
t
t
Address Hold Time
0
0
0
0
ns
t
Read Recover Time Before Write
CE# Setup Time
ns
GHEL
t
ns
WS
t
t
CE# Hold Time
ns
EHWH
WH
t
t
Write Pulse Width
40
45
50
50
ns
ELEH
EHEL
CP
t
t
Write Pulse Width High
Byte Programming Operation (Note 2)
20
7
ns
CPH
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
1
sec
sec
t
t
Sector Erase Operation (Note 2)
8
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F017D
35
AC CHARACTERISTICS
XXX for program
PA for program
XXX for erase
SA for sector erase
XXX for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
= Array Data.
OUT
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
36
Am29F017D
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Sector Erase Time
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
1
32
8
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
256
300
43.2
Byte Programming Time
Chip Programming Time (Note 3)
Notes:
7
Excludes system-level overhead
(Note 5)
14.4
sec
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 4.5 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for programming. See Table 6 for further
information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Min
Max
+ 1.0 V
Input Voltage with respect to V on I/O pins
–1.0 V
V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 5.0 Volt, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Conditions
Min
6
Max
7.5
12
Unit
pF
C
Input Capacitance
V
V
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
= 0
= 0
8.5
7.5
pF
OUT
OUT
C
9
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
Am29F017D
37
PHYSICAL DIMENSIONS
TS 040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
38
Am29F017D
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse Thin Small Outline Package
Dwg rev AA; 10/99
Am29F017D
39
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
40
Am29F017D
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse Thin Small Outline Package
Dwg rev AA; 10/99
Am29F017D
41
REVISION SUMMARY
Revision A (July 1997)
Revision B+3 (August 1998)
Initial release of the Am29F017B device (0.35 µm).
Global
The Am29F017B is now available in 40-pin standard
and reverse TSOP packages.
Revision B (January 1998)
Global
DC Characteristics
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Moved the VCCmax test condition for ICC specifications
to notes.
The online version has slightly modified formatting.
Revision C (January 1999)
Revision B+1 (January 1998)
Global
Reset Command
Updated for CS39S process technology.
Deleted paragraph referring to RESET# waveforms.
Distinctive Characteristics
AC Characteristics—Read-only Operations
Added:
Deleted note referring to output driver disable time.
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
Figure 16—Temporary Sector Group Unprotect
Timings
Ordering Information
Corrected title to indicate “sector group.”
Valid Combinations: Eliminated the extended tempera-
ture range option for Am29F017B-70.
Revision B+2 (April 1998)
DC Characteristics—CMOS Compatible
Global
ICC3, ICC4: Added Note 5, “For CMOS mode only ICC3
ICC4 = 20 µA at extended temperature (>+85°C)”.
,
Added -70 speed option, deleted -75 speed option.
Distinctive Characteristics
Revision C+1 (March 23, 1999)
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
Operating Ranges
Ordering Information
The temperature ranges are now specified as ambient.
Added extended temperature availability.
Revision C+2 (May 17, 1999)
Operating Ranges
Product Seletor Guide
Added extended temperature range.
Corrected the tOE specification for the 150 ns speed
option to 55 ns.
DC Characteristics, CMOS Compatible
Corrected the CE# and RESET# test conditions for
ICC3 and ICC4 to VCC ±0.5 V.
Operating Ranges
VCC Supply Voltages: Added VCC for ± 5% devices.
Changed “VCC for± all devices” to “VCC for ± 10% all
devices.”
AC Characteristics
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for tWHWH1 and tWHWH2. These
parameters are 100% tested. Corrected the note
reference for tVCS. This parameter is not 100% tested.
Revision D (November 16, 1999)
Distinctive Characteristics
Package Options: Added 40-pin TSOP.
Temporary Sector Unprotect Table
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
Added note reference for tVIDR. This parameter is not
100% tested.
Erase and Programming Performance
Deleted tGHWL and changed OE# waveform to start at
high.
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Physical Dimensions
Replaced figures with more detailed illustrations.
42
Am29F017D
The device now has the Unlock Bypass Program fea-
ture.
Revision E (May 19, 2000)
Global
The publication number of the document describing
sector protection/unprotection implementation is now
23923.
Changed part number to Am29F017D. This reflects the
new 0.23 µm process technology upon which this de-
vice will now be built.
Revision E+1 (December 5, 2000)
The Am29F016D is compatible with the previous 0.32
µm Am29F016B device, with the exception of the sec-
tor group protect and unprotect algorithms. These algo-
rithms are provided in a seperate document. Contact
AMD for more information or to request a copy of that
document.
Added table of contents. Removed Preliminary status
from the document.
Revision E+2 (March 23, 2001)
Common Flash Memory Interface (CFI)
Added section.
The data sheet will be marked preliminary until the de-
vice has been in full production for a number of months.
Table 9, Am29F017D Command Definitions
The -75 speed option (70 ns, ±5% VCC) has been re-
placed by a -70 speed option (70 ns, ±10 VCC).
Added Note 9 and CFI Query command to table.
The burn-in option is no longer available.
Trademarks
Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F017D
43
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