AM29LV004B-70RFC [SPANSION]
Flash, 512KX8, 70ns, PDSO40, PLASTIC, TSOP-40;
| 型号： | AM29LV004B-70RFC |
| 厂家： | 
SPANSION |
| 描述： | Flash, 512KX8, 70ns, PDSO40, PLASTIC, TSOP-40 光电二极管 |
| 文件： | 总36页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am29LV004
4 Megabit (512 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Top or bottom boot block configurations
available
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
■ Embedded Algorithms
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
■ High performance
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Full voltage range: access times as fast as 100
ns
■ Typical 1,000,000 write cycles per sector
— Regulated voltage range: access times as fast
as 90 ns
(100,000 cycles minimum guaranteed)
■ Package option
■ Ultra low power consumption (typical values at
— 40-pin TSOP
5 MHz)
■ Compatibility with JEDEC standards
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
— 20 mA program/erase current
■ Data# Polling and toggle bits
■ Flexible sector architecture
— Provides a software method of detecting
program or erase operation completion
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors
■ Ready/Busy# pin (RY/BY#)
— Supports full chip erase
— Provides a hardware method of detecting
program or erase cycle completion
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
Sectors can be locked via programming
equipment
■ Hardware reset pin (RESET#)
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Hardware method to reset the device to reading
array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20510 Rev: D Amendment/+1
Issue Date: March 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV004 is an 4 Mbit, 3.0 volt-only Flash
memory organized as 524,288 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
a single, 3.0 volt V supply to perform read, program,
CC
and erase operations. A standard EPROM pro-
grammer can also be used to program and erase the
device.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 90, 100,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
V
detector that automatically inhibits write opera-
CC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an internal algorithm that automatically prepro-
grams the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
2
Am29LV004
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV004
Regulated Voltage Range: V =3.0–3.6 V
-90R
CC
Speed Options
Full Voltage Range: V = 2.7–3.6 V
-100
-120
120
120
40
-150
150
150
55
CC
Max access time, ns (t
)
90
90
40
100
100
40
ACC
Max CE# access time, ns (t
Max OE# access time, ns (t
)
CE
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A18
21522A-1
Am29LV004
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A17
VSS
NC
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A8
WE#
RESET#
NC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
Standard TSOP
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
A17
VSS
NC
NC
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
A8
9
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
10
11
12
13
14
15
16
17
18
19
20
Reverse TSOP
CE#
VSS
CE#
A0
A2
A1
21522A-2
4
Am29LV004
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ7 = 8 data inputs/outputs
A0–A18
8
CE#
=
=
=
=
=
=
Chip enable
DQ0–DQ7
OE#
Output enable
WE#
Write enable
CE#
OE#
RESET#
RY/BY#
Hardware reset pin, active low
Ready/Busy# output
WE#
RESET#
V
3.0 volt-only single power supply
CC
(see Product Selector Guide for speed
options and voltage supply tolerances)
RY/BY#
V
=
=
Device ground
SS
NC
Pin not connected internally
21522A-3
Am29LV004
5
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV004
T
-90R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E
=
40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F
=
40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV004
4 Megabit (512 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Valid Combinations
Am29LV004T-70R,
Am29LV004B-70R
EC, EI, FC, FI
Am29LV004T-80,
Am29LV004B-80
Am29LV004T-90,
Am29LV004B-90
EC, EI, EE, FC, FI, FE
Am29LV004T-120,
Am29LV004B-120
6
Am29LV004
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV004 Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses (See Note)
DQ0–DQ7
Read
Write
H
H
A
A
D
OUT
IN
IN
L
H
L
D
IN
V
0.3 V
±
V
0.3 V
±
CC
CC
Standby
X
X
X
High-Z
Output Disable
Reset
L
X
X
H
X
X
H
X
X
H
L
X
X
High-Z
High-Z
Temporary Sector Unprotect
V
A
D
IN
ID
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D
= Data Out
IL
IH
ID
IN
IN
OUT
Note: Addresses are A18–A0.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad-
dress” consists of the address bits required to uniquely
select a sector. The “Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V .
IH
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The
device remains enabled for read access until the com-
mand register contents are altered.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
in the DC Characteristics table represents the ac-
CC2
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing diagram. I
the DC Characteristics table represents the active cur-
rent specification for reading array data.
in
CC1
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
Writing Commands/Command Sequences
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V , and OE# to V .
IL
IH
Am29LV004
7
P R E L I M I N A R Y
SET# pin is driven low for at least a period of t , the
device immediately terminates any operation in
Standby Mode
RP
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V ± 0.3 V.
CC
(Note that this is a more restricted voltage range than
Current is reduced for the duration of the RESET#
V .) If CE# and RESET# are held at V , but not within
IH
IH
pulse. When RESET# is held at V ±0.3 V, the device
SS
V
± 0.3 V, the device will be in the standby mode, but
CC
draws CMOS standby current (I
). If RESET# is held
CC4
the standby current will be greater. The device requires
at V but not within V ±0.3 V, the standby current will
IL
SS
standard access time (t ) for read access when the
CE
be greater.
device is in either of these standby modes, before it is
ready to read data.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
In the DC Characteristics tables, I
sents the standby current specification.
and I
repre-
CC4
CC3
time of t
(during Embedded Algorithms). The
READY
Automatic Sleep Mode
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
+ 30 ns. The automatic sleep mode is indepen-
completed within a time of t
(not during Embed-
ACC
READY
dent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
ded Algorithms). The system can read data t
after
RH
the RESET# pin returns to V .
IH
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 13 for the timing diagram.
data is latched and always available to the system. I
CC5
in the DC Characteristics table represents the auto-
matic sleep mode current specification.
Output Disable Mode
RESET#: Hardware Reset Pin
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high imped-
ance state.
IH
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
8
Am29LV004
P R E L I M I N A R Y
Table 2. Am29LV004T Top Boot Block Sector Address Table
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A18
0
A17
A16
A15
X
X
X
X
X
X
X
0
A14
A13
(Kbytes)
0
0
X
X
64
64
64
64
64
64
64
32
8
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-77FFFh
78000h-79FFFh
7A000h-7BFFFh
7C000h-7FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
1
1
1
1
0
0
1
1
1
1
0
1
8
1
1
1
1
1
X
16
Table 3. Am29LV004B Bottom Boot Block Sector Address Table
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
A18
0
A17
A16
A15
A14
A13
(Kbytes)
0
0
0
0
X
16
8
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
0
0
0
0
1
0
0
0
0
0
1
1
8
0
0
0
1
X
X
32
64
64
64
64
64
64
64
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
tor address must appear on the appropriate highest
order address bits (see Tables 2 and 3). Table 4 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding iden-
tifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
When using programming equipment, the autoselect
mode requires V (11.5 V to 12.5 V) on address pin A9.
does not require V . See “Command Definitions” for
ID
ID
Address pins A6, A1, and A0 must be as shown in Table
4. In addition, when verifying sector protection, the sec-
details on using the autoselect mode.
Am29LV004
9
P R E L I M I N A R Y
Table 4. Am29LV004 Autoselect Codes (High Voltage Method)
A18 A12
to to
CE# OE# WE# A13 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
A6
A1
A0
Manufacturer ID: AMD
L
L
L
L
H
H
X
X
X
X
V
V
X
X
L
X
X
L
L
01h
B5h
ID
ID
Device ID: Am29LV004T
(Top Boot Block)
L
L
L
L
H
H
Device ID: Am29LV004B
(Bottom Boot Block)
L
L
L
L
H
H
X
X
X
V
X
X
X
X
B6h
ID
ID
01h
(protected)
Sector Protection Verification
SA
V
L
H
L
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 19 shows the timing diagrams, for this feature.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
START
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
RESET# = V
(Note 1)
ID
Perform Erase or
Program Operations
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Sector protection/unprotection must be implemented
using programming equipment.The procedure requires
RESET# = V
IH
a high voltage (V ) on address pin A9 and OE#. De-
ID
tails on this method are provided in a supplement, pub-
lication number 20874. Contact an AMD representative
to request a copy.
Temporary Sector
Unprotect Completed
(Note 2)
21522A-4
Temporary Sector Unprotect
Notes:
1. All protected sectors unprotected.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
2. All previously protected sectors are protected once
again.
SET# pin to V . During this mode, formerly protected
ID
sectors can be programmed or erased by selecting the
Figure 1. Temporary Sector Unprotect Operation
sector addresses. Once V is removed from the RE-
ID
10
Am29LV004
P R E L I M I N A R Y
Write Pulse “Glitch” Protection
Hardware Data Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a
logical one.
spurious system level signals during V
power-up
CC
and power-down transitions, or from system noise.
Power-Up Write Inhibit
Low V Write Inhibit
CC
If WE# = CE# = V and OE# = V during power up, the
IL
IH
When V
is less than V
, the device does not ac-
LKO
CC
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
CC
device resets. Subsequent writes are ignored until V
CC
is greater than V
. The system must provide the
LKO
proper signals to the control pins to prevent uninten-
tional writes when V is greater than V
.
CC
LKO
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
Am29LV004
11
P R E L I M I N A R Y
Programming is allowed in any sequence and across
Autoselect Command Sequence
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and requires
V
on address bit A9.
ID
Figure 2 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 14 for
timing diagrams.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Tables 2
and 3 for valid sector addresses.
START
Write Program
Command Sequence
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Data Poll
from System
Byte Program Command Sequence
Embedded
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. Table 5 shows the address and
data requirements for the byte program command se-
quence.
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Programming
Completed
21522A-4
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Note: See Table 5 for program command sequence.
Figure 2. Program Operation
12
Am29LV004
P R E L I M I N A R Y
that processor interrupts be disabled during this time to
Chip Erase Command Sequence
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the ris-
ing edge of the final WE# pulse in the command se-
quence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for informa-
tion on these status bits.)
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 15 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. Table 5 shows the address and data re-
quirements for the sector erase command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
Am29LV004
13
P R E L I M I N A R Y
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
START
Write Erase
Command Sequence
Data Poll
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
Yes
Erasure Completed
21522A-5
Notes:
1. See Table 5 for erase command sequence.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3. Erase Operation
14
Am29LV004
P R E L I M I N A R Y
Table 5. Am29LV004 Command Definitions
Bus Cycles (Notes 2-4)
Third Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
Sequence
(Note 1)
First
Second
Fifth
Sixth
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
4
4
RA
XXX
555
555
555
RD
F0
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
90
90
90
X00
X01
X01
01
B5
B6
00
Device ID, Top Boot Block
Auto-
select
(Note 7)
Device ID, Bottom Boot Block
Sector Protect Verify
(Note 8)
(SA)
X02
4
555
AA
2AA
55
555
90
01
Program
4
6
6
1
1
555
555
555
XXX
XXX
AA
AA
AA
B0
30
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
PA
555
555
PD
AA
AA
Chip Erase
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 9)
Erase Resume (Note 10)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
2. All values are in hexadecimal.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
3. Except when reading array or autoselect data, all
commandbus cycles are write operations.
4. Address bits A18–A11 are don’t cares for unlock and
command cycles.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29LV004
15
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 6 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 16, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
21522A-6
Figure 4. Data# Polling Algorithm
16
Am29LV004
P R E L I M I N A R Y
Table 6 shows the outputs for Toggle Bit I on DQ6.
RY/BY#: Ready/Busy#
Refer to Figure 5 for the toggle bit algorithm, and to Fig-
ure 17 in the “AC Characteristics” section for the toggle
bit timing diagrams. Figure 18 shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
DQ2: Toggle Bit II
pull-up resistor to V
.
CC
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 12, 13,
14 and 15 shows RY/BY# for read, reset, program, and
erase operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Figure 17 shows the toggle bit timing diagram. Figure
18 shows the differences between DQ2 and DQ6 in
graphical form.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Am29LV004
17
P R E L I M I N A R Y
The remaining scenario is that the system initially de-
DQ5: Exceeded Timing Limits
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
START
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
Read DQ7–DQ0
(Note 1)
DQ3: Sector Erase Timer
Read DQ7–DQ0
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0”
to “1.” The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50 µs. See
also the “Sector Erase Command Sequence” section.
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
21522A-7
Figure 5. Toggle Bit Algorithm
18
Am29LV004
P R E L I M I N A R Y
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29LV004
19
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
V
(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
A9, OE#,
and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V
20 ns
All other pins
(Note 1). . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3) . . . . . . 200 mA
21522A-8
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
Figure 6. Maximum Negative Overshoot
Waveform
voltage transitions, input or I/O pins may undershoot V
SS
to –2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is V +0.5 V.
CC
During voltage transitions, input or I/O pins may overshoot
to V +2.0 V for periods up to 20 ns. See Figure 7.
CC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
20 ns
RESET# may undershoot V to –2.0 V for periods of up
V
SS
CC
+2.0 V
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
V
CC
+0.5 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
2.0 V
20 ns
20 ns
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
21522A-9
Figure 7. Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C
A
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C
A
Extended (E) Devices
Ambient Temperature (T ) . . . . . . . . –55°C to +125°C
A
V
V
V
Supply Voltages
CC
CC
CC
for regulated voltage range. . . . . . .3.0 V to 3.6 V
for full voltage range. . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20
Am29LV004
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
CC
,
OUT
SS
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
10
2
16
4
V
Active Read Current
CC
I
CE# = V OE#
V
V
mA
CC1
IL,
=
=
IH
(Note 1)
V
Active Write Current
CC
I
I
I
I
CE# = V OE#
20
0.2
0.2
0.2
30
5
mA
µA
µA
µA
CC2
CC3
CC4
CC5
IL,
IH
(Notes 2 and 4)
V
= V
;
CC
CC max
V
V
Standby Current
CC
CE#, RESET# = V ±0.3 V
CC
V
= V
;
CC
CC max
Standby Current During Reset
5
CC
RESET# = V ± 0.3 V
SS
V
V
= V ± 0.3 V;
CC
IH
IL
Automatic Sleep Mode (Note 3)
5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
0.85 V
OH1
OH2
CC
CC min
CC min
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage (Note
4)
CC
V
2.3
2.5
V
LKO
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IH
CC
2.
I
active while Embedded Erase or Embedded Program is in progress.
CC
3. Automatic sleep mode enables the low power mode when addresses remain stable for t
4. Not 100% tested.
+ 30 ns.
ACC
Am29LV004
21
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
21522A-10
Figure 8.
I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
15
10
5
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
21522A-11
Figure 9. Typical I
vs. Frequency
CC1
22
Am29LV004
P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
3.3 V
-90R,
-100
-120,
-150
Test Condition
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
21522A-12
Figure 10. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
21522A-13
Figure 11. Input Waveforms and Measurement Levels
Am29LV004
23
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
Min
-90R -100 -120 -150 Unit
t
t
Read Cycle Time (Note 1)
Address to Output Delay
90
90
100
100
120
120
150
150
ns
ns
AVAV
RC
CE# = V
IL
t
t
Max
AVQV
ACC
OE# = V
IL
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
90
40
30
30
100
40
120
50
150
55
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
40
DF
DF
t
t
30
30
40
Read
0
Output Enable
t
OEH
Toggle and
Data# Polling
Hold Time (Note 1)
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
0
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 10 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
21522A-14
Figure 12. Read Operations Timings
24
Am29LV004
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
t
20
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
Max
500
ns
READY
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21522A-15
Figure 13. RESET# Timings
Am29LV004
25
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std
Description
-90R
-100
-120
-150
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
90
100
120
150
AVAV
WC
t
t
0
ns
AVWL
WLAX
AS
AH
DS
DH
t
t
50
50
50
50
50
50
65
65
ns
t
t
t
ns
DVWH
WHDX
t
Data Hold Time
0
0
ns
t
Output Enable Setup Time
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
Min
0
ns
GHWL
GHWL
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
Min
Min
0
0
ns
ns
ns
ns
µs
sec
µs
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
t
CE# Hold Time
t
Write Pulse Width
50
30
50
30
50
30
65
35
t
t
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
WPH
t
t
9
WHWH1
WHWH2
WHWH1
WHWH2
t
t
t
V
Setup Time (Note 1)
CC
50
0
VCS
t
Recovery Time from RY/BY#
RB
t
Program/Erase Valid to RY/BY# Delay
90
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
26
Am29LV004
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
21522A-16
Figure 14. Program Operation Timings
Am29LV004
27
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
21522A-17
Figure 15. Chip/Sector Erase Operation Timings
28
Am29LV004
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
Valid Data
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21522A-18
Figure 16. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21522A-19
Figure 17. Toggle Bit Timings (During Embedded Algorithms)
Am29LV004
29
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
21522A-20
Figure 18. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
Rise and Fall Time (See Note)
ID
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21522A-21
Figure 19. Temporary Sector Unprotect Timing Diagram
30
Am29LV004
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std
Description
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Unit
ns
t
t
t
Min
Min
Min
Min
Min
Min
90
100
120
150
AVAV
AVEL
ELAX
WC
t
0
ns
AS
AH
DS
DH
t
t
50
50
50
50
50
50
65
65
ns
t
t
t
Data Setup Time
ns
DVEH
EHDX
t
Data Hold Time
0
0
ns
t
Output Enable Setup Time
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WS
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
50
30
50
30
50
30
65
35
ns
ELEH
EHEL
CP
t
t
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
ns
CPH
t
t
9
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
t
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29LV004
31
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, D
to the device.
is the data written
21522A-22
OUT
2. Figure indicates the last two bus cycles of the command sequence.
Figure 20. Alternate CE# Controlled Write Operation Timings
32
Am29LV004
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
Byte Programming Time
1
11
9
15
Excludes 00h programming
prior to erasure (Note 4)
s
300
µs
Excludes system level
overhead (Note 5)
Chip Programming Time
(Note 3)
4.5
13.5
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 100,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V, 100,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
SS
CC
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
OUT
8.5
7.5
pF
OUT
C
V
= 0
9
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
Am29LV004
33
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
40
9.90
10.10
0.50 BSC
21
20
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
1.20
MAX
0.10
0.21
0˚
5˚
0.50
0.70
16-038-TSOP-1_AE
TS 040
2-27-97 lv
* For reference only. BSC is an ANSI standard for Basic Space Centering.
34
Am29LV004
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
TSR048—48-Pin Reverse TSOP (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
40
9.90
10.10
0.50 BSC
21
20
0.05
0.15
18.30
18.50
19.80
20.20
0.08
0.20
1.20
MAX
0.10
0.21
0˚
5˚
0.50
0.70
16-038-TSOP-1_AE
TSR040
2-27-97 lv
Am29LV004
35
P R E L I M I N A R Y
REVISION SUMMARY
Global
ence for t
and t
. These parameters are
WHWH2
WHWH1
100% tested. Corrected the note reference for t
This parameter is not 100% tested.
.
VCS
Revised formatting to be consistent with other current
3.0 volt-only data sheets.
Temporary Sector Unprotect Table
Revision D+1
Added note reference for t
100% tested.
. This parameter is not
VIDR
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the notes refer-
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
36
Am29LV004
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