AM29LV033C-90WDE [SPANSION]
Flash, 4MX8, 90ns, PBGA63, 8 X 14 MM, 0.80 MM PITCH, FBGA-63;型号: | AM29LV033C-90WDE |
厂家: | SPANSION |
描述: | Flash, 4MX8, 90ns, PBGA63, 8 X 14 MM, 0.80 MM PITCH, FBGA-63 内存集成电路 |
文件: | 总49页 (文件大小:1009K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV033C
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29AL032D supersedes Am29LV033C and is the factory-recommended migration path. Please refer
to the S29AL032D datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22268 Revision B Amendment +5 Issue Date September 12, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV033C
32 Megabit (4 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29AL032D supersedes Am29LV033C and is the factory-recommended migration path.
Please refer to the S29AL032D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
SOFTWARE FEATURES
■ Zero Power Operation
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
— Suspends erase operations to allow programming
in same bank
■ Package options
— 63-ball FBGA
— 40-pin TSOP
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status
of program or erase cycles
■ Compatible with JEDEC standards
■ Unlock Bypass Program command
— Pinout and software compatible with
single-power-supply flash standard
— Reduces overall programming time when issuing
multiple program command sequences
■ Single power supply operation
HARDWARE FEATURES
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
— Hardware method for detecting program or erase
cycle completion
■ Hardware reset pin (RESET#)
■ Flexible sector architecture
— Hardware method of resetting the internal state
machine to the read mode
— Sixty-four 64 Kbyte sectors
■ Manufactured on 0.32 µm process technology
■ ACC input pin
PERFORMANCE CHARACTERISTICS
■ High performance
— Acceleration (ACC) function provides accelerated
program times
— Access times as fast as 70 ns
■ Sector protection
— Program time: 7 µs/byte typical utilizing Accelerate
function
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— Temporary Sector Unprotect allows changing data
in protected sectors in-system
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■ Command sequence optimized for mass storage
■ Minimum 1 million write cycles guaranteed
— Specific addresses not required for unlock cycles
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22268 Rev: B Amendment/5
Issue Date: September 12, 2006
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV033C is a 32 Mbit, 3.0 Volt-only Flash
memory organized as 4,194,304 bytes. The device is
offered in 63-ball FBGA and 40-pin TSOP packages.
The byte-wide (x8) data appears on DQ7–DQ0. All
read, program, and erase operations are accomplished
using only a single power supply. The device can also
be programmed in standard EPROM programmers.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle is
completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This is achieved in-system or via programming
equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read the boot-up firmware from the Flash
memory.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The device offers two power-saving features. When
addresses are stable for a specified amount of time,
the device enters the automatic sleep mode. The
system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
TABLE OF CONTENTS
Continuity of Specifications ....................................1
For More Information ..............................................1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Standard Products ................................................10
Table 1. Am29LV033C Device Bus Operations ..........11
Requirements for Reading Array Data .................11
Writing Commands/Command Sequences ..........11
Accelerated Program Operation ...........................12
Program and Erase Operation Status ..................12
Standby Mode ......................................................12
Automatic Sleep Mode .........................................12
RESET#: Hardware Reset Pin .............................12
Output Disable Mode ............................................13
Table 2. Am29LV033C Sector Address Table ............13
Autoselect Mode ...................................................15
Table 3. Am29LV033C Autoselect Codes
DQ7: Data# Polling ............................................... 26
Figure 5. Data# Polling Algorithm................................ 26
RY/BY#: Ready/Busy# ......................................... 27
DQ6: Toggle Bit I .................................................. 27
DQ2: Toggle Bit II ................................................. 27
Reading Toggle Bits DQ6/DQ2 ............................ 27
DQ5: Exceeded Timing Limits .............................. 28
DQ3: Sector Erase Timer ..................................... 28
Figure 6. Toggle Bit Algorithm..................................... 28
Table 10. Write Operation Status ................................29
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
CMOS Compatible ............................................... 31
Zero Power Flash ................................................. 32
Figure 9. ICC1 Current vs. Time (Showing Active
and Automatic Sleep Currents) ................................... 32
Figure 10. Typical ICC1 vs. Frequency ......................... 32
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Test Setup.................................................. 33
Table 11. Test Specifications ......................................33
Figure 12. Input Waveforms and
Measurement Levels................................................... 33
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Read Operations .................................................. 34
Figure 13. Read Operations Timings .......................... 34
Hardware Reset (RESET#) .................................. 35
Figure 14. RESET# Timings........................................ 35
Erase/Program Operations ................................... 36
Figure 15. Program Operation Timings....................... 37
Figure 16. Accelerated Program Timing Diagram....... 37
Figure 17. Chip/Sector Erase Operation Timings........ 38
Figure 18. Data# Polling Timings (During
(High Voltage Method) ................................................15
Sector/Sector Block Protection and Unprotection 15
Table 4. Sector Block Addresses for
Protection/Unprotection ...............................................16
Figure 1. Temporary Sector Unprotect Operation....... 16
Figure 2. In-System Sector Protect/
Unprotect Algorithms................................................... 17
Hardware Data Protection ....................................18
Low VCC Write Inhibit ............................................18
Write Pulse “Glitch” Protection .............................18
Logical Inhibit .......................................................18
Power-Up Write Inhibit .........................................18
Table 5. CFI Query Identification String ......................18
Table 6. System Interface String .................................19
Table 7. Device Geometry Definition ..........................19
Table 8. Primary Vendor-Specific Extended Query ....20
Reading Array Data ..............................................21
Reset Command ..................................................21
Autoselect Command Sequence ..........................21
Byte Program Command Sequence .....................21
Unlock Bypass Command Sequence ...................22
Accelerated Program Operations .........................22
Figure 3. Program Operation ...................................... 22
Chip Erase Command Sequence .........................22
Sector Erase Command Sequence ......................23
Erase Suspend/Erase Resume Commands .........23
Figure 4. Erase Operation........................................... 24
Table 9. Am29LV033C Command Definitions ...........25
Embedded Algorithms)................................................ 39
Figure 19. Toggle Bit Timings (During
Embedded Algorithms)................................................ 39
Figure 20. DQ2 vs. DQ6.............................................. 39
Figure 21. Temporary Sector/Sector
Block Unprotect Timing Diagram................................. 40
Figure 22. Sector Protect/Unprotect
Timing Diagram........................................................... 41
Figure 23. Alternate CE# Controlled Write
Operation Timings....................................................... 43
Erase and Programming Performance . . . . . . . 44
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45
TS 040—40-Pin Standard TSOP ......................... 45
TSR040—40-Pin Reverse TSOP ........................ 46
FBD063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 14 mm ............................................... 47
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 48
22268B5 September 12, 2006
Am29LV033C
3
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV033C
Speed Option
Full Voltage Range: VCC = 2.7–3.6 V
-70
70
70
30
-90
90
90
40
-120
120
120
50
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
Command
Register
ACC
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A21
4
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
CONNECTION DIAGRAMS
A17
VSS
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
5
6
7
A8
8
WE#
RESET#
ACC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
40-Pin Standard TSOP
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
A17
VSS
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A21
DQ3
DQ2
DQ1
DQ0
A8
9
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
10
11
12
13
14
15
16
17
18
19
20
40-Pin Reverse TSOP
OE#
VSS
A2
A1
CE#
A0
22268B5 September 12, 2006
Am29LV033C
5
D A T A S H E E T
CONNECTION DIAGRAMS
63-Ball FBGA (Top View, Balls Down)
L8
M8
A8
B8
NC*
NC*
NC*
NC*
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
A7
B7
A14
A13
A15
A16
A17
NC
A20
V
SS
NC*
NC*
NC*
NC*
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A11
A12
A19
A10
DQ6
DQ7
C5
D5
E5
F5
G5
H5
J5
K5
WE# RESET#
NC
NC
DQ5
NC
V
DQ4
CC
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY# ACC
NC
NC
DQ2
DQ3
V
A21
CC
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A18
DQ0
NC
NC
DQ1
A2
L2
M2
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
NC*
CE#
OE#
V
NC*
NC*
SS
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory
products in FBGA packages.
6
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
PIN CONFIGURATION
LOGIC SYMBOL
A0–A21
=
22 addresses
22
DQ0–DQ7 = 8 data inputs/outputs
A0–A21
8
CE#
=
=
=
=
=
=
=
Chip enable
DQ0–DQ7
OE#
Output enable
WE#
Write enable
CE#
OE#
RESET#
RY/BY#
ACC
Hardware reset pin, active low
Ready/Busy output
Hardware Acceleration Pin
WE#
RESET#
ACC
RY/BY#
VCC
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
NC
=
=
Device ground
Pin not connected internally
22268B5 September 12, 2006
Am29LV033C
7
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV033C
-70
E
C
TEMPERATURE RANGE
I
=
=
=
=
Industrial (–40°C to + 85°C)
E
F
K
Extended (–55°C to + 125°C)
Industrial (-40oC to + 85oC) with Pb-free Package
Extended (-55oC to + 125oC) with Pb-free Package
PACKAGE TYPE
E
=
=
=
40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F
40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
WD
63-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 14 mm package (FBD063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29LV033C
32 Megabit (4 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations for TSOP Packages
Valid Combinations for FBGA Packages
Order Number Package Marking
AM29LV033C-70
EI, FI, EF, FF
AM29LV033C-90
AM29LV033C-120
WDI,
WDF
EI, EE, EF, EK
FI, FE, FF, FK
AM29LV033C-70
L033C70V
I, F
AM29LV033C-90
AM29LV033C-120
WDI, L033C90V
WDE,
I, E, F,
K
Valid Combinations
WDF,
L033C12V
WDK
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
8
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29LV033C Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses
DQ0–DQ7
DOUT
Read
H
H
AIN
AIN
Write (Note 1)
Standby
L
H
L
DIN
VCC
0.3 V
±
VCC ±
0.3 V
X
X
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
X
Sector/Sector Block Protect
(Note 2)
Sector Addresses,
A6 = L, A1 = H, A0 = L
L
L
X
H
H
X
L
L
X
VID
VID
VID
DIN, DOUT
DIN, DOUT
DIN
Sector/Sector Block Unprotect
(Note 2)
Sector Addresses
A6 = H, A1 = H, A0 = L
Temporary Sector/Sector Block
Unprotect
AIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See “Accelerated Program Operations” on
page 22 for more information.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” on page 15 section.
ing specifications and to Figure 13, on page 34 for the
Requirements for Reading Array Data
timing diagram. ICC1 in the DC Characteristics table
To read array data from the outputs, the system must
represents the active current specification for reading
drive the CE# and OE# pins to VIL. CE# is the power
array data.
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
The internal state machine is set for reading array data
cludes programming data to the device and erasing
upon device power-up, or after a hardware reset. This
sectors of memory), the system must drive WE# and
ensures that no spurious alteration of the memory
CE# to VIL, and OE# to VIH.
content occurs during the power transition. No com-
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” on page 21 section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” on page 21 for more infor-
mation. Refer to the AC Read Operations table for tim-
22268B5 September 12, 2006
Am29LV033C
9
D A T A S H E E T
An erase operation can erase one sector, multiple sec-
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (tCE) for read access when the de-
vice is in either of these standby modes, before it is
ready to read data.
tors, or the entire device. Table 2, on page 13 indi-
cates the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. The “Command Defini-
tions” section contains details for erasing a sector or
the entire chip, or suspending/resuming the erase op-
eration.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” on page 15
and “Autoselect Command Sequence” on page 21
sections for more information.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” on page 34 section contains timing
specification tables and timing diagrams for write oper-
ations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tAC C + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current
specification.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the ACC pin. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system then
uses a two-cycle program command sequence as re-
quired by the Unlock Bypass mode. Removing VHH
from the ACC pin returns the device to normal opera-
tion. Note that the ACC pin must not be at VHH for op-
erations other than accelerated programming, or
device damage may result.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Program and Erase Operation Status
During an erase or program operation, the system
checks the status of the operation by reading the sta-
tus bits on DQ7–DQ0. Standard read cycle timings
and ICC read specifications apply. Refer to “Write Op-
eration Status” on page 26 for more information, and
to “AC Characteristics” on page 34 for timing dia-
grams.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current is
greater.
Standby Mode
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would also reset the Flash mem-
ory, enabling the system to read the boot-up firmware
from the Flash memory.
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
10
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
time of tREADY (during Embedded Algorithms). The sys-
Refer to the “AC Characteristics” on page 34 tables for
RESET# parameters and to Figure 14, on page 35 for
the timing diagram.
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high im-
pedance state.
Table 2. Am29LV033C Sector Address Table (Sheet 1 of 2)
Address Range
(in hexadecimal)
Sector
SA0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
22268B5 September 12, 2006
Am29LV033C
11
D A T A S H E E T
Table 2. Am29LV033C Sector Address Table (Sheet 2 of 2)
Address Range
Sector
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
A21
1
A20
0
A19
0
A18
0
A17
1
A16
0
(in hexadecimal)
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
Note: All sectors are 64 Kbytes in size.
12
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
ing address bits that are don’t care. When all neces-
Autoselect Mode
sary bits are set as required, the programming
equipment may then read the corresponding identifier
code on DQ7-DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9, on page 25.
This method does not require VID. See “Writing spe-
cific address and data commands or sequences into
the command register initiates device operations.
Table 9, on page 25 defines the valid register com-
mand sequences. Writing incorrect address and data
values or writing them in the improper sequence re-
sets the device to reading array data.” for details on
using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits. Table 3 shows the remain-
Table 3. Am29LV033C Autoselect Codes (High Voltage Method)
A21 A15
to to
OE# WE# A16 A10
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29LV033C
CE#
L
A9
VID
VID
A6
L
A1
L
A0
L
L
L
H
H
X
X
X
X
X
X
X
X
01h
A3h
L
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
cessor bus cycle timing. For sector unprotect, all un-
protected sectors must first be protected prior to the
first sector unprotect write cycle.
Sector/Sector Block Protection and
Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table 4,
on page 16).
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices.
Publication number 22269 contains further details;
contact an AMD representative to request a copy.
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2, on page 17 shows
the algorithms and Figure 22, on page 41 shows the
timing diagram. This method uses standard micropro-
It is possible to determine whether a sector is pro-
tected or unprotected. See “Autoselect Mode” on
page 15 for details.
22268B5 September 12, 2006
Am29LV033C
13
D A T A S H E E T
Table 4. Sector Block Addresses for
Protection/Unprotection
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see
Table 4, on page 16).
Sector/
Sector/
Sector Block
A21–A16
Sector Block Size
SA0
000000
64 Kbytes
000001,000010,
000011
SA1-SA3
192 (3x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1, on page 16 shows the algo-
rithm, and Figure 21, on page 40 shows the timing dia-
grams, for this feature.
000100, 000101,
000110, 000111
SA4-SA7
001000, 001001,
001010, 001011
SA8-SA11
001100, 001101,
001110, 001111
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
010000, 010001,
010010, 010011
010100, 010101,
010110, 010111
011000, 011001,
011010, 011011
011100, 011101,
011110, 011111
START
100000, 100001,
100010, 100011
100100, 100101,
100110, 100111
RESET# = VID
(Note 1)
101000, 101001,
101010, 101011
101100, 101101,
101110, 101111
Perform Erase or
Program Operations
110000, 110001,
110010, 110011
RESET# = VIH
110100, 110101,
110110, 110111
111000, 111001,
111010, 111011
Temporary Sector
Unprotect Completed
(Note 2)
111100, 111101,
111110
SA60-SA62
SA63
192 (4x64) Kbytes
64 Kbytes
111111
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
14
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/
Unprotect Algorithms
22268B5 September 12, 2006
Am29LV033C
15
D A T A S H E E T
vide the proper signals to the control pins to prevent
Hardware Data Protection
unintentional writes when VCC is greater than VLKO
.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9, on
page 25 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent ac-
cidental erasure or programming, which might
otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or
from system noise.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must pro-
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
page 20. To terminate reading CFI data, the system
must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 5 to Table 8,
on page 20. The system must write the reset com-
mand to return the device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represen-
tative for copies of these documents.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables Table 5, on page 18 to Table 8, on
Table 5. CFI Query Identification String
Description
Addresses
Data
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
Primary OEM Command Set
13h
14h
02h
00h
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
00h
00h
16
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
Table 6. System Interface String
Addresses
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
27h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
00h
00h
04h
00h
0Ah
00h
05h
00h
04h
00h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition
Addresses
Data
Description
27h
16h
Device Size = 2N byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
3Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
00h
00h
00h
00h
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
22268B5 September 12, 2006
Am29LV033C
17
D A T A S H E E T
Table 8. Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
44h
31h
30h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
01h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
47h
48h
01h
04h
Sector Temporary Unprotect: 04 = Supported
Sector Protect/Unprotect scheme
49h
04h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
4Bh
20h
00h
Simultaneous Operation: 20 = Not Supported
Burst Mode Type: 00 = Not Supported, 01 = Supported
Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
4Ch
00h
18
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 9, on page 25 defines the valid register
command sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading array data.
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in “AC
Characteristics” on page 34.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
Reading Array Data
The autoselect command sequence allows the host
system to access the manufacturer and devices
codes, and determine whether or not a sector is pro-
tected. Table 9, on page 25 shows the address and
data requirements. This method is an alternative to
that shown in Table 3, on page 15, which is intended
for PROM programmers and requires VID on address
bit A9.
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” on page 23 for
more information on this mode.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command se-
quence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h re-
turns the device code. A read cycle containing a sector
address (SA) and the address 02h returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
Table 4, on page 16 for valid sector addresses.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” on page 21 section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” on
page 11 in the “Device Bus Operations” section for
more information. The Read Operations table provides
the read parameters, and Figure 13, on page 34
shows the timing diagram.
Byte Program Command Sequence
The device programs one byte of data for each pro-
gram operation. The command sequence requires four
bus cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically generates the pro-
gram pulses and verifies the programmed cell margin.
Table 9, on page 25 shows the address and data re-
quirements for the byte program command sequence.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
on page 26 for information on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
22268B5 September 12, 2006
Am29LV033C
19
D A T A S H E E T
Any commands written to the device during the Em-
Figure 3 illustrates the algorithm for the program oper-
ation. See the “Erase/Program Operations” on
page 36 table in “AC Characteristics” for parameters,
and to Figure 15, on page 37 for timing diagrams.
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read shows that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
START
Write Program
Command Sequence
Data Poll
from System
Unlock Bypass Command Sequence
Embedded
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
lock cycles. This is followed by a third write cycle con-
taining the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle un-
lock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9, on page 25 shows the require-
ments for the command sequence.
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t cares for both cycles. The device then returns to
reading array data.
Note: See Table 9, on page 25 for program command se-
quence.
Figure 3. Program Operation
Chip Erase Command Sequence
Accelerated Program Operations
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9, on
page 25 shows the address and data requirements for
the chip erase command sequence.
The device offers accelerated program operations
through the ACC pin. When the system asserts VHH on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence, eliminating two cycles from the command se-
quence. In addition, the device uses the higher voltage
on the ACC pin to accelerate the operation. Note that
the ACC pin must not be at VHH during read or erase
operations, or device damage may result. If ACC is to
be permanently set, it is recommended that it be tied
to VCC to minimize current consumption.
20
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
Any commands written to the chip during the Embed-
Erase Timer” on page 28 section.) The time-out be-
gins from the rising edge of the final WE# pulse in the
command sequence.
ded Erase algorithm are ignored. Note that a hard-
ware reset during the chip erase operation
immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the de-
vice has returned to reading array data, to ensure data
integrity.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Note that a hardware reset dur-
ing the sector erase operation immediately terminates
the operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” on page 26 for information on
these status bits. When the Embedded Erase algo-
rithm is complete, the device returns to reading array
data and addresses are no longer latched.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. (Refer to “Write Operation Status”
on page 26 for information on these status bits.)
Figure 4, on page 24 illustrates the algorithm for the
erase operation. See the “Erase/Program Operations”
on page 36 for parameters, and Figure 17, on page 38
for timing diagrams.
Figure 4, on page 24 illustrates the algorithm for the
erase operation. Refer to the “Erase/Program Opera-
tions” on page 36 tables in the “AC Characteristics”
section for parameters, and to Figure 17, on page 38
for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 9, on page 25 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase al-
gorithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might
not be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. If the time between addi-
tional sector erase commands can be assumed to be
less than 50 µs, the system need not monitor DQ3.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the de-
vice to reading array data. The system must rewrite
the command sequence and any additional sector ad-
dresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” on page 26 for informa-
tion on these status bits.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out. (See the “DQ3: Sector
22268B5 September 12, 2006
Am29LV033C
21
D A T A S H E E T
After an erase-suspended program operation is com-
plete, the system can once again read array data
within non-suspended sectors. The system deter-
mines the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard pro-
gram operation. See “Write Operation Status” on
page 26 for more information.
START
Write Erase
Command Sequence
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
on page 21 for more information.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase sus-
pend mode and continue the sector erase operation.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the device has resumed erasing.
Yes
Erasure Completed
Notes:
1. See Table 9, on page 25 for erase command sequence.
2. See “DQ3: Sector Erase Timer” on page 28 for more
information.
Figure 4. Erase Operation
22
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
Table 9. Am29LV033C Command Definitions
Bus Cycles (Notes 2–4)
Command Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID (Note 8)
1
1
4
4
RA
RD
F0
XXX
XXX
XXX
XXX
AA
AA
XXX
XXX
XXX
55
55
0XXXXX
0XXXXX
90
90
0XXX00
01
Device ID (Note 8)
0XXX01 A3
0XXXXX
or
2XXXXX
00
Sector Protect Verify
(Note 9)
SA
X02
4
AA
55
90
XXX
XXX
01
Byte Program
4
3
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
XXX
A0
20
PA
PD
Unlock Bypass
Unlock Bypass Program
(Note 10)
2
2
XXX
XXX
A0
90
PA
PD
00
Unlock Bypass Reset
(Note 11)
XXX
Chip Erase
6
6
1
1
1
XXX
XXX
XXX
XXX
XXX
AA
AA
B0
30
XXX
XXX
55
55
XXX
XXX
80
80
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
SA
10
30
Sector Erase
Erase Suspend (Note 12)
Erase Resume (Note 13)
CFI Query (Note 14)
98
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data is latched on
the rising edge of WE# or CE# pulse.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased or verified. Address bits
A21–A16 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Ad-
dresses are latched on the falling edge of the WE# or CE#
pulse.
Notes:
8. In the third and fourth cycles of the command sequence, set
A21 to 0.
1. See Table 1, on page 11 for descriptions of bus operations.
9. In the third cycle of the command sequence, address bit A21
must be set to 0 if verifying sectors 0–31, or to 1 if verifying
sectors 32–64. The data in the fourth cycle is 00h for an
unprotected sector/sector block and 01h for a protected
sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the Unlock Bypass
mode.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits are don’t care for unlock and command cycles,
except when PA or SA is required.
5. No unlock or command cycles required when device is in read
mode.
6. The Reset command is required to return to the read mode
when the device is in the autoselect mode or if DQ5 goes high.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
12. The system may read and program functions in non-erasing
sectors, or enter the autoselect mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only
during a sector erase operation.
13. The Erase Resume command is valid only during the Erase
Suspend mode.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
22268B5 September 12, 2006
Am29LV033C
23
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10, on page 29 and the following
subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or
in progress. These three bits are discussed first.
Table 10, on page 29 shows the outputs for Data#
Polling on DQ7. Figure 5 shows the Data# Polling al-
gorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum out-
put described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to
“1”; prior to this, the device outputs the “complement,”
or “0.” The system must provide an address within any
of the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
Figure 18, on page 39, Data# Polling Timings (During
Embedded Algorithms), in the “AC Characteristics”
section illustrates this.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5. Data# Polling Algorithm
24
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
DQ6 also toggles during the erase-suspend-program
RY/BY#: Ready/Busy#
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
Table 10, on page 29 shows the outputs for Toggle Bit
I on DQ6. Figure 6, on page 28 shows the toggle bit al-
gorithm in flowchart form, and the section “Reading
Toggle Bits DQ6/DQ2” on page 27 explains the algo-
rithm. Figure 19, on page 39 in the “AC Characteris-
tics” section shows the toggle bit timing diagrams.
Figure 20, on page 39 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on “DQ2: Toggle Bit II”.
pull-up resistor to VCC
.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data (includ-
ing during the Erase Suspend mode), or is in the
standby mode.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 10, on page 29 shows the outputs for RY/BY#.
Figures “RESET# Timings” on page 35, Figure 15, on
page 37 and Figure 17, on page 38 shows RY/BY# for
reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but cannot dis-
tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode infor-
mation. Refer to Table 10, on page 29 to compare out-
puts for DQ2 and DQ6.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or
CE# to control the read cycles). When the operation is
complete, DQ6 stops toggling.
Figure 6, on page 28 shows the toggle bit algorithm in
flowchart form, and the section “Reading Toggle Bits
DQ6/DQ2” explains the algorithm. See also the “DQ6:
Toggle Bit I” subsection. Figure 19, on page 39 shows
the toggle bit timing diagram. Figure 20, on page 39
shows the differences between DQ2 and DQ6 in
graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 28 for the following discus-
sion. Whenever the system initially begins reading tog-
gle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
22268B5 September 12, 2006
Am29LV033C
25
D A T A S H E E T
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
START
Read DQ7–DQ0
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 6).
(Note 1)
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
Table 10, on page 29 shows the outputs for Toggle Bit
I on DQ6. Figure 6 shows the toggle bit algorithm. Fig-
ure 19, on page 39 in the “AC Characteristics” section
shows the toggle bit timing diagrams. Figure 20, on
page 39 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II” on page 27.
No
DQ5 = 1?
Yes
DQ5: Exceeded Timing Limits
(Notes
1, 2)
Read DQ7–DQ0
Twice
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle
was not successfully completed.
Toggle Bit
= Toggle?
No
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation
has exceeded the timing limits, DQ5 produces a “1.”
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
DQ3: Sector Erase Timer
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out is complete, DQ3
switches from “0” to “1.” If the time between additional
sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not
monitor DQ3. See also “Sector Erase Command Se-
quence” on page 23.
Figure 6. Toggle Bit Algorithm
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device accepts additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted. Table 10 shows the outputs for DQ3.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
26
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
Table 10. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” on page 28 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
22268B5 September 12, 2006
Am29LV033C
27
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Industrial (I) Devices
Voltage with Respect to Ground
Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
Extended (E) Devices
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
Ambient Temperature (TA). . . . . . . . .–55°C to +125°C
All other pins (Note 1). . . . . . .–0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
VCC Supply Voltages
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Notes:
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 7, on page 30. Maximum DC voltage on input or
I/O pins is VCC +0.5 V. During voltage transitions, input
or I/O pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 8, on page 30.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and RESET#
may overshoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 7, on page 30. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
20 ns
20 ns
20 ns
+0.8 V
V
V
CC+2.0 V
CC+0.5 V
V
SS–0.5 V
VSS–2.0 V
2.0 V
20 ns
20 ns
20 ns
Figure 7. Maximum Negative
Overshoot Waveform
Figure 8. Maximum Positive
Overshoot Waveform
28
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
IN = VSS to VCC
Min
Typ
Max
±1.0
35
Unit
µA
V
,
ILI
Input Load Current (Note 1)
A9 Input Load Current
VCC = VCC max
VCC = VCC max; A9 = 12.5 V
OUT = VSS to VCC
ILIT
ILO
µA
V
,
Output Leakage Current
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
10
2
16
4
VCC Active Read Current
(Notes 2, 3)
ICC1
CE# = VIL, OE# = VIH
CE# = VIL, OE# = VIH
mA
VCC Active Write Current
(Notes 2, 4, 6)
ICC2
ICC3
ICC4
15
0.2
0.2
30
5
mA
µA
µA
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET#, ACC = VCC±0.3 V
RESET# = VSS ± 0.3 V,
ACC = VCC ± 0.3 V
5
V
IH = VCC 0.3 V;
Automatic Sleep Mode
(Notes 2, 5)
ICC5
VIL = VSS ± 0.3 V,
ACC = VCC ± 0.3 V
0.2
5
µA
ACC
pin
ACC Accelerated Program
Current,
5
10
mA
IACC
CE# = VIL, OE# = VIH
Word or Byte
VCC pin
15
30
0.8
mA
V
VIL
VIH
Input Low Voltage
–0.5
Input High Voltage
Voltage for ACC Sector
0.7 x VCC
VCC + 0.3
V
VHH
Protect/Unprotect and Program VCC = 3.0 V 10%
Acceleration
8.5
9.5
V
V
Voltage for Autoselect and
VCC = 3.3 V
VID
11.5
12.5
0.45
Temporary Sector Unprotect
VOL
VOH1
VOH2
Output Low Voltage
Output High Voltage
IOL = 4.0 mA, VCC = VCC min
OH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
I
0.85 VCC
VCC–0.4
Low VCC Lock-Out Voltage
(Note 6)
VLKO
2.3
2.5
V
Notes:
1. On the ACC pin only, the maximum input load current when ACC = VIL is 5.0 µA.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0 V.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
6. Not 100% tested.
22268B5 September 12, 2006
Am29LV033C
29
D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
30
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
3.3 V
Test Condition
Output Load
-70
-90, -120
Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load
Capacitance, CL
(including jig capacitance)
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and
Measurement Levels
22268B5 September 12, 2006
Am29LV033C
31
D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std Description
Test Setup
Min
-70
-90
-120
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
70
70
90
120
120
ns
CE# = VIL
tAVQV
tACC Address to Output Delay
Max
90
ns
OE# = VIL
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
70
30
25
25
90
40
30
30
0
120
50
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11, on page 33 and Table 11, on page 33 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
32
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
tREADY
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
22268B5 September 12, 2006
Am29LV033C
33
D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Option
JEDEC
tAVAV
Std
tWC
tAS
Description
-70
-90
90
0
-120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Min
Min
Min
Min
Min
Min
70
120
tAVWL
tWLAX
tDVWH
tWHDX
ns
tAH
45
35
45
45
0
50
50
ns
tDS
Data Setup Time
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time (Note 1)
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tCS
tCH
tWP
tWPH
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Max
0
0
ns
ns
ns
ns
µs
µs
sec
µs
ns
ns
CE# Hold Time
tWLWH
Write Pulse Width
Write Pulse Width High
30
45
30
9
50
tWHWL
tWHWH1
tWHWH1
tWHWH2
tWHWH1 Programming Operation (Note 2)
tWHWH1 Accelerated Programming Operation (Note 2)
tWHWH2 Sector Erase Operation (Note 2)
7
0.7
50
0
tVCS
tRB
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
tBUSY
90
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” on page 44 section for more information.
34
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
XXXh
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15. Program Operation Timings
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Figure 16. Accelerated Program Timing Diagram
22268B5 September 12, 2006
Am29LV033C
35
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
tWC
VA
Addresses
CE#
XXXh
SA
XXXh for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on
page 26).
Figure 17. Chip/Sector Erase Operation Timings
36
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
Complement
High Z
High Z
DQ7
DQ0–DQ6
RY/BY#
Valid Data
Complement
Status Data
True
Status Data
True
Valid Data
tBUSY
Note: VA = Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 18. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended
sector.
Figure 20. DQ2 vs. DQ6
22268B5 September 12, 2006
Am29LV033C
37
D A T A S H E E T
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
ns
RESET# Setup Time for Temporary
Sector/Sector Block Unprotect
tRSP
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 21. Temporary Sector/Sector Block Unprotect Timing Diagram
38
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector/Sector Block Protect or Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22. Sector Protect/Unprotect
Timing Diagram
22268B5 September 12, 2006
Am29LV033C
39
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Option
JEDEC
tAVAV
Std
tWC
tAS
Description
-70
-90
90
0
-120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
70
120
tAVEL
ns
tELAX
tAH
45
35
45
45
0
50
50
ns
tDVEH
tEHDX
tDS
ns
tDH
tOES
Data Hold Time
ns
Output Enable Setup Time
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tWS
tWH
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WE# Hold Time
tCP
CE# Pulse Width
30
45
30
9
50
ns
tEHEL
tCPH
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
ns
tWHWH1
tWHWH2
tWHWH1
tWHWH2
µs
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” on page 44 section for more information.
40
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
AC CHARACTERISTICS
XXX for program
PA for program
XXX for erase
SA for sector erase
XXX for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, DOUT = Data Out, DQ7# = complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 23. Alternate CE# Controlled Write Operation Timings
22268B5 September 12, 2006
Am29LV033C
41
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
0.7
45
9
15
Excludes 00h programming
prior to erasure (Note 4)
s
Byte Programming Time
Accelerated Byte Program Time
Chip Programming Time (Note 3)
Notes:
300
210
108
µs
µs
s
Excludes system level
overhead (Note 5)
7
36
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 9, on page 25 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
VCC Current
–1.0 V
VCC + 1.0 V
+100 mA
–100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Years
Years
150°C
125°C
Minimum Pattern Data Retention Time
20
42
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
22268B5 September 12, 2006
Am29LV033C
43
D A T A S H E E T
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
22268B5 September 12, 2006
Am29LV033C
44
D A T A S H E E T
PHYSICAL DIMENSIONS
FBD063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm
Dwg rev AF; 10/99
45
Am29LV033C
22268B5 September 12, 2006
D A T A S H E E T
REVISION SUMMARY
Accelerated Program Timing Diagram
Revision A+1 (January 1999)
Deleted WP# designation from ACC signal.
Device Bus Operations
Revision A+8 (August 18, 1999)
Sector/Sector Block Addresses for Protection/Unpro-
tection Table: Corrected the address bits and values in
the middle column of the table.
Ordering Information, Physical Dimensions
Corrected FBGA package dimensions to 8 x 14 mm.
Autoselect Codes (High Voltage Method Table:
Revision A+9 (August 31, 1999)
Changed the device ID to A3h.
Revision A+2 (January 1999)
Ordering Information
Speed Option: Changed 70R to 70.
Command Definitions
Revision B (January 3, 2000)
Command Definition Table: Changed the device ID to
A3h.
AC Characteristics—Figure 15. Program
Operations Timing and Figure 17. Chip/Sector
Erase Operations
Revision A+3 (March 17, 1999)
Connection Diagrams
Deleted tGHWL and changed OE# waveform to start at
high.
Modified FBGA drawing to show how outrigger balls
are shorted.
Physical Dimensions
Revision A+4 (May 17, 1999)
Replaced figures with more detailed illustrations.
Global
Revision B+1 (February 21, 2000)
Deleted references to WP#. The device does not offer
this function.
Global
Changed data sheet status to “Preliminary” from “Ad-
vance Information. Added dash to speed options.
Table 4. Sector Block Addresses for
Protection/Unprotection
Deleted “Top Boot Sector/” from table title.
Ordering Information
Added dash to OPN.
Revision A+5 (June 7, 1999)
Revision B+2 (November 7, 2000)
Global
The 70 ns speed option now operates over the full
2.7–3.6 V VCC range.
Global
Added Table of Contents. Deleted burn-in option. De-
leted Preliminary status from data sheet.
Common Flash Memory Interface
Corrected data for the following addresses: 27h, 2Dh,
37h, 48h, and 49h. Modified the description for 48h
and 49h.
Revision B+3 (October 27, 2004)
Global
Added Colophon
Revision A+6 (June 25, 1999)
Added reference links
Command Definitions Table
Ordering Information
Indicated that address bit A21 must be specified in the
third cycle when entering the autoselect mode.
Added temperature ranges for Pb-free Package
Revision A+7 (August 2, 1999)
Valid Combinations for TSOP Packages
Added new combinations — EF, FF, for package
AM29LV033C-70
Block Diagram
Added ACC signal to drawing.
Added new combinations — EF, EK, FF, FK for pack-
ages AM29LV033C-90 and AM29LV033C-120
Accelerated Program Operations
Clarified how to permanently set ACC.
22268B5 September 12, 2006
Am29LV033C
46
D A T A S H E E T
Valid Combination for FBGA Packages
Added new combinations for Order Number — WDF
for AM29LV033C-70 and WDF, WDK for
AM29LV033C-90 and AM29LV033C-120
Added new combinations for Package Marking — F for
L033C70V and F, K for L033C90V and L033C120V
Revision B+4 (June 7, 2005)
Modified EOL disclaimer
Cover page and Title page
Added notation to superseding documents.
Revision B5 (September 12, 2006)
Erase and Program Operations table
Changed tBUSY to a maximum specification.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are
trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
47
Am29LV033C
22268B5 September 12, 2006
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