AM29LV065MU101RFF_技术文档

Am29LV065MU

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29GL064A supersedes Am29LV065MU and is the factory-recommended migration path. Please

refer to the S29GL064A datasheet for specifications and ordering information. Availability of this

document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 25262 Revision C Amendment 4 Issue Date September 12, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV065MU

64 Megabit (8 M x 8-Bit) MirrorBit™ 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O™ Control

This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV065MU and is the factory-recom-

mended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference

and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 8-byte read page buffer

— 32-byte write buffer

Single power supply operation

— 3 volt read, erase, and program operations

Low power consumption (typical values at 3.0 V,

5 MHz)

VersatileI/O™ control

— 30 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— Device generates and tolerates data voltages on CE#

and DQ inputs/outputs as determined by the voltage

on the V_IOpin; operates from 1.65 to 3.6 V

Manufactured on 0.23 µm MirrorBit process

technology

Package options

— 48-pin TSOP

— 63-ball FBGA

SecSi™ (Secured Silicon) Sector region

— 256-byte sector for permanent, secure identification

through an 16-byte random Electronic Serial Number,

accessible through a command sequence

SOFTWARE & HARDWARE FEATURES

Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— May be programmed and locked at the factory or by

the customer

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

Flexible sector architecture

— One hundred twenty-eight 64 Kbyte sectors

— Data# polling & toggle bits provide status

Compatibility with JEDEC standards

— Unlock Bypass Program command reduces overall

multiple-byte programming time

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Minimum 100,000 erase cycle guarantee per sector

Hardware features

20-year data retention at 125°C

— Sector Group Protection: hardware method of

preventing write operations within a sector group

PERFORMANCE CHARACTERISTICS

High performance

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

— 90 ns access time

— 25 ns page read times

— 0.5 s typical sector erase time

— ACC (high voltage) pin accelerates programming

time for higher throughput during system production

— 11 µs typical effective write buffer byte programming

time: 32-byte write buffer reduces overall

— Hardware reset pin (RESET#) resets device

— Ready/Busy# pin (RY/BY#) detects program or erase

cycle completion

programming time for multiple-byte updates

Publication# 25262

Issue Date: September 12, 2006

Rev: C Amendment/4

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29LV065MU is a 64 Mbit, 3.0 volt single power

supply flash memory devices organized as 8,388,608

bytes. The device has an 8-bit wide data bus, and can

be programmed either in the host system or in stan-

dard EPROM programmers.

and tolerates on the CE# control input and DQ I/Os to

the same voltage level that is asserted on the V_IOpin.

See “Ordering Information” on page 9. for valid V_IOop-

tions.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

An access time of 90, 100, 110, or 120 ns is available.

Note that each device has a specific operating voltage

range (V_CC) and an I/O voltage range (V_IO), as speci-

fied in “Product Selector Guide” on page 5 and “Order-

ing Information” on page 9. The device is offered in a

48-pin TSOP or 63-ball FBGA package. Each device

has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

Each device requires only a single 3.0 volt power

supply for both read and write functions. In addition to

a V_CCinput, a high-voltage accelerated program

(ACC) input provides shorter programming times

through increased current. This feature is intended to

facilitate factory throughput during system production,

but may also be used in the field if desired.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The SecSi™ (Secured Silicon) Sector provides a 256

byte area for code or data that can be permanently

protected. Once this sector is protected, no further

changes within the sector can occur.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

2

Am29LV065MU

September 12, 2006

D A T A S H E E T

MIRRORBIT 64 MBIT DEVICE FAMILY

Sector

Architecture

Device

Bus

x8

Packages

V_IO

Yes

No

RY/BY#

Yes

WP#, ACC

ACC only

WP# Protection

48-pin TSOP (std. & rev. pinout),

63-ball FBGA

LV065MU

LV640MT/B

LV640MH/L

LV641MH/L

LV640MU

Uniform (64 Kbyte)

No WP#

Boot (8 x 8 Kbyte

at top & bottom)

48-pin TSOP, 63-ball Fine-pitch BGA,

64-ball Fortified BGA

2 x 8 Kbyte

top or bottom

x8/x16

Yes

WP#/ACC pin

56-pin TSOP (std. & rev. pinout),

64 Fortified BGA

1 x 64 Kbyte

high or low

x8/x16 Uniform (64 Kbyte)

Yes

Separate WP#

and ACC pins

1 x 32 Kword

top or bottom

x16

Uniform (32 Kword)

48-pin TSOP (std. & rev. pinout)

No

63-ball Fine-pitch BGA,

64-ball Fortified BGA

Yes

ACC only

No WP#

RELATED DOCUMENTS

To download related documents, click on the following

links or go to www.amd.com→Flash Memory→Prod-

uct Information→MirrorBit→Flash Information→Tech-

nical Documentation.

Implementing a Common Layout for AMD MirrorBit

and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

AMD MirrorBit™ White Paper

MirrorBit™ Flash Memory Write Buffer Programming

and Page Buffer Read

September 12, 2006

Am29LV065MU

3

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations .....................................................10

VersatileIO™ (V_IO) Control ..................................................... 10

Requirements for Reading Array Data ................................... 10

Page Mode Read .................................................................... 11

Writing Commands/Command Sequences ............................ 11

Write Buffer ............................................................................. 11

Accelerated Program Operation ............................................. 11

Autoselect Functions .............................................................. 11

Standby Mode ........................................................................ 11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Table 2. Sector Address Table ........................................................13

Autoselect Mode..................................................................... 17

Table 3. Autoselect Codes, (High Voltage Method) .......................17

Sector Group Protection and Unprotection ............................. 18

Table 4. Sector Group Protection/Unprotection Address Table .....18

Temporary Sector Group Unprotect ....................................... 19

Figure 1. Temporary Sector Group Unprotect Operation................ 19

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20

SecSi (Secured Silicon) Sector Flash Memory Region .......... 21

Table 5. SecSi Sector Contents ......................................................21

Figure 3. SecSi Sector Protect Verify.............................................. 22

Hardware Data Protection ...................................................... 22

Low VCC Write Inhibit ............................................................ 22

Write Pulse “Glitch” Protection ............................................... 22

Logical Inhibit .......................................................................... 22

Power-Up Write Inhibit ............................................................ 22

Common Flash Memory Interface (CFI) . . . . . . . 22

Table 6. CFI Query Identification String .............................. 23

Table 7. System Interface String......................................................23

Table 8. Device Geometry Definition................................... 24

Table 9. Primary Vendor-Specific Extended Query............. 25

Command Definitions . . . . . . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................ 25

Reset Command ..................................................................... 26

Autoselect Command Sequence ............................................ 26

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 26

Byte Program Command Sequence ....................................... 26

Unlock Bypass Command Sequence ..................................... 27

Write Buffer Programming ...................................................... 27

Accelerated Program .............................................................. 28

Figure 4. Write Buffer Programming Operation............................... 29

Figure 5. Program Operation .......................................................... 30

Program Suspend/Program Resume Command Sequence ... 30

Figure 6. Program Suspend/Program Resume............................... 31

Chip Erase Command Sequence ........................................... 31

Sector Erase Command Sequence ........................................ 31

Erase Suspend/Erase Resume Commands ........................... 32

Figure 7. Erase Operation............................................................... 33

Command Definitions ............................................................. 34

Table 10. Command Definitions.......................................................34

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 35

DQ7: Data# Polling ................................................................. 35

Figure 8. Data# Polling Algorithm .................................................. 35

RY/BY#: Ready/Busy#............................................................ 36

DQ6: Toggle Bit I .................................................................... 36

Figure 9. Toggle Bit Algorithm........................................................ 36

DQ2: Toggle Bit II ................................................................... 37

Reading Toggle Bits DQ6/DQ2 ............................................... 37

DQ5: Exceeded Timing Limits ................................................ 37

DQ3: Sector Erase Timer ....................................................... 37

DQ1: Write-to-Buffer Abort ..................................................... 38

Table 11. Write Operation Status ................................................... 38

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 39

Figure 10. Maximum Negative Overshoot Waveform ................... 39

Figure 11. Maximum Positive Overshoot Waveform..................... 39

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 1. Maximum Negative Overshoot Waveform ..................... 39

Figure 2. Maximum Positive Overshoot Waveform....................... 39

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 39

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12. Test Setup.................................................................... 41

Table 12. Test Specifications ......................................................... 41

Key to Switching Waveforms. . . . . . . . . . . . . . . . 41

Figure 13. Input Waveforms and

Measurement Levels...................................................................... 41

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Read-Only Operations ........................................................... 42

Figure 14. Read Operation Timings............................................... 42

Figure 15. Page Read Timings ...................................................... 43

Hardware Reset (RESET#) .................................................... 44

Figure 16. Reset Timings............................................................... 44

Erase and Program Operations .............................................. 45

Figure 17. Program Operation Timings.......................................... 46

Figure 18. Accelerated Program Timing Diagram.......................... 46

Figure 19. Chip/Sector Erase Operation Timings .......................... 47

Figure 20. Data# Polling Timings

(During Embedded Algorithms)...................................................... 48

Figure 21. Toggle Bit Timings

(During Embedded Algorithms)...................................................... 49

Figure 22. DQ2 vs. DQ6................................................................. 49

Temporary Sector Unprotect .................................................. 50

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 50

Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 51

Alternate CE# Controlled Erase and Program Operations ..... 52

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 53

Erase And Programming Performance. . . . . . . . 54

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 54

TSOP Pin and BGA Package Capacitance . . . . . 55

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56

TS 048—48-Pin Standard Thin Small Outline Package .........56

TSR048—48-Pin Reverse Thin Small Outline Package .........57

FBE063—63-Ball Fine-Pitch Ball Grid Array, 12 x 11 mm

Package .................................................................................. 58

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 59

4

Am29LV065MU

September 12, 2006

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29LV065MU

90R

(Note 3)

V_CC= 3.0–3.6 V

101R

Speed

Option

(V_IO= 3.0–3.6 V)

(V_IO= 2.7–3.6 V)

101

112R

112

120R

120

V_CC= 2.7–3.6 V

(V_IO= 2.7–3.6 V)

(V_IO= 1.65–3.6V) (V_IO= 1.65–3.6 V) (V_IO= 1.65–3.6 V) (V_IO= 1.65–3.6 V)

Max. Access Time (ns)

90

25

100

30

110

120

Max. CE# Access Time (ns)

Max. Page access time (t_PACC

Max. OE# Access Time (ns)

)

30

40

30

40

30

Note:

1. See “AC Characteristics” for full specifications.

2. For the Am29LV065MU device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only.

Please use OPNs as listed when placing orders.

3. Contact factory for availability and ordering information.

BLOCK DIAGRAM

DQ0–DQ7

RY/BY#

V_CC

V_SS

Sector Switches

V_IO

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

ACC

State

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A22–A0

September 12, 2006

Am29LV065MU

5

D A T A S H E E T

CONNECTION DIAGRAMS

NC

A17

V_SS

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

NC

A22

A16

A15

A14

A13

A12

A11

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

9

A8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48-Pin Standard TSOP

WE#

RESET#

ACC

RY/BY#

A18

A7

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

CE#

A0

NC

A6

A5

A4

A3

A2

A1

NC

A17

V_SS

1

2

3

4

5

6

7

8

NC

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A22

A16

A15

A14

A13

A12

A11

A9

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

CE#

A0

NC

48-Pin Reverse TSOP

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A8

WE#

RESET#

ACC

RY/BY#

A18

A7

A6

A5

A4

A3

A2

A1

NC

6

Am29LV065MU

September 12, 2006

D A T A S H E E T

CONNECTION DIAGRAMS

63-Ball FBGA

Top View, Balls Facing Down

L8

M8

A8

B8

NC*

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

A7

B7

A14

A13

A15

A16

A17

NC

A20

V

SS

NC*

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A11

A12

A19

A10

DQ6

DQ7

C5

D5

E5

F5

G5

H5

J5

K5

WE# RESET# A22

NC

DQ5

NC

V

DQ4

CC

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY# ACC

NC

DQ2

DQ3

V

A21

IO

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A18

DQ0

NC

DQ1

A2

L2

M2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

NC*

CE#

OE#

V

NC*

SS

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, SSOP, PLCC,

PDIP). The package and/or data integrity may be

September 12, 2006

Am29LV065MU

7

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A22–A0

= 23 Address inputs

23

DQ7–DQ0 = 8 Data inputs/outputs

A22–A0

8

CE#

= Chip Enable input

= Output Enable input

= Write Enable input

= Acceleration input

= Hardware Reset Pin input

= Ready/Busy output

DQ7–DQ0

CE#

OE#

WE#

ACC

RESET#

RY/BY#

V_CC

RESET#

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

NC

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

8

Am29LV065MU

September 12, 2006

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV065M

U

120R

WH

I

TEMPERATURE RANGE

F

I

=

Industrial (-40°C to +85°C) with Pb-free Package

Industrial (–40°C to +85°C)

PACKAGE TYPE

E

=

48-Pin Standard Pinout Thin Small Outline Package (TS 048)

48-Pin Reverse Pinout Thin Small Outline Package (TSR048)

F

WH

63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 11 x 12 mm package (FBE063)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE

U

=

Uniform sector device

DEVICE NUMBER/DESCRIPTION

Am29LV065MU

64 Megabit (8 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

TSOP Package

Speed

(ns)

V_IO

Range

V_CC

Range

Valid Combinations for

Fine-Pitch BGA Package

Am29LV065MU101

100

110

120

100

110

120

2.7–3.6 V

Speed

(ns)

V_IO

V_CC

Range Range

Am29LV065MU112

Am29LV065MU120

Am29LV065MU101R

Am29LV065MU112R

Am29LV065MU120R

1.65–3.6 V 2.7–3.6 V

1.65–3.6 V

Package

Order Number

Am29LV065MU101

Am29LV065MU112

Am29LV065MU120

Am29LV065MU101R

Am29LV065MU112R

Am29LV065MU120R

Marking

EI, FI,

EF

2.7–

3.6 V

2.7–3.6 V

L065MU01V

100

110

120

100

110

120

1.65–3.6 V 3.0–3.6 V

1.65–3.6 V

1.65–

3.6 V

2.7–

3.6 V

L065MU11V

L065MU12V

L065MU01R

L065MU11R

L065MU12R

1.65–

3.6 V

WHI

WHF

I,

F

2.7–

3.6 V

1.65–

3.6 V

3.0–

3.6 V

1.65–

3.6 V

Valid Combinations

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Note:

1. For the Am29LV065MU device, the last numeric digit in the speed

option (e.g. 101, 112, 120) is used for internal purposes only. Please

use OPNs as listed when placing orders.

2. For 90R speed option shown in product selector guide, contact

AMD for availability and ordering information.

September 12, 2006

Am29LV065MU

9

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

Addresses

(Note 2)

DQ7–

DQ0

Operation

CE#

OE# WE# RESET#

ACC

L/H

V_HH

Read

L

H

L

H

A_IN

D_OUT

Write (Program/Erase)

Accelerated Program

(Note 3)

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

L/H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z

X

SA, A6=L, A3=L,

A2=L, A1=H, A0=L

Sector Group Protect (Note 2)

L

H

X

L

V_ID

L/H

(Note 3)

Sector Group Unprotect

(Note 2)

SA, A6=H, A3=L,

A2=L, A1=H, A0=L

Temporary Sector Group

Unprotect

X

A_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A22:A0. Sector addresses are A22:A16.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector Group

Protection and Unprotection” on page 18..

3. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see Figure 2).

trol and gates array data to the output pins. WE#

should remain at V_IH.

VersatileIO™ (V_IO) Control

The VersatileIO™ (V_IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V_IO. See “Ordering Informa-

tion” on page 9. for V_IOoptions on this device.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

For example, a V_I/Oof 1.65–3.6 volts allows for I/O at

the 1.8 or 3 volt levels, driving and receiving signals to

and from other 1.8 or 3 V devices on the same data

bus.

Requirements for Reading Array Data

See “Reading Array Data” on page 25. for more infor-

mation. “Read-Only Operations” on page 42 for timing

specifications and to Figure 13 for the timing diagram.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

10

Am29LV065MU

September 12, 2006

D A T A S H E E T

See the table, “DC Characteristics” on page 40 for the

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the ACC pin returns the device to normal op-

eration. Note that the ACC pin must not be at V_HHfor

operations other than accelerated programming, or

device damage may result. In addition, the ACC pin

must not be left floating or unconnected; inconsistent

behavior of the device may result.

active current specification for reading array data.

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 8 bytes. The appropriate page is selected

by the higher address bits A(max)–A3. Address bits

A2–A0 determine the specific byte within a page. This

is an asynchronous operation; the microprocessor

supplies the specific byte location.

The random or initial page access is equal to t_ACCor

t_CEand subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t_PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t_ACCor t_CE. Fast page mode ac-

cesses are obtained by keeping the “read-page ad-

dresses” constant and changing the “intra-read page”

addresses.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. See “Autoselect Mode” on page 17. and

“Autoselect Command Sequence” on page 26 for

more information.

Writing Commands/Command Sequences

Standby Mode

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a byte, instead of four. The “Byte

Program Command Sequence” on page 26 has de-

tails on programming data to the device using both

standard and Unlock Bypass command sequences.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_IO0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_IO0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

See the table, “DC Characteristics” on page 40 for the

active current specification for the write mode. “AC

Characteristics” on page 42 contains timing specifica-

tion tables and timing diagrams for write operations.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

See the table, “DC Characteristics” on page 40 for the

standby current specification.

Write Buffer

Write Buffer Programming allows the system to write a

maximum of 32 bytes in one programming operation.

This results in faster effective programming time than

the standard programming algorithms. See “Write

Buffer” for more information.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

September 12, 2006

Am29LV065MU

11

D A T A S H E E T

See the table, “DC Characteristics” on page 40 for the

automatic sleep mode current specification.

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

See the tables in “AC Characteristics” on page 42 for

RESET# parameters and to Figure 15 for the timing di-

agram.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current. If RESET# is held at V_IL

but not within V_SS0.3 V, the standby current will be

greater.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

12

Am29LV065MU

September 12, 2006

D A T A S H E E T

Table 2. Sector Address Table (Sheet 1 of 4)

8-bit Address Range

(in hexadecimal)

Sector

SA0

A22

0

A21

0

1

A20

0

1

0

A19

0

1

0

1

0

A18

0

1

0

1

0

1

0

1

0

A17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

September 12, 2006

Am29LV065MU

13

D A T A S H E E T

Table 2. Sector Address Table (Sheet 2 of 4)

8-bit Address Range

(in hexadecimal)

Sector

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

A22

0

1

A21

1

0

A20

0

1

0

A19

0

1

0

1

0

A18

0

1

0

1

0

1

0

1

0

1

A17

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

400000–40FFFF

410000–41FFFF

420000–42FFFF

430000–43FFFF

440000–44FFFF

14

Am29LV065MU

September 12, 2006

D A T A S H E E T

Table 2. Sector Address Table (Sheet 3 of 4)

8-bit Address Range

(in hexadecimal)

Sector

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

A22

1

A21

0

1

A20

0

1

0

A19

0

1

0

1

0

A18

1

0

1

0

1

0

1

0

1

A17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A16

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

660000–66FFFF

670000–67FFFF

September 12, 2006

Am29LV065MU

15

D A T A S H E E T

Table 2. Sector Address Table (Sheet 4 of 4)

8-bit Address Range

(in hexadecimal)

Sector

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

A22

1

A21

1

A20

0

1

A19

1

0

1

A18

0

1

0

1

0

1

A17

0

1

0

1

0

1

0

1

0

1

0

1

A16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

7E0000–7EFFFF

7F0000–7FFFFF

Note: All sectors are 64 Kbytes in size.

16

Am29LV065MU

September 12, 2006

D A T A S H E E T

In addition, when verifying sector protection, the sector

Autoselect Mode

address must appear on the appropriate highest order

address bits (see Table 2). Table 3 shows the remain-

ing address bits that are don’t care. When all neces-

sary bits have been set as required, the programming

equipment may then read the corresponding identifier

code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 10. This method

does not require V_ID. See “Autoselect Command Se-

quence” on page 26. for more information.

When using programming equipment, the autoselect

mode requires VID on address pin A9. Address pins

A6, A3, A2, A1, and A0 must be as shown in Table 3.

Table 3. Autoselect Codes, (High Voltage Method)

A21

to

A14

to

A8

to

A5

to

A3

to

Description

CE# OE# WE#

A9

A6

A1

A0

DQ7 to DQ0

A15

A10

A7

A4

A2

V_ID

Manufacturer ID: AMD

Cycle 1

L

H

X

L

X

L

H

L

01h

7Eh

13h

00h

L

V_ID

Cycle 2

X

L

X

H

Cycle 3

H

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

X

L

X

L

H

L

SecSi Sector Indicator Bit

(DQ7)

90h (factory locked),

10h (not factory locked)

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

September 12, 2006

Am29LV065MU

17

D A T A S H E E T

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group Protection and

Unprotection

Sector Group

A22–A18

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

The hardware sector group protection feature disables

both program and erase operations in any sector

group. In this device, a sector group consists of four

adjacent sectors that are protected or unprotected at

the same time (see Table 4). The hardware sector

group unprotection feature re-enables both program

and erase operations in previously protected sector

groups. Sector group protection/unprotection can be

implemented via two methods.

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

Sector protection/unprotection requires V_IDon the RE-

SET# pin only, and can be implemented either in-sys-

tem or via programming equipment. Figure 2 shows

the algorithms and Figure 23 shows the timing dia-

gram. This method uses standard microprocessor bus

cycle timing. For sector group unprotect, all unpro-

tected sector groups must first be protected prior to

the first sector group unprotect write cycle.

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and pro-

tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See “Autoselect Mode” on

page 17. for details.

Note: All sector groups are 256 Kbytes in size.

18

Am29LV065MU

September 12, 2006

D A T A S H E E T

Temporary Sector Group Unprotect

(Note: In this device, a sector group consists of four adjacent

sectors that are protected or unprotected at the same time

(see Table 4).

START

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to VID. During this mode, for-

merly protected sector groups can be programmed or

erased by selecting the sector group addresses. Once

V_IDis removed from the RESET# pin, all the previously

protected sector groups are protected again. Figure 1

shows the algorithm, and Figure 22 shows the timing

diagrams, for this feature.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected

once again.

Figure 1. Temporary Sector Group

Unprotect Operation

September 12, 2006

Am29LV065MU

19

D A T A S H E E T

START

PLSCNT = 1

RESET# = V_ID

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 μs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Yes

Sector Group Protect:

Write 60h to sector

group address with

A6–A0 = 0xx0010

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6–A0 = 1xx0010

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

Read from

sector group address

with A6–A0

= 0xx0010

Increment

PLSCNT

A6–A0 = 1xx0010

No

PLSCNT

= 25?

Read from

sector group

address with

Data = 01h?

Yes

A6–A0 = 1xx0010

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

Am29LV065MU

20

September 12, 2006

D A T A S H E E T

Factory Locked: SecSi Sector Programmed and

SecSi (Secured Silicon) Sector Flash

Memory Region

Protected At the Factory

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. A factory locked

device has an 16-byte random ESN at addresses

000000h–00000Fh.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. The de-

vices are then shipped from AMD’s factory with the

SecSi Sector permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to program the

sector after receiving the device. The customer-lock-

able version also has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sector Indi-

cator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

As an alternative to the factory-locked version, the de-

vice may be ordered such that the customer may pro-

gram and protect the 256-byte SecSi sector.

The system may program the SecSi Sector using the

write-buffer, accelerated and/or unlock bypass meth-

ods, in addition to the standard programming com-

mand sequence. See “Command Definitions” on

page 25..

The SecSi sector address space in this device is allo-

cated as follows:

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

Table 5. SecSi Sector Contents

SecSi Sector

Address Range

Standard

Factory Locked Factory Locked

ExpressFlash

Customer

Lockable

ESN or

000000h–00000Fh

000010h–0000FFh

ESN

determined by

customer

The SecSi Sector area can be protected using one of

the following procedures:

Determined by

customer

Determined by

customer

Unavailable

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0. Note that the ACC

function and unlock bypass modes are not available

when the SecSi Sector is enabled.

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

September 12, 2006

Am29LV065MU

21

D A T A S H E E T

spurious system level signals during V_CCpower-up

.

and power-down transitions, or from system noise.

START

Low V_CCWrite Inhibit

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

Wait 1 μs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

greater than V_LKO

.

Write reset

command

A1 = 1, A0 = 0

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

Logical Inhibit

A1 = 1, A0 = 0

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

Power-Up Write Inhibit

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (see Table 10 for command

definitions). In addition, the following hardware data

protection measures prevent accidental erasure or

programming, which might otherwise be caused by

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the

device to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 6–9. To terminate reading CFI data,

the system must write the reset command.

22

Am29LV065MU

September 12, 2006

D A T A S H E E T

Table 6. CFI Query Identification String

Addresses

Data

Description

10h

11h

12h

51h

52h

59h

Query Unique ASCII string “QRY”

13h

14h

02h

00h

Primary OEM Command Set

15h

16h

40h

00h

Address for Primary Extended Table

17h

18h

00h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

00h

Table 7. System Interface String

Description

Addresses

Data

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

27h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

36h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

00h

07h

0Ah

00h

01h

05h

04h

00h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

September 12, 2006

Am29LV065MU

23

D A T A S H E E T

Table 8. Device Geometry Definition

Addresses

Data

Description

27h

17h

Device Size = 2^Nbyte

28h

29h

00h

Flash Device Interface description (refer to CFI publication 100)

(00h not supported)

2Ah

2Bh

05h

00h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot

device)

2Ch

01h

2Dh

2Eh

2Fh

30h

7Fh

00h

01h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

00h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

00h

39h

3Ah

3Bh

3Ch

00h

24

Am29LV065MU

September 12, 2006

D A T A S H E E T

Table 9. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

50h

52h

49h

Query-unique ASCII string “PRI”

43h

44h

31h

33h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

09h

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

02h

04h

01h

04h

00h

01h

Sector Protect

0 = Not Supported, X = Number of sectors per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 8 Byte Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

B5h

C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top

Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top

WP# protect

4Fh

50h

00h

01h

Program Suspend

00h = Not Supported, 01h = Supported

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 10 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence may

place the device in an unknown state. A reset com-

mand is then required to return the device to reading

array data.

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

September 12, 2006

Am29LV065MU

25

D A T A S H E E T

non-erase-suspended sector. After completing a pro-

Table 10 shows the address and data requirements.

This method is an alternative to that shown in Table 3,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

mand sequence may be written to an address that is

either in the read or erase-suspend-read mode. The

autoselect command may not be written while the de-

vice is actively programming or erasing.

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See “Erase Suspend/Erase Resume Com-

mands” on page 32. for more information.

The system must issue the reset command to return

the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the device is in the autoselect mode. See

the next section, Reset Command, for more informa-

tion.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system

may read at any address any number of times without

initiating another autoselect command sequence:

See “Requirements for Reading Array Data” on

page 10. for more information. See the table,

“Read-Only Operations” on page 42 provides the read

parameters, and Figure 13 shows the timing diagram.

■ A read cycle at address XX00h returns the manu-

facturer code.

Reset Command

■ Three read cycles at addresses 01h, 0Eh, and 0Fh

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

return the device code.

■ A read cycle to an address containing a sector

group address (SA), and the address 02h on A7–A0

returns 01h if the sector group is protected, or 00h

if it is unprotected. (See Table 4 for valid sector ad-

dresses).

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing an 16-byte random Electronic Serial Num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. Table 10 shows the address

and data requirements for both command sequences.

See also “SecSi (Secured Silicon) Sector Flash

Memory Region” for further information. Note that the

ACC function and unlock bypass modes are not avail-

able when the SecSi Sector is enabled.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 10 shows the address

Note that if DQ1 goes high during a Write Buffer Pro-

gramming operation, the system must write the

Write-to-Buffer-Abort Reset command sequence to

reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

26

Am29LV065MU

September 12, 2006

D A T A S H E E T

and data requirements for the byte program command

dard programming algorithms. The write buffer pro-

gramming command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle containing the Write Buffer Load command

written at the Sector Address in which programming

will occur. The fourth cycle writes the sector address

and the number of byte locations, minus one, to be

programmed. For example, if the system will program

6 unique address locations, then 05h should be written

to the device. This tells the device how many write

buffer addresses will be loaded with data and therefore

when to expect the Program Buffer to Flash command.

The number of locations to program cannot exceed

the size of the write buffer or the operation will abort.

sequence.

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

on page 35. for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device has returned to the read

mode, to ensure data integrity. Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

The fifth cycle writes the first address location and

data to be programmed. A write-buffer-page is se-

lected by address bits A_MAX–A₅. All subsequent ad-

dress/data pairs must fall within the

selected-write-buffer-page. The system then writes the

remaining address/data pairs into the write buffer.

Write buffer locations may be loaded in any order.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The write-buffer-page address must be the same for

all address/data pairs loaded into the write buffer. That

is, write buffer programming cannot occur across mul-

tiple write-buffer pages or sectors. If the system at-

tempts to load programming data outside of the

selected write-buffer page, the operation will abort.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 10 shows the requirements for the

command sequence.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter will be

decremented for every data load operation. The host

system must therefore account for loading a

write-buffer location more than once. The counter dec-

rements for each data load operation, not for each

unique write-buffer-address location. Additionally, the

last data loaded prior to the Program Buffer to Flash

command will be programmed into the device. Note

also that if an address location is loaded more than

once into the buffer, the final data loaded for that ad-

dress will be programmed.

Once the specified number of write buffer locations

have been loaded, the system must then write the Pro-

gram Buffer to Flash command at the sector address.

Any other address and data combination aborts the

Write Buffer Programming operation. The device then

begins programming. Data polling should be used

while monitoring the last address location loaded into

the write buffer. DQ7, DQ6, DQ5, and DQ1 should be

monitored to determine the device status during Write

Buffer Programming.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to the read mode.

The write-buffer programming operation can be sus-

pended using the standard program suspend/resume

commands. Upon successful completion of the Write

Buffer Programming operation, the device is ready to

execute the next command.

Write Buffer Programming

Write buffer programming allows the system to write a

maximum of 32 bytes in one programming operation.

The effective programming time is faster than the stan-

September 12, 2006

Am29LV065MU

27

D A T A S H E E T

The Write Buffer Programming Sequence can be

aborted in the following ways:

quired when using Write-Buffer-Programming features

in Unlock Bypass mode.

■ Load a value that is greater than the page buffer

size during the Number of Locations to Program

step.

Accelerated Program

The device offers accelerated program operations

through the ACC pin. When the system asserts V_HHon

the ACC pin, the device automatically enters the Un-

lock Bypass mode. The system may then write the

two-cycle Unlock Bypass program command se-

quence. The device uses the higher voltage on the

ACC pin to accelerate the operation. Note that the

ACC pin must not be at V_HHfor operations other than

accelerated programming, or device damage may re-

sult. In addition, the ACC pin must not be left floating

or unconnected; inconsistent behavior of the device

may result.

■ Write to an address in a sector different than the

one specified during the Write-Buffer-Load com-

mand.

■ Write an Address/Data pair to

a

different

write-buffer-page than the one selected by the

Starting Address during the write buffer data load-

ing stage of the operation.

■ Write data other than the Confirm Command after

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 =

DATA# (for the last address location loaded), DQ6 =

toggle, and DQ5=0. A Write-to-Buffer-Abort Reset

command sequence must be written to reset the de-

vice for the next operation. Note that the full 3-cycle

Write-to-Buffer-Abort Reset command sequence is re-

Figure 4 illustrates the algorithm for the program oper-

ation. See the table, “Erase and Program Operations”

on page 45 for parameters, and Figure 16 for timing di-

agrams.

28

Am29LV065MU

September 12, 2006

D A T A S H E E T

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Buffer Operation?

Yes

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

((Note 1))

Write next address/data pair

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Notes:

1. When Sector Address is specified, any address in

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

Read DQ7 - DQ0 at

Last Loaded Address

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached because

DQ5= “1”, then the device FAILED. If this flowchart

location was reached because DQ1= “1”, then the

Write to Buffer operation was ABORTED. In either

case, the proper reset command must be written

before the device can begin another operation. If

DQ1=1, write the

Yes

DQ7 = Data?

No

Write-Buffer-Programming-Abort-Reset

command. if DQ5=1, write the Reset command.

No

DQ1 = 1?

Yes

DQ5 = 1?

Yes

4. See Table 10 for command sequences required for

write buffer programming.

Read DQ7 - DQ0 with

address = Last Loaded

Address

Yes

((Note 2))

DQ7 = Data?

No

((Note 3))

FAIL or ABORT

PASS

Figure 4. Write Buffer Programming Operation

Am29LV065MU

September 12, 2006

29

D A T A S H E E T

Program Suspend/Program Resume

Command Sequence

The Program Suspend command allows the system to

interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from

any non-suspended sector. When the Program Sus-

pend command is written during a programming pro-

cess, the device halts the program operation within

15 μs maximum (5 μs typical) and updates the status

bits. Addresses are not required when writing the Pro-

gram Suspend command.

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

After the programming operation has been sus-

pended, the system can read array data from any

non-suspended sector. The Program Suspend com-

mand may also be issued during a programming oper-

ation while an erase is suspended. In this case, data

may be read from any addresses not in Erase Sus-

pend or Program Suspend. If a read is needed from

the SecSi Sector area (One-time Program area), then

user must use the proper command sequences to

enter and exit this region.

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect codes

as required. When the device exits the autoselect

mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See

“Autoselect Command Sequence” on page 26. for

more information.

Programming

Completed

Note: See Table 10 for program command sequence.

Figure 5. Program Operation

After the Program Resume command is written, the

device reverts to programming. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See “Write Operation Status” on

page 35. for more information.

The system must write the Program Resume com-

mand (address bits are don’t care) to exit the Program

Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ig-

nored. Another Program Suspend command can be

written after the device has resume programming.

30

Am29LV065MU

September 12, 2006

D A T A S H E E T

When the Embedded Erase algorithm is complete, the

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. See “Write Operation Status” on page 35. for

information on these status bits. Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when an erase operation is in progress.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0h

Command is also valid for

Erase-suspended-program

operations

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Wait 15 μs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

Figure 6 illustrates the algorithm for the erase opera-

tion. See the table, “Erase and Program Operations”

on page 45 for parameters, and Figure 18 section for

timing diagrams.

Done

reading?

No

Yes

Sector Erase Command Sequence

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 10 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Device reverts to

operation prior to

Program Suspend

Figure 6. Program Suspend/Program Resume

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10

shows the address and data requirements for the chip

erase command sequence.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands. Note that the SecSi Sector,

autoselect, and CFI functions are unavailable when an

erase operation is in progress.

September 12, 2006

Am29LV065MU

31

D A T A S H E E T

The system can monitor DQ3 to determine if the sec-

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” on page 35. for informa-

tion on these status bits.

tor erase timer has timed out (See “DQ3: Sector Erase

Timer” on page 37..). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6,

DQ2, or RY/BY# in the erasing sector. See “Write Op-

eration Status” on page 35. for information on these

status bits.

After an erase-suspended program operation is com-

plete, the device returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard byte program operation. See

“Write Operation Status” on page 35. for more infor-

mation.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. See “Au-

toselect Mode” on page 17. and “Autoselect Com-

mand Sequence” on page 26 for details.

Figure 6 illustrates the algorithm for the erase opera-

tion. See the tables, “Erase and Program Operations”

on page 45 for parameters, and Figure 18 for timing di-

agrams.

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip

has resumed erasing.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. This command is valid only during the sec-

tor erase operation, including the 50 µs time-out pe-

riod during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program

algorithm.

Note: During an erase operation, this flash device per-

forms multiple internal operations which are invisible

to the system. When an erase operation is suspended,

any of the internal operations that were not fully com-

pleted must be restarted. As such, if this flash device

is continually issued suspend/resume commands in

rapid succession, erase progress will be impeded as a

function of the number of suspends. The result will be

a longer cumulative erase time than without suspends.

Note that the additional suspends do not affect device

reliability or future performance. In most systems rapid

erase/suspend activity occurs only briefly. In such

cases, erase performance will not be significantly im-

pacted.

When the Erase Suspend command is written during

the sector erase operation, the device requires a typi-

cal of 5 µs (maximum 20 μs) to suspend the erase op-

eration. However, when the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and sus-

pends the erase operation.

32

Am29LV065MU

September 12, 2006

D A T A S H E E T

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10 for erase command sequence.

2. See “DQ3: Sector Erase Timer” on page 37 for

information on the sector erase timer.

Figure 7. Erase Operation

September 12, 2006

Am29LV065MU

33

D A T A S H E E T

Command Definitions

Table 10. Command Definitions

Bus Cycles (Notes 1, 2, 3, and 4)

Third Fourth

First

Second

Fifth

Sixth

Command Sequence (Notes)

Read ((Note 5))

Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data Addr Data

1

4

6

RA

RD

F0

Reset ((Note 6))

XXX

Manufacturer ID

AA

XXX

55

XXX

90

X00

X01

01

7E

Device ID ((Note 8))

X0E

13

X0F

00

SecSi™ Sector Factory Protect

((Note 9))

4

XXX

AA

XXX

55

XXX

90

X03

(9)

Sector Group Protect Verify

((Note 10))

4

XXX

AA

XXX

55

XXX

90

(SA)X02

00/01

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

6

1

XXX

SA

AA

29

XXX

55

XXX

SA

88

90

A0

25

XXX

PA

00

PD

WC

Write to Buffer

SA

PA

PD

WBL

PD

Program Buffer to Flash

Write to Buffer Abort Reset ((Note

11))

3

XXX

AA

XXX

55

XXX

F0

20

Unlock Bypass

3

2

6

1

XXX

55

AA

A0

90

XXX

PA

55

PD

00

55

Unlock Bypass Program ((Note 12))

Unlock Bypass Reset ((Note 13))

Chip Erase

XXX

AA

B0

30

98

XXX

80

XXX

AA

XXX

55

XXX

SA

10

30

Sector Erase

Program/Erase Suspend ((Note 14))

Program/Erase Resume ((Note 15))

CFI Query ((Note 15))

Legend:

X = Don’t care

RA = Read Address of the memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on the falling edge of the WE#

or CE# pulse, whichever happens later.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A22–A16 uniquely select any sector.

WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.

BC = Byte Count. Number of write buffer locations to load minus 1.

PD = Program Data for location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

9. The data is 88h for factory locked and 08h for not factory locked.

2. All values are in hexadecimal.

10. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

11. Command sequence resets device for next command after

aborted write-to-buffer operation.

4. During unlock and command cycles, when lower address bits are

don’t cares, address bits A22–A12 are also don’t cares.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. No unlock or command cycles required when device is in read

mode.

13. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

6. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status information).

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

7. The fourth cycle of the autoselect command sequence is a read

cycle. See “Autoselect Command Sequence” on page 26. for

more information.

15. The Erase Resume command is valid only during the Erase

Suspend mode.

8. The device ID must be read in three cycles.

16. Command is valid when device is ready to read array data or when

device is in autoselect mode.

34

Am29LV065MU

September 12, 2006

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 11 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

Table 11 shows the outputs for Data# Polling on DQ7.

Figure 7 shows the Data# Polling algorithm. Figure 19

in “AC Characteristics” shows the Data# Polling timing

diagram.

DQ7: Data# Polling

START

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then the device returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 8. Data# Polling Algorithm

September 12, 2006

Am29LV065MU

35

D A T A S H E E T

Table 11 shows the outputs for Toggle Bit I on DQ6.

RY/BY#: Ready/Busy#

Figure 8 shows the toggle bit algorithm. Figure 20 in

the AC Characteristics shows the toggle bit timing dia-

grams. Figure 21 shows the differences between DQ2

and DQ6 in graphical form. See “DQ2: Toggle Bit II” on

page 37..

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or the device is in the erase-suspend-read

mode.

START

Read DQ7–DQ0

Table 11 shows the outputs for RY/BY#.

Read DQ7–DQ0

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Read DQ7–DQ0

Twice

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (See “DQ7: Data# Polling”

on page 35.).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 μs after the program

command sequence is written, then returns to reading

array data.

Figure 9. Toggle Bit Algorithm

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

36

Am29LV065MU

September 12, 2006

D A T A S H E E T

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 8).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 11 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program, erase, or

write-to-buffer time has exceeded a specified internal

pulse count limit. Under these conditions DQ5 produces a

“1,” indicating that the program or erase cycle was not suc-

cessfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Figure 8 shows the toggle bit algorithm in flowchart

form, and “DQ2: Toggle Bit II” explains the algorithm.

Also, see “DQ6: Toggle Bit I” on page 36. Figure 20

shows the toggle bit timing diagram. Figure 21 shows

the differences between DQ2 and DQ6 in graphical

form.

In all these cases, the system must write the reset

command to return the device to the reading the array

(or to erase-suspend-read if the device was previously

in the erase-suspend-program mode).

DQ3: Sector Erase Timer

Reading Toggle Bits DQ6/DQ2

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. Also, see “Sector Erase Command Se-

quence” on page 31.

Refer to Figure 8 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(See “DQ5: Exceeded Timing Limits” on page 37.). If it

is, the system should then determine again whether

the toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went high. If the toggle

bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still

toggling, the device did not completed the operation

successfully, and the system must write the reset com-

mand to return to reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

Table 11 shows the status of DQ3 relative to the other

status bits.

September 12, 2006

Am29LV065MU

37

D A T A S H E E T

turn the device to reading array data. See “Write Buffer

Programming” on page 27. for more details.

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation

was aborted. Under these conditions DQ1 produces a

“1”.

The

system

must

issue

the

Write-to-Buffer-Abort-Reset command sequence to re-

Table 11. Write Operation Status

DQ7

DQ5

DQ2

Status

((Note 2))

DQ6

((Note 1)) DQ3

((Note 2))

DQ1 RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspended

DQ7#

0

Toggle

0

N/A

1

No toggle

Toggle

0

Standard

Mode

N/A

Invalid (not allowed)

Data

1

0

Program

Suspend

Mode

Program-

Sector

Suspend

Non-Program

Read

Suspended Sector

Erase-Suspended

1

No toggle

Toggle

0

N/A

Toggle

N/A

Erase-

Sector

Suspend

Erase

Suspend

Mode

Non-EraseSuspended

Read

Data

Sector

Erase-Suspend-Program

(Embedded Program)

DQ7#

0

N/A

Busy ((Note 3))

Abort ((Note 4))

DQ7#

Toggle

0

N/A

0

1

0

Write-to-

Buffer

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. See “DQ5: Exceeded Timing Limits” on page 37. for more information.

2. DQ7 and DQ2 require a valid address when reading status information. See “DQ7: Data# Polling” on page 35. and “DQ2: Toggle

Bit II” on page 37 for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

38

Am29LV065MU

September 12, 2006

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

+0.8 V

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V_CC((Note 1)) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

20 ns

A9, OE#, ACC, and RESET#

((Note 2)) . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

Figure 10. Maximum Negative

Overshoot Waveform

All other pins ((Note 1)). . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current ((Note 3)) . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 9. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 10.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

2. Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,

ACC, and RESET# may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 9. Maximum DC input

voltage on pin A9, OE#, ACC, and RESET# is +12.5 V

which may overshoot to +14.0 V for periods up to 20 ns.

20 ns

Figure 11. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Supply Voltages

V_CCfor standard voltage range . . . . . . . . . . 2.7–3.6 V

V

_CCfor regulated voltage range . . . . . . . . . . 3.0–3.6 V

V_IO(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.0 V

Notes:

1. Operating ranges define those limits between which the

functionality of the device is guaranteed.

2. See Ordering Information section for valid V_CC/V_IOrange

combinations. The I/Os cannot go to 3 V when V_IO= 1.8V.

September 12, 2006

Am29LV065MU

39

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

_IN= V_SSto V_CC

V_CC= V_{CC max}

Min

Typ

Max

Unit

V

,

I_LI

Input Load Current (Note 1)

±1.0

µA

I_LIT

I_LR

A9, ACC Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

V_CC= V_{CC max}= 12.5 V

35

µA

V

_OUT= V_SSto V_CC

,

I_LO

Output Leakage Current

±1.0

µA

V_CC= V_{CC max}

5 MHz

1 MHz

15

30

10

50

20

50

20

60

V_CCActive Read Current

(Notes 1, 2)

I_CC1

CE# = V_IL,OE# = V_IH

mA

I_CC2

I_CC3

I_CC4

V_CCInitial Page Read Current (1, 2) CE# = V_IL,OE# = V_IH

V_CCIntra-Page Read Current (1, 2) CE# = V_IL,OE# = V_IH

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# = V_IH

mA

CE#, RESET# = V_CC± 0.3 V,

WP# = V_IH

I_CC5

I_CC6

I_CC7

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

1

5

µA

RESET# = V_SS± 0.3 V, WP# = V_IH

_IH= V_CC± 0.3 V;

V

Automatic Sleep Mode (Notes 2, 4)

V_IL= V_SS± 0.3 V, WP# = V_IH

V_IL1

V_IH1

V_IL2

V_IH2

Input Low Voltage 1(Notes 5, 6)

Input High Voltage 1 (Notes 5, 6)

Input Low Voltage 2 (Notes 5, 7)

Input High Voltage 2 (Notes 5, 7)

–0.5

0.7 x V_CC

–0.5

0.8

V

V_CC+ 0.5

0.3 x V_IO

V_IO+ 0.5

0.7 x V_IO

Voltage for ACC Program

Acceleration

V_HH

V_ID

V_CC= 2.7 –3.6 V

11.5

12.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_CC= 2.7 –3.6 V

12.5

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage (Note 9)

I_OL= 4.0 mA, V_CC= V_{CC min}= V_IO

0.15 x V_IO

V

I_OH= –2.0 mA, V_CC= V_{CC min}= V_IO0.85 V_IO

Output High Voltage

I_OH= –100 µA, V_CC= V_{CC min}= V_IO

V_IO–0.4

2.3

Low V_CCLock-Out Voltage (Note 8)

2.5

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

5. If V_IO< V_CC, maximum V_ILfor CE# and DQ I/Os is 0.3 V_IO. If V_IO< V_CC, minimum V_IHfor CE# and DQ I/Os is 0.7 V_IO. Maximum V_IH

for these connections is V_IO+ 0.3 V

6. V_CCvoltage requirements.

7. V_IOvoltage requirements. V_CC= 3 V and V_IO= 3 V or 1.8 V. When V_IOis at 1.8 V, I/Os cannot operate at 3 V.

8. Not 100% tested.

9. Includes RY/BY# pin.

40

Am29LV065MU

September 12, 2006

D A T A S H E E T

TEST CONDITIONS

Table 12. Test Specifications

Test Condition All Speeds

1 TTL gate

3.3 V

Unit

Output Load

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels (See Note)

1.5

V

Output timing measurement

reference levels

0.5 V_IO

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Changing, State Unknown

Don’t Care, Any Change Permitted

Does Not Apply

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

0.5 V_IOV

Input

Measurement Level

Output

0.0 V

Note: If V_IO< V_CC, the input measurement reference level is 0.5 V_IO.

Figure 13. Input Waveforms and

Measurement Levels

September 12, 2006

Am29LV065MU

41

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDE

C

101,

90R 101R 112R 112 120R 120 Unit

Std. Description

Test Setup

t_AVAV

t_RCRead Cycle Time (Note 1)

Min

90

100

110

120

ns

CE#, OE# =

V_IL

t_AVQVt_ACCAddress to Output Delay

Max

t_ELQV

t_CEChip Enable to Output Delay

t_PACCPage Access Time

OE# = V_IL

Max

90

25

100

30

ns

30

40

30

40

t_GLQVt_OEOutput Enable to Output Delay

30

Chip Enable to Output High Z

t_EHQZt_DF

(Note 1)

Max

25

ns

Output Enable to Output High Z

t_GHQZt_DF

(Note 1)

Output Hold Time From Addresses,

t_AXQXt_OH

Min

0

ns

CE# or OE#, Whichever Occurs First

Read

Output Enable

t_OEHHold Time

Toggle and

Data# Polling

10

(Note 1)

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 12 for test specifications.

3. AC specifications listed are tested with V_IO= V_CC.Contact AMD for more information on AC Operation with V_IO≠V_CC

.

t_RC

Addresses Stable

Addresses

CE#

t_ACC

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

42

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

Same Page

A22

-

A3

A0

A2

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

Figure 15. Page Read Timings

September 12, 2006

Am29LV065MU

43

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

μs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

μs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 16. Reset Timings

44

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

101, 112, 120,

JEDEC Std. Description

90R 101R 112R 120R Unit

t_AVAV

t_WCWrite Cycle Time (Note 1)

t_ASAddress Setup Time

Min 90 100 110 120 ns

t_AVWL

Min

0

ns

t_ASOAddress Setup Time to OE# low during toggle bit polling

t_AHAddress Hold Time

15

45

t_WLAX

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DSData Setup Time

Min

45

0

ns

t_DHData Hold Time

t_OEPHOutput Enable High during toggle bit polling

Read Recovery Time Before Write

(OE# High to WE# Low)

t_CSCE# Setup Time

t_CHCE# Hold Time

20

t_GHWLt_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

Min

Typ

0

ns

µs

t_WPWrite Pulse Width

35

30

352

11

t_WPHWrite Pulse Width High

Write Buffer Program Operation (Note 2), (Note 3)

Effective Byte Program Time, using the Write Buffer (Note 2), (Note 4)

Effective Accelerated Byte Program Time, using the Write Buffer (Notes

t_WHWH1t_WHWH1

Typ

8.8

µs

(Note 2), (Note 4)

Single Byte Program Operation (Note 2), (Note 5)

Accelerated Single Byte Programming Operation (Note 2), (Note 5)

Typ

Min

100

90

µs

t_WHWH2t_WHWH2Sector Erase Operation (Note 2)

t_VHHV_HHRise and Fall Time (Note 1)

t_VCSV_CCSetup Time (Note 1)

0.5

250

50

sec

ns

µs

t_RBWrite Recovery Time from RY/BY#

t_BUSYWE# High to RY/BY# Low

0

ns

Max 90 100 110 120 ns

Max µs

t_POLLProgram Valid Before Status Polling (Note 7)

4

Notes:

1. Not 100% tested.

command is issued within t_POLL, t_POLLmust be fully re-applied upon

resuming the programming operation. If the suspend command is

issued after t_POLL, t_POLLis not required again prior to reading the

status bits upon resuming.

2. See the “Erase And Programming Performance” section for more

information.

3. For 1–32 bytes programmed.

4. Effective write buffer specification is based upon a 32-byte write

buffer operation.

5. five Byte programming specification is based upon a single byte

programming operation not utilizing the write buffer.

6. AC specifications listed are tested with V_IO= V_CC. Contact AMD for

^{information on AC operation with V}_IO≠ V_CC

.

7. When using the program suspend/resume feature, if the suspend

September 12, 2006

Am29LV065MU

45

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_POLL

t_WP

WE#

Data

t_WPH

t_WHWH1

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:. PA = program address, PD = program data, D_OUTis the true data at the program address.

Figure 17. Program Operation Timings

V_HH

V_ILor V_IH

ACC

V_ILor V_IH

t_VHH

Figure 18. Accelerated Program Timing Diagram

46

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

XXXh

XXXh for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”)

Figure 19. Chip/Sector Erase Operation Timings

September 12, 2006

Am29LV065MU

47

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_POLL

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

WE#

t_OH

High Z

DQ15 and DQ7

Valid Data

Complement

True

DQ14–DQ8, DQ6–DQ0

RY/BY#

Status Data

True

Valid Data

Status Data

t_BUSY

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings

(During Embedded Algorithms)

48

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 21. Toggle Bit Timings

(During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

September 12, 2006

Am29LV065MU

49

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Group Unprotect

t_RRB

Min

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Group Unprotect Timing Diagram

50

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect or Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

September 12, 2006

Am29LV065MU

51

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

101,

112,

120,

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

90R

101R

112R

120R

Unit

ns

Write Cycle Time (Note Notes 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

90

100

110

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

45

0

ns

t_AH

ns

t_DS

ns

t_DH

Data Hold Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

0

ns

CE# Pulse Width

CE# Pulse Width High

45

30

t_CPH

Write Buffer Program Operation

(Notes Notes 2, Notes 3)

Typ

352

11

µs

Effective Byte Program Time, using the

Write Buffer (Notes Notes 2, Notes 4)

Effective Accelerated Byte Program Time,

using the Write Buffer (Notes Notes 2,

Notes 4)

t_WHWH1

Typ

8.8

µs

Single Byte Program Operation (Note

Notes 2, Notes 5)

100

Accelerated Single Byte Programming

Operation (Note Notes 2, Notes 5)

Typ

Min

90

0.5

50

µs

sec

ns

t_WHWH2

t_RH

Sector Erase Operation (Note Notes 2)

RESET # High Time Before Write (Note

Notes 1)

Program Valid Before Status Polling (Note

Notes 7)

t_POLL

Max

4

µs

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

3. For 1–32 bytes programmed.

4. Effective write buffer specification is based upon a 32-byte write buffer operation.

5. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer.

6. AC specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC.

7. When using the program suspend/resume feature, if the suspend command is issued within t_POLL, t_POLLmust be fully re-applied

upon resuming the programming operation. If the suspend command is issued after t_POLL, t_POLLis not required again prior to

reading the status bits upon resuming.

52

Am29LV065MU

September 12, 2006

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

OE#

t_POLL

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#,

DQ15

D_OUT

Data

t_RH

A0A0 for program PD for program

5555 for erase

3030 for sector erase

1010 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

September 12, 2006

Am29LV065MU

53

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.5

64

15

Excludes 00h programming

prior to erasure (Note 5)

128

Effective Byte Program Time, using the Write

Buffer (Note 3)

11

57

49

µs

Effective Accelerated Byte Program Time, using

the Write Buffer (Note 3)

8.8

Excludes system level

overhead (Note 6)

Single Byte Program Time

100

90

800

720

170

µs

Accelerated Single Byte Program Time (Note 4)

Chip Program Time, using the Write Buffer

Notes:

92

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 3.0 V, 100,000 cycles.

3. Effective write buffer specification is based upon a 32–byte write buffer operation.

4. Byte programming specification is based upon a single byte programming operation not utilizing the write buffer.

5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

10 for further information on command definitions.

7. The device has a minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

54

Am29LV065MU

September 12, 2006

D A T A S H E E T

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

BGA

C_IN

Input Capacitance

Output Capacitance

Control Pin Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

4.2

8.5

5.4

7.5

3.9

TSOP

BGA

C_OUT

6.5

9

TSOP

BGA

C_IN2

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

Unit

Years

10

20

Minimum Pattern Data Retention Time

125°C

September 12, 2006

Am29LV065MU

55

D A T A S H E E T

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

56

Am29LV065MU

September 12, 2006

D A T A S H E E T

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse Thin Small Outline Package

Dwg rev AA; 10/99

September 12, 2006

Am29LV065MU

57

D A T A S H E E T

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-Pitch Ball Grid Array, 12 x 11 mm Package

Dwg rev AF; 10/99

58

Am29LV065MU

September 12, 2006

D A T A S H E E T

REVISION SUMMARY

Revision A (August 3, 2001)

Revision B+2 (September 10, 2002)

Initial release as abbreviated Advance Information

data sheet.

Product Selector Guide

Added Note 2.

Revision A+1 (October 3, 2001)

Ordering Information

Global

Added Note 1.

Added 120 ns device, changed 100 ns, V_IO= 1.65–2.7

V device to 110 ns, changed 90 ns operating range to

3.0–3.6 V.

Sector Erase Command Sequence

Deleted statement that describes the outcome of

when the Embedded Erase operation is in progress.

Physical Dimensions

Revision B+3 (November 7, 2002)

Added section.

Product Selector Guide and Read Only Operations

Revision B (April 26, 2002)

Expanded data sheet to full specification version.

Changed the page access times and T_OE

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Revision B+1 (August 9, 2002)

MIRRORBIT 64 MBIT Device Family

Added second bullet, SecSi sector-protect verify text

and figure 3.

Added 64 Fortified BGA to LV640MU device.

SecSi Sector Flash Memory Region, and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Alternate CE# Controlled Erase and Program

Operations

Added t_RHparameter to table.

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Erase and Program Operations

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Added t_BUSYparameter to table.

Figure 16. Program Operation Timings

Added RY/BY# to waveform.

Noted that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.”

TSOP and BGA PIN Capacitance

Added the FBGA package.

Common Flash Memory Interface (CFI)

Program Suspend/Program Resume Command

Sequence

Changed wording in last sentence of third paragraph

from, “...the autoselect mode.” to “...reading array

data.”

Changed 15 μs typical to maximum and added 5 μs

typical.

Changed CFI website address.

Erase Suspend/Erase Resume Commands

Revision B+4 (February 17, 2003)

Changed typical from 20 μs to 5 μs and added a maxi-

mum of 20 μs.

Distinctive Characteristics

Corrected performance characteristics.

Special package handling instructions

Modified the special handling wording.

Product Selector Guide

Removed 90R speed option.

DC Characteristics table

Deleted the I_ACCspecification row.

CFI

Added note 2.

Ordering Information

Changed text in the third paragraph of CFI to read

“reading array data.”

Corrected Valid Combination to reflect speed option

changes.

Added Note.

September 12, 2006

Am29LV065MU

59

D A T A S H E E T

AC Characteristics - Erase and Program

AC Characteristics

Operations

Added Note

Added t_POLLinformation.

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Erase and Program Options table that were previ-

ously TBD. Also added notes 5 and 6.

Added note.

Trademarks

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Alternate CE# Controlled Erase and Program Op-

tions table that were previously TBD. Also added notes

5.

Updated.

ESN.

Revision C + 1 (August 23, 2004)

Erase and Programming Performance

Added Max programming specifications.

Input values into table that were previously TBD.

Added notation referencing superseding documenta-

tion.

Added note 4.

Revision C + 2 (November 9, 2004)

Added Pb-free options.

SecSi (Secured Silicon) Sector Flash Memory

Region

Revision C + 3 (December 13, 2005)

Corrected SecSi Sector address range in table.

This product has been retired and is not available for

designs. For new and current designs, S29GL064A

supersedes Am29LV065MU and is the factory-recom-

mended migration path. Please refer to the

S29GL064A datasheet for specifications and ordering

information. Availability of this document is retained for

reference and historical purposes only.

Corrected the address to find the 16–byte random

ESN.

Revision C (February 17, 2004)

Table 1 Device Bus Operations

Modified ACC column to replace instances of X to L/H.

Table 10: Command Definitions

Trademark updated.

Replaced the Addr information for both Program/Erase

Suspend and Program/Erase Resume from BA to

XXX.

Revision C4 (September 12, 2006)

Erase and Program Operations table

Changed t_BUSYto a maximum specification.

DC Characteristics - CMOS Compatible

Removed additional sentence from note 4.

Erase Suspend/Erase Resume Commands

Added note on flash device performance during sus-

pend/erase mode.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and

may be trademarks of their respective companies.

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

60

Am29LV065MU

September 12, 2006


型号：	AM29LV065MU101RFF
厂家：	SPANSION
描述：	Flash, 8MX8, 100ns, PDSO48, REVERSE, MO-142DD, TSOP-48 光电二极管存储闪存
文件：	总62页 (文件大小：1226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV065MU101RFF [SPANSION]

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