AM29LV081B-90FK [SPANSION]
Flash, 1MX8, 90ns, PDSO40, REVERSE, MO-142CD, TSOP-40;型号: | AM29LV081B-90FK |
厂家: | SPANSION |
描述: | Flash, 1MX8, 90ns, PDSO40, REVERSE, MO-142CD, TSOP-40 CD 光电二极管 |
文件: | 总41页 (文件大小:1230K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV081B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 21525 Revision D Amendment +3 Issue Date June 4, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV081B
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Minimum 1,000,000 write cycle guarantee
per sector
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV081 device
— 40-pin TSOP
■ High performance
— Access times as fast as 70 ns
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
■ Ultra low power consumption (typical values at 5
MHz)
— Superior inadvertent write protection
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
— 15 mA program/erase current
■ Ready/Busy# pin (RY/BY#)
■ Flexible sector architecture
— Sixteen 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
■ Hardware reset pin (RESET#)
Sectors can be locked in-system or via
programming equipment
— Hardware method to reset the device to reading
array data
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Command sequence optimized for mass storage
■ Unlock Bypass Program Command
— Specific addresses not required for unlock cycles
— Reduces overall programming time when issuing
multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21525 Rev: D Amendment/+3
Issue Date: June 4, 2004
GENERAL DESCRIPTION
The Am29LV081B is an 8 Mbit, 3.0 volt-only Flash
memory organized as 1,048,576 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only
a single, 3.0 volt VCC supply to perform read, program,
and erase operations. A standard EPROM programmer
can also be used to program and erase the device.
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29LV081, which was manufactured using
0.5 µm process technology. In addition, the
Am29LV081B features unlock bypass programming
and in-system sector protection/unprotection.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algo-
rithm—an internal algorithm that automatically prepro-
grams the array (if it is not already programmed) before
4
Am29LV081B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9
Standard Products .................................................................... 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .10
Table 1. Am29LV081B Device Bus Operations ..............................10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29LV081B Sector Address Table ................................12
Autoselect Mode ..................................................................... 12
Table 3. Am29LV081B Autoselect Codes (High Voltage Method) ..12
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Hardware Data Protection ...................................................... 13
Low VCC Write Inhibit .............................................................. 13
Write Pulse “Glitch” Protection ............................................... 13
Logical Inhibit .......................................................................... 13
Power-Up Write Inhibit ............................................................ 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . .15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte Program Command Sequence ....................................... 15
Unlock Bypass Command Sequence ..................................... 16
Chip Erase Command Sequence ........................................... 16
Figure 3. Program Operation .......................................................... 16
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 17
Figure 4. Erase Operation............................................................... 18
Command Definitions ............................................................. 19
Table 4. Am29LV081B Command Definitions .................................19
Write Operation Status . . . . . . . . . . . . . . . . . . . . .20
DQ7: Data# Polling ................................................................. 20
Figure 5. Data# Polling Algorithm ................................................... 20
RY/BY#: Ready/Busy# ........................................................... 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Reading Toggle Bits DQ6/DQ2 ............................................... 21
Figure 6. Toggle Bit Algorithm........................................................ 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Table 5. Write Operation Status ..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform ...................... 24
Figure 8. Maximum Positive Overshoot Waveform........................ 24
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. I
Current vs. Time (Showing Active
CC1
and Automatic Sleep Currents)...................................................... 26
Figure 10. Typical I vs. Frequency ........................................... 26
CC1
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup..................................................................... 27
Table 6. Test Specifications ........................................................... 27
Figure 12. Input Waveforms and Measurement Levels ................. 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Operations .................................................................... 28
Figure 13. Read Operations Timings ............................................. 28
Hardware Reset (RESET#) .................................................... 29
Figure 14. RESET# Timings .......................................................... 29
Erase/Program Operations ..................................................... 30
Figure 15. Program Operation Timings.......................................... 31
Figure 16. Chip/Sector Erase Operation Timings .......................... 32
Figure 17. Data# Polling Timings (During Embedded Algorithms). 33
Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 33
Figure 19. DQ2 vs. DQ6................................................................. 34
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 34
Figure 21. Sector Protect/Unprotect Timing Diagram .................... 35
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 37
Erase and Programming Performance . . . . . . . 38
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 38
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 38
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TSR040—40-Pin Reverse TSOP ........................................... 40
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision A (December 1997) .................................................. 41
Revision B (July 1998) ............................................................ 41
Revision C (January 1999) ..................................................... 41
Revision C+1 (May 17, 1999) ................................................. 41
Revision D (November 19, 1999) ........................................... 41
Revision D+1 (November 8, 2000) ......................................... 41
Revision D+2 (September 4, 2003) ........................................ 41
Revision D+3 (May 26, 2004) ................................................. 41
Am29LV081B
5
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV081B
Speed Options (V = 2.7–3.6 V)
-70
70
70
30
-90
90
90
35
-120
120
120
50
CC
Max access time, ns (t
)
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A0–A19
6
Am29LV081B
CONNECTION DIAGRAMS
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
A8
8
WE#
RESET#
NC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
Standard TSOP
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
A8
8
WE#
RESET#
NC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
Reverse TSOP
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
Am29LV081B
7
PIN CONFIGURATION
LOGIC SYMBOL
A0–A19
= 20 addresses
20
DQ0–DQ7 = 8 data inputs/outputs
A0–A19
8
CE#
= Chip enable
DQ0–DQ7
OE#
= Output enable
WE#
= Write enable
CE#
OE#
RESET#
RY/BY#
VCC
= Hardware reset pin, active low
= Ready/Busy# output
WE#
RESET#
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
RY/BY#
VSS
NC
= Device ground
= Pin not connected internally
8
Am29LV081B
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV081B
-70
E
C
TEMPERATURE RANGE
C
D
I
=
=
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-Free Package
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-free Package
Extended (–55°C to +125°C)
Extended (–55°C to +125°C) with Pb-free Package
F
E
K
PACKAGE TYPE
E
=
40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
F
=
40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29LV081B
8 Megabit (1 M x 8-Bit) Uniform Sector CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
EC, EI, EF, ED
FC, FI
AM29LV081B-70
AM29LV081B-90
AM29LV081B-120
EC, EI, EF, EE, ED
FC, FI, FE, EK
Am29LV081B
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV081B Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses (Note 1)
DQ0–DQ7
Read
Write
H
H
A
A
D
OUT
IN
IN
L
H
L
D
IN
V
0.3 V
V
CC
0.3 V
CC
Standby
X
X
X
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z
High-Z
X
Sector Address, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
H
L
V
X
ID
Sector Address, A6 = H,
A1 = H, A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
X
X
ID
Temporary Sector Unprotect
X
X
X
ID
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A19–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un-
lock Bypass mode, only two write cycles are required to
program a byte, instead of four. The “Byte Program
Command Sequence” section has details on program-
ming data to the device using both standard and Unlock
Bypass command sequences.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicate the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
10
Am29LV081B
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of tREADY (not during Embed-
ded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
When the RESET# input is held at VSS 0.3 V, the de-
vice enters the standby mode within a period of tRPD
,
tristates all data output pins, and ignores all read/write
attempts for the duration of the RESET# pulse. This
mode is “RESET# controlled,” since CE# is don’t care
under this condition. Once the RESET# pin is set
high, the device requires tRH of wake up time in addi-
tion to tCE access time for reading data. This method
also terminates any operation in progress and resets
the device.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
ICC3 in the DC Characteristics table represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Am29LV081B
11
Table 2. Am29LV081B Sector Address Table
A19
0
A18
0
A17
0
A16
0
A15
X
A14
X
A13
X
Sector Size
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
SA0
SA1
0
0
0
1
X
X
X
SA2
0
0
1
0
X
X
X
SA3
0
0
1
1
X
X
X
SA4
0
1
0
0
X
X
X
SA5
0
1
0
1
X
X
X
SA6
0
1
1
0
X
X
X
SA7
0
1
1
1
X
X
X
SA8
1
0
0
0
X
X
X
SA9
1
0
0
1
X
X
X
SA10
SA11
SA12
SA13
SA14
SA15
1
0
1
0
X
X
X
1
0
1
1
X
X
X
1
1
0
0
X
X
X
1
1
0
1
X
X
X
1
1
1
0
X
X
X
1
1
1
1
X
X
X
3. In addition, when verifying sector protection, the sec-
tor address must appear on the appropriate highest
order address bits (see Table 2). Table 3 shows the re-
maining address bits that are don’t care. When all nec-
essary bits have been set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Table
Table 3. Am29LV081B Autoselect Codes (High Voltage Method)
A19 A12
to to
CE# OE# WE# A13 A10 A9
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
Manufacturer ID: AMD
Device ID: Am29LV081B
A6
L
A1
L
A0
L
L
L
L
L
H
H
X
X
X
X
V
V
X
X
X
X
01h
38h
ID
ID
L
L
H
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
V
X
L
X
H
L
ID
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
12
Am29LV081B
Low V
Write Inhibit
Sector Protection/Unprotection
CC
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algo-
rithms and Figure 21 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.
tional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
The alternate method intended only for programming
equipment requires VID on address pin A9, OE#, and
RESET#. This method is compatible with programmer
routines written for earlier 3.0 volt-only AMD flash de-
vices. Publication number 21225 contains further de-
tails; contact an AMD representative to request a copy.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
START
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
RESET# = V
(Note 1)
ID
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 20 shows the timing diagrams, for this feature.
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
Am29LV081B
13
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
14
Am29LV081B
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 4 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires VID
on address bit A9.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address 00h retrieves the manufacturer
code. A read cycle at address 01h returns the device
code. A read cycle containing a sector address (SA)
and the address 02h returns 01h if that sector is pro-
tected, or 00h if it is unprotected. Refer to Table 2 for
valid sector addresses.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the Embed-
ded Program algorithm. The system is not required to
provide further controls or timings. The device auto-
matically generates the program pulses and verifies the
programmed cell margin. Table 4 shows the address
and data requirements for the byte program command
sequence.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
Am29LV081B
15
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
START
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the com-
mand sequence.
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 4 for program command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. The device then re-
turns to reading array data.
Figure 3. Program Operation
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
16
Am29LV081B
erase command. Table 4 shows the address and data
requirements for the sector erase command sequence.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for informa-
tion on these status bits.)
Am29LV081B
17
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
START
Write Erase
Command Sequence
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 4 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
18
Am29LV081B
Command Definitions
Table 4. Am29LV081B Command Definitions
Bus Cycles (Notes 2-4)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
4
RA
RD
F0
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
AA
AA
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
55
55
XXX
XXX
XXX
XXX
XXX
XXX
90
90
X00
X01
01
38
00
01
PD
Auto-
select
Device ID
Sector Protect Verify
(Note 8)
(SA)
X02
(Note 7)
4
AA
55
90
Program
4
3
2
2
6
6
1
1
AA
AA
A0
90
55
55
PD
00
55
55
A0
20
PA
Unlock Bypass
Unlock Bypass Program (Note 9)
Unlock Bypass Reset (Note 10)
Chip Erase
AA
AA
B0
30
XXX
XXX
80
80
XXX
XXX
AA
AA
XXX
XXX
55
55
XXX
SA
10
30
Sector Erase
Erase Suspend (Note 11)
Erase Resume (Note 12)
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A13 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
9. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
4. All address bits are don’t cares for unlock and command
cycles, except when SA or PA required.
10. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
5. No unlock or command cycles required when reading array
data.
11. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
12. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29LV081B
19
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 5 and the following subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
Yes
DQ7 = Data?
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Figure 5. Data# Polling Algorithm
20
Am29LV081B
Table 5 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 18 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
DQ2: Toggle Bit II
pull-up resistor to VCC
.
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 5 shows the outputs for RY/BY#. Figures 14, 15
and 16 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 18 shows the toggle bit timing diagram. Figure
19 shows the differences between DQ2 and DQ6 in
graphical form.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE#
to control the read cycles. When the operation is com-
plete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twice in a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the
toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Am29LV081B
21
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
START
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
(Note 1)
DQ3: Sector Erase Timer
Read DQ7–DQ0
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” If the time between additional sector erase com-
mands from the system can be assumed to be less than
50 µs, the system need not monitor DQ3. See also the
“Sector Erase Command Sequence” section.
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 5 shows the outputs for DQ3.
(Notes
1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
Figure 6. Toggle Bit Algorithm
22
Am29LV081B
Table 5. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend Reading within Non-Erase
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Suspended Sector
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29LV081B
23
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
–2.0 V
VCC (Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . –0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 7. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot V to
SS
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC voltage on input or I/O pins is V +0.5 V. During
CC
voltage transitions, input or I/O pins may overshoot to V
+2.0 V for periods up to 20 ns. See Figure 8.
CC
20 ns
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
V
CC
+2.0 V
RESET# may overshoot V to –2.0 V for periods of up to
SS
V
CC
20 ns. See Figure 7. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
+0.5 V
2.0 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . .+3.0 V to +3.6 V
VCC for full voltage range . . . . . . . . . .+2.7 V to +3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
24
Am29LV081B
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
= V to V
Min
Typ
Max
1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
,
CC
OUT
SS
I
1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
7
2
12
4
V
Active Read Current
CC
I
I
CE# = V OE#
V
V
mA
mA
CC1
CC2
IL,
=
=
IH
(Notes 1, 2)
V
Active Write Current
CC
CE# = V OE#
15
30
IL,
IH
(Notes 2, 3, 5)
I
I
V
V
Standby Current (Note 2)
Reset Current (Note 2)
CE#, RESET# = V
0.3 V
0.2
0.2
5
5
µA
µA
CC3
CC
CC
CC
RESET# = V
0.3 V
CC4
SS
Automatic Sleep Mode
(Notes 2, 4)
V
V
= V
= V
0.3 V;
0.3 V
IH
IL
CC
SS
I
0.2
5
µA
CC5
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
0.85 V
OH1
OH2
CC
CC min
CC min
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
(Note 5)
CC
V
2.3
2.5
V
LKO
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.
CC
IL
CC
2. Maximum I specifications are tested with V = V .
CCmax
CC
CC
3. I active while Embedded Erase or Embedded Program is in progress.
CC
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
5. Not 100% tested.
+ 30 ns.
ACC
Am29LV081B
25
DC CHARACTERISTICS (CONTINUED)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
26
Am29LV081B
TEST CONDITIONS
Table 6. Test Specifications
-90,
3.3 V
Test Condition
-70
-120
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 12. Input Waveforms and Measurement Levels
Am29LV081B
27
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
Min
-70
-90
-120
Unit
t
t
Read Cycle Time (Note 1)
70
90
120
ns
AVAV
RC
CE# = V
OE# = V
IL
IL
t
t
Address to Output Delay
Max
70
90
120
ns
AVQV
ACC
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
70
30
25
25
90
35
30
30
0
120
50
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
DF
DF
t
t
30
Read
Output Enable
Hold Time (Note 1)
t
OEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
OH
AXQX
Notes:
1. Not 100% tested.
2. See Figure 11 Figure 11and Table 6Table 6 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
28
Am29LV081B
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
t
t
20
µs
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
READY
t
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
RH
t
RPD
t
RB
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14. RESET# Timings
Am29LV081B
29
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
Write Cycle Time (Note 1)
-70
70
45
35
35
-90
90
45
45
35
0
-120
120
50
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
AVAV
WC
t
t
Address Hold Time
Data Setup Time
ns
WLAX
DVWH
WLWH
AH
DS
WP
t
t
50
ns
t
t
t
Write Pulse Width
Address Setup Time
Data Hold Time
50
ns
t
t
ns
AVWL
AS
t
0
ns
WHDX
DH
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHWL
GHWL
t
t
t
CE# Setup Time
Min
Min
Min
Typ
Typ
Typ
Min
Min
Min
0
0
ns
ns
ns
ELWL
WHEH
WHWL
CS
CE# Hold Time
CH
t
t
Write Pulse Width High
30
9
WPH
Byte
t
t
t
t
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
µs
WHWH1
WHWH2
WHWH1
Word
11
0.7
50
0
sec
µs
WHWH2
t
V
Setup Time (Note 1)
CC
VCS
t
Recovery Time from RY/BY#
ns
RB
t
Program/Erase Valid to RY/BY# Delay
90
ns
BUSY
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
30
Am29LV081B
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
XXX
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, D
is the true data at the program address.
OUT
Figure 15. Program Operation Timings
Am29LV081B
31
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
XXX
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 16. Chip/Sector Erase Operation Timings
32
Am29LV081B
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Valid Data
Status Data
True
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 17. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
RY/BY#
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Am29LV081B
33
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 19. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
t
V
Rise and Fall Time (See Note)
Min
Min
500
ns
VIDR
ID
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 20. Temporary Sector Unprotect Timing Diagram
34
Am29LV081B
AC CHARACTERISTICS
V
ID
V
IH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
40h
Data
60h
60h
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21. Sector Protect/Unprotect Timing Diagram
Am29LV081B
35
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
Write Cycle Time (Note 1)
Address Hold Time
-70
70
45
35
35
-90
90
45
45
35
0
-120
120
50
Unit
ns
t
t
Min
Min
Min
Min
Min
Min
Min
AVAV
ELAX
DVEH
WC
t
t
ns
AH
DS
CP
AS
DH
t
t
Data Setup Time
50
ns
t
t
t
CE# Pulse Width
50
ns
ELEH
t
Address Setup Time
Data Hold Time
ns
AVEL
t
t
0
ns
EHDX
t
Output Enable Setup Time
0
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
t
WE# Setup Time
Min
Min
Min
Typ
Typ
0
0
ns
ns
WS
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
30
9
ns
EHEL
CPH
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
36
Am29LV081B
AC CHARACTERISTICS
XXX for program
PA for program
XXX for erase
SA for sector erase
XXX for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
DOUT
Data
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
device.
= data written to the
OUT
2. Figure indicates the last two bus cycles of the command sequence.
Figure 22. Alternate CE# Controlled Write Operation Timings
Am29LV081B
37
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
Byte Programming Time
0.7
11
9
15
Excludes 00h programming
prior to erasure (Note 4)
s
300
27
µs
Excludes system level
overhead (Note 5)
Chip Programming Time
(Note 3)
9
s
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
V
= 0
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
38
Am29LV081B
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Am29LV081B
39
PHYSICAL DIMENSIONS *
TSR040—40-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
40
Am29LV081B
REVISION SUMMARY
Revision A (December 1997)
Revision C+1 (May 17, 1999)
First release.
Global
In title of data sheet and in ordering information sec-
tion, changed “sector erase” to “uniform sector.”
Revision B (July 1998)
Expanded data sheet from Advanced Information to
Preliminary version.
Revision D (November 19, 1999)
Distinctive Characteristics
AC Characteristics—Figure 15. Program
Operations Timing and Figure 16. Chip/Sector
Erase Operations
Changed “Manufactured on 0.35 µm process technology”
to “Manufactured on 0.32 µm process technology”.
Deleted tGHWL and changed OE# waveform to start at
high.
General Description
Second paragraph: Changed “This device is manufac-
tured using AMD’s 0.35 µm process technology” to
“This device is manufactured using AMD’s 0.32 µm
process technology”.
Physical Dimensions
Replaced figures with more detailed illustrations.
Corrected “TSR048—48-Pin Reverse TSOP” to
“TSR040—40-Pin Reverse TSOP”.
Revision C (January 1999)
Distinctive Characteristics
Revision D+1 (November 8, 2000)
Added the following bullet: 20-year data retention at
125°C.
Global
Deleted burn-in option from Ordering Information sec-
tion. Added table of contents.
Ordering Information
Valid Combinations: Replaced Am29LV081B-100 with
Am29LV081B-90.
Revision D+2 (September 4, 2003)
Ordering Information
DC Characteristics—CMOS Compatible
Added Pb-free compliant package and Pb-free pack-
age to industrial temperature ordering options.
ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “Maximum
ICC specifications are tested with VCC = VCCmax”.
Revision D+3 (June 4, 2004)
Ordering Information
Added Pb-free OPNs.
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29LV081B
41
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