AM29LV160MB-70PCF_技术文档

ADVANCE INFORMATION

Am29LV160M

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit^TM

3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■ Low power consumption (typical values at 5 MHz)

— 400 nA standby mode current

■ Single power supply operation

— 3 V for read, erase, and program operations

— 15 mA read current

— 40 mA program/erase current

— 400 nA Automatic Sleep mode current

■ Manufactured on 0.23 µm MirrorBit^TMprocess

technology

— Fully compatible with Am29LV160D device

■ Package options

— 48-ball Fine-pitch BGA

— 64-ball Fortified BGA

— 48-pin TSOP

■ SecSi (Secured Silicon) Sector region

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

SOFTWARE & HARDWARE FEATURES

■ Software features

— May be programmed and locked at the factory or by

the customer

— Program Suspend & Resume: read other sectors

before programming operation is completed

■ Flexible sector architecture

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-

one 64 Kbyte sectors (byte mode)

— Data# polling & toggle bits provide status

— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-

one 32 Kword sectors (word mode)

— Unlock Bypass Program command reduces overall

multiple-word programming time

■ Compatibility with JEDEC standards

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

— Provides pinout and software compatibility for single-

power supply flash, and superior inadvertent write

protection

■ Hardware features

■ Top or bottom boot block configurations available

■ Minimum 100,000 erase cycle guarantee per sector

■ 20-year data retention at 125°C

— Sector Protection: hardware-level method of

preventing write operations within a sector

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

PERFORMANCE CHARACTERISTICS

■ High performance

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

— Access times as fast as 70 ns

— 0.4 s typical sector erase time

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 25974

Issue Date: January 6, 2003

Rev: A Amendment/+3

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV160M is a 16 Mbit, 3.0 Volt-only Flash

memory organized as 2,097,152 bytes or 1,048,576

words. The device is offered in a 48-ball Fine-pitch

BGA, 64-ball Fortified BGA, and 48-pin TSOP pack-

ages. The word-wide data (x16) appears on DQ15–

DQ0; the byte-wide (x8) data appears on DQ7–DQ0.

This device is . The device requires only a single 3.0

volt power supply for both read and write functions,

designed to be programmed in-system with the stan-

dard system 3.0 volt V_CCsupply. The device can also

be programmed in standard EPROM programmers.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a

given sector to read or program any other sector and

then complete the erase operation. The Program

Suspend/Program Resume feature enables the host

system to pause a program operation in a given sector

to read any other sector and then complete the pro-

gram operation.

The device offers access times of 70, 90, and 120 ns,

allowing high speed microprocessors to operate

without wait states. To eliminate bus contention the

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The SecSi (Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

2

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . .10

Table 1. Am29LV160M Device Bus Operations ..............................10

Word/Byte Configuration ........................................................ 10

Requirements for Reading Array Data ...................................10

Writing Commands/Command Sequences ............................ 11

Program and Erase Operation Status .................................... 11

Standby Mode ........................................................................11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Table 2. Sector Address Tables (Am29LV160MT) .........................13

Table 3. Sector Address Tables (Am29LV160MB) .........................14

Autoselect Mode ..................................................................... 15

Table 4. Am29LV160M Autoselect Codes (High Voltage Method) .15

Sector Protection/Unprotection ............................................... 15

Temporary Sector Unprotect .................................................. 15

Figure 1. Temporary Sector Unprotect Operation........................... 16

Figure 2. In-System Single High Voltage Sector Protect/Unprotect Al-

gorithms .......................................................................................... 17

SecSi (Secured Silicon) Sector Flash Memory Region .......... 18

Table 5. SecSi Sector Addressing ..................................................18

Figure 3. SecSi Sector Protect Verify.............................................. 19

Common Flash Memory Interface (CFI) ................................. 19

Table 6. CFI Query Identification String ..........................................19

Table 7. System Interface String .....................................................20

Table 8. Device Geometry Definition ..............................................20

Table 9. Primary Vendor-Specific Extended Query ........................21

Hardware Data Protection ......................................................21

Low V_CCWrite Inhibit .............................................................. 21

Write Pulse “Glitch” Protection ............................................... 21

Logical Inhibit .......................................................................... 21

Power-Up Write Inhibit ............................................................ 21

Command Definitions . . . . . . . . . . . . . . . . . . . . . .22

Reading Array Data ................................................................ 22

Reset Command ..................................................................... 22

Autoselect Command Sequence ............................................ 22

Word/Byte Program Command Sequence ............................. 22

Unlock Bypass Command Sequence ..................................... 23

Figure 4. Program Operation .......................................................... 23

Chip Erase Command Sequence ........................................... 23

Sector Erase Command Sequence ........................................ 24

Erase Suspend/Erase Resume Commands ........................... 24

Figure 5. Erase Operation............................................................... 25

Program Suspend/Program Resume Command Sequence ... 26

Figure 6. Program Suspend/Program Resume............................... 26

Command Definitions ............................................................. 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . 29

DQ7: Data# Polling ................................................................. 29

Figure 7. Data# Polling Algorithm .................................................. 29

RY/BY#: Ready/Busy# ............................................................30

DQ6: Toggle Bit I .................................................................... 30

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ............................................... 30

Figure 8. Toggle Bit Algorithm........................................................ 31

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer .......................................................32

Table 12. Write Operation Status ................................................... 32

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33

Figure 9. Maximum Negative Overshoot Waveform ...................... 33

Figure 10. Maximum Positive Overshoot Waveform...................... 33

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 33

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup..................................................................... 35

Table 13. Test Specifications ......................................................... 35

Figure 12. Input Waveforms and Measurement Levels ................. 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Operations .................................................................... 36

Figure 13. Read Operations Timings ............................................. 36

Hardware Reset (RESET#) .................................................... 37

Figure 14. RESET# Timings .......................................................... 37

Word/Byte Configuration (BYTE#) ........................................ 38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Erase/Program Operations .....................................................39

Figure 17. Program Operation Timings.......................................... 40

Figure 18. Chip/Sector Erase Operation Timings .......................... 41

Figure 19. Data# Polling Timings (During Embedded Algorithms). 42

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 42

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations............................................................ 43

Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 43

Figure 23. Sector Protect/Unprotect Timing Diagram .................... 44

Figure 24. Alternate CE# Controlled Write Operation Timings ...... 46

Erase and Programming Performance . . . . . . . 47

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 47

TSOP Pin and BGA Package Capacitance . . . . . 47

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48

TS 048—48-Pin Standard TSOP ............................................48

TSR048—48-Pin Reverse TSOP ........................................... 49

FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)

6 x 8 mm Package .................................................................. 50

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm

Package ..................................................................................51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52

January 6, 2003

Am29LV160M

3

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV160M

Regulated Voltage Range: V_CC= 3.0–3.6 V

70R

70

90R

90

120R

120

50

Speed Option

Full Voltage Range: V_CC= 2.7–3.6 V

)

Max access time, ns (t_ACC

70

90

Max CE# access time, ns (t_CE

)

70

90

Max OE# access time, ns (t_OE

)

30

35

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ15–DQ0 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A19–A0

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

1

2

3

4

5

6

7

8

9

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

48

A16

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

Reverse TSOP

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

January 6, 2003

Am29LV160M

5

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

Fine-pitch BGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

A19

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

6

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAMS

64-Ball Fortified BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

NC

H8

NC

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A13

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

RESET#

NC

A19

DQ5

DQ12

V_CC

DQ4

WE#

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY#

NC

A18

NC

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

B1

C1

D1

E1

F1

G1

NC

H1

NC

temperatures above 150°C for prolonged periods of

time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, SSOP, PDIP,

PLCC). The package and/or data integrity may be

compromised if the package body is exposed to

January 6, 2003

Am29LV160M

7

A D V A N C E I N F O R M A T I O N

PIN CONFIGURATION

LOGIC SYMBOL

A19–A0

= 20 addresses

20

DQ14–DQ0 = 15 data inputs/outputs

A19–A0

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ15–DQ0

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

OE#

WE#

Write enable

WE#

RESET#

RY/BY#

V_CC

Hardware reset pin

Ready/Busy output

RESET#

BYTE#

RY/BY#

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

=

Device ground

Pin not connected internally

8

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29LV160M

T

70

E

I

TEMPERATURE RANGE

Industrial (–40°C to +85°C)

I

=

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

F

WA

48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

PC

=

64-ball Fortified Ball Grid Array (FBGA)

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV160M

16 Megabit (2M x 8-Bit/1M x 16-Bit) MirrorBit^TMFlash Memory

3.0 Volt-only Read, Program, and Erase

V

Valid Combinations for FBGA Packages

Package

CC

Valid Combinations

for TSOP Packages

Access Time

(ns)

Voltage

Range

Access

Time

V

CC

Voltage

Order Number

Marking

(ns)

Range

Am29LV160MT70R,

Am29LV160MB70R

70

90

L160MT70RI,

L160MB70RI

WAI

PCI

WAI

PCI

WAI

PCI

WAI

PCI

WAI

PCI

WAI

PCI

Am29LV160MT70R,

Am29LV160MB70R

Am29LV160MT90R,

Am29LV160MB90R

70

90

3.0–3.6 V

L160MT70NI,

L160MB70NI

Am29LV160MT120R,

Am29LV160MB120R

120

70

L160MT90RI,

L160MB90RI

Am29LV160MT90R,

Am29LV160MB90R

EI, FI

Am29LV160MT70,

Am29LV160MB70

3.0–3.6 V

L160MT90NI,

L160MB90NI

Am29LV160MT90,

Am29LV160MB90

90

2.7–3.6 V

L160MT12RI,

L160MB12RI

Am29LV160MT120R,

Am29LV160MB120R

Am29LV160MT120,

Am29LV160MB120

120

70

120

L160MT12NI,

L160MB12NI

L160MT70VI,

L160MB70VI

Valid Combinations

Am29LV160MT70,

Am29LV160MB70

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

L160MT70PI,

L160MB70PI

L160MT90VI,

L160MB90VI

Am29LV160MT90,

Am29LV160MB90

90

2.7–3.6 V

L160MT90PI,

L160MB90PI

L160MT12VI,

L160MB12VI

Am29LV160MT120,

Am29LV160MB120

120

L160MT12PI,

L160MB12PI

January 6, 2003

Am29LV160M

9

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location.

The register is composed of latches that store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29LV160M Device Bus Operations

DQ8–DQ15

DQ0– BYTE# BYTE#

Addresses

(Note 1)

Operation

CE# OE# WE# RESET#

DQ7

D_OUT

D_IN

= V_IH

D_OUT

D_IN

= V_IL

Read

Write

L

H

L

H

A_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector

Unprotect

X

A_IN

D_IN

High-Z

Legend:

L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± 0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V_IH), A19:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

main at V_IH. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. The

device remains enabled for read access until the com-

mand register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I_CC1in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

10

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

bits on DQ7–DQ0. Standard read cycle timings and I_CC

Writing Commands/Command Sequences

read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Standby Mode

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command

sequences.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V

_CC± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics table, I_CC3and I_CC4repre-

sents the standby current specification.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings

apply in this mode. Refer to the “Autoselect Mode” and

“Autoselect Command Sequence” sections for more

information.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically

enables this mode when addresses remain stable for

t_{A CC}+ 30 ns. The automatic sleep mode is

independent of the CE#, WE#, and OE# control

signals. Standard address access timings provide new

data when addresses are changed. While in sleep

mode, output data is latched and always available to

the system. I_CC4in the DC Characteristics table

represents the automatic sleep mode current

specification.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

January 6, 2003

Am29LV160M

11

A D V A N C E I N F O R M A T I O N

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the system

drives the RESET# pin to V_ILfor at least a period of t_RP

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is

completed within a time of t_READY(not during Embed-

ded Algorithms). The system can read data t_RHafter

the RESET# pin returns to V_IH.

,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

12

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

Table 2. Sector Address Tables (Am29LV160MT)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Kwords)

Byte Mode (x8)

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

Word Mode (x16)

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FBFFF

0FC000–0FCFFF

0FD000–0FDFFF

0FE000–0FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

1

0

1

8/4

1

X

16/8

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.

January 6, 2003

Am29LV160M

13

A D V A N C E I N F O R M A T I O N

Table 3. Sector Address Tables (Am29LV160MB)

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Kwords)

Byte Mode (x8)

000000–003FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

Word Mode (x16)

000000–001FFF

002000–002FFF

003000–003FFF

004000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

16/8

8/4

SA2

0

1

8/4

SA3

1

X

32/16

64/32

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.

14

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

Table 4. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7-DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Tables 10–11. This

method does not require V_ID. See “Command Defini-

tions” for details on using the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Table 4. Am29LV160M Autoselect Codes (High Voltage Method)

A19 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V_ID

X

L

X

L

X

01h

C4h

Device ID:

Am29LV160M

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V_ID

X

L

X

L

H

L

H

X

22h

X

C4h

49h

Device ID:

Am29LV160M

(Bottom Boot Block)

X

V_ID

X

H

L

01h

(protected)

X

Sector Protection Verification

L

H

SA

V_ID

L

H

00h

(unprotected)

L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 10–11.

Sector protection and unprotection requires V_IDon the

RESET# pin only, and can be implemented either in-

system or via programming equipment. Figure 2 shows

the algorithms and Figure 23 shows the timing dia-

gram. This method uses standard microprocessor bus

cycle timing. For sector unprotect, all unprotected sec-

tors must first be protected prior to the first sector un-

protect write cycle.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure shows the algorithm, and Fig-

ure 22 shows the timing diagrams, for this feature.

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Sector protection/unprotection can be implemented via

two methods.

January 6, 2003

Am29LV160M

15

A D V A N C E I N F O R M A T I O N

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

16

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

In-System Single

High Voltage

Sector Unprotect

Algorithm

from RESET#

In-System Single

High Voltage

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Single High Voltage Sector Protect/Unprotect Algorithms

January 6, 2003

Am29LV160M

17

A D V A N C E I N F O R M A T I O N

Factory Locked: SecSi Sector Programmed and

SecSi (Secured Silicon) Sector Flash

Memory Region

Protected At the Factory

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. See Table 5 for

SecSi Sector addressing.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 128 words/256 bytes in

length, and uses a SecSi Sector Indicator Bit (DQ7) to

indicate whether or not the SecSi Sector is locked

when shipped from the factory. This bit is permanently

set at the factory and cannot be changed, which pre-

vents cloning of a factory locked part. This ensures the

security of the ESN once the product is shipped to the

field.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. The de-

vices are then shipped from AMD’s factory with the

SecSi Sector permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The factory-

locked version is always protected when shipped from

the factory, and has the SecSi (Secured Silicon) Sec-

tor Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi

Sector unprotected, allowing customers to program

the sector after receiving the device. The customer-

lockable version also has the SecSi Sector Indicator

Bit permanently set to a “0.” Thus, the SecSi Sector In-

dicator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

As an alternative to the factory-locked version, the de-

vice may be ordered such that the customer may pro-

gram and protect the 128-word/256 bytes SecSi

sector.

The system may program the SecSi Sector using the

write-buffer, accelerated and/or unlock bypass meth-

ods, in addition to the standard programming com-

mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

The SecSi sector address space in this device is allo-

cated as follows:

Table 5. SecSi Sector Addressing

SecSi Sector Address

The SecSi Sector area can be protected using one of

the following procedures:

Range

Standard

Factory

Locked

ExpressFlash

Factory Locked

Customer

Lockable

x16

x8

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2,

except that RESET# may be at either V_IHor V_ID.

This allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

ESN or

determined

by customer

000000h–

000007h

000000h–

00000Fh

ESN

Determined

by customer

000008h–

00007Fh

000010h–

0000FFh

Determined

by customer

Unavailable

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

18

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-indepen-

dent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families.

Flash vendors can standardize their existing interfaces

for long-term compatibility.

START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Wait 1 µs

This device enters the CFI Query mode when the

system writes the CFI Query command, 98h, to

address 55h in word mode (or address AAh in byte

mode), any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 6–9. In word mode, the upper address

bits (A7–MSB) must be all zeros. To terminate reading

CFI data, the system must write the reset command.

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the

device to the read/reset mode.

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. SecSi Sector Protect Verify

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available online at

http://www.amd.com/flash/cfi. Alternatively, contact an

AMD representative for copies of these documents.

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

Table 6. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

January 6, 2003

Am29LV160M

19

A D V A N C E I N F O R M A T I O N

Table 7. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0007h

0000h

000Ah

0000h

0001h

0000h

0004h

0000h

V

_PPMin. voltage (00h = no V_PPpin present)

_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 8. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0080h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

001Eh

0000h

0001h

20

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

Table 9. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bit 1–0)

0b = Required, 1b = Not Required

45h

8Ah

0008h

Process Technology (Bits 7–2)

0010b = 0.23 µm MirrorBit

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Tables 10–11 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental era-

sure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

proper signals to the control pins to prevent uninten-

tional writes when V_CCis greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

January 6, 2003

Am29LV160M

21

A D V A N C E I N F O R M A T I O N

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Tables 10–11 define the valid register

command sequences. Note that writing incorrect

address and data values or writing them in the

improper sequence may place the device in an

unknown state. A reset command is then required to

set the device for the next operation.

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected. Ta-

bles 10–11 show the address and data requirements.

This method is an alternative to that shown in Table 4,

which is intended for PROM programmers and requires

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

V

_IDon address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command sequence.

After the device accepts an Erase Suspend com-

mand, the device enters the Erase Suspend mode.

The system can read array data using the standard

read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs

status data. After completing a programming opera-

tion in the Erase Suspend mode, the system may

once again read array data with the same exception.

See “Erase Suspend/Erase Resume Commands” for

more information on this mode.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h returns the

device code. A read cycle containing a sector address

(SA) and the address XX02h in word mode (or XX04h

in byte mode) returns XX01h if that sector is protected,

or 00h if it is unprotected. Refer to Tables 2 and 3 for

valid sector addresses.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Figure 13 shows the timing diagram.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or

timings. The device automatically generates the pro-

gram pulses and verifies the programmed cell margin.

Tables 10–11 show the address and data require-

ments for the byte program command sequence. Note

that the SecSi Sector, autoselect, and CFI functions

are unavailable when a program operation is in

progress.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

22

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

START

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command se-

quence should be reinitiated once the device has reset

to reading array data, to ensure data integrity.

Write Program

Command Sequence

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock by-

pass command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The de-

vice then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 10–11 show the requirements for the

command sequence.

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Tables 10–11 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Tables 10–11

show the address and data requirements for the chip

erase command sequence. Note that the SecSi Sec-

tor, autoselect, and CFI functions are unavailable

when an erase operation is in progress.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

Figure 4 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

January 6, 2003

Am29LV160M

23

A D V A N C E I N F O R M A T I O N

The system can determine the status of the erase op-

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

eration by using DQ7, DQ6, DQ2, or RY/BY#. See “Au-

toselect Command Sequence” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and

addresses are no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. (Refer to “Write Operation Status” for informa-

tion on these status bits.)

Figure 5 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to Figure 18 for

timing diagrams.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

Figure 18 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the ad-

dress of the sector to be erased, and the sector erase

command. Tables 10–11 show the address and data

requirements for the sector erase command sequence.

Note that the SecSi Sector, autoselect, and CFI func-

tions are unavailable when an erase operation is in

progress.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” for information on these

status bits.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector

Erase Timer” section.) The time-out begins from the ris-

ing edge of the final WE# pulse in the command se-

quence.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

24

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

START

Write Erase

Command Sequence

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Tables 10–11 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 5. Erase Operation

January 6, 2003

Am29LV160M

25

A D V A N C E I N F O R M A T I O N

The system must write the Program Resume com-

Program Suspend/Program Resume

Command Sequence

mand (address bits are don’t care) to exit the Program

Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ig-

nored. Another Program Suspend command can be

written after the device has resume programming.

The Program Suspend command allows the system to

interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from

any non-suspended sector. When the Program Sus-

pend command is written during a programming pro-

cess, the device halts the program operation within 15

µs maximum (5 µs typical) and updates the status bits.

Addresses are not required when writing the Program

Suspend command.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

After the programming operation has been sus-

pended, the system can read array data from any non-

suspended sector. The Program Suspend command

may also be issued during a programming operation

while an erase is suspended. In this case, data may

be read from any addresses not in Erase Suspend or

Program Suspend. If a read is needed from the SecSi

Sector area (One-time Program area), then user must

use the proper command sequences to enter and exit

this region.

Write address/data

XXXh/B0h

Command is also valid for

Erase-suspended-program

operations

Wait 15 µs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect

codes as required. When the device exits the autose-

lect mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See

Autoselect Command Sequence for more information.

Done

reading?

No

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

After the Program Resume command is written, the

device reverts to programming. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See Write Operation Status for more

information.

Device reverts to

operation prior to

Program Suspend

Figure 6. Program Suspend/Program Resume

26

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

Command Definitions

Table 10. Command Definitions (x16 Mode, BYTE# = V_IH)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

1

4

6

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

X03

0001

22C4

Device ID, Top Boot (Note 8)

Device ID, Bottom Boot (Note 8)

SecSi Sector Factory Protect

2249

(Note 9)

Sector Group Protect Verify

(Note 9)

4

555

AA

2AA

55

555

90

(SA)X02

00/01

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

2

6

1

555

XXX

555

BA

AA

A0

90

2AA

PA

55

PD

00

55

555

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

Chip Erase

XXX

2AA

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (Note 12)

Program/Erase Resume (Note 13)

CFI Query (Note 14)

BA

55

98

Legend:

X = Don’t care

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A19–A15 uniquely select any sector.

RA = Read Address of memory location to be read.

RD = Read Data read from location RA during read operation.

WBL = Write Buffer Location. Address must be within same write buffer

page as PA.

PA = Program Address . Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

WC = Word Count. Number of write buffer locations to load minus 1.

PD = Program Data for location PA. Data latches on rising edge of WE#

or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

8. Device ID must be read in three cycles.

2. All values are in hexadecimal.

9. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Shaded cells indicate read cycles. All others are write cycles.

10. Unlock Bypass command is required prior to Unlock Bypass

Program command.

4. During unlock and command cycles, when lower address bits are

555 or 2AA as shown in table, address bits above A11 and data

bits above DQ7 are don’t care.

11. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

5. No unlock or command cycles required when device is in read

mode.

12. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

6. Reset command is required to return to read mode (or to erase-

suspend-read mode if previously in Erase Suspend) when device

is in autoselect mode, or if DQ5 goes high while device is

providing status information.

13. Erase Resume command is valid only during Erase Suspend

mode.

7. Fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See Autoselect

Command Sequence section for more information.

14. Command is valid when device is ready to read array data or

when device is in autoselect mode.

January 6, 2003

Am29LV160M

27

A D V A N C E I N F O R M A T I O N

Table 11. Command Definitions (x8 Mode, BYTE# = V_IL)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

1

4

6

RA

RD

F0

XXX

AAA

AA

555

55

AAA

90

X00

X02

01

Device ID, Top Boot (Note 8)

C4

Device ID, Bottom Boot (Note

8)

6

4

AAA

AA

555

55

AAA

90

X02

X06

49

SecSi Sector Factory Protect

(Note 9)

00/01

Sector Group Protect Verify

(Note 9)

90 (SA)X04

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

2

6

1

AAA

XXX

AAA

BA

AA

A0

90

555

PA

55

PD

00

55

AAA

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

Chip Erase

XXX

555

AA

B0

30

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Program/Erase Suspend (Note 12)

Program/Erase Resume (Note 13)

CFI Query (Note 14)

BA

AA

98

Legend:

X = Don’t care

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A19–A15 uniquely select any sector.

RA = Read Address of memory location to be read.

RD = Read Data read from location RA during read operation.

WBL = Write Buffer Location. Address must be within same write buffer

page as PA.

PA = Program Address . Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

BC = Byte Count. Number of write buffer locations to load minus 1.

PD = Program Data for location PA. Data latches on rising edge of WE#

or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

8. Device ID must be read in three cycles.

2. All values are in hexadecimal.

9. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Shaded cells indicate read cycles. All others are write cycles.

10. Unlock Bypass command is required prior to Unlock Bypass

Program command.

4. During unlock and command cycles, when lower address bits are

555 or AAA as shown in table, address bits above A11 are don’t

care.

11. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

5. No unlock or command cycles required when device is in read

mode.

12. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

6. Reset command is required to return to read mode (or to erase-

suspend-read mode if previously in Erase Suspend) when device

is in autoselect mode, or if DQ5 goes high while device is

providing status information.

13. Erase Resume command is valid only during Erase Suspend

mode.

7. Fourth cycle of autoselect command sequence is a read cycle.

Data bits DQ15–DQ8 are don’t care. See Autoselect Command

Sequence section or more information.

14. Command is valid when device is ready to read array data or

when device is in autoselect mode.

28

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 12 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each offer a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

Table 12 shows the outputs for Data# Polling on DQ7.

Figure 7 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Figure 7. Data# Polling Algorithm

January 6, 2003

Am29LV160M

29

A D V A N C E I N F O R M A T I O N

Table 12 shows the outputs for Toggle Bit I on DQ6.

RY/BY#: Ready/Busy#

Figure 8 shows the toggle bit algorithm in flowchart

form, and the section “Reading Toggle Bits DQ6/DQ2”

explains the algorithm. Figure 20 in the “AC Character-

istics” section shows the toggle bit timing diagrams.

Figure 21 shows the differences between DQ2 and

DQ6 in graphical form. See also the subsection on

“DQ2: Toggle Bit II”.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel

with a pull-up resistor to V_CC

.

DQ2: Toggle Bit II

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 12 shows the outputs for RY/BY#. Figures 13, 14,

17 and 18 show RY/BY# for read, reset, program, and

erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 12 to compare

outputs for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. (The system may use either OE#

or CE# to control the read cycles.) When the operation

is complete, DQ6 stops toggling.

Figure 8 shows the toggle bit algorithm in flowchart

form, and the section “Reading Toggle Bits DQ6/DQ2”

explains the algorithm. See also the DQ6: Toggle Bit I

subsection. Figure 20 shows the toggle bit timing dia-

gram. Figure 21 shows the differences between DQ2

and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6

toggles for approximately 100 µs, then returns to

reading array data. If not all selected sectors are pro-

tected, the Embedded Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that

is, the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

30

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

the system must write the reset command to return to

reading array data.

START

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 8).

Read DQ7–DQ0

(Note 1)

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

(Notes

1, 2)

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

Figure 8. Toggle Bit Algorithm

January 6, 2003

Am29LV160M

31

A D V A N C E I N F O R M A T I O N

sectors are selected for erasure, the entire time-out also

DQ5: Exceeded Timing Limits

applies after each additional sector erase command.

When the time-out is complete, DQ3 switches from “0”

to “1.” The system may ignore DQ3 if the system can

guarantee that the time between additional sector

erase commands will always be less than 50 µs. See

also the “Sector Erase Command Sequence” section.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 12 shows the outputs for DQ3.

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If additional

Table 12. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Invalid (not allowed)

Data

1

Program

Suspend

Mode

Suspended Sector

Program-

Suspend Read

Non-Program

Suspended Sector

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

Erase

Suspend

Mode

Reading within Non-Erase Suspended

Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

32

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2). .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 9. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V_SS

to –2.0 V for periods of up to 20 ns. See Figure 9.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

During voltage transitions, input or I/O pins may

overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 10.

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is -0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V_SSto –2.0 V for periods of up

to 20 ns. See Figure 9. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

V_CC

+2.0 V

V_CC

+0.5 V

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Figure 10. Maximum Positive

Overshoot Waveform

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V_CCSupply Voltages

V_CCfor regulated voltage range . . . . . .3.0 V to 3.6 V

V_CCfor full voltage range . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

January 6, 2003

Am29LV160M

33

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

V

,

I_LI

I_LIT

I_LR

Input Load Current

V_CC= V_{CC max}

A9 Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

µA

V

_CC= V_{CC max}; RESET# =

12.5 V

35

µA

V

_OUT= V_SSto V_CC

_CC= V_{CC max}

,

I_LO

Output Leakage Current

±1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

15

2

30

10

30

10

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

15

2

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

I_CC3

I_CC4

CE# = V_IL,OE# = V_IH

40

0.4

0.8

60

5

mA

µA

V_CCStandby Current (Notes 2, 4) CE#, RESET# = V_CC±0.3 V

V_CCStandby Current During Reset

RESET# = V_SS± 0.3 V

(Notes 2, 4)

5

Automatic Sleep Mode

(Notes 2, 4, 6)

V_IH= V_CC± 0.3 V;

V_IL= V_SS± 0.3 V

I_CC5

0.4

5

µA

V_IL1

V_IH1

V_IL2

V_IH2

Input Low Voltage 1(6, 7)

Input High Voltage 1 (6, 7)

Input Low Voltage 2 (6, 8)

Input High Voltage 2 (6, 8)

–0.5

1.9

0.8

V

V_CC+ 0.5

0.3 x V_IO

V_IO+ 0.5

–0.5

1.9

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 3.3 V

11.5

12.5

0.45

V

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

V

I

_OH= -2.0 mA, V_CC= V_{CC min}

0.85 x V_CC

V_CC–0.4

2.3

Output High Voltage

I_OH= -100 µA, V_CC= V_{CC min}

Low V_CCLock-Out Voltage (Note 4)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH. Typical V_CCis 3.0 V.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

6. Not 100% tested.

7. V_CCvoltage requirements.

8. V_IOvoltage requirements.

34

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 13. Test Specifications

3.3 V

70R,

70

90R, 90,

120R, 120 Unit

Test Condition

Output Load

2.7 kΩ

Device

Under

Test

1 TTL gate

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–3.0

1.5

Input timing measurement

reference levels

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

1.5

Figure 11. Test Setup

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

January 6, 2003

Am29LV160M

35

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

70R,

70

90R,

90

120R,

120

JEDEC

Std

Description

Test Setup

Unit

t_AVAV

t_RC

Read Cycle Time (Note 1)

Address to Output Delay

Min

70

90

120

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACC

Max

70

120

ns

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

70

30

25

90

35

30

0

120

50

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

Read

Output Enable

t_OEH

Toggle and

Data# Polling

Hold Time (Note 1)

Min

10

0

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t_AXQX

t_OH

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 13 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read or Write (See Note)

t_READY

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RESET# High Time Before Read (See Note)

t_RPDRESET# Low to Standby Mode

t_RBRY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

70R,

70

90R,

90

120R,

120

JEDEC

Std

Description

Unit

ns

t

_ELFL/t_ELFH

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

t_FLQZ

t_FHQV

25

70

30

90

30

ns

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

BYTE#

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 16. BYTE# Timings for Write Operations

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January 6, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

70R,

70

90R,

90

120R,

120

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

90

0

120

t_AVWL

t_WLAX

t_DVWH

t_WHDX

ns

t_AH

45

35

45

0

50

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

0

ns

CE# Hold Time

t_WP

Write Pulse Width

Write Pulse Width High

35

50

t_WPH

30

Byte

TBD

0.4

50

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

Word

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

0

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

January 6, 2003

Am29LV160M

39

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

January 6, 2003

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41

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erase

Resume

Erasing

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect/Timing Diagram

January 6, 2003

Am29LV160M

43

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

70R,

70

90R,

90

120R,

120

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

90

0

120

t_AVEL

ns

t_ELAX

t_DVEH

t_EHDX

t_AH

45

35

45

0

50

ns

t_DS

ns

t_DH

t_OES

Data Hold Time

ns

Output Enable Setup Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

35

50

t_CPH

30

Byte

TBD

0.4

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

µs

Word

sec

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

January 6, 2003

Am29LV160M

45

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D_OUT= data written to the

device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

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Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

0.4

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

15

Excludes 00h programming

prior to erasure (Note 4)

25

s

Byte Programming Time

Word Programming Time

TBD

µs

s

TBD

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

TBD

Chip Programming Time

(Note 3)

TBD

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Tables 2–3 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

pF

C_OUT

Output Capacitance

Fine-pitch BGA

TSOP

6.5

9

pF

C_IN2

Control Pin Capacitance

Fine-pitch BGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

January 6, 2003

Am29LV160M

47

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

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Am29LV160M

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A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

January 6, 2003

Am29LV160M

49

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)

6 x 8 mm Package

Dwg rev AF; 10/99

50

Am29LV160M

January 6, 2003

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

January 6, 2003

Am29LV160M

51

A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Program Suspend/Program Resume Command

Sequence

Revision A (June 24, 2002)

Initial release.

Added text and flowchart.

Revision A + 1 (July 3, 2002)

Added LAA064 package.

Sector Protection/Unprotection

Deleted reference to alternate, high-voltage method of

sector protection.

Corrected power consumption currents.

Changed DC Characteristics Zero Power Flash tables

to TBD.

Command Definitions

Modified introductory paragraph to indicate device

behavior when presented with incorrect commands

and data. Added mode restrictions to first paragraphs

of program, sector erase and chip erase subsections.

Corrected minimum erase and program cycle endur-

ance.

Revision A+2 (December 6, 2002)

Command Definitions tables

Global

Replaced previous table with two tables. Byte mode

and word mode are now shown seperately. Added

SecSi Sector Factory Protect command sequence.

Removed 44-pin SO package. Deleted dashes from

ordering part numbers.

Distinctive Characteristics

Table 10. Write Operation Status

Added information for SecSi sector, Program Suspend

& Resume. Corrected erase endurance to 100K cycles.

Changed section flow to match other MirrorBit data

sheets.

Added Program Suspend Mode rows to table.

BGA and TSOP Capacitance

Added fine-pitch BGA capacitance to table.

General Description

AC Characteristics tables

Changed section flow to match other MirrorBit data

sheets.

Typical sector erase time is now 0.4 s in all tables.

Physical Dimensions

Connection Diagrams

Corrected Fortified BGA drawing to FBA048.

Corrected Fortified BGA diagram: balls C5, D8, D4,

and F1 are now NC.

Revision A+3 (January 6, 2003)

Global

Ordering Information and Operating Ranges

Deleted references to WP# and ACC. The

Am29LV160M does not offer those features.

Removed Commercial and Extended temperature

ranges. Corrected Fine-pitch BGA type to 6 x 8 mm

package, FBA048.

Command Definitions table

Added package markings for the LAA064.

Deleted references to write buffers. This device does

not offer that feature.

SecSi (Secured Silicon) Sector Flash

Memory Region

AC Characteristics

Added section.

Erase and Program Operations table; Alternate CE#

Controlled Erase/Operations table: Changed t_WHWH1

to TBD.

Trademarks

AMD, the AMD logo, MirrorBit^TMand combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

52

Am29LV160M

January 6, 2003


型号：	AM29LV160MB-70PCF
厂家：	SPANSION
描述：	Flash, 1MX16, 70ns, PBGA64, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64
文件：	总53页 (文件大小：1280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV160MB-70PCF [SPANSION]

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