M750000009_技术文档

ADVANCE INFORMATION

Am75PDL191CHH/Am75PDL193CHH

128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory

with Enhanced Versatile I/O Control and Dual Chip Enable Input plus, for Additional Code

or Data Storage, 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write

Flash Memory and 64 Mbit (4 M x 16-Bit)

CMOS Pseudo Static RAM

DISTINCTIVE CHARACTERISTICS

■ Both top and bottom boot blocks in one device

For Code Storage:

Am29PDL127H/Am29PDL129H Features

■ Manufactured on 0.13 µm process technology

■ 20-year data retention at 125°C

ARCHITECTURAL ADVANTAGES

■ Minimum 1 million erase cycle guarantee per sector

■ 128 Mbit Page Mode device

PERFORMANCE CHARACTERISTICS

—

Page size of 8 words: Fast page read access from random

locations within the page

■ High Performance

■ Dual Chip Enable inputs (PDL129 only)

—

Page access times as fast as 30 ns

Random access times as fast as 70 ns

—

Two CE inputs control selection of each half of the memory

space

■ Power consumption (typical values at 10 MHz)

■ Single power supply operation

—

45 mA active read current

25 mA program/erase current

1 µA typical standby mode current

—

Full Voltage range: 2.7 to 3.3 volt read, erase, and program

operations for battery-powered applications

■ Simultaneous Read/Write Operation

SOFTWARE FEATURES

—

Data can be continuously read from one bank while

executing erase/program functions in another bank

Zero latency switching from write to read operations

■ Software command-set compatible with JEDEC 42.4

—

standard

—

Backward compatible with Am29F and Am29LV families

■ FlexBank Architecture

4 separate banks, with up to two simultaneous operations

per device

PDL127:

—

■ CFI (Common Flash Interface) complaint

—

Provides device-specific information to the system, allowing

host software to easily reconfigure for different Flash devices

—

Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank B: 48 Mbit (32 Kw x 96)

Bank C: 48 Mbit (32 Kw x 96)

Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

■ Erase Suspend / Erase Resume

—

Suspends an erase operation to allow read or program

operations in other sectors of same bank

■ Unlock Bypass Program command

PDL129:

—

Reduces overall programming time when issuing multiple

program command sequences

—

Bank 1A: 48 Mbit (32 Kw x 96)

Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 2B: 48 Mbit (32 Kw x 96)

■ SecSi^TM(Secured Silicon) Sector region

—

Up to 128 words accessible through a command sequence

Up to 64 factory-locked words

Up to 64 customer-lockable words

Publication# 31096 Rev: A Amendment 1

Issue Date: February 5, 2004

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E I N F O R M A T I O N

— Pinout and software compatible with

HARDWARE FEATURES

single-power-supply flash standard

■ Ready/Busy# pin (RY/BY#)

—

Provides a hardware method of detecting program or erase

cycle completion

PERFORMANCE CHARACTERISTICS

■ High performance

■ Hardware reset pin (RESET#)

Hardware method to reset the device to reading array data

■ WP#/ACC (Write Protect/Acceleration) input

— Access time as fast as 70 ns

—

— Program time: 4 µs/word typical utilizing Accelerate

function

—

At V_IL, hardware level protection for the first and last two 4K

word sectors.

■ Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

—

At V_IH, allows removal of sector protection

At V_HH, provides accelerated programming in a factory

setting

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■ Persistent Sector Protection

■ Minimum 1 million erase cycles guaranteed per

sector

■ 20 year data retention at 125°C

— Reliable operation for the life of the system

—

A command sector protection method to lock combinations

of individual sectors and sector groups to prevent program or

erase operations within that sector

—

Sectors can be locked and unlocked in-system at V_CClevel

■ Password Sector Protection

SOFTWARE FEATURES

—

A sophisticated sector protection method to lock

combinations of individual sectors and sector groups to

prevent program or erase operations within that sector using

a user-defined 64-bit password

■ Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

FOR CODE OR DATA STORAGE:

AM29DL640H

■ Supports Common Flash Memory Interface (CFI)

■ Erase Suspend/Erase Resume

■ Simultaneous Read/Write operations

— Suspends erase operations to allow reading from

other sectors in same bank

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

— Zero latency between read and write operations

■ Flexible Bank^TMarchitecture

— Read may occur in any of the three banks not being

written or erased.

■ Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

— Four banks may be grouped by customer to achieve

desired bank divisions.

HARDWARE FEATURES

■ Boot Sectors

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

— Top and bottom boot sectors in the same device

— Any combination of sectors can be erased

■ Manufactured on 0.13 µm process technology

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte

sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

■ WP#/ACC input pin

— Write protect (WP#) function protects sectors 0, 1,

140, and 141, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

— Customer lockable: One-time programmable only.

Once locked, data cannot be changed

■ Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

■ Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero.

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

■ Compatible with JEDEC standards

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Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

PSRAM FEATURES

■ Organized as 4,194,304 words by 16 bits

■ Single power supply voltage of 2.7 to 3.3 V

■ Direct TTL compatibility for all inputs and outputs

■ Deep power-down mode: Memory cell data invalid

■ Page operation mode:

■ 8-word Page read operation

■ Logic compatible with SRAM R/W (WE) pin

■ Standby current

—

Standby 100 µA

Deep power-down standby 5 µA

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

3

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION (PDL129)

The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device orga-

nized as 8 Mwords. The word-wide data (x16) appears on

DQ15-DQ0. This device can be programmed in-system or in

standard EPROM programmers. A 12.0 V V_PPis not required

for write or erase operations.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

The device offers fast page access time of 25 and 30 ns,

with corresponding random access times of 65 and 85 ns,

respectively, allowing high speed microprocessors to oper-

ate without wait states. To eliminate bus contention the de-

vice has separate chip enable (CE#f1, CE#f2), write enable

(WE#) and output enable (OE#) controls. Dual Chip Enables

allow access to two 64 Mbit partitions of the 128 Mbit mem-

ory space.

Device programming occurs by executing the program com-

mand sequence. The Unlock Bypass mode facilitates faster

programming times by requiring only two write cycles to pro-

gram data instead of four. Device erasure occurs by execut-

ing the erase command sequence.

The host system can detect whether a program or erase op-

eration is complete by reading the DQ7 (Data# Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or ac-

cept another command.

Simultaneous Read/Write Operation with

Zero Latency

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into 4

banks, which can be considered to be four separate memory

arrays as far as certain operations are concerned. The de-

vice can improve overall system performance by allowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with two simultaneous operations operating at any

one time). This releases the system from waiting for the

completion of a program or erase operation, greatly improv-

ing system performance.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or

via programming equipment.

The device can be organized in both top and bottom sector

configurations. The banks are organized as follows:

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

Chip Enable Configuration

CE#f1 Control

CE#f2 Control

Bank 1A

Bank 2A

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Bank 1B

Bank 2B

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

Page Mode Features

The page size is 8 words. After initial page access is accom-

plished, the page mode operation provides fast read access

speed of random locations within that page.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

Standard Flash Memory Features

AMD’s Flash technology combined years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

The device requires a single 3.0 volt power supply (2.7 V

to 3.3 V) for both read and write functions. Internally gener-

ated and regulated voltages are provided for the program

and erase operations.

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Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION (PDL127)

The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device orga-

nized as 8 Mwords. The word-wide data (x16) appears on

DQ15-DQ0. This device can be programmed in-system or in

standard EPROM programmers. A 12.0 V V_PPis not required

for write or erase operations.

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

The device offers fast page access time of 25 and 30 ns,

with corresponding random access times of 65 and 85 ns,

respectively, allowing high speed microprocessors to oper-

ate without wait states. To eliminate bus contention the de-

vice has separate chip enable (CE#f1), write enable (WE#)

and output enable (OE#) controls. Simultaneous Read/Write

Operation with Zero Latency

Device programming occurs by executing the program com-

mand sequence. The Unlock Bypass mode facilitates faster

programming times by requiring only two write cycles to pro-

gram data instead of four. Device erasure occurs by execut-

ing the erase command sequence.

The host system can detect whether a program or erase op-

eration is complete by reading the DQ7 (Data# Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or ac-

cept another command.

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into 4

banks, which can be considered to be four separate memory

arrays as far as certain operations are concerned. The de-

vice can improve overall system performance by allowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with two simultaneous operations operating at any

one time). This releases the system from waiting for the

completion of a program or erase operation, greatly improv-

ing system performance.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or

via programming equipment.

The device can be organized in both top and bottom sector

configurations. The banks are organized as follows:

Bank

Sectors

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

A

B

C

D

16 Mbit (4 Kw x 8 and 32 Kw x 31)

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

Page Mode Features

The page size is 8 words. After initial page access is accom-

plished, the page mode operation provides fast read access

speed of random locations within that page.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V

to 3.3 V) for both read and write functions. Internally gener-

ated and regulated voltages are provided for the program

and erase operations.

AMD’s Flash technology combined years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

5

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION (DL640)

The Am29DL640H is a 64 megabit, 3.0 volt-only flash

memory device, organized as 4,194,304 words of 16

bits each or 8,388,608 bytes of 8 bits each. Word

mode data appears on DQ15–DQ0; byte mode data

appears on DQ7–DQ0. The device is designed to be

programmed in-system with the standard 3.0 volt V_CC

supply, and can also be programmed in standard

EPROM programmers.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

other flash sector, or may permanently lock their own

code there.

The device is available with an access time of 70, 90,

or 120 ns and is offered in 48-pin TSOP, 63-ball

Fine-Pitch BGA, and 64-ball Fortified BGA packages.

Standard control pins—chip enable (CE#), write en-

able (WE#), and output enable (OE#)—control normal

read and write operations, and avoid bus contention

issues.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into four banks, two 8 Mb banks with small and

large sectors, and two 24 Mb banks of large sectors.

Sector addresses are fixed, system software can be

used to form user-defined bank groups.

During an Erase/Program operation, any of the three

non-busy banks may be read from. Note that only two

banks can operate simultaneously. The device can im-

prove overall system performance by allowing a host

system to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system from

waiting for the completion of program or erase

operations.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The Am29DL640H can be organized as both a top and

bottom boot sector configuration.

Bank

Megabits

Sector Sizes

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 1

8 Mb

Bank 2

Bank 3

24 Mb

Forty-eight 64 Kbyte/32 Kword

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

Eight 8 Kbyte/4 Kword,

Fifteen 64 Kbyte/32 Kword

Bank 4

8 Mb

Am29DL640H Features

The SecSi™ (Secured Silicon) Sector is an extra

256 byte sector capable of being permanently locked

by AMD or customers. The SecSi Customer Indica-

tor Bit (DQ6) is permanently set to a 1 if the part has

been customer locked, permanently set to 0 if the part

has been factory locked, and is 0 if customer lock-

able. This way, customer lockable parts can never be

used to replace a factory locked part.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

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Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Pseudo SRAM Memory

The pSRAM device is a 64 Mbit pseudo static random

access memory (PSRAM) organized as 4,194,304

words by 16 bits. The device operates a single power

supply. The device also features SRAM-like W/R tim-

ing whereby the device is controlled by CE1#, OE#,

and WE# on anynchronous. The device also supports

deep power-down mode, realizing low-power standby.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

7

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . 11

MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 12

Connection Diagram–PDL127 . . . . . . . . . . . . . . . 13

Special Package Handling Instructions .................................. 13

Connection Diagram–PDL129 . . . . . . . . . . . . . . . 14

Special Package Handling Instructions .................................. 14

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 16

Am29PDL127H/AM29PDL129H Device Bus Operations ....... 17

Table 1. Device Bus Operations ..................................................... 18

Requirements for Reading Array Data ................................... 19

Random Read (Non-Page Read) ........................................ 19

Page Mode Read ................................................................ 19

Table 2. Page Select .......................................................................19

Simultaneous Operation ......................................................... 19

Table 3. Bank Select (PDL129H) ....................................................19

Table 4. Bank Select (PDL127H) ....................................................19

Writing Commands/Command Sequences ............................ 20

Accelerated Program Operation .......................................... 20

Autoselect Functions ........................................................... 20

Standby Mode ........................................................................ 20

Automatic Sleep Mode ........................................................... 20

RESET#: Hardware Reset Pin ............................................... 21

Output Disable Mode .............................................................. 21

Table 5. SecSi^TMSector Addresses ................................................21

Table 6. Am29PDL127H Sector Architecture ..................................22

Table 7. Am29PDL129H Sector Architecture ..................................29

Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................37

Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection

SecSi Sector Protection Bits ................................................ 46

Hardware Data Protection ...................................................... 46

Low VCC Write Inhibit ......................................................... 46

Write Pulse “Glitch” Protection ............................................ 46

Logical Inhibit ....................................................................... 46

Power-Up Write Inhibit ......................................................... 46

Common Flash Memory Interface (CFI) . . . . . . . 46

Table 12. CFI Query Identification String........................................ 47

System Interface String................................................................... 47

Table 14. Device Geometry Definition ............................................ 48

Table 15. Primary Vendor-Specific Extended Query ...................... 49

Command Definitions . . . . . . . . . . . . . . . . . . . . . 50

Reading Array Data ................................................................ 50

Reset Command ..................................................................... 50

Autoselect Command Sequence ............................................ 50

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 51

Word Program Command Sequence ...................................... 51

Unlock Bypass Command Sequence .................................. 51

Figure 4. Program Operation ......................................................... 52

Chip Erase Command Sequence ........................................... 52

Sector Erase Command Sequence ........................................ 52

Figure 5. Erase Operation.............................................................. 53

Erase Suspend/Erase Resume Commands ........................... 53

Password Program Command ................................................ 53

Password Verify Command .................................................... 54

Password Protection Mode Locking Bit Program Command .. 54

Persistent Sector Protection Mode Locking Bit Program Com-

mand ....................................................................................... 54

SecSi Sector Protection Bit Program Command .................... 54

PPB Lock Bit Set Command ................................................... 54

DYB Write Command ............................................................. 54

Password Unlock Command .................................................. 55

PPB Program Command ........................................................ 55

All PPB Erase Command ........................................................ 55

DYB Write Command ............................................................. 55

PPB Lock Bit Set Command ................................................... 55

PPB Status Command ............................................................ 55

PPB Lock Bit Status Command .............................................. 55

Sector Protection Status Command ....................................... 55

Command Definitions Tables .................................................. 56

Table 16. Memory Array Command Definitions ............................. 56

Table 17. Sector Protection Command Definitions ........................ 57

Write Operation Status . . . . . . . . . . . . . . . . . . . . 58

DQ7: Data# Polling ................................................................. 58

Figure 6. Data# Polling Algorithm .................................................. 58

RY/BY#: Ready/Busy# ............................................................ 59

DQ6: Toggle Bit I .................................................................... 59

Figure 7. Toggle Bit Algorithm........................................................ 59

DQ2: Toggle Bit II ................................................................... 60

Reading Toggle Bits DQ6/DQ2 ............................................... 60

DQ5: Exceeded Timing Limits ................................................ 60

CE#f1 Control ..................................................................................38

Table 10. Am29PDL129H Boot Sector/Sector Block Addresses for

Protection/Unprotection

CE#f2 Control ..................................................................................38

Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . 39

Persistent Sector Protection ................................................... 39

Persistent Protection Bit (PPB) ............................................ 39

Persistent Protection Bit Lock (PPB Lock) .......................... 39

Dynamic Protection Bit (DYB) ............................................. 39

Table 11. Sector Protection Schemes .............................................40

Persistent Sector Protection Mode Locking Bit ................... 40

Password Protection Mode ..................................................... 40

Password and Password Mode Locking Bit ........................ 41

64-bit Password ................................................................... 41

Write Protect (WP#) ................................................................ 41

Persistent Protection Bit Lock .............................................. 41

High Voltage Sector Protection .............................................. 42

Figure 1. In-System Sector Protection/

Sector Unprotection Algorithms ...................................................... 43

Temporary Sector Unprotect .................................................. 44

Figure 2. Temporary Sector Unprotect Operation........................... 44

SecSi™ (Secured Silicon) Sector

DQ3: Sector Erase Timer ....................................................... 60

Table 18. Write Operation Status ................................................... 61

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 62

Figure 8. Maximum Negative Overshoot Waveform ...................... 62

Figure 9. Maximum Positive Overshoot Waveform........................ 62

Flash Memory Region ............................................................ 44

Factory-Locked Area (64 words) ......................................... 44

Customer-Lockable Area (64 words) ................................... 44

Figure 3. SecSi Protection Algorithm .............................................. 45

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Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

ESD Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 64

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 10. Test Setup..................................................................... 65

Figure 11. Input Waveforms and Measurement Levels .................. 65

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 66

CE#1ps Timing ....................................................................... 66

Figure 12. Timing Diagram for Alternating

Flash Memory Region ............................................................. 90

Figure 3. SecSi Sector Protect Verify............................................. 91

Hardware Data Protection ...................................................... 91

Low VCC Write Inhibit ......................................................... 91

Write Pulse “Glitch” Protection ............................................ 91

Logical Inhibit ....................................................................... 91

Power-Up Write Inhibit ......................................................... 91

Common Flash Memory Interface (CFI) . . . . . . . 91

Table 7. CFI Query Identification String.......................................... 92

System Interface String................................................................... 92

Table 9. Device Geometry Definition .............................................. 93

Table 10. Primary Vendor-Specific Extended Query ...................... 94

Command Definitions . . . . . . . . . . . . . . . . . . . . . 95

Between Pseudo SRAM and Flash................................................. 66

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67

Read-Only Operations – Am29PDL127H ............................... 67

Read-Only Operations – Am29PDL129H ............................... 67

Figure 13. Read Operation Timings................................................ 68

Figure 14. Page Read Operation Timings....................................... 68

Hardware Reset (RESET#) .................................................... 69

Figure 15. Reset Timings................................................................ 69

Erase and Program Operations .............................................. 70

Figure 16. Program Operation Timings........................................... 71

Figure 17. Accelerated Program Timing Diagram........................... 71

Figure 18. Chip/Sector Erase Operation Timings ........................... 72

Figure 19. Back-to-back Read/Write Cycle Timings ....................... 73

Figure 20. Data# Polling Timings (During Embedded Algorithms).. 73

Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 74

Figure 22. DQ2 vs. DQ6.................................................................. 74

Temporary Sector Unprotect .................................................. 75

Figure 23. Temporary Sector Unprotect Timing Diagram ............... 75

Figure 24. Sector/Sector Block Protect and

Reading Array Data ................................................................ 95

Reset Command ..................................................................... 95

Autoselect Command Sequence ............................................ 95

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 95

Word Program Command Sequence ...................................... 96

Unlock Bypass Command Sequence .................................. 96

Figure 4. Program Operation ......................................................... 97

Chip Erase Command Sequence ........................................... 97

Sector Erase Command Sequence ........................................ 97

Figure 5. Erase Operation.............................................................. 98

Erase Suspend/Erase Resume Commands ........................... 98

Table 11. Am29DL640H Command Definitions .............................. 99

Write Operation Status . . . . . . . . . . . . . . . . . . . 100

DQ7: Data# Polling ...............................................................100

Figure 6. Data# Polling Algorithm ................................................ 100

RY/BY#: Ready/Busy# .......................................................... 101

DQ6: Toggle Bit I ..................................................................101

Figure 7. Toggle Bit Algorithm...................................................... 101

DQ2: Toggle Bit II ................................................................. 102

Reading Toggle Bits DQ6/DQ2 .............................................102

DQ5: Exceeded Timing Limits .............................................. 102

DQ3: Sector Erase Timer ..................................................... 102

Table 12. Write Operation Status ................................................. 103

Absolute Maximum Ratings . . . . . . . . . . . . . . . 104

Figure 8. Maximum Negative Overshoot Waveform .................... 104

Figure 9. Maximum Positive Overshoot Waveform...................... 104

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 10. I_CC1Current vs. Time (Showing Active and

Automatic Sleep Currents)........................................................... 106

Figure 11. Typical I_CC1vs. Frequency.......................................... 106

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 12. Test Setup.................................................................. 107

Figure 13. Input Waveforms and Measurement Levels ............... 107

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108

Unprotect Timing Diagram .............................................................. 76

Alternate CE# Controlled Erase and Program Operations ..... 77

Figure 25. Flash Alternate CE# Controlled Write (Erase/Program)

Operation Timings........................................................................... 78

Erase And Programming Performance . . . . . . . . 79

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 79

Package Pin Capacitance . . . . . . . . . . . . . . . . . . 79

Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 79

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 80

Table 1. Am29DL640H Device Bus Operations ..............................80

Word/Byte Configuration ........................................................ 80

Requirements for Reading Array Data ................................... 80

Writing Commands/Command Sequences ............................ 81

Accelerated Program Operation .......................................... 81

Autoselect Functions ........................................................... 81

Simultaneous Read/Write Operations with Zero Latency ....... 81

Standby Mode ........................................................................ 81

Automatic Sleep Mode ........................................................... 81

RESET#: Hardware Reset Pin ............................................... 82

Output Disable Mode .............................................................. 82

Table 2. Am29DL640H Sector Architecture ....................................82

Table 3. Bank Address ....................................................................85

SecSi^TMSector Addresses.............................................................. 85

Autoselect Mode ..................................................................... 85

Sector/Sector Block Protection and Unprotection .................. 87

Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................87

Write Protect (WP#) ................................................................ 87

Table 6. WP#/ACC Modes ..............................................................88

Temporary Sector Unprotect .................................................. 88

Figure 1. Temporary Sector Unprotect Operation........................... 88

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 89

SecSi™ (Secured Silicon) Sector

Read-Only Operations .........................................................108

Figure 14. Read Operation Timings............................................. 108

Hardware Reset (RESET#) .................................................. 109

Figure 15. Reset Timings............................................................. 109

Erase and Program Operations ............................................110

Figure 16. Program Operation Timings........................................ 111

Figure 17. Accelerated Program Timing Diagram........................ 111

Figure 18. Chip/Sector Erase Operation Timings ........................ 112

Figure 19. Back-to-back Read/Write Cycle Timings .................... 113

Figure 20. Data# Polling Timings (During Embedded Algorithms) 113

Figure 21. Toggle Bit Timings (During Embedded Algorithms).... 114

Figure 22. DQ2 vs. DQ6............................................................... 114

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

9

A D V A N C E I N F O R M A T I O N

Temporary Sector Unprotect ................................................ 115

Figure 23. Temporary Sector Unprotect Timing Diagram ............. 115

Figure 24. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................ 116

Alternate CE# Controlled Erase and Program Operations ... 117

Figure 25. Alternate CE# Controlled Write (Erase/Program)

Operation Timings......................................................................... 118

Erase And Programming Performance . . . . . . . 119

Latchup Characteristics . . . . . . . . . . . . . . . . . . 119

PSRAM AC Characteristics . . . . . . . . . . . . . . . . 120

CE#s Timing ......................................................................... 120

Figure 26. Timing Diagram for Alternating

Between Pseudo SRAM to Flash.................................................. 120

Figure 27. Timing Waveform of Power-up .................................... 120

pSRAM AC CHaracteristics . . . . . . . . . . . . . . . . 121

Absolute Maximum Ratings .................................................. 121

DC Recommended Operating Conditions (Ta = -25oC to 85oC)

121

DC Characteristics (Ta = -25oC to 85oC, VDD = 2.6 to 3.3 V) ..

122

Capacitance (Ta = -25oC, f = 1 MHz) .................................. 122

AC Characteristics and Operating Conditions ...................... 123

AC Test Conditions ............................................................... 124

Timing Diagrams ................................................................... 125

Page Read Cycle (8 words access) ......................................125

Write Cycle 1 ........................................................................ 126

Write Cycle 2 ........................................................................ 126

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . 128

FMB073—73-Ball Fine-Pitch Grid Array 9 x 12 mm ............. 128

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . 129

Functional Description .......................................................... 121

10

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Am29PDL129H

70

Speed Option

V_CC, V_IO= 2.7–3.3 V

Max Access Time, ns (t_ACC

)

70

30

Max CE# Access, ns (t_CE

Max Page Access, ns (t_PACC

)

Max OE# Access, ns (t_OE

)

Part Number

Am29DL640H

Speed Option

Standard Voltage Range: V_CC= 2.7–3.3 V

70

30

Max Access Time (ns), t_ACC

CE# Access (ns), t_CE

OE# Access (ns), t_OE

Part Number

pSRAM

70

Speed Option

Standard Voltage Range: V_CC= 2.7–3.3 V

Max Access Time, ns (t_ACC

Max CE# Access, ns (t_CE

Max OE# Access, ns (t_OE

Page Access, ns (t_AA

)

70

)

pSRAM

)

25

30

)

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

11

A D V A N C E I N F O R M A T I O N

MCP BLOCK DIAGRAM

V_CC

V_SS

A0 to A21

(A22 PDL127 Only)

A0 to A21 (A22)

Am29PDL127H

or

Am29PDL129H

CE#f1

CE#f2

DQ0 to DQ15

V

_IO= V_CC

DQ0 to DQ15

V_CC

V_SS

A0 to A21

Am29DL640G

WP#/ACC

OE#

DQ0 to DQ15

CE#f3

WE#

RESET#

V_SSA

V_SS

A0 to A21

64 Mb

CE#1ps

CE2ps

pSRAM

_CC= V_CCQ

DQ0 to DQ15

V

UB#

LB#

V_CCps

V_CC

V_SSQ

12

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAM–PDL127

73-Ball FBGA

Top View

A1

A10

DL640G Only

NC

Pseudo

SRAM Only

B1

B5

CE#f3

C5

B6

B10

NC

Flash Shared Only

PDL127H Only

C1

C3

C4

C6

C7

C8

NC

A7

LB# WP#/ACC WE#

A8

A11

D2

A3

D3

A6

D4

D5

D6

D7

A19

E7

A9

D8

A12

E8

A13

F8

D9

A15

E9

A21

F9

UB# RESET# CE2ps

E5

E2

A2

E3

A5

E4

E6

A18 RY/BY# A20

F1

NC

G1

NC

F2

A1

F3

A4

F4

A17

G4

DQ1

F7

F10

A10

G7

DQ6

H7

A14

G8

NC

A22

NC

G2

A0

G3

G9 G10

V

SS

A16

H9

NC

J9

NC

H2

CE#f1

J2

H3

OE#

J3

H4

DQ9

J4

H5

DQ3

J5

H6

DQ4

J6

H8

DQ13 DQ15

J7

DQ12

K7

J8

DQ7

K8

V

CC

f

V

CC

ps

CE#1ps DQ0

DQ10

K4

V

SS

K3

K5

DQ11

L5

K6

NC

L6

NC

DQ8

DQ2

DQ5

DQ14

L1

NC

M1

NC

L10

NC

M10

NC

exposed to temperatures above 150°C for prolonged

periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (BGA). The package and/or data

integrity may be compromised if the package body is

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

13

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAM–PDL129

73-Ball FBGA

Top View

DL640G Only

A1

A10

NC

Pseudo

SRAM Only

B1

B5

CE#f3

C5

B6

B10

NC

Flash Shared Only

PDL129 Only

C1

C3

C4

C6

C7

C8

NC

A7

LB# WP#/ACC WE#

A8

A11

D2

A3

D3

A6

D4

D5

D6

D7

A19

E7

A9

D8

A12

E8

A13

F8

D9

A15

E9

UB# RESET# CE2ps

E5

E2

A2

E3

A5

E4

E6

A18 RY/BY# A20

A21

F9

F1

NC

G1

NC

F2

A1

F3

A4

F4

A17

G4

DQ1

F7

F10

A10

G7

DQ6

H7

A14

G8

NC

CE#f2

NC

G2

A0

G3

G9 G10

V

SS

A16

H9

NC

J9

NC

H2

CE#f1

J2

H3

OE#

J3

H4

DQ9

J4

H5

DQ3

J5

H6

DQ4

J6

H8

DQ13 DQ15

J7

DQ12

K7

J8

DQ7

K8

V

CC

f

V ps

CC

CE#1ps DQ0

DQ10

K4

V

SS

K3

K5

DQ11

L5

K6

NC

L6

NC

DQ8

DQ2

DQ5

DQ14

L1

NC

M1

NC

L10

NC

M10

NC

integrity may be compromised if the package body is

exposed to temperatures above 150°C for prolonged

periods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (BGA). The package and/or data

14

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

WP/ACC#= 12V, program and erase

PIN DESCRIPTION

A21–A0

operations are accelerated.

= 22 Address Inputs (Common)

V_CC

f

= Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

A22

=

Address Input (PDL127 only)

(Flash)

DQ15–DQ0

CE#f1

= 16 Data Inputs/Outputs (Common)

= Chip Enable 1 (Flash) (PDL 127

only)

V_CC

V_SS

NC

s

= pSRAM Power Supply

= Device Ground (Common)

= Pin Not Connected Internally

CE#f1, CE#f2 = Chip Enable Inputs. CE#f1 controls

the 64 Mb in Banks 1A and 1B.

CE#f2 controls the 64 Mb in Banks

2A and 2B.

LOGIC SYMBOL

22

CE#1ps

= Chip Enable 1 (pSRAM) (PDL129

only)

A21–A0

CE2ps

OE#

= Chip Enable 2 (pSRAM)

= Output Enable (Common)

= Write Enable (Common)

A22 (PDL127 Only)

CE#f1

16

WE#

DQ15–DQ0

RY/BY#

= Ready/Busy Output and open drain.

When RY/BY# = V_IH, the device is

ready to accept read operations and

CE#f2 (PDL129 Only)

CE#1ps

commands. When RY/BY# = V_OL

,

CE2ps

RY/BY#

the device is either executing an em-

bedded algorithm or the device is

executing a hardware reset opera-

tion.

OE#

WE#

UB#s

= Upper Byte Control (pSRAM)

= Lower Byte Control (pSRAM)

= Hardware Reset Pin, Active Low

WP#/ACC

LB#s

RESET#

UB#s

RESET#

WP#/ACC

= Write Protect/Acceleration Input.

When WP/ACC#= V_IL, the highest

and lowest two 4K-word sectors are

write protected regardless of other

sector protection configurations.

When WP/ACC#= V_IH, these sector

are unprotected unless the DYB or

PPB is programmed. When

LB#s

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

15

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following:

Am75PDL19 70

1

C

H

N

TEMPERATURE RANGE

Light Industrial (–25°C to +85°C)

N

=

SPEED OPTION

See “Product Selector Guide” on page 5.

PROCESS TECHNOLOGY OF AM29DL640

H

=

0.13 µm

PROCESS TECHNOLOGY OF AM29PDL127/129

0.13 µm

H

=

PSEUDO SRAM DEVICE DENSITY

64 Mbits

C

=

CONTROL PINS

1

3

=

1 CE Flash

2 CE Flash

AMD DEVICE NUMBER/DESCRIPTION

Am75PDL191CHH/Am75PDL193CHH

Am29PDL127H/129H–128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous

Operation Flash Memory, One Chip Enable Input on Am29PDL127H, Dual Chip Enable

Inputs on Am29PDL129H

Am29DL640H–64 Megabit (4M x 16-Bit) CMOS Flash Memory

64 Mb pSRAM

Valid Combinations

Valid Combinations for BGA Packages

Valid Combinations list configurations planned to be supported in vol-

ume for this device. Consult the local AMD sales office to confirm

availability of specific valid combinations and to check on newly re-

leased combinations.

Order Number

Am75PDL191CHH70I

Am75PDL193CHH70I

Package Marking

M750000008

M750000009

V_IORange

2.7–3.3 V

16

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Am29PDL127H/AM29PDL129H Device Bus Operations

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Tables 1-2 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

17

A D V A N C E I N F O R M A T I O N

Table 1. Device Bus Operations

CE#f2

LB#s UB#s

(Note (Note RESET#

WP#/

ACC

(Note 4)

Operation

(Notes 1, 2)

CE#f1

Active

DQ7– DQ15–

(PDL129 CE#1ps CE2ps OE# WE#

only)

Addr.

DQ0

DQ8

3)

(Note 7)

(Note 8)

(Note 7)

(Note 8)

H

L

Read from

Active Flash

A_IN

D_OUT

L (H)

H (L)

L

H

L

X

H

L/H

H

L

Write to Active

Flash

D_IN

H

X

(Note 4)

V_CC

0.3 V

V_CC0.3 V

Standby

H

L

X

H

High-Z High-Z

V_CC

Deep Power-down

Standby

0.3 V

H

X

Output Disable (Note 9)

L (H)

H (L)

L

H

L

L/H

High-Z High-Z

(Note 7)

H

L

Flash Hardware

Reset

X

(Note 8)

(Note 7)

H

SADD,

A6 = L,

A1 = H,

A0 = L

Sector Protect

(Notes 6, 10)

V_ID

D_IN

L (H)

H (L)

H

L

X

L/H

X

(Note 9)

(Note 7)

(Note 8)

H

L

H

L

SADD,

A6 = H,

A1 = H,

A0 = L

Sector

Unprotect

(Notes 5, 9)

V_ID

D_IN

H

X

L

X

H

X

(Note 6)

X

Temporary

Sector

Unprotect

(Note 7)

(Note 8)

H

L

V_ID

D_IN

X

High-Z

D_OUT

L

H

L

A_IN

Read from pSRAM

Write to pSRAM

H

L

H

High-Z

D_OUT

D_IN

H

L

High-Z

D_IN

L

A_IN

D_IN

X

L

H

L

X

High-Z

D_IN

H

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 9.0 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A_IN

=

Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Other operations except for those indicated in this column are

6. If WP#/ACC = V_IL, the two outermost boot sectors remain

protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or

inhibited.

2. Do not apply CE#f1 or 2 = V_IL, CE#1ps = V_ILand CE2ps = V_IHat

the same time.

unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH,all sectors will

be unprotected.

3. Don’t care or open LB#s or UB#s.

4. If WP#/ACC = V_IL, the boot sectors will be protected. If WP#/ACC

= V_IHthe boot sectors protection will be removed.

If WP#/ACC = V_ACC(9V), the program time will be reduced by

40%.

7. Data will be retained in pSRAM.

8. Data will be lost in pSRAM.

9. Both CE#f1 inputs may be held low for this operation.

5. The sector protect and sector unprotect functions may also be

implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

18

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

page mode accesses are obtained by keeping

A22–A3 (A21–A3 for PDL129) constant and changing

A2 to A0 to select the specific word within that page.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the OE# and appropriate CE#f1/CE#f2 (PDL129

only) pins to V_IL. CE#f1 and CE#f2 are the power con-

trol and for PDL129 select the lower (CE#f1) or upper

(CE#f2) halves of the device. OE# is the output control

and gates array data to the output pins. WE# should

remain at V_IH.

Table 2. Page Select

Word

A2

0

A1

0

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

0

1

0

1

0

1

0

1

0

1

0

1

Refer to the AC Characteristics table for timing specifi-

cations and to Figure 13 for the timing diagram. I_CC1in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Simultaneous Operation

In addition to the conventional features (read, pro-

gram, erase-suspend read, and erase-suspend pro-

gram), the device is capable of reading data from one

bank of memory while a program or erase operation is

in progress in another bank of memory (simultaneous

operation), The bank can be selected by bank ad-

dresses (A22–A20) (A21–A20 for PDL129) with zero

latency.

Random Read (Non-Page Read)

Address access time (t_ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable ad-

dresses and stable CE#f1 to valid data at the output

inputs. The output enable access time is the delay

from the falling edge of the OE# to valid data at the

output inputs (assuming the addresses have been sta-

ble for at least t_ACC–t_OEtime).

The simultaneous operation can execute multi-func-

tion mode in the same bank.

Table 3. Bank Select (PDL129H)

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. Address bits

A22–A3 (A21–A3 for PDL129) select an 8-word page,

and address bits A2–A0 select a specific word within

that page. This is an asynchronous operation with the

microprocessor supplying the specific word location.

Bank

CE#f1

CE#f2

A21–A20

00, 01, 10

11

Bank 1A

Bank 1B

Bank 2A

Bank 2B

0

1

0

00

01, 10, 11

Table 4. Bank Select (PDL127H)

The random or initial page access is t_ACCor t_CEand

subsequent page read accesses (as long as the loca-

tions specified by the microprocessor fall within that

page) are t_PACC. When CE#f1 and CE#f2 (PDL129

only) are deasserted (CE#f1=CE#f2=V_IH), the reasser-

tion of CE#f1 or CE#f2 (PDL129 only) for subsequent

access has access time of t_ACCor t_CE. Here again,

CE#f1/CE#f2 (PDL129 only) selects the device and

OE# is the output control and should be used to gate

data to the output inputs if the device is selected. Fast

Bank

A22–A20

000

Bank A

Bank B

Bank C

Bank D

001, 010, 011

100, 101, 110

111

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

19

A D V A N C E I N F O R M A T I O N

Autoselect Functions

Writing Commands/Command Sequences

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Command Se-

quence sections for more information.

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE#f1 or CE#f2 (PDL 129 only) to V_IL, and OE# to V_IH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Pro-

gram Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 4 indicates the address

space that each sector occupies. A “bank address” is

the address bits required to uniquely select a bank.

Similarly, a “sector address” refers to the address bits

required to uniquely select a sector. The “Command

Definitions” section has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

The device enters the CMOS standby mode when the

CE#f1, CE#f2 (PDL129 only) and RESET# pins are all

held at V_IO0.3 V. (Note that this is a more restricted

voltage range than V_IH.) If CE#f1, CE#f2 (PDL129

only), and RESET# are held at V_IH, but not within V_CC

0.3 V, the device will be in the standby mode, but the

standby current will be greater. The device requires

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput at the

factory.

I_CC3in the DC Characteristics table represents the

CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin should be raised to V_CCwhen not in

use. That is, the WP#/ACC pin should not be left float-

ing or unconnected; inconsistent behavior of the de-

vice may result.

this mode when addresses remain stable for t_ACC

+

150 ns. The automatic sleep mode is independent of

the CE#f1/CE#f2 (PDL129 only), WE#, and OE# con-

trol signals. Standard address access timings provide

new data when addresses are changed. While in

sleep mode, output data is latched and always avail-

able to the system. Note that during automatic sleep

mode, OE# must be at V_IHbefore the device reduces

current to the stated sleep mode specification. I_CC5in

the DC Characteristics table represents the automatic

sleep mode current specification.

20

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

internal reset operation is complete, which requires a

RESET#: Hardware Reset Pin

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 15 for the timing dia-

gram.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins (except for RY/BY#) are

placed in the highest Impedance state

Table 5. SecSi^TMSector Addresses

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Sector Size

Address Range

Am29PDL127H/

Am29PDL129H

128 words

000000h–00007Fh

Factory-Locked Area

64 words

000000h-00003Fh

000040h-00007Fh

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

Customer-Lockable Area

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

21

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture

Bank

Sector

SA0

Sector Address (A22-A12)

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

00000100XXX

00000101XXX

00000110XXX

00000111XXX

00001000XXX

00001001XXX

00001010XXX

00001011XXX

00001100XXX

00001101XXX

00001110XXX

00001111XXX

00010000XXX

00010001XXX

00010010XXX

00010011XXX

00010100XXX

00010101XXX

00010110XXX

00010111XXX

00011000XXX

00011001XXX

00011010XXX

00011011XXX

00011100XXX

00011101XXX

00011110XXX

00011111XXX

Sector Size (Kwords)

Address Range (x16)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA1

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

22

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

Sector Address (A22-A12)

00100000XXX

00100001XXX

00100010XXX

00100011XXX

00100100XXX

00100101XXX

00100110XXX

00100111XXX

00101000XXX

00101001XXX

00101010XXX

00101011XXX

00101100XXX

00101101XXX

00101110XXX

00101111XXX

00110000XXX

00110001XXX

00110010XXX

00110011XXX

00110100XXX

00110101XXX

00110110XXX

00110111XXX

00111000XXX

00111001XXX

00111010XXX

00111011XXX

00111100XXX

00111101XXX

00111110XXX

00111111XXX

01000000XXX

01000001XXX

01000010XXX

01000011XXX

01000100XXX

01000101XXX

01000110XXX

01000111XXX

Sector Size (Kwords)

Address Range (x16)

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

32

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

23

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA79

Sector Address (A22-A12)

01001000XXX

01001001XXX

01001010XXX

01001011XXX

01001100XXX

01001101XXX

01001110XXX

01001111XXX

01010000XXX

01010001XXX

01010010XXX

01010011XXX

01010100XXX

01010101XXX

01010110XXX

01010111XXX

01011000XXX

01011001XXX

01011010XXX

01011011XXX

01011100XXX

01011101XXX

01011110XXX

01011111XXX

01100000XXX

01100001XXX

01100010XXX

01100011XXX

01100100XXX

01100101XXX

01100110XXX

01100111XXX

01101000XXX

01101001XXX

01101010XXX

01101011XXX

01101100XXX

01101101XXX

01101110XXX

01101111XXX

Sector Size (Kwords)

Address Range (x16)

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

32

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

24

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

Sector Address (A22-A12)

01110000XXX

01110001XXX

01110010XXX

01110011XXX

01110100XXX

01110101XXX

01110110XXX

01110111XXX

01111000XXX

01111001XXX

01111010XXX

01111011XXX

01111100XXX

01111101XXX

01111110XXX

01111111XXX

10000000XXX

10000001XXX

10000010XXX

10000011XXX

10000100XXX

10000101XXX

10000110XXX

10000111XXX

10001000XXX

10001001XXX

10001010XXX

10001011XXX

10001100XXX

10001101XXX

10001110XXX

10001111XXX

10010000XXX

10010001XXX

10010010XXX

10010011XXX

10010100XXX

10010101XXX

10010110XXX

10010111XXX

Sector Size (Kwords)

Address Range (x16)

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

400000h–407FFFh

408000h–40FFFFh

410000h–417FFFh

418000h–41FFFFh

420000h–427FFFh

428000h–42FFFFh

430000h–437FFFh

438000h–43FFFFh

440000h–447FFFh

448000h–44FFFFh

450000h–457FFFh

458000h–45FFFFh

460000h–467FFFh

468000h–46FFFFh

470000h–477FFFh

478000h–47FFFFh

480000h–487FFFh

488000h–48FFFFh

490000h–497FFFh

498000h–49FFFFh

4A0000h–4A7FFFh

4A8000h–4AFFFFh

4B0000h–4B7FFFh

4B8000h–4BFFFFh

32

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

25

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

Sector Address (A22-A12)

10011000XXX

10011001XXX

10011010XXX

10011011XXX

10011100XXX

10011101XXX

10011110XXX

10011111XXX

10100000XXX

10100001XXX

10100010XXX

10100011XXX

10100100XXX

10100101XXX

10100110XXX

10100111XXX

10101000XXX

10101001XXX

10101010XXX

10101011XXX

10101100XXX

10101101XXX

10101110XXX

10101111XXX

10110000XXX

10110001XXX

10110010XXX

10110011XXX

10110100XXX

10110101XXX

10110110XXX

10110111XXX

10111000XXX

10111001XXX

10111010XXX

10111011XXX

10111100XXX

10111101XXX

10111110XXX

10111111XXX

Sector Size (Kwords)

Address Range (x16)

4C0000h–4C7FFFh

4C8000h–4CFFFFh

4D0000h–4D7FFFh

4D8000h–4DFFFFh

4E0000h–4E7FFFh

4E8000h–4EFFFFh

4F0000h–4F7FFFh

4F8000h–4FFFFFh

500000h–507FFFh

508000h–50FFFFh

510000h–517FFFh

518000h–51FFFFh

520000h–527FFFh

528000h–52FFFFh

530000h–537FFFh

538000h–53FFFFh

540000h–547FFFh

548000h–54FFFFh

550000h–557FFFh

558000h–15FFFFh

560000h–567FFFh

568000h–56FFFFh

570000h–577FFFh

578000h–57FFFFh

580000h–587FFFh

588000h–58FFFFh

590000h–597FFFh

598000h–59FFFFh

5A0000h–5A7FFFh

5A8000h–5AFFFFh

5B0000h–5B7FFFh

5B8000h–5BFFFFh

5C0000h–5C7FFFh

5C8000h–5CFFFFh

5D0000h–5D7FFFh

5D8000h–5DFFFFh

5E0000h–5E7FFFh

5E8000h–5EFFFFh

5F0000h–5F7FFFh

5F8000h–5FFFFFh

32

26

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

Sector Address (A22-A12)

11000000XXX

11000001XXX

11000010XXX

11000011XXX

11000100XXX

11000101XXX

11000110XXX

11000111XXX

11001000XXX

11001001XXX

11001010XXX

11001011XXX

11001100XXX

11001101XXX

11001110XXX

11001111XXX

11010000XXX

11010001XXX

11010010XXX

11010011XXX

11010100XXX

11010101XXX

11010110XXX

11010111XXX

11011000XXX

11011001XXX

11011010XXX

11011011XXX

11011100XXX

11011101XXX

11011110XXX

11011111XXX

Sector Size (Kwords)

Address Range (x16)

600000h–607FFFh

608000h–60FFFFh

610000h–617FFFh

618000h–61FFFFh

620000h–627FFFh

628000h–62FFFFh

630000h–637FFFh

638000h–63FFFFh

640000h–647FFFh

648000h–64FFFFh

650000h–657FFFh

658000h–65FFFFh

660000h–667FFFh

668000h–66FFFFh

670000h–677FFFh

678000h–67FFFFh

680000h–687FFFh

688000h–68FFFFh

690000h–697FFFh

698000h–69FFFFh

6A0000h–6A7FFFh

6A8000h–6AFFFFh

6B0000h–6B7FFFh

6B8000h–6BFFFFh

6C0000h–6C7FFFh

6C8000h–6CFFFFh

6D0000h–6D7FFFh

6D8000h–6DFFFFh

6E0000h–6E7FFFh

6E8000h–6EFFFFh

6F0000h–6F7FFFh

6F8000h–6FFFFFh

32

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

27

A D V A N C E I N F O R M A T I O N

Table 6. Am29PDL127H Sector Architecture (Continued)

Bank

Sector

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

Sector Address (A22-A12)

11100000XXX

11100001XXX

11100010XXX

11100011XXX

11100100XXX

11100101XXX

11100110XXX

11100111XXX

11101000XXX

11101001XXX

11101010XXX

11101011XXX

11101100XXX

11101101XXX

11101110XXX

11101111XXX

11110000XXX

11110001XXX

11110010XXX

11110011XXX

11110100XXX

11110101XXX

11110110XXX

11110111XXX

11111000XXX

11111001XXX

11111010XXX

11111011XXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

11111111100

11111111101

11111111110

11111111111

Sector Size (Kwords)

Address Range (x16)

700000h–707FFFh

708000h–70FFFFh

710000h–717FFFh

718000h–71FFFFh

720000h–727FFFh

728000h–72FFFFh

730000h–737FFFh

738000h–73FFFFh

740000h–747FFFh

748000h–74FFFFh

750000h–757FFFh

758000h–75FFFFh

760000h–767FFFh

768000h–76FFFFh

770000h–777FFFh

778000h–77FFFFh

780000h–787FFFh

788000h–78FFFFh

790000h–797FFFh

798000h–79FFFFh

7A0000h–7A7FFFh

7A8000h–7AFFFFh

7B0000h–7B7FFFh

7B8000h–7BFFFFh

7C0000h–7C7FFFh

7C8000h–7CFFFFh

7D0000h–7D7FFFh

7D8000h–7DFFFFh

7E0000h–7E7FFFh

7E8000h–7EFFFFh

7F0000h–7F7FFFh

7F8000h–7F8FFFh

7F9000h–7F9FFFh

7FA000h–7FAFFFh

7FB000h–7FBFFFh

7FC000h–7FCFFFh

7FD000h–7FDFFFh

7FE000h–7FEFFFh

7FF000h–7FFFFFh

32

4

28

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture

Sector Address

(A21-A12)

Sector Size

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

(Kwords)

32

SA1-0

SA1-1

0

1

0000000XXX

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

000000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

SA1-2

SA1-3

SA1-4

SA1-5

SA1-6

SA1-7

SA1-8

SA1-9

SA1-10

SA1-11

SA1-12

SA1-13

SA1-14

SA1-15

SA1-16

SA1-17

SA1-18

SA1-19

SA1-20

SA1-21

SA1-22

SA1-23

SA1-24

SA1-25

SA1-26

SA1-27

SA1-28

SA1-29

SA1-30

SA1-31

SA1-32

SA1-33

SA1-34

SA1-35

SA1-36

SA1-37

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

29

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

(Kwords)

32

SA1-38

SA1-39

SA1-40

SA1-41

SA1-42

SA1-43

SA1-44

SA1-45

SA1-46

SA1-47

SA1-48

SA1-49

SA1-50

SA1-51

SA1-52

SA1-53

SA1-54

SA1-55

SA1-56

SA1-57

SA1-58

SA1-59

SA1-60

SA1-61

SA1-62

SA1-63

SA1-64

SA1-65

SA1-66

SA1-67

SA1-68

SA1-69

SA1-70

SA1-71

SA1-72

SA1-73

SA1-74

SA1-75

SA1-76

SA1-77

0

1

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

30

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

(Kwords)

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

SA1-78

SA1-79

SA1-80

SA1-81

SA1-82

SA1-83

SA1-84

SA1-85

SA1-86

SA1-87

SA1-88

SA1-89

SA1-90

SA1-91

SA1-92

SA1-93

SA1-94

SA1-95

0

1

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

32

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

32

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

31

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

(Kwords)

32

4

SA1-96

SA1-97

0

1

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

SA1-98

SA1-99

SA1-100

SA1-101

SA1-102

SA1-103

SA1-104

SA1-105

SA1-106

SA1-107

SA1-108

SA1-109

SA1-110

SA1-111

SA1-112

SA1-113

SA1-114

SA1-115

SA1-116

SA1-117

SA1-118

SA1-119

SA1-120

SA1-121

SA1-122

SA1-123

SA1-124

SA1-125

SA1-126

SA1-127

SA1-128

SA1-129

SA1-130

SA1-131

SA1-132

SA1-133

SA1-134

4

32

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

(Kwords)

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

SA2-0

SA2-1

1

0

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

0000100XXX

0000101XXX

0000110XXX

0000111XXX

0001000XXX

0001001XXX

0001010XXX

0001011XXX

0001100XXX

0001101XXX

0001110XXX

0001111XXX

0010000XXX

0010001XXX

0010010XXX

0010011XXX

0010100XXX

0010101XXX

0010110XXX

0010111XXX

0011000XXX

0011001XXX

0011010XXX

0011011XXX

0011100XXX

0011101XXX

0011110XXX

0011111XXX

4

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

4

SA2-2

4

SA2-3

4

SA2-4

4

SA2-5

4

SA2-6

4

SA2-7

4

SA2-8

32

SA2-9

SA2-10

SA2-11

SA2-12

SA2-13

SA2-14

SA2-15

SA2-16

SA2-17

SA2-18

SA2-19

SA2-20

SA2-21

SA2-22

SA2-23

SA2-24

SA2-25

SA2-26

SA2-27

SA2-28

SA2-29

SA2-30

SA2-31

SA2-32

SA2-33

SA2-34

SA2-35

SA2-36

SA2-37

SA2-38

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

33

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

(Kwords)

32

SA2-39

SA2-40

SA2-41

SA2-42

SA2-43

SA2-44

SA2-45

SA2-46

SA2-47

SA2-48

SA2-49

SA2-50

SA2-51

SA2-52

SA2-53

SA2-54

SA2-55

SA2-56

SA2-57

SA2-58

SA2-59

SA2-60

SA2-61

SA2-62

SA2-63

SA2-64

SA2-65

SA2-66

SA2-67

SA2-68

SA2-69

SA2-70

SA2-71

SA2-72

SA2-73

SA2-74

SA2-75

SA2-76

SA2-77

SA2-78

1

0

0100000XXX

0100001XXX

0100010XXX

0100011XXX

0100100XXX

0100101XXX

0100110XXX

0100111XXX

0101000XXX

0101001XXX

0101010XXX

0101011XXX

0101100XXX

0101101XXX

0101110XXX

0101111XXX

0110000XXX

0110001XXX

0110010XXX

0110011XXX

0110100XXX

0110101XXX

0110110XXX

0110111XXX

0111000XXX

0111001XXX

0111010XXX

0111011XXX

0111100XXX

0111101XXX

0111110XXX

0111111XXX

1000000XXX

1000001XXX

1000010XXX

1000011XXX

1000100XXX

1000101XXX

1000110XXX

1000111XXX

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

34

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

(Kwords)

32

SA2-79

SA2-80

SA2-81

SA2-82

SA2-83

SA2-84

SA2-85

SA2-86

SA2-87

SA2-88

SA2-89

SA2-90

SA2-91

SA2-92

SA2-93

SA2-94

SA2-95

SA2-96

SA2-97

SA2-98

SA2-99

SA2-100

SA2-101

SA2-102

SA2-103

SA2-104

SA2-105

SA2-106

SA2-107

SA2-108

SA2-109

SA2-110

SA2-111

SA2-112

SA2-113

SA2-114

SA2-115

SA2-116

SA2-117

SA2-118

1

0

1001000XXX

1001001XXX

1001010XXX

1001011XXX

1001100XXX

1001101XXX

1001110XXX

1001111XXX

1010000XXX

1010001XXX

1010010XXX

1010011XXX

1010100XXX

1010101XXX

1010110XXX

1010111XXX

1011000XXX

1011001XXX

1011010XXX

1011011XXX

1011100XXX

1011101XXX

1011110XXX

1011111XXX

1100000XXX

1100001XXX

1100010XXX

1100011XXX

1100100XXX

1100101XXX

1100110XXX

1100111XXX

1101000XXX

1101001XXX

1101010XXX

1101011XXX

1101100XXX

1101101XXX

1101110XXX

1101111XXX

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–287FFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2F7FFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

35

A D V A N C E I N F O R M A T I O N

Table 7. Am29PDL129H Sector Architecture (Continued)

Sector Address

(A21-A12)

Sector Size

(Kwords)

Bank

Sector

CE#f1

CE#f2

Address Range (x16)

SA2-119

SA2-120

SA2-121

SA2-122

SA2-123

SA2-124

SA2-125

SA2-126

SA2-127

SA2-128

SA2-129

SA2-130

SA2-131

SA2-132

SA2-133

SA2-134

1

0

1110000XXX

1110001XXX

1110010XXX

1110011XXX

1110100XXX

1110101XXX

1110110XXX

1110111XXX

1111000XXX

1111001XXX

1111010XXX

1111011XXX

1111100XXX

1111101XXX

1111110XXX

1111111XXX

32

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3FFFFFh

32

36

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 8. Am29PDL127H Boot Sector/Sector Block

Sector/

Sector Block Size

Sector

A22-A12

Addresses for Protection/Unprotection

SA131-SA134

SA135-SA138

SA139-SA142

SA143-SA146

SA147-SA150

SA151-SA154

SA155-SA158

SA159-SA162

SA163-SA166

SA167-SA170

SA171-SA174

SA175-SA178

SA179-SA182

SA183-SA186

SA187-SA190

SA191-SA194

SA195-SA198

SA199-SA202

SA203-SA206

SA207-SA210

SA211-SA214

SA215-SA218

SA219-SA222

SA223-SA226

SA227-SA230

SA231-SA234

SA235-SA238

SA239-SA242

SA243-SA246

SA247-SA250

SA251-SA254

SA255-SA258

SA259

011111XXXXX

100000XXXXX

100001XXXXX

100010XXXXX

100011XXXXX

100100XXXXX

100101XXXXX

100110XXXXX

100111XXXXX

101000XXXXX

101001XXXXX

101010XXXXX

101011XXXXX

101100XXXXX

101101XXXXX

101110XXXXX

101111XXXXX

110000XXXXX

110001XXXXX

110010XXXXX

110011XXXXX

110100XXXXX

110101XXXXX

110110XXXXX

110111XXXXX

111000XXXXX

111001XXXXX

111010XXXXX

111011XXXXX

111100XXXXX

111101XXXXX

111110XXXXX

11111100XXX

11111101XXX

11111110XXX

11111111000

11111111001

11111111010

11111111011

11111111100

11111111101

11111111110

11111111111

128 (4x32) Kwords

32 Kwords

Sector/

Sector Block Size

Sector

A22-A12

SA0

00000000000

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

00000001XXX

00000010XXX

00000011XXX

000001XXXXX

000010XXXXX

000011XXXXX

000100XXXXX

000101XXXXX

000110XXXXX

000111XXXXX

001000XXXXX

001001XXXXX

001010XXXXX

001011XXXXX

001100XXXXX

001101XXXXX

001110XXXXX

001111XXXXX

010000XXXXX

010001XXXXX

010010XXXXX

010011XXXXX

010100XXXXX

010101XXXXX

010110XXXXX

010111XXXXX

011000XXXXX

011001XXXXX

011010XXXXX

011011XXXXX

011100XXXXX

011101XXXXX

011110XXXXX

4 Kwords

SA1

4 Kwords

SA2

4 Kwords

SA3

4 Kwords

SA4

4 Kwords

SA5

4 Kwords

SA6

4 Kwords

SA7

4 Kwords

SA8

32 Kwords

SA9

32 Kwords

SA10

32 Kwords

SA11-SA14

SA15-SA18

SA19-SA22

SA23-SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55-SA58

SA59-SA62

SA63-SA66

SA67-SA70

SA71-SA74

SA75-SA78

SA79-SA82

SA83-SA86

SA87-SA90

SA91-SA94

SA95-SA98

SA99-SA102

SA103-SA106

SA107-SA110

SA111-SA114

SA115-SA118

SA119-SA122

SA123-SA126

SA127-SA130

128 (4x32) Kwords

SA260

32 Kwords

SA261

32 Kwords

SA262

4 Kwords

SA263

4 Kwords

SA264

4 Kwords

SA265

4 Kwords

SA266

4 Kwords

SA267

4 Kwords

SA268

4 Kwords

SA269

4 Kwords

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

37

A D V A N C E I N F O R M A T I O N

Table 9. Am29PDL129H Boot Sector/Sector Block

Table 10. Am29PDL129H Boot Sector/Sector

Block Addresses for Protection/Unprotection

CE#f2 Control

Addresses for Protection/Unprotection

CE#f1 Control

Sector

Group

Sector/Sector

Block Size

Sector

Group

A21-12

Sector/Sector

Block Size

A21-12

SA1-0–SA1-3

SA1-4–SA1-7

SA1-8–SA1-11

SA1-12–SA1-15

SA1-16–SA1-19

SA1-20–SA1-23

SA1-24–SA1-27

SA1-28–SA1-31

SA1-32–SA1-35

SA1-36–SA1-39

SA1-40–SA1-43

SA1-44–SA1-47

SA1-48–SA1-51

SA1-52–SA1-55

SA1-56–SA1-59

SA1-60–SA1-63

SA1-64–SA1-67

SA1-68–SA1-71

SA1-72–SA1-75

SA1-76–SA1-79

SA1-80–SA1-83

SA1-84–SA1-87

SA1-88–SA1-91

SA1-92–SA1-95

SA1-96–SA1-99

SA1-100–SA1-103

SA1-104–SA1-107

SA1-108–SA1-111

SA1-112–SA1-115

SA1-116–SA1-119

SA1-120–SA1-123

SA1-124

00000XXXXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

1111100XXX

1111101XXX

1111110XXX

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

128 (4x32) Kwords

32 Kwords

SA2-0

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

0000010XXX

0000011XXX

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

11111XXXXX

4 Kwords

SA2-1

4 Kwords

SA2-2

4 Kwords

SA2-3

4 Kwords

SA2-4

4 Kwords

SA2-5

4 Kwords

SA2-6

4 Kwords

SA2-7

4 Kwords

SA2-8

32 Kwords

SA2-9

32 Kwords

SA2-10

32 Kwords

SA2-11 - SA2-14

SA2-15 - SA2-18

SA2-19 - SA2-22

SA2-23 - SA2-26

SA2-27 - SA2-30

SA2-31 - SA2-34

SA2-35 - SA2-38

SA2-39 - SA2-42

SA2-43 - SA2-46

SA2-47 - SA2-50

SA2-51 - SA2-54

SA2-55 - SA2-58

SA2-59 - SA2-62

SA2-63 - SA2-66

SA2-67 - SA2-70

SA2-71 - SA2-74

SA2-75 - SA2-78

SA2-79 - SA2-82

SA2-83 - SA2-86

SA2-87 - SA2-90

SA2-91 - SA2-94

SA2-95 - SA2-98

SA2-99 - SA2-102

SA2-103 - SA2-106

SA2-107 - SA2-110

SA2-111 - SA2-114

SA2-115 - SA2-118

SA2-119 - SA2-122

SA2-123 - SA2-126

SA2-127 - SA2-130

SA2-131 - SA2-134

128 (4x32) Kwords

SA1-125

32 Kwords

SA1-126

32 Kwords

SA1-127

4 Kwords

SA1-128

4 Kwords

SA1-129

4 Kwords

SA1-130

4 Kwords

SA1-131

4 Kwords

SA1-132

4 Kwords

SA1-133

4 Kwords

SA1-134

4 Kwords

38

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

SECTOR PROTECTION

The Am50PDL191CH/Am50PDL193CH features sev-

eral levels of sector protection, which can disable both

the program and erase operations in certain sectors or

sector groups:

■ Dynamically Locked—The sector is protected and

can be changed by a simple command.

■ Unlocked—The sector is unprotected and can be

changed by a simple command.

Persistent Sector Protection

To achieve these states, three types of “bits” are used:

A command sector protection method that replaces

the old 12 V controlled protection method.

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sectors (see the sector ad-

dress tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector

Persistent Protection Bits (PPBs) for greater flexibility.

Each PPB is individually modifiable through the PPB

Write Command.

Password Sector Protection

A highly sophisticated protection method that requires

a password before changes to certain sectors or sec-

tor groups are permitted.

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in sectors 0, 1, 268, and 269 in PDL 127 or

in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. The

WP# Hardware Protection feature is always available,

regardless of which of the other two methods are cho-

sen.

The device erases all PPBs in parallel. If any PPB re-

quires erasure, the device must be instructed to pre-

program all of the sector PPBs prior to PPB erasure.

Otherwise, a previously erased sector PPBs can po-

tentially be over-erased. The flash device does not

have a built-in means of preventing sector PPBs

over-erasure.

Selecting a Sector Protection Mode

The device defaults to the Persistent Sector Protection

mode. However, to prevents a program or virus from

later setting the Password Mode Locking Bit, which

would cause an unexpected shift from the default Per-

sistent Sector Protection Mode into the Password Pro-

tection Mode, it is recommended that either of two

one-time programmable non-volatile bits that perma-

nently define which sector protection method be set

before the device is first programmed. The Persis-

tent Sector Protection Mode Locking Bit perma-

nently sets the device to the Persistent Sector

Protection mode. The Password Mode Locking Bit

permanently sets the device to the Password Sector

Protection mode. It is not possible to switch between

the two protection modes once a locking bit has been

set.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a glo-

bal volatile bit. When set to “1”, the PPBs cannot be

changed. When cleared (“0”), the PPBs are change-

able. There is only one PPB Lock bit per device. The

PPB Lock is cleared after power-up or hardware reset.

There is no command sequence to unlock the PPB

Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

When the parts are first shipped, the PPBs are

cleared, the DYBs are cleared, and PPB Lock is de-

faulted to power up in the cleared state – meaning the

PPBs are changeable.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determined by the logical OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector in

the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

switch back and forth between the protected and un-

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

It is possible to determine whether a sector is pro-

tected or unprotected. See Autoselect Command Se-

quence for details.

Persistent Sector Protection

The Persistent Sector Protection method replaces the

12 V controlled protection method in previous AMD

flash devices. This new method provides three differ-

ent sector protection states:

■ Persistently Locked—The sector is protected and

cannot be changed.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

39

A D V A N C E I N F O R M A T I O N

not prevent the easy removal of protection when

Table 11. Sector Protection Schemes

changes are needed. The DYBs maybe set or cleared

as often as needed.

PPB

DYB

PPB

Lock

Sector State

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycles because they are non-volatile. In-

dividual PPBs are set with a command but must all be

cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

Unprotected—PPB and DYB are

changeable

0

Unprotected—PPB not

changeable, DYB is changeable

0

1

0

1

0

1

0

1

0

1

0

1

Protected—PPB and DYB are

changeable

The PPB Lock bit adds an additional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands

to the non-volatile PPBs. In effect, the PPB Lock Bit

locks the PPBs into their current state. The only way to

clear the PPB Lock is to go through a power cycle.

System boot code can determine if any changes to the

PPB are needed; for example, to allow new system

code to be downloaded. If no changes are needed

then the boot code can set the PPB Lock to disable

any further changes to the PPBs during system opera-

tion.

Protected—PPB not

changeable, DYB is changeable

Table 11 contains all possible combinations of the

DYB, PPB, and PPB lock relating to the status of the

sector.

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynami-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

The WP#/ACC write protect pin adds a final level of

hardware protection to sectors 0, 1, 268, and 269 in

PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in

PDL 129. When this pin is low it is not possible to

change the contents of these sectors. These sectors

generally hold system boot code. The WP#/ACC pin

can prevent any changes to the boot code that could

override the choices made while setting up sector pro-

tection during system initialization.

If the user attempts to program or erase a protected

sector, the device ignores the command and returns to

read mode. A program command to a protected sector

enables status polling for approximately 1 µs before

the device returns to read mode without having modi-

fied the contents of the protected sector. An erase

command to a protected sector enables status polling

for approximately 50 µs after which the device returns

to read mode without having erased the protected sec-

tor.

It is possible to have sectors that have been persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write command sequence is all that is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change the

status of the persistently locked sectors, a few more

steps are required. First, the PPB Lock bit must be dis-

abled by either putting the device through a power-cy-

cle, or hardware reset. The PPBs can then be

changed to reflect the desired settings. Setting the

PPB lock bit once again will lock the PPBs, and the de-

vice operates normally again.

The programming of the DYB, PPB, and PPB lock for a

given sector can be verified by writing a

DYB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protection mode locking bit exists to guarantee that

the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

The best protection is achieved by executing the PPB

lock bit set command early in the boot code, and pro-

tect the boot code by holding WP#/ACC = V_IL.

Password Protection Mode

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

40

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

■ When the device is first powered on, or comes out

of a reset cycle, the PPB Lock bit set to the locked

state, rather than cleared to the unlocked state.

■ The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

64-bit Password

The Password Sector Protection method is otherwise

identical to the Persistent Sector Protection method.

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Verify Command”). The password function works in

conjunction with the Password Mode Locking Bit,

which when set, prevents the Password Verify com-

mand from reading the contents of the password on

the pins of the device.

A 64-bit password is the only additional tool utilized in

this method.

Once the Password Mode Locking Bit is set, the pass-

word is permanently set with no means to read, pro-

gram, or erase it. The password is used to clear the

PPB Lock bit. The Password Unlock command must

be written to the flash, along with a password. The

flash device internally compares the given password

with the pre-programmed password. If they match, the

PPB Lock bit is cleared, and the PPBs can be altered.

If they do not match, the flash device does nothing.

There is a built-in 2 µs delay for each “password

check.” This delay is intended to thwart any efforts to

run a program that tries all possible combinations in

order to crack the password.

Write Protect (WP#)

The Write Protect feature provides a hardware method

of protecting sectors 0, 1, 268, and 269 in PDL 127 or

in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 with-

out using V_ID. This function is provided by the WP# pin

and overrides the previously discussed High Voltage

Sector Protection method.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously pro-

tected or unprotected.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. The password may be correlated to the unique

Electronic Serial Number (ESN) of the particular flash

device. Each ESN is different for every flash device;

therefore each password should be different for every

flash device. While programming in the password re-

gion, the customer may perform Password Verify oper-

ations.

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether sectors 0, 1, 268, and 269 in

PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in

PDL 129 were last set to be protected or unprotected.

That is, sector protection or unprotection for these sec-

tors depends on whether they were last protected or

unprotected using the method described in High Volt-

age Sector Protection.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

1. Permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

Persistent Protection Bit Lock

2. Disables all further commands to the password re-

gion. All program, and read operations are ignored.

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set after a hardware reset (RESET#

asserted) or a power-up reset, the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1” when the

Password Mode Lock Bit is not set.

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

41

A D V A N C E I N F O R M A T I O N

If the Password Mode Locking Bit is not set, including

High Voltage Sector Protection

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set com-

mand. Once set the only means for clearing the PPB

Lock Bit is by issuing a hardware or power-up reset.

The Password Unlock command is ignored in Persis-

tent Protection Mode.

Sector protection and unprotection may also be imple-

mented using programming equipment. The proce-

dure requires high voltage (V_ID) to be placed on the

RESET# pin. Refer to Figure 1 for details on this pro-

cedure. Note that for sector unprotect, all unprotected

sectors must first be protected prior to the first sector

write cycle.

42

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

PLSCNT = 1

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 4 µs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A7-A0 =

Yes

Set up first sector

address

00000010

Sector Unprotect:

Wait 100 µs

Write 60h to sector

address with

A7-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.2 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

Read from

sector address

with A7-A0 =

00000010

Increment

PLSCNT

No

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7-A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

Remove V_ID

from RESET#

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

No

Write reset

command

Yes

Remove V_ID

from RESET#

Remove V_ID

from RESET#

No

Last sector

verified?

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Unprotect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Figure 1. In-System Sector Protection/

Sector Unprotection Algorithms

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

43

A D V A N C E I N F O R M A T I O N

tection mode and Password Protection mode. It uses

indicator bits (DQ6, DQ7) to indicate the fac-

tory-locked and customer-locked status of the part.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 23 shows the timing diagrams, for this feature.

While PPB lock is set, the device cannot enter the

Temporary Sector Unprotection Mode.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi™ Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the normal address space.

Factory-Locked Area (64 words)

The factory-locked area of the SecSi Sector

(000000h-00003Fh) is locked when the part is

shipped, whether or not the area was programmed at

the factory. The SecSi Sector Factory-locked Indicator

Bit (DQ7) is permanently set to a “1”. AMD offers the

ExpressFlash service to program the factory-locked

area with a random ESN, a customer-defined code, or

any combination of the two. Because only AMD can

program and protect the factory-locked area, this

method ensures the security of the ESN once the

product is shipped to the field. Contact an AMD repre-

sentative for details on using AMD’s ExpressFlash ser-

vice. Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-

abled.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Customer-Lockable Area (64 words)

The customer-lockable area of the SecSi Sector

(000040h-00007Fh) is shipped unprotected, which al-

lows the customer to program and optionally lock the

area as appropriate for the application. The SecSi

Sector Customer-locked Indicator Bit (DQ6) is shipped

as “0” and can be permanently locked to “1” by issuing

the SecSi Protection Bit Program Command. The

SecSi Sector can be read any number of times, but

can be programmed and locked only once. Note that

the accelerated programming (ACC) and unlock by-

pass functions are not available when programming

the SecSi Sector.

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

sectors 0, 1, 268, 269 in PDL 127 or in SA1-133,

SA1-134, SA2-0, SA2-1 in PDL 129.will remain

protected).

2. All previously protected sectors are protected once

again.

Figure 2. Temporary Sector Unprotect Operation

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The Customer-lockable SecSi Sector area can be pro-

tected using one of the following procedures:

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN) The 128-word SecSi sector is divided into 64

factory-lockable words that can be programmed and

locked by the customer. The SecSi sector is located at

addresses 000000h-00007Fh in both Persistent Pro-

■ Follow the SecSi Sector Protection Algorithm as

shown in . This allows in-system protection of the

SecSi Sector without raising any device pin to a

high voltage. Note that this method is only applica-

ble to the SecSi Sector.

44

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

START

SecSi^TMSector Entry

Write AAh to address 555h

Write 55h to address 2AAh

Write 88h to address 555h

SecSi Sector Entry

SecSi Sector

Protection Entry

Write AAh to address 555h

Write 55h to address 2AAh

Write 60h to address 555h

PLSCNT = 1

Protect SecSi Sector:

write 68h to sector address

with A7–A0 = 00011010

SecSi Sector Protection

Time out 256 µs

Verify SecSi Sector:

write 48h to sector address

with A7–A0 = 00011010

Increment PLSCNT

Read from sector address

(SA0 + 1Ah)

No

PLSCNT = 25?

Data = 01h?

Yes

Device Failed

SecSi Sector

Protection Completed

SecSi Sector Exit

Write 555h/AAh

Write 2AAh/55h

SecSi Sector Exit

Write SA0+555h/90h

Write XXXh/00h

Figure 3. SecSi Protection Algorithm

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

45

A D V A N C E I N F O R M A T I O N

Once the SecSi Sector is locked and verified, the sys-

write cycle, CE#f1/CE#f2 and WE# must be a logical

zero while OE# is a logical one.

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

Power-Up Write Inhibit

If WE# = CE#f1 = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

COMMON FLASH MEMORY INTERFACE

(CFI)

SecSi Sector Protection Bits

The SecSi Sector Protection Bits prevent program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 12–15. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 12–15. The

system must write the reset command to return the

device to reading array data.

greater than V_LKO

.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#,

CE#f1, CE#f2 or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE#f1 =CE#f2 = V_IHor WE# = V_IH. To initiate a

46

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 12. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 13. System Interface String

Description

Addresses

Data

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

47

A D V A N C E I N F O R M A T I O N

Table 14. Device Geometry Definition

Description

Addresses

Data

27h

0018h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

00FDh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

48

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 15. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

000Ch

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0007h

00E7h

0000h

0002h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

4Fh

0001h

00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both

Top and Bottom

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

0001h

0004h

0027h

0060h

0027h

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

49

A D V A N C E I N F O R M A T I O N

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 16 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence may

place the device in an unknown state. A reset com-

mand is then required to return the device to reading

array data.

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

All addresses are latched on the falling edge of WE#

or CE#f1/CE#f2 (PDL129H only), whichever happens

later. All data is latched on the rising edge of WE# or

CE#f1/CE#f2 (PDL129H only), whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device out-

puts status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume Com-

mands section for more information.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read any number of

autoselect codes without reinitiating the command se-

quence.

See also Requirements for Reading Array Data in the

MCP Device Bus Operations section for more informa-

tion. The Read-Only Operations – Am29PDL127H and

Read-Only Operations – Am29PDL127H tables pro-

vide the read parameters, and Figure 13 shows the

timing diagram.

Table 16 shows the address and data requirements.

To determine sector protection information, the system

must write to the appropriate bank address (BA) and

sector address (SA). Table 4 shows the address range

and bank number associated with each sector.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

50

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Programming is allowed in any sequence and across

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The SecSi Sector region provides a secured data area

containing a random, eight word electronic serial num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. The SecSi Sector is not ac-

cessible when the device is executing an Embedded

Program or embedded Erase algorithm. Table 16

shows the address and data requirements for both

command sequences. See also “SecSi™ (Secured Sili-

con) Sector Flash Memory Region” for further informa-

tion. Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-

abled.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram data to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 16 shows the requirements for the

command sequence.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 16 shows the address

and data requirements for the program command se-

quence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. Note that the SecSi sector, autoselect, and

CFI functions are unavailable when the SecSi Sector

is enabled. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figures 16 and 17 for timing diagrams.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

51

A D V A N C E I N F O R M A T I O N

the SecSi sector, autoselect, and CFI functions are un-

available when the SecSi Sector is enabled. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

Write Program

Command Sequence

Sector Erase Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command.Table 16 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

No

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to the read mode. Note that the SecSi sec-

tor, autoselect, and CFI functions are unavailable

when the SecSi Sector is enabled. The system must

rewrite the command sequence and any additional ad-

dresses and commands.

Note: See Table 16 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 16

shows the address and data requirements for the chip

erase command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. Note that

52

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

termine the status of the erase operation by reading

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation. Addresses are “don’t-cares” when

writing the Erase suspend command.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

START

Write Erase

Command Sequence

(Notes 1, 2)

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Word Program operation.

Refer to the Write Operation Status section for more

information.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. The device

allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid operation.

Refer to the Autoselect Command Sequence sections

for details.

No

Data = FFh?

Yes

Erasure Completed

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Notes:

1. See Table 16 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Erase Suspend/Erase Resume

Commands

Password Program Command

The Password Program Command permits program-

ming the password that is used as part of the hard-

ware protection scheme. The actual password is

64-bits long. Four Password Program commands are

required to program the password. The system must

enter the unlock cycle, password program command

(38h) and the program address/data for each portion

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 80 µs time-out

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

53

A D V A N C E I N F O R M A T I O N

of the password when programming. There are no pro-

Persistent Sector Protection Mode

Locking Bit Program Command

visions for entering the 2-cycle unlock cycle, the pass-

word program command, and all the password data.

There is no special addressing order required for pro-

gramming the password. Also, when the password is

undergoing programming, Simultaneous Operation is

disabled. Read operations to any memory location will

return the programming status. Once programming is

complete, the user must issue a Read/Reset com-

mand to return the device to normal operation. Once

the Password is written and verified, the Password

Mode Locking Bit must be set in order to prevent verifi-

cation. The Password Program Command is only ca-

pable of programming “0”s. Programming a “1” after a

cell is programmed as a “0” results in a time-out by the

Embedded Program Algorithm™ with the cell remain-

ing as a “0”. The password is all ones when shipped

from the factory. All 64-bit password combinations are

valid as a password.

The Persistent Sector Protection Mode Locking Bit

Program Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word Mode Locking Bit from ever being programmed.

If the Persistent Sector Protection Mode Locking Bit is

verified as programmed without margin, the Persistent

Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once

this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by

writing the Read/Reset command.

SecSi Sector Protection Bit Program

Command

Password Verify Command

The SecSi Sector Protection Bit Program Command

programs the SecSi Sector Protection Bit, which pre-

vents the SecSi sector memory from being cleared. If

the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Bit Program Command should be reissued to improve

program margin. Exiting the V_CC-level SecSi Sector

Protection Bit Program Command is accomplished by

writing the Read/Reset command.

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Password, the device will al-

ways drive all F’s onto the DQ data bus.

The Password Verify command is permitted if the

SecSi sector is enabled. Also, the device will not oper-

ate in Simultaneous Operation when the Password

Verify command is executed. Only the password is re-

turned regardless of the bank address. The lower two

address bits (A1-A0) are valid during the Password

Verify. Writing the Read/Reset command returns the

device back to normal operation.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command was successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the device is taken through a power-on clear or

the Password Unlock command is executed. Upon set-

ting the PPB Lock Bit, the PPBs are latched into the

DYBs. If the Password Mode Locking Bit is set, the

PPB Lock Bit status is reflected as set, even after a

power-on reset cycle. Exiting the PPB Lock Bit Set

command is accomplished by writing the Read/Reset

command (only in the Persistent Protection Mode).

Password Protection Mode Locking Bit

Program Command

The Password Protection Mode Locking Bit Program

Command programs the Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the Password. Once programmed, the Password

Protection Mode Locking Bit cannot be erased! If the

Password Protection Mode Locking Bit is verified as

program without margin, the Password Protection

Mode Locking Bit Program command can be executed

to improve the program margin. Once the Password

Protection Mode Locking Bit is programmed, the Per-

sistent Sector Protection Locking Bit program circuitry

is disabled, thereby forcing the device to remain in the

Password Protection mode. Exiting the Mode Locking

Bit Program command is accomplished by writing the

Read/Reset command.

DYB Write Command

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits

A22-A12 for PDL127 and (A21–A12) for PDL129H are

issued at the same time as the code 01h or 00h on

DQ7-DQ0. All other DQ data bus pins are ignored dur-

ing the data write cycle. The DYBs are modifiable at

any time, regardless of the state of the PPB or PPB

Lock Bit. The DYBs are cleared at power-up or hard-

ware reset. Exiting the DYB Write command is accom-

plished by writing the Read/Reset command.

54

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

determine whether the PPB has been erased with

Password Unlock Command

margin. If the PPBs has been erased without margin,

the erase command should be reissued to improve the

program margin.

The Password Unlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlocking function to occur.

This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through all

64-bit combinations in an attempt to correctly match a

password. If the command is issued before the 2 µs

execution window for each portion of the unlock, the

command will be ignored.

It is the responsibility of the user to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the user attempts to erase a cleared PPB, over-era-

sure may occur making it difficult to program the PPB

at a later time. Also note that the total number of PPB

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

DYB Write Command

Once the Password Unlock command is entered, the

RY/BY# indicates that the device is busy. Approxi-

mately 1 µs is required for each portion of the unlock.

Once the first portion of the password unlock com-

pletes (RY/BY# is not low or DQ6 does not toggle

when read), the next part of the password is written.

The system must thus monitor RY/BY# or the status

bits to confirm when to write the next portion of the

password. Seven cycles are required to successfully

clear the PPB Lock Bit.

The DYB Write command is used for setting the DYB,

which is a volatile bit that is cleared at reset. There is

one DYB per sector. If the PPB is set, the sector is pro-

tected regardless of the value of the DYB. If the PPB is

cleared, setting the DYB to a 1 protects the sector from

programs or erases. Since this is a volatile bit, remov-

ing power or resetting the device will clear the DYBs.

The bank address is latched when the command is

written.

PPB Lock Bit Set Command

PPB Program Command

The PPB Lock Bit set command is used for setting the

DYB, which is a volatile bit that is cleared at reset.

There is one DYB per sector. If the PPB is set, the sec-

tor is protected regardless of the value of the DYB. If

the PPB is cleared, setting the DYB to a 1 protects the

sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear

the DYBs. The bank address is latched when the com-

mand is written.

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

grammed (but is bulk erased with the other PPBs).

The specific sector address (A21–A12) are written at

the same time as the program command 60h with A6

= 0. If the PPB Lock Bit is set and the corresponding

PPB is set for the sector, the PPB Program command

will not execute and the command will time-out without

programming the PPB.

After programming a PPB, two additional cycles are

needed to determine whether the PPB has been pro-

grammed with margin. If the PPB has been pro-

grammed without margin, the program command

should be reissued to improve the program margin.

Also note that the total number of PPB program/erase

cycles is limited to 100 cycles. Cycling the PPBs be-

yond 100 cycles is not guaranteed.

PPB Status Command

The programming of the PPB for a given sector can be

verified by writing a PPB status verify command to the

device.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sec-

tor can be verified by writing a PPB Lock Bit status ver-

ify command to the device.

The PPB Program command does not follow the Em-

bedded Program algorithm.

Sector Protection Status Command

The programming of either the PPB or DYB for a given

sector or sector group can be verified by writing a Sec-

tor Protection Status command to the device.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

ing a specific PPB. Unlike the PPB program, no spe-

cific sector address is required. However, when the

PPB erase command is written all Sector PPBs are

erased in parallel. If the PPB Lock Bit is set the ALL

PPB Erase command will not execute and the com-

mand will time-out without erasing the PPBs. After

erasing the PPBs, two additional cycles are needed to

Note that there is no single command to independently

verify the programming of a DYB for a given sector

group.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

55

A D V A N C E I N F O R M A T I O N

Command Definitions Tables

Table 16. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data Addr Data

RA RD

XXX F0

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

1

4

6

Manufacturer ID

555

AA 2AA

55

555

90 (BA)X00

90 (BA)X01

01

7E

Device ID (10)

AA 2AA

(BA)X0E (Note 10) (BA)X0F

00

Autoselect

(Note 7)

SecSi Sector Factory

Protect (8)

(see

note 8)

4

555

AA 2AA

55

555

90

X03

Sector Group Protect

Verify (9)

XX00/

XX01

555 AAA 2AA

90 (SA)X02

Program

4

6

1

2

3

2

1

2

555

BA

55

AA 2AA

B0

55

555

A0

80

PA

555

PD

AA

Chip Erase

Sector Erase

2AA

55

555

SA

10

30

Program/Erase Suspend (11)

Program/Erase Resume (12)

CFI Query (13)

30

98

Accelerated Program (15)

Unlock Bypass Entry (15)

Unlock Bypass Program (15)

Unlock Bypass Erase (15)

Unlock Bypass CFI (13, 15)

Unlock Bypass Reset (15)

XX

555

XX

A0

PA

PD

55

AA 2AA

555

20

A0

80

98

PA

PD

10

XX

XXX 90 XXX 00

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or

erase operation. Determined by A22:A20, (A21:A20 for PDL129) see

Tables 4 and 5 for more detail.

PA = Program Address (A22:A0) (A21:A0 for PDL129). Addresses

latch on falling edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse,

whichever happens later.

PD = Program Data (DQ15:DQ0) written to location PA. Data latches

on rising edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse,

whichever happens first.

RA = Read Address (A22:A0) (A21:A0 for PDL129).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A22:A12) (A21:A12 for PDL129) for verifying (in

autoselect mode) or erasing.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Don’t care

Notes:

1. See Table 1 for description of bus operations.

8. The data is C0h for factory or customer locked and 80h for factory

locked.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

10. Device ID must be read across cycles 4, 5, and 6. 20 for

Am29PDL127H and 21 for Am29PDL129H.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

11. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector

erase operation, and requires bank address.

5. No unlock or command cycles required when bank is reading

array data.

12. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

6. The Reset command is required to return to reading array (or to

erase-suspend-read mode if previously in Erase Suspend) when

bank is in autoselect mode, or if DQ5 goes high (while bank is

providing status information).

13. Command is valid when device is ready to read array data or

when device is in autoselect mode.

7. Fourth cycle of autoselect command sequence is a read cycle.

System must provide bank address to obtain manufacturer ID or

device ID information. See Autoselect Command Sequence

section for more information.

14. WP#/ACC must be at V_IDduring the entire operation of command.

15. Unlock Bypass Entry command is required prior to any Unlock

Bypass operation. Unlock Bypass Reset command is required to

return to the reading array.

56

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 17. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command

(Notes)

Addr Data Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

1

3

4

XXX

555

F0

SecSi Sector Entry

SecSi Sector Exit

AA 2AA

55

555

88

90

XX

00

68

SecSi Protection

Bit Program (5, 6)

6

5

4

7

555

AA 2AA

55

555

60

38

C8

28

OW

48

OW

RD(0)

SecSi Protection

Bit Status

OW

48

RD(0)

PasswordProgram

(5, 7, 8)

XX[0-3]

PWA[0-3]

PWA[0]

PD[0-3]

PWD[0-3]

PWD[0]

Password Verify

(6, 8, 9)

Password Unlock

(7, 10, 11)

PWA[1]

PWD[1]

PWA[2]

(SA)WP

PWD[2]

RD(0)

PWA[3]

PWD[3]

PPBProgram (5, 6,

12, 17)

6

5

6

555

AA 2AA

55

555

60

(SA)WP

WP

68

48

60

(SA)WP

(SA)

48

RD (0)

40

PPB Status

All PPB Erase (5,

6, 13, 14)

(SA)WP

RD(0)

PPB Lock Bit Set

(17)

3

4

555

AA 2AA

55

555

78

58

PPB Lock Bit

Status (15)

SA

RD(1)

DYB Write (7)

4

555

AA 2AA

55

555

48

58

SA

X1

X0

DYB Erase (7)

DYB Status (6, 18)

RD(0)

PPMLB Program

(5, 6, 12)

6

5

6

5

555

AA 2AA

55

555

60

PL

SL

68

48

68

48

PL

SL

48

PL

SL

RD(0)

PPMLB Status (5)

RD(0)

48

SPMLB Program

(5, 6, 12)

SPMLB Status (5)

RD(0)

Legend:

DYB = Dynamic Protection Bit

RD(1) = Read Data DQ1 for PPB Lock status.

OW = Address (A7:A0) is (00011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

SA = Sector Address where security command applies. Address bits

A21:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010)

WP = PPB Address (A7:A0) is (00000010) (NoteTable.16

31096a1.fm)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

PL = Password Protection Mode Lock Address (A7:A0) is (00001010)

RD(0) = Read Data DQ0 for protection indicator bit.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

10. The password is written over four consecutive cycles, at

addresses 0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed to prevent PPB

overerasure.

5. The reset command returns device to reading array.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0

in cycle 6, program command must be issued and verified again.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For PDL128G and PDL640G, the WP address is 0111010. The

EP address (PPB Erase Address) is 1111010.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of

password.

17. Following the final cycle of the command sequence, the user must

write the first three cycles of the Autoselect command and then

write a Reset command.

9. Command sequence returns FFh if PPMLB is set.

18. If checking the DYB status of sectors in multiple banks, the user

must follow Note 17 before crossing a bank boundary.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

57

A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 18 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ15–DQ0 may be still

invalid. Valid data on DQ15–DQ0 will appear on suc-

cessive read cycles.

Table 18 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 6

in the AC Characteristics section shows the Data#

Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 400 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 on the following read cycles. Just prior to

the completion of an Embedded Program or Erase op-

eration, DQ7 may change asynchronously with

DQ15–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

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Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 18 shows the outputs for Toggle Bit I on DQ6.

Figure 7 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 22 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read Byte

(DQ7–DQ0)

Address =VA

Table 18 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE#f1 to control the read cycles. When the operation

is complete, DQ6 stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 400 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Read Byte Twice

(DQ7–DQ0)

Address = VA

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 7. Toggle Bit Algorithm

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

59

A D V A N C E I N F O R M A T I O N

The remaining scenario is that the system initially de-

DQ2: Toggle Bit II

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 7).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE#f1 to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 18 to compare out-

puts for DQ2 and DQ6.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Figure 7 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 21 shows the toggle bit timing diagram. Figure

22 shows the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

Reading Toggle Bits DQ6/DQ2

DQ3: Sector Erase Timer

Refer to Figure 7 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” See also the Sector Erase

Command Sequence section.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 18 shows the status of DQ3 relative to the other

status bits.

60

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 18. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

61

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . . –40°C to +85°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CCf, V_CCs (Note 1) . . . . . . . . . . . .–0.5 V to +4.0 V

RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1) . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Figure 8. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 9.

20 ns

V_CC

+2.0 V

2. Minimum DC input voltage on pins RESET#, and

WP#/ACC is –0.5 V. During voltage transitions,

WP#/ACC, and RESET# may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 8. Maximum DC input

voltage on pin RESET# is +12.5 V which may overshoot

to +14.0 V for periods up to 20 ns. Maximum DC input

voltage on WP#/ACC is +9.5 V which may overshoot to

+12.0 V for periods up to 20 ns.

V_CC

+0.5 V

2.0 V

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

devices that are developed by a third party (‘third-party

components”).

OPERATING RANGES

Industrial (I) Devices

Spansion components are tested and guaranteed to

the ESD immunity levels listed in the corresponding

Spansion Flash memory Qualification Database.

Third-party components are neither tested nor guaran-

teed by FASL LLC for ESD immunity. However, ESD

test results for third-party components may be avail-

able from the component manufacturer. Component

manufacturer contact information is listed in the Span-

sion MCP Qualification Report, when available.

Ambient Temperature (T_A) . . . . . . . . . –25°C to +85°C

V_CCf/V_CCs Supply Voltages

V

_CCf/V_CCs for standard voltage range . .2.7 V to 3.3 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

ESD IMMUNITY

Spansion Flash memory Multi-Chip Products (MCPs)

may contain component devices that are developed by

FASL LLC (“Spansion components”) and component

The Spansion Flash memory Qualification Database

and Spansion MCP Qualification Report are available

from AMD and Fujitsu sales offices.

62

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

63

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

V_CC= V_{CC max}

,

I_LI

Input Load Current

1.0

µA

I_LIT

I_LR

A9, OE#, RESET# Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

35

µA

V_OUT= V_SSto V_CC, OE# = V_IH

V_CC= V_{CC max}

I_LO

Output Leakage Current

1.0

µA

mA

5 MHz

20

45

30

55

V_CCActive Read Current (Notes Table.1

31096a1.fm, 2, 3)

OE# = V_IH, V_CC= V_{CC max}

(Note 1)

I_CC1

10 MHz

V_CCActive Write Current (Notes Table.1

31096a1.fm, 3, 4)

I_CC2

OE# = V_IH, WE# = V_IL

15

25

CE#f1, CE#f2 (PDL129 only),

RESET#, WP/ACC# = V_IO0.3 V

I_CC3

I_CC4

I_CC5

V_CCStandby Current (Note 3)

V_CCReset Current (Note 3)

1

5

µA

RESET# = V_SS0.3 V, CE# = V_SS

V_IH= V_IO0.3 V;

V_IL= V_SS0.3 V, CE# = V_SS

Automatic Sleep Mode (Notes 3, 5)

V_CCActive Read-While-Program Current

(Notes 1, 2, 3)

I_CC6

I_CC7

I_CC8

OE# = V_IH

Word

21

17

45

25

mA

V_CCActive Read-While-Erase Current

(Notes 1, 2, 3)

V_CCActive Program-While-Erase-

Suspended Current (Notes 1, 3, 6)

V_IL

V_IH

V_HH

Input Low Voltage

V_IO= 2.7–3.6 V

V_CC= 3.0 V 10%

–0.5

2.0

0.8

V

_CC+0.3

Input High Voltage

Voltage for ACC Program Acceleration

8.5

9.5

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 3.0 V 10%

11.5

12.5

0.4

V

V_OL

V_OH

V_LKO

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

V

Output High Voltage

2.4

2.3

Low V_CCLock-Out Voltage (Note 6)

2.5

Notes:

1. Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= V_IL, CE#f2=

_IH) or (CE#f1= V_IH, CE#f2= V_IL)

4. I_CCactive while Embedded Erase or Embedded Program is in

progress.

V

2. The I_CCcurrent listed is typically less than 5 mA/MHz, with OE# at

V_IH.

5. Automatic sleep mode enables the low power mode when

addresses remain stable for t_ACC+ 150 ns. Typical sleep mode

current is 1 µA.

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax

.

6. Not 100% tested.

64

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 19. Test Specifications

3.3 V

Test Condition

Output Load

70

Unit

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

70

5

pF

Input Rise and Fall Times

Input Pulse Levels

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 10. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 11. Input Waveforms and Measurement Levels

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

65

A D V A N C E I N F O R M A T I O N

pSRAM AC CHARACTERISTICS

CE#1ps Timing

Parameter

Test Setup

AllSpeeds

Unit

JEDEC

Std

Description

—

t_CCR

CE#1ps Recover Time

—

Min

0

ns

CE#1ps

CE2ps

t_CCR

Figure 12. Timing Diagram for Alternating

Between Pseudo SRAM and Flash

66

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read-Only Operations – Am29PDL127H

Parameter

All Speeds

JEDEC

t_AVAV

Std. Description

Test Setup

70

30

16

Unit

ns

t_RC

t_ACC

t_CE

Read Cycle Time (Note 1)

Min

Max

t_AVQV

Address to Output Delay

CE#f1, OE# = V_IL

OE# = V_IL

ns

t_ELQV

Chip Enable to Output Delay

ns

t_PACCPage Access Time

ns

t_GLQV

t_EHQZ

t_GHQZ

t_OE

t_DF

Output Enable to Output Delay

ns

Chip Enable to Output High Z (Note 1, 3)

Output Enable to Output High Z (Notes 1, 3)

ns

Output Hold Time From Addresses, CE#f1 or

OE#, Whichever Occurs First (Notes 3)

t_AXQX

t_OH

Min

5

0

ns

Read

Output Enable Hold Time

(Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

3. Measurements performed by placing a 50 ohm termination on the

data pin with a bias of V_CC/2. The time from OE# high to the data

2. See Figure 10 and Table 19 for test specifications

bus driven to V_CC/2 is taken as t_DF

.

Read-Only Operations – Am29PDL129H

Parameter

All Speeds

JEDEC

t_AVAV

Std. Description

Test Setup

70

30

16

Unit

ns

t_RC

t_ACC

t_CE

Read Cycle Time (Note 1)

Min

Max

t_AVQV

Address to Output Delay (Note 3)

CE#f1, OE# = V_IL

OE# = V_IL

ns

t_ELQV

Chip Enable to Output Delay (Note 4)

ns

t_PACCPage Access Time

ns

t_GLQV

t_EHQZ

t_GHQZ

t_OE

t_DF

Output Enable to Output Delay

ns

Chip Enable to Output High Z (Notes 1, 5, 6)

Output Enable to Output High Z (Notes 1, 5)

ns

Output Hold Time From Addresses,

CE#f1/CE#f2 or OE#, Whichever Occurs First

(Notes 5, 6)

t_AXQX

t_OH

Min

5

ns

Read

Min

0

ns

Output Enable Hold Time

(Note 1)

t_OEH

Toggle and

Data# Polling

10

Notes:

1. Not 100% tested.

5. Measurements performed by placing a 50 ohm termination on the

data pin with a bias of V_CC/2. The time from OE# high to the data

2. See Figure 10 and Table 19 for test specifications

bus driven to V_CC/2 is taken as t_DF

.

3. Valid CE#f1/CE#f2 conditions: (CE#f1= V_IL, CE#f2= V_IH) or

(CE#f1= V_IH, CE#f2=V_IL).

6. Valid CE#f1/CE#f2 transitions: (CE#f1= V_IL, CE#f2= V_IH) or

(CE#f1= V_IH, CE#f2=V_IL) to (CE#f1= CE#f2= V_IH).

4. Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= V_IH) to (CE#f1=

V_IL, CE#f2=V_IH) or (CE#f1= V_IH, CE#f2=V_IL).

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

67

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_RC

Addresses Stable

t_ACC

Addresses

CE#f1

or CE#f2

(PDL 129 only)

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

Same Page

Addresses

A2-A0

Ad

Qd

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data

Qa

Qb

Qc

CE# f1

or CE#f2 (PDL129 only)

OE#

Figure 14. Page Read Operation Timings

Notes: During CE#f1 transitions, CE#f2= V_IH; During CE#f2 transitions, CE#f1= V_IH

68

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

RESET# Pin Low (During Embedded Algorithms)

All Speed Options

Unit

t_Ready

Max

20

µs

to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#f1,

CE#f2 (PDL129 only),

OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#1

t_RB

CE#f1,

CE#f2 (PDL129 only),

OE#

RESET#

t_RP

Figure 15. Reset Timings

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

69

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase and Program Operations

Parameter

All

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Speeds

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

65

0

t_AVWL

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

35

ns

t_WLAX

ns

Address Hold Time From CE#1f or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

30

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

10

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_WLEL

t_ELWL

t_WS

t_CS

WE# Setup Time (CE#f1 to WE#)

CE#f1 Setup Time

Min

Typ

0

ns

µs

t_EHWH

t_WHEH

t_WLWH

t_WHDL

t_WH

WE# Hold Time (CE#f1 to WE#)

CE#f1 Hold Time

0

t_CH

0

t_WP

Write Pulse Width

40

25

0

t_WPH

t_SR/W

t_WHWH1

Write Pulse Width High

Latency Between Read and Write Operations

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Word

6

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

Typ

4

µs

t_WHWH2

t_VCS

Sector Erase Operation (Note 2)

V_CCSetup Time (Note 1)

Typ

Min

Max

0.5

50

0

sec

µs

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

70

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#f1

or CE#f2

(PDL129 only)

t_CH

t_GHWL

OE#

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

t_BUSY

t_RB

RY/BY#

V

_CCf

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

3. For PDL129 during CE#f1 transitions the other CE#f1 pin = V_IH.

Figure 16. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 17. Accelerated Program Timing Diagram

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

71

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

t_WC

VA

Addresses

2AAh

SADD

555h for chip erase

t_AH

CE#f1

(PDL129 only)

t_GHWL

t_CH

OE#

WE#

t_WP

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

t_VCS

V_CC

f

Notes:

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.

2. For PDL129 during CE#f1 transitions the other CE#f1 pin = V_IH.

Figure 18. Chip/Sector Erase Operation Timings

72

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

t_AH

Valid RA

Valid PA

Addresses

t_CPH

t_ACC

t_CE

CE#f1 or

CE#f2 (PDL129 only)

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE#f Controlled Write Cycles

Figure 19. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#f1 or

CE#f2 (PDL129 only)

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

73

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#f1 or

CE#f2 (PDL129 only)

t_CEPH

t_OEH

WE#

OE#

t_OEPH

t_DH

t_OE

Valid

Status

Valid

Status

Valid

Status

Valid Data

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#f1 to

toggle DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

74

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#f1 or

CE#f2 (PDL129 only)

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Unprotect Timing Diagram

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

75

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SADD,

A6, A1, A0

Valid*

Sector/Sector Block Protect or Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#f1 or

CE#f1(PDL129 only)

WE#

OE#

1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.

2. For PDL129 during CE#f1 transitions the other CE#f1 pin = V_IH

.

Figure 24. Sector/Sector Block Protect and

Unprotect Timing Diagram

76

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

All

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

Speeds

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

0

t_AVWL

t_ELAX

t_DVEH

t_EHDX

ns

t_AH

t_DS

t_DH

35

30

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

0

ns

CE#f Pulse Width

CE#f Pulse Width High

40

25

t_CPH

Programming Operation

(Note 2)

t_WHWH1

Word

Typ

6

µs

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Typ

4

µs

Sector Erase Operation (Note 2)

0.4

sec

1. Not 100% tested.

2. See the “Flash Erase And Programming Performance” section for more information.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

77

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SADD for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#f1 or

CE#f2 (PDL129 only)

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SADD = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

Figure 25. Flash Alternate CE# Controlled Write (Erase/Program) Operation Timings

78

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.4

5

Excludes 00h programming

prior to erasure (Note 4)

108

Excludes system level

overhead (Note 5)

Word Program Time

6

210

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

4

120

200

µs

50

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern. All values are subject to change.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles. All values are subject to change.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables

Table 16 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

PACKAGE PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

11

Max

14

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

V_OUT= 0

V_IN= 0

12

16

pF

Control Pin Capacitance

WP#/ACC Pin Capacitance

14

16

pF

C_IN3

V_IN= 0

17

20

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

FLASH DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

79

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29DL640H Device Bus Operations

Addresses

(Note 2)

DQ7–

DQ0

Operation

CE#

L

OE#

L

WE#

H

RESET#

WP#/ACC

L/H

DQ15–DQ8

D_OUT

Read

Write

H

A_IN

D_OUT

D_IN

L

H

L

(Note 3)

A_IN

D_IN

V_CC

0.3 V

V_CC

0.3 V

Standby

X

L/H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

H

X

L

X

V_ID

L/H

X

D_IN

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

(Note 3)

Temporary Sector

Unprotect

X

A_IN

D_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 9.0 0.5 V, X = Don’t Care, SA = Sector Address,

_IN= Address In, D_IN= Data In, D_OUT= Data Out

A

Notes:

1. Addresses are A21:A0 in word mode.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

3. If WP#/ACC = V_IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = V_IH, protection on sectors 0, 1, 140, and 141

depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection

and Unprotection”. If WP#/ACC = V_HH, all sectors will be unprotected.

control and selects the device. OE# is the output con-

Word/Byte Configuration

trol and gates array data to the output pins. WE#

The BYTE# pin controls whether the device data I/O

should remain at V_IH. The BYTE# pin determines

pins operate in the byte or word configuration. If the

whether the device outputs array data in words or

BYTE# pin is set at logic ‘1’, the device is in word con-

bytes.

figuration, DQ15–DQ0 are active and controlled by

CE# and OE#.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ14–DQ8 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

80

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Refer to the AC AC Characteristics table for timing

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 87 for related infor-

mation.

specifications and to Figure 13 for the timing diagram.

I_CC1in the DC Characteristics table represents the ac-

tive current specification for reading array data.

Autoselect Functions

Writing Commands/Command Sequences

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Requirements for Reading Array

Data” for more information.

Simultaneous Read/Write Operations with

Zero Latency

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The “Word

Program Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 19 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I_CC6and I_CC7in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

I_CC3in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

81

A D V A N C E I N F O R M A T I O N

dresses are changed. While in sleep mode, output

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

data is latched and always available to the system.

I_CC5in the DC Characteristics table represents the

automatic sleep mode current specification.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Refer to the pSRAM AC Characteristics tables for RE-

SET# parameters and to Figure 15 for the timing dia-

gram.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Am29DL640H Sector Architecture

Sector Address

A21–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA0

SA1

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001111xxx

4

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank 1

82

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 2. Am29DL640H Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011000xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0101011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0100100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

32

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

F9000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Bank 2

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

83

A D V A N C E I N F O R M A T I O N

Table 2. Am29DL640H Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

32

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–28FFFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2FFFFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

Bank 3

84

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 2. Am29DL640H Sector Architecture (Continued)

Sector Address

A21–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

1111110xxx

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

32

4

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

Bank 4

4

Table 3. Bank Address

Bank

A21–A19

1

2

3

4

000

001, 010, 011

100, 101, 110

111

Table 4. SecSi^TMSector Addresses

(x16)

Device

Sector Size

Address Range

Am29DL640H

256 bytes

00000h–0007Fh

set as required, the programming equipment may then

read the corresponding identifier code on DQ7–DQ0.

However, the autoselect codes can also be accessed

in-system through the command register, for instances

when the Am29DL640 is erased or programmed in a

system without access to high voltage on the A9 pin.

The command sequence is illustrated in Table 11.

Note that if a Bank Address (BA) on address bits A21,

A20, and A19 is asserted during the third write cycle of

the autoselect command, the host system can read

autoselect data from that bank and then immediately

read array data from the other bank, without exiting the

autoselect mode.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipment, the autoselect

mode requires V_IDon address pin A9. Address pins

must be as shown in Table 5. In addition, when verify-

ing sector protection, the sector address must appear

on the appropriate highest order address bits (see

Table 2). Table 5 shows the remaining address bits

that are don’t care. When all necessary bits have been

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 11. This method

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

85

A D V A N C E I N F O R M A T I O N

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

86

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Sector/Sector Block Protection and

Unprotection

Sector/

Sector Block Size

Sector

A21–A12

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

256 (4x64) Kbytes

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table

10).

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

1111100XXX,

1111101XXX,

1111110XXX

SA131–SA133

192 (3x64) Kbytes

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111111

8 Kbytes

Table 5. Am29DL640H Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A21–A12

Sector Block Size

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

8 Kbytes

Sector protection/sector unprotection requires V_IDon

the RESET# pin only, and can be implemented either

in-system or via programming equipment. Figure 1

shows the algorithms and Figure 24 shows the timing

diagram. For sector unprotect, all unprotected sectors

must first be protected prior to the first sector unpro-

tect write cycle. Note that the sector unprotect algo-

rithm unprotects all sectors in parallel. All previously

protected sectors must be individually re-protected. To

change data in protected sectors efficiently, the tem-

porary sector unprotect function is available. See

“Temporary Sector Unprotect”.

8 Kbytes

0000001XXX,

0000010XXX,

0000011XXX,

SA8–SA10

192 (3x64) Kbytes

SA11–SA14

SA15–SA18

SA19–SA22

SA23–SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55–SA58

SA59–SA62

SA63–SA66

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

256 (4x64) Kbytes

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode sec-

tion for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting without using V_ID. This function is

one of two provided by the WP#/ACC pin.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in sectors

0, 1, 140, and 141, independently of whether those

sectors were protected or unprotected using the

method described in “Sector/Sector Block Protection

and Unprotection”.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

87

A D V A N C E I N F O R M A T I O N

If the system asserts V_IHon the WP#/ACC pin, the de-

Temporary Sector Unprotect

vice reverts to whether sectors 0, 1, 140, and 141

were last set to be protected or unprotected. That is,

sector protection or unprotection for these sectors de-

pends on whether they were last protected or unpro-

tected using the method described in “Sector/Sector

Block Protection and Unprotection”.

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table

10).

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 23 shows the timing diagrams, for this feature.

If the WP#/ACC pin is at V_IL, sectors 0, 1, 140, and

141 will remain protected during the Temporary sector

Unprotect mode.

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

Table 6. WP#/ACC Modes

Device

Mode

WP# Input

Voltage

Disables programming and erasing in

SA0, SA1, SA140, and SA141

V_IL

V_IH

Enables programming and erasing in

SA0, SA1, SA140, and SA141

Enables accelerated programming

(ACC). See “Accelerated Program

Operation” on page 20.

V_HH

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

sectors 0, 1, 140, and 141 will remain protected).

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

88

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

PLSCNT = 1

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 4 µs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A7-A0 =

Yes

Set up first sector

address

00000010

Sector Unprotect:

Wait 100 µs

Write 60h to sector

address with

A7-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A7-A0 =

01000010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.2 ms

00000010

Verify Sector

Unprotect: Write

40h to sector

address with

A7-A0 =

Read from

sector address

with A7-A0 =

00000010

Increment

PLSCNT

No

00000010

No

PLSCNT

= 25?

Read from

sector address

with A7-A0 =

00000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

Remove V_ID

from RESET#

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

No

Write reset

command

Yes

Remove V_ID

from RESET#

Remove V_ID

from RESET#

No

Last sector

verified?

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Unprotect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

89

A D V A N C E I N F O R M A T I O N

programmed in the next 8 words at addresses

SecSi™ (Secured Silicon) Sector

Flash Memory Region

000008h–00000Fh (or 000010h–00001Fh in byte

mode). The device is available preprogrammed with

one of the following:

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize the that

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicator Bit permanently set to a “0.” Thus, the SecSi

Sector Indicator Bit prevents customer-lockable de-

vices from being used to replace devices that are fac-

tory locked.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space.

The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

The system accesses the SecSi Sector Secure

through a command sequence (see “Enter SecSi™

Sector/Exit SecSi Sector Command Sequence”). After

the system has written the Enter SecSi Sector com-

mand sequence, it may read the SecSi Sector by

using the addresses normally occupied by the boot

sectors. This mode of operation continues until the

system issues the Exit SecSi Sector command se-

quence, or until power is removed from the device. On

power-up, or following a hardware reset, the device re-

verts to sending commands to the first 256 bytes of

Sector 0. Note that the ACC function and unlock by-

pass modes are not available when the SecSi Sector

is enabled.

The SecSi Sector area can be protected using one of

the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 1, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a secure ESN. The 8-word random number is at

addresses 000000h–000007h in word mode (or

000000h–00000Fh in byte mode). The secure ESN is

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

90

Am75PDL191CHH/Am75PDL193CHH

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A D V A N C E I N F O R M A T I O N

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

START

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Wait 1 µs

COMMON FLASH MEMORY INTERFACE

(CFI)

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 12–15. To terminate reading CFI data,

the system must write the reset command.The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or embedded Erase al-

gorithm.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 11 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 12–15. The

system must write the reset command to return the

device to reading array data.

Low V_CCWrite Inhibit

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

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A D V A N C E I N F O R M A T I O N

Table 7. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 8. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

92

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Table 9. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0017h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

007Dh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

93

A D V A N C E I N F O R M A T I O N

Table 10. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

Query-unique ASCII string “PRI”

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0004h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors (excluding Bank 1)

4Ah

4Bh

4Ch

94h

96h

98h

0077h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

9Ah

9Ch

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot

with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Both Top and Bottom

4Fh

9Eh

0004h

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

A0h

AEh

B0h

B2h

B4h

B6h

0001h

0004h

0017h

0030h

0017h

0 = Not supported, 1 = Supported, but not tested

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

94

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 11 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place

the device to an unknown state. A reset command is

required to return the device to read array data.

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the pSRAM AC Characteristics section

for timing diagrams.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device out-

puts status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume Com-

mands section for more information.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read any number of

autoselect codes without reinitiating the command se-

quence.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the

section for more information. The AC Characteristics

table provides the read parameters, and Figure 13

shows the timing diagram.

Table 11 shows the address and data requirements.

To determine sector protection information, the system

must write to the appropriate bank address (BA) and

sector address (SA). Table 2 shows the address range

and bank number associated with each sector.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

The SecSi Sector region provides a secured data area

containing a random, sixteen-byte electronic serial

number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system is-

The reset command may be written between the

sequence cycles in a program command sequence

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

95

A D V A N C E I N F O R M A T I O N

sues the four-cycle Exit SecSi Sector command se-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

quence. The Exit SecSi Sector command sequence

returns the device to normal operation. The SecSi

Sector is not accessible when the device is executing

an Embedded Program or embedded Erase algorithm.

Table 11 shows the address and data requirements for

both command sequences. See also “SecSi™ (Se-

cured Silicon) Sector Flash Memory Region” for further

information. Note that the ACC function and unlock by-

pass modes are not available when the SecSi Sector

is enabled.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 11 shows the require-

ments for the command sequence.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 11 shows the address

and data requirements for the byte program command

sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. See Table 12.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. SecSi sector, autoselect, and CFI are not

allowed. The program command sequence should be

reinitiated once that bank has returned to the read

mode, to ensure data integrity. Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 16 for timing diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

96

Am75PDL191CHH/Am75PDL193CHH

February 5, 2004

A D V A N C E I N F O R M A T I O N

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 11 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 80 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to the read mode. No SecSi sector, au-

toselect, or CFI is available. The system must rewrite

the command sequence and any additional addresses

and commands.

Note: See Table 11 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 11

shows the address and data requirements for the chip

erase command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits. Note that the

SecSi Sector, autoselect, and CFI functions are un-

available when a program operation is in progress.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

February 5, 2004

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97

A D V A N C E I N F O R M A T I O N

termine the status of the erase operation by reading

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 80 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation. Addresses are “don’t-cares” when

writing the Erase suspend command.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

START

Write Erase

Command Sequence

(Notes 1, 2)

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. The device

allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid operation.

Refer to the Autoselect Mode and Autoselect Com-

mand Sequence sections for details.

Yes

Erasure Completed

Notes:

1. See Table 11 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Figure 5. Erase Operation

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

98

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A D V A N C E I N F O R M A T I O N

Table 11. Am29DL640H Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Addr

Sixth

Addr

Addr Data Addr Data

Data

Addr

Data

Read (Note 5)

Reset (Note 6)

1

RA

XXX

555

AAA

555

AAA

555

AAA

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

Word

2AA

555

2AA

555

2AA

555

2AA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

Manufacturer ID

4

6

4

AA

55

90 (BA)X00

01

7E

(BA)X01

90

(BA)X0E

(BA)X1C

(BA)X0F

(BA)X1E

Device ID (Note 9)

02

01

(BA)X02

(BA)X03

(BA)X06

SecSi Sector Factory

Protect (Note 10)

90

80/00

Sector/Sector Block

Protect Verify

(Note 11)

(SA)X02

4

AA

55

90

00/01

Byte

AAA

555

(BA)AAA

(SA)X04

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

555

AAA

XXX

555

AAA

555

AAA

BA

2AA

555

2AA

555

2AA

555

2AA

555

PA

XXX

2AA

555

2AA

555

AAA

555

AAA

555

AAA

555

AAA

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

AA

55

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 15)

Unlock Bypass Reset (Note 15)

2

A0

90

PD

00

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

AAA

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

Word

Sector Erase

Byte

SA

AAA

Erase Suspend (Note 11)

Erase Resume (Note 12)

1

B0

30

BA

Word

CFI Query (Note 13)

Byte

55

AA

1

98

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A21–A12 uniquely select any sector. Refer to

Table 2 for information on sector addresses.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased. A21–A19 uniquely select a bank.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

9. The device ID must be read across the fourth, fifth, and sixth

cycles.

10. The data is 80h for factory locked, 40h for customer locked, and

00h for not factory/customer locked.

11. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

3. Except for the read cycle and the fourth, fifth, and sixth cycle of

the autoselect command sequence, all bus cycles are write

cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A21–A11 are don’t cares for

unlock and command cycles, unless SA or PA is required.

6. No unlock or command cycles required when bank is reading

array data.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15–DQ8 are don’t care. While reading

the autoselect addresses, the bank address must be the same

until a reset command is given. See the Autoselect Command

Sequence section for more information.

16. Command is valid when device is ready to read array data or when

device is in autoselect mode.

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A D V A N C E I N F O R M A T I O N

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 18 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

vice has completed the program or erase operation

and DQ7 has valid data, the data outputs on

DQ15–DQ0 may be still invalid. Valid data on

DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will ap-

pear on successive read cycles.

Table 18 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 20

in the pSRAM AC Characteristics section shows the

Data# Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the

following read cycles. Just prior to the completion of an

Embedded Program or Erase operation, DQ7 may

change asynchronously with DQ15–DQ8 (DQ7–DQ0

for x8-only device) while Output Enable (OE#) is as-

serted low. That is, the device may change from pro-

viding status information to valid data on DQ7.

Depending on when the system samples the DQ7 out-

put, it may read the status or valid data. Even if the de-

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

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A D V A N C E I N F O R M A T I O N

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 18 shows the outputs for Toggle Bit I on DQ6.

Figure 7 shows the toggle bit algorithm. Figure 21 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 22 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read Byte

(DQ7–DQ0)

Address =VA

Table 18 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Read Byte Twice

(DQ7–DQ0)

Address = VA

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 7. Toggle Bit Algorithm

February 5, 2004

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101

A D V A N C E I N F O R M A T I O N

not gone high. The system may continue to monitor

DQ2: Toggle Bit II

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 7).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 18 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Figure 7 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 21 shows the toggle bit timing diagram. Figure

22 shows the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

Reading Toggle Bits DQ6/DQ2

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Refer to Figure 7 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only

device) at least twice in a row to determine whether a

toggle bit is toggling. Typically, the system would note

and store the value of the toggle bit after the first read.

After the second read, the system would compare the

new value of the toggle bit with the first. If the toggle bit

is not toggling, the device has completed the program

or erase operation. The system can read array data on

DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the

following read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 18 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

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A D V A N C E I N F O R M A T I O N

Table 12. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

February 5, 2004

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103

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1) . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 8. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 9.

20 ns

V_CC

+2.0 V

V_CC

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 8. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

+0.5 V

2.0 V

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Spansion Flash MultiChip memory products are not

tested or guaranteed for any level of ESD immunity on

components not designed and manufactured by FASL

LLC. Please refer to individual MCP product qualifica-

tion reports for information on how to obtain ESD im-

munity information from manufacturers of such

components.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor standard voltage range . . . . . . .2.7 V to 3.3 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

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A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

V_IN= V_SSto V_CC

_CC= V_{CC max}

V_CC= V_{CC max}; A9 = 12.5 V

Min

Typ

Max

1.0

35

Unit

µA

,

I_LI

Input Load Current

V

I_LIT

I_LO

I_LR

A9 Input Load Current

Output Leakage Current

Reset Leakage Current

µA

V

_OUT= V_SSto V_CC

,

1.0

µA

V_CC= V_{CC max}

V_CC= V_{CC max}; RESET= 12.5 V

35

16

4

µA

5 MHz

10

2

CE# = V_IL, OE# ₌V_IH,

Byte Mode

1 MHz

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

5 MHz

10

2

16

4

CE# = V_IL, OE# = V_IH,

Word Mode

1 MHz

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3) CE# = V_IL, OE# = V_IH, WE# = V_IL

15

0.2

30

5

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC0.3 V

RESET# = V_SS0.3 V

5

V_IH= V_CC0.3 V;

V_IL= V_SS0.3 V

I_CC5

I_CC6

I_CC7

Automatic Sleep Mode (Notes 2, 4)

0.2

21

5

µA

mA

V_CCActive Read-While-Program

Current (Notes 1, 2)

CE# = V_IL, OE# = V_IH

Word

45

V_CCActive Read-While-Erase

Current (Notes 1, 2)

V_CCActive

I_CC8

Program-While-Erase-Suspended

Current (Notes 2, 5)

CE# = V_IL, OE# = V_IH

17

35

mA

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

V

0.7 x V_CC

V_CC+ 0.3

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V

_CC= 3.0 V 10%

8.5

9.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V

11.5

12.5

0.45

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 2.0 mA, V_CC= V_{CC min}

_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

I

0.85 V_CC

V_CC–0.4

2.0

Output High Voltage

Low V_CCLock-Out Voltage (Note 5)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

105

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I_CC1vs. Frequency

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A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 13. Test Specifications

3.1 V

Test Condition

Output Load

All Speed Options Unit

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

70

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 13. Input Waveforms and Measurement Levels

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read-Only Operations

Parameter

JEDEC

Std. Description

t_RCRead Cycle Time (Note 1)

Test Setup

All Speed Options Unit

t_AVAV

Min

70

ns

CE#,

OE# = V_IL

t_AVQV

t_ACCAddress to Output Delay

Max

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

70

30

16

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Notes 1, 3)

Output Enable to Output High Z (Notes 1, 3)

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold Time

(Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 19 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V_CC/2. The time from OE# high to

the data bus driven to V_CC/2 is taken as t_DF

.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

RESET# Pin Low (During Embedded Algorithms)

All Speed Options

Unit

t_Ready

Max

20

µs

to Read Mode (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 15. Reset Timings

February 5, 2004

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

All Speed Options

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

70

0

t_AVWL

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

40

ns

t_WLAX

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

40

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

µs

CE# Hold Time

t_WP

Write Pulse Width

30

0

t_WPH

t_SR/W

t_WHWH1

Write Pulse Width High

Latency Between Read and Write Operations

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

Typ

4

µs

t_WHWH2

t_VCS

Sector Erase Operation (Note 2)

V_CCSetup Time (Note 1)

Typ

Min

Max

0.4

50

0

sec

µs

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 16. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 17. Accelerated Program Timing Diagram

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operation Timings

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February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# or CE2# Controlled Write Cycles

Figure 19. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

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AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Unprotect Timing Diagram

February 5, 2004

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 24. Sector/Sector Block Protect and

Unprotect Timing Diagram

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February 5, 2004

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

All Speed Options

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

0

t_AVWL

t_ELAX

t_DVEH

t_EHDX

ns

t_AH

40

0

ns

t_DS

ns

t_DH

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

0

ns

CE# Pulse Width

CE# Pulse Width High

40

30

t_CPH

Programming Operation

(Note 2)

t_WHWH1

Word

Typ

7

µs

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Typ

4

µs

Sector Erase Operation (Note 2)

0.4

sec

1. Not 100% tested.

2. See the “Erase and Programming” section for more information.

February 5, 2004

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A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings

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A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

Chip Erase Time

0.4

56

5

Excludes 00h programming

prior to erasure (Note 4)

Byte Program Time

Accelerated Byte/Word Program Time

Word Program Time

Chip Program Time

150

120

210

4

µs

Excludes system level

overhead (Note 5)

7

µs

Word Mode

28

84

sec

(Note 3)

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

11 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

DATA RETENTION

Parameter Description

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

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PSRAM AC CHARACTERISTICS

CE#s Timing

Parameter

Test Setup

AllSpeeds

Unit

JEDEC

Std

Description

—

t_CCR

CE#s Recover Time

—

Min

0

ns

CE#1ps

CE2ps

t_CCR

Figure 26. Timing Diagram for Alternating

Between Pseudo SRAM to Flash

V_CC(Min)

V_CC

Min. 0 ns

CS2s

Min. 200 µs

CS#1s

Normal Operation

Power Up Mode

Note: After V_CCreaches V_CC(MIn), wait 200 µs with CS#1s and CS2s high. The device will enter into normal operation.

Figure 27. Timing Waveform of Power-up

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A D V A N C E I N F O R M A T I O N

PSRAM AC CHARACTERISTICS

Functional Description

Power

Mode

Read (Word)

CE1# CE2 OE# WE# LB# UB# Add I/01 to I/08

I/01 to I/08

D_OUT

L

H

L

H

L

H

L

X

D_OUT

I_DDO

Read (Lower Byte)

Read (Upper Byte)

Write (Word)

High-Z

D_OUT

L

H

L

High-Z

D_IN

X

H

X

L

D_IN

Write (Lower Byte)

Write (Upper Byte)

Outputs Disabled

Standby

L

H

L

D_IN

Invalid

D_IN

L

H

X

Invalid

High-Z

H

X

High-Z

Deep Power-down Standby

X

Note: L = Low-level Input (V_IL), H = High-level Input (V_IH), X = V_IHor V_IL, High-Z = High-impedance.

Absolute Maximum Ratings

Symbol

V_DD

Ratings

Value

-1.0 to 3.6

-25 to 85

-55 to 150

0.6

Unit

V

Power Supply Voltage

Input Voltage

V_IN

V

V_OUT

T_opr.

Output Voltage

V

Operating Temperature

Storage Temperature

Power Dissipation

Short Circuit Output Current

^oC

W

^oC

T_strg.

P_D

I_OUT

50

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

DC Recommended Operating Conditions (Ta = -25^oC to 85^oC)

Symbol

V_DD

Ratings

Power Supply Voltage

Input High Voltage

Input Low Voltage

Min

2.6

Typ

Max

3.3

Unit

2.75

V_IH

2.0

-

V_DD+ 0.3*

0.4

V

I_OUT

-0.3*

Note: All voltages are reference to GND. *: VI_H(Max) V_DD+1.0 V with 10 ns pulse width, V_IL(Min) -1.0 V with 10 ns pulse width.

February 5, 2004

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A D V A N C E I N F O R M A T I O N

DC Characteristics (Ta = -25^oC to 85^oC, VDD = 2.6 to 3.3 V)

Symbol

I_IL

Parameter

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

Test Condition

V_IN= 0 V to V_DD

Min

-1.0

2.4

-

Typ

Max

+1.0

Unit

µA

V

-

I_LO

Output disable, V_OUT= 0 V to V_DD

I_OH= -0.5 mA

V_OH

V_OL

I_OL= -1.0 mA

0.4

50

V

CE1# = V_IL

-

I_DDO1

Operating Current

t

_RC= min

-

mA

CE2 = V_IH,I_{OUT =}0 mA

CE1# = V_IL,CE2 = V_IH,

-

I_DDO2

Page Access Operating Current

Standby Current (MOS)

t_PC= min

25

Page add. cycling_,I_{OUT =}0 mA

I_DDS

CE1# = V_DD- 0.2V CE2 = V_DD- 0.2V

-

100

5

µA

,

I_DDSD

Deep Power-down Standby Current CE2 = 0.2V

Notes:

1. IDDO depends on the cycle time.

2. IDDO depends on output loading. Specified values are defined with

the output open condition.

Capacitance (Ta = -25^oC, f = 1 MHz)

Symbol

C_IN

Parameter

Test Condition

Max

10

Unit

pF

Input Capitance

V_IN= GND

C_OUT

Output Capitance

V_OUT= GND

10

pF

Note:

1. This parameter is sampled periodically and is not 100% tested.

6. During the output state of I/O signals, input signals of reverse

polarity must not be applied.

2. AC measurements are assumed t_R, t_F= 5 ns.

7. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes

LOW, the outputs will remain at high impedance.

3. Parameters t_OD, t_ODO, t_BDand t_ODWdefine the time at which the

output goes the open condition and are not output voltage

reference levels.

8. If CE1 or LB#/UB# goes HIGH coincident with or before WE#

goes HIGH, the outputs will remain at high impedance.

4. Data cannot be retained at deep power-down standby mode.

5. If OE# is high during the write cycle, the outputs will remain at

high impedance.

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AC Characteristics and Operating Conditions

Symbol

t_RC

Parameter

Min

70

-

Max

Unit

ns

Read Cycle Time

1000

t_ACC

t_CO

Address Access Time

70

Chip Enable (CE1#) Access Time

Output Enable Access Time

Data Byte Control Access Time

Chip Enable Low to Output Active

Output Enable Low to Output Active

Data Byte Control Low to Output Active

Chip Enable High to Output High-Z

Output Enable High to Output High-Z

Data Byte Control High to Output High-Z

Output Data Hold Time

-

70

t_OE

-

25

t_BA

-

25

t_COE

t_OEE

t_BE

10

0

-

0

-

t_OD

-

20

t_ODO

t_BD

-

20

-

20

t_OH

10

70

30

-

t_PM

Page Mode Time

10000

t_PC

Page Mode Cycle Time

-

t_AA

Page Mode Address Access Time

Page Mode Output Data Hold Time

Write Cycle Time

30

t_AOH

t_WC

t_WP

10

70

50

70

60

0

-

10000

Write Pulse Width

-

t_CW

t_BW

Chip Enable to End of Write

Data Byte Control to End of Write

Address Valid to End of Write

Address Set-up Time

-

t_AW

-

t_AS

-

t_WR

t_CEH

t_WEH

t_ODW

Write Recovery Time

0

-

Chip Enable High Pulse Width

Write Enable High Pulse Width

WE# Low to Output High-Z

10

6

-

20

t_OEW

t_DS

WE# High to Output Active

Data Set-up Time

0

30

0

-

ns

ms

ns

µs

t_DH

Data Hold Time

t_CS

CE2 Set-up Time

0

t_CH

CE2 Hold Time

300

10

0

t_CPD

t_CHC

t_CHP

CE2 Pulse Width

CE2 Hold from CE1#

CE2 Hold from Power on

30

Notes:

1. Stresses greater than listed under “Absolute Maximum Ratings” may

cause permanent damage to the device.

5. AC measurements are assumed t_R, t_F= 5 ns.

6. Parameters t_OD, t_ODO, t_BDand t_ODWdefine the time at which the

output goes the open condition and are not output voltage

reference levels.

2. All voltages are reference to GND.

3. IDDO depends on the cycle time.

7. Data cannot be retained at deep power-down standby mode.

4. IDDO depends on output loading. Specified values are defined

with the output open condition.

February 5, 2004

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123

A D V A N C E I N F O R M A T I O N

AC Test Conditions

Parameter

Condition

Output Load

30 pF + 1 TTL Gate

Input Pulse Level

Timing Measurements

Reference Level

V

_DD- 0.2 V, 0.2 V

_DDx 0.5

t_R,t_F

5 ns

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A D V A N C E I N F O R M A T I O N

Timing Diagrams

Read Cycle

Page Read Cycle (8 words access)

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A D V A N C E I N F O R M A T I O N

Write Cycle 1

Write Cycle 2

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February 5, 2004

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A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FMB073—73-Ball Fine-Pitch Grid Array 9 x 12 mm

A

D1

D

eD

0.15

(2X)

C

10

9

8

7

6

5

4

3

2

1

SE

7

E

B

E1

eE

L

J

H

G

F

E

D

C

B

A

M

K

INDEX MARK

10

PIN A1

CORNER

PIN A1

CORNER

7

TOP VIEW

SIDE VIEW

0.15

(2X)

C

SD

BOTTOM VIEW

0.20

0.08

C

A2

A

C

A1

6

73X

b

0.15

0.08

M

C

A B

M

NOTES:

PACKAGE

JEDEC

FMB 073

N/A

1. DIMENSIONING AND TOLERANCING METHODS PER

ASME Y14.5M-1994.

13.00 mm X 9.00 mm PACKAGE

NOTE

2. ALL DIMENSIONS ARE IN MILLIMETERS.

SYMBOL

A

MIN.

---

NOM.

---

MAX.

1.40

---

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION.

PROFILE

A1

0.20

1.02

---

BALL HEIGHT

BODY THICKNESS

BODY SIZE

A2

---

1.17

D

13.00 BSC

9.00 BSC

8.80 BSC

7.20 BSC

12

n IS THE NUMBER OF POPULATED SOLDER BALL

POSITIONS FOR MATRIX SIZE MD X ME.

E

BODY SIZE

D1

MATRIX FOOTPRINT

6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

E1

7. SD AND SE ARE MEASURED WITH RESPECT TO

DATUMS A AND B AND DEFINE THE POSITION OF THE

CENTER SOLDER BALL IN THE OUTER ROW.

MD

ME

n

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

10

73

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS

IN THE OUTER ROW SD OR SE = 0.000.

Ob

eE

0.29

---

0.39

BALL DIAMETER

0.80 BSC

0.40 BSC

BALL PITCH

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS

IN THE OUTER ROW, SD OR SE = E/2

eD

BALL PITCH

8. "+" INDICATES THE THEORETICAL CENTER OF

DEPOPULATED BALLS.

SD/SE

SOLDER BALL PLACEMENT

A2,A3,A4,A5,A6,A7,A8,A9

B2,B3,B4,B5,B6,B7,B8,B9

DEPOPULATED SOLDER BALLS

9. NOT USED.

C2,C9,C10,D1,D10,E1,E10

F5,F6,G5,G6,H1,H10,J1,J10

K1,K2,K9,K10,L2,L3,L4,L7,L8,L9

M2,M3,M4,M5,M6,M7,M8,M9

10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER

OR INK MARK, METALLIZED MARK INDENTATION OR

OTHER MEANS.

w053003f-163814c

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A D V A N C E I N F O R M A T I O N

REVISION SUMMARY

Revision A (December 5, 2003)

Initial release.

Revision A+1 (February 5, 2004)

ESD Immunity

Added an ESD Immunity qualification statement re-

garding component devices manufactured by third par-

ties.

February 5, 2004

Am75PDL191CHH/Am75PDL193CHH

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A D V A N C E I N F O R M A T I O N

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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