MB90F352CSPFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13737-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90350 Series

MB90F352/S/C/CS, MB90352/S/C/CS

■ DESCRIPTION

The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive

and industrial applications. Its main feature is the on-board CAN Interface, which conform to V2.0 Part A and Part

B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN

approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory

up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.

An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms

of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free

running timers. 2 channels UART constitute additional functionality for communication purposes.

* : Controller Area Network (CAN) - License of Robert Bosch GmbH

Note : F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■ PACKAGE

64-pin Plastic LQFP

(FPT-64P-M09)

MB90350 Series

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and

multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).

• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without

S-suffix only)

• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-

plied PLL clock).

• 16 Mbyte CPU memory space

• 24-bit internal addressing

• External Bus Interface

• 4 MByte external memory space

• Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

• Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

• Increased processing speed

• 4-byte instruction queue

• Powerful interrupt function

• Powerful 8-level, 34-condition interrupt feature

• Up to 8 channels external interrupts are supported

• Automatic data transfer function independent of CPU

• Extended intelligent I/O service function (EI²OS) : up to 16 channels

• DMA : up to 16 channels

• Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Main timer mode (a timebase timer mode switched from the main clock mode)

• PLL timer mode (a timebase timer mode switched from the PLL clock mode)

• Watch mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

• Process

• CMOS technology

• I/O port

• General-purpose input/output port (CMOS output)

- 49 ports (devices without S-suffix)

- 51 ports (devices with S-suffix)

(Continued)

2

MB90350 Series

(Continued)

• Timer

• Time-base timer, clock timer, watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit × 10 channels, or 16-bit × 6 channels

• 16-bit reload timer : 4 channels

• 16- bit input/output timer

- 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)

- 16- bit input capture: (ICU) : 6 channels

- 16-bit output compare : (OCU) : 4 channels

• Full-CAN interface : 1 channel

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• Flexible message buffering (mailbox and FIFO buffering can be mixed)

• CAN wake-up function

• UART (LIN/SCI) : 2 channels

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available

• I²C interface* : 1 channel (devices with C-suffix only)

• Up to 400 kbit/s transfer rate

• DTP/External interrupt : 8 channels, CAN wakeup : 1 channel

• Module for activation of extended intelligent I/O service (EI²OS), DMA, and generation of external interrupt.

• Delay interrupt generator module

• Generates interrupt request for task switching.

• 8/10-bit A/D converter : 15 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)

• Program patch function

• Address matching detection for 6 address pointers.

• Internal voltage regulator

• Supports 3 V MCU core, offering low EMI and low power consumption figures

• Programmable input levels

• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)

• TTL level (initial level for External bus mode)

• Flash security function

• Protects the content of Flash (Flash device only)

* : I²C license :

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these com-

ponents in an I²C system provided that the system conforms to the I²C Standard Specification as defined by

Philips.

3

MB90350 Series

■ PRODUCT LINEUP

Part Number

MB90F352/S/C/CS, MB90352/S/C/CS*¹

MB90V340/S

Parameter

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)

System clock

Boot-block, Flash memory

128 Kbytes

ROM

RAM

External

30 Kbytes

Yes

4 Kbytes

Emulator-specific

power supply^*2

0.35 µm CMOS with on-chip voltage regulator for internal

power supply + Flash memory with

On-chip charge pump for programming voltage

0.35 µm CMOS with

on-chip voltage regulator

for internal power supply

Technology

3.5 V - 5.5 V : at normal operating (not using A/D converter)

4.0 V - 5.5 V : at using A/D converter/Flash programming

4.5 V - 5.5 V : at using external bus

Operating

voltage range

5 V ± 10%

Temperature range

Package

−40 °C to +105 °C (125 °C up to 16 MHz machine clock)

LQFP-64

2 channels

PGA-299

3 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

UART

devices with ‘C’-suffix

devices without ‘C’-suffix :

: 1 channel

I²C (400 kbit/s)

1 channel

15 channels

A/D

Converter

10-bit or 8-bit resolution

Conversion time : Min 3 µs include sample time (per one channel)

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

(4 channels)

Supports External Event Count function

Signals an interrupt when overflowing

Supports Timer Clear when a match with Output Compare (Channel 0, 4)

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1

I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7

16-bit

I/O Timer

(2 channels)

16-bit Output

Compare

(4 channels)

Signals an interrupt when 16-bit I/O Timer match output compare registers.

A pair of compare registers can be used to generate an output signal.

16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive

(6 channels) Signals an interrupt upon external event

(Continued)

4

MB90350 Series

Part Number

Parameter

MB90F352/S/C/CS, MB90352/S/C/CS*¹

Supports 8-bit and 16-bit operation modes

MB90V340/S

8-bit reload counters × 12

8-bit reload registers for L pulse width × 12

8-bit reload registers for H pulse width × 12

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 128 µs@fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

8/16-bit

ProgrammablePulse

Generator

6 channels (16-bit) /

10 channels (8-bit)

1 channel

2 channels

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

CAN Interface

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps

External Interrupt

(8 channels)

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,

extended intelligent I/O services (EI²OS) and DMA

D/A converter

1 channel

Subclock

devices with ‘S’-suffix

: without subclock

(up to100 kHz)

devices without ‘S’-suffix : with subclock

Virtually all external pins can be used as general purpose I/O port

All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral signal

Settable as CMOS schmitt trigger/ automotive inputs (default)

TTL input level settable for external bus (30 terminals only for external bus)

Supports automatic programming, Embedded Algorithm^TM*3

Write/Erase/Erase-Suspend/Resume commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 10 years

Boot block configuration

Flash

Memory

Erase can be performed on each block

Block protection with external programming voltage

Flash Security Feature for protecting the content of the Flash

*1 : The devices are under development.

*2 : It is setting of Jumper switch (TOOL V^CC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

5

MB90350 Series

■ PIN ASSIGNMENTS

• MB90F352/S, MB90352/S

(TOP VIEW)

(LQFP-64P)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P10/AD08/TIN1

P07/AD07/INT15

Vcc

C

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

P25/A21/IN1/ADTG

P44/FRCK0

P06/AD06/INT14

P05/AD05/INT13

P04/AD04/INT12

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

MD0

P45//FRCK1

P30/ALE/IN4

P31/RD/IN5

P32/WRL/WR/INT10R

P33/WRH

P34/HRQ/OUT4

P35/HAK/OUT5

P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0

MD1

MD2

P41/X1A*

P40/X0A*

P61/AN1

Vss

AVcc

P43/IN7/TX1

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FPT-64P-M09)

* : MB90F352/352

: X0A, X1A

MB90F352S/352S : P40, P41

6

MB90350 Series

• MB90F352C/CS, MB90352C/CS

(TOP VIEW)

(LQFP-64P)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

P10/AD08/TIN1

P07/AD07/INT15

Vcc

C

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

P25/A21/IN1/ADTG

P44/SDA0/FRCK0

P45/SCL0/FRCK1

P30/ALE/IN4

P31/RD/IN5

P06/AD06/INT14

P05/AD05/INT13

P04/AD04/INT12

P03/AD03/INT11

P02/AD02/INT10

P01/AD01/INT9

P00/AD00/INT8

MD0

P32/WRL/WR/INT10R

P33/WRH

P34/HRQ/OUT4

P35/HAK/OUT5

P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0

MD1

MD2

P41/X1A*

P40/X0A*

P61/AN1

Vss

AVcc

P43/IN7/TX1

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(FPT-64P-M09)

* : MB90F352C/352C

: X0A, X1A

MB90F352CS/352CS : P40, P41

7

MB90350 Series

■ PIN DESCRIPTION

Pin No.

Circuit

Pin name

Function

type

LQFP64*

46

47

45

X1

X0

Oscillation output pin.

Oscillation input pin.

Reset input pin.

A

E

RST

P62 to P67

AN2 to AN7

General purpose I/O ports.

Analog input pins for A/D converter.

3 to 8

I

PPG4, 6, 8,

A, C, E

Output pins for PPGs.

P50

AN8

General purpose I/O port.

9

O

I

Analog input pin for A/D converter.

Serial data input pin for UART2.

General purpose I/O port.

SIN2

P51

10

11

12

AN9

Analog input pin for A/D converter.

Serial data output pin for UART2.

General purpose I/O port.

SOT2

P52

AN10

SCK2

P53

I

Analog input pin for A/D converter.

Serial data output pin for UART2.

General purpose I/O port.

AN11

TIN3

I

Analog input pin for A/D converter.

Event input pin for reload timer3.

General purpose I/O port.

P54

13

AN12

TOT3

P55, P56

AN13, AN14

P42

I

Analog input pin for A/D converter.

Output pin for reload timer3.

General purpose I/O ports.

14, 15

Analog input pins for A/D converter.

General purpose I/O port.

IN6

Data sample input pin for input capture ICU6.

RX input pin for CAN1.

16

F

RX1

INT9R

P43

External interrupt request input pin for INT9.

General purpose I/O port.

17

IN7

F

Data sample input pin for input capture ICU7.

TX output pin for CAN1.

TX1

P40, P41

X0A, X1A

F

B

General purpose I/O ports (devices with S-suffix) .

Oscillation input pins for sub clock (devices without S-suffix) .

19, 20

(Continued)

8

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O ports.The register can be set to select whether to use

a pull-up resistor.This function is enabled in single-chip mode.

P00 to P07

24 to 31

G

Input/output pins of external address data bus lower 8 bit. This function is

enabled when the external bus is enabled.

AD00 to AD07

INT8 to INT15

P10

External interrupt request input pins for INT8 to INT15.

General purpose I/O port.The register can be set to select whether to use

a pull-up resistor.This function is enabled in single-chip mode.

32

Input/output pin for external bus address data bus bit 8.

This function is enabled when external bus is enabled.

AD08

TIN1

P11

Event input pin for reload timer1.

General purpose I/O.The register can be set to select whether to use a

pull-up resistor.This function is enabled in single-chip mode.

33

Input/output pin for external bus address data bus bit 9. This function is en-

abled when external bus is enabled.

AD09

TOT1

P12

Output pin for reload timer1.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 10. This function is

enabled when external bus is enabled.

AD10

34

N

SIN3

Serial data input pin for UART3.

INT11R

External interrupt request input pin for INT11

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P13

35

36

G

Input/output pin for external bus address data bus bit 11.

This function is enabled when external bus is enabled.

AD11

SOT3

P14

Serial data output pin for UART3.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 12.

This function is enabled when external bus is enabled.

AD12

SCK3

P15

Clock input/output pin for UART3.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

37

38

N

G

Input/output pin for external bus address data bus bit 13.

This function is enabled when external bus is enabled.

AD13

P16

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 14.

This function is enabled when external bus is enabled.

AD14

(Continued)

9

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P17

39

G

Input/output pin for external bus address data bus bit 15.

This function is enabled when external bus is enabled.

AD15

General purpose I/O ports. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P20 to P23

40 to 43

Output pins for A16 to A19 of the external address bus.

A16 to A19

When the corresponding bit in the external address output control register

(HACR) is 0, the pins are enabled as high address output pins A16 to A19.

PPG9, PPGB,

PPGD, PPGF

Output pins for PPGs.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P24

44

G

Output pins for A20 of the external address bus. When the corresponding

bit in the external address output control register (HACR) is 0, the pin is

enabled as high address output pins A20.

A20

IN0

Data sample input pin for input capture ICU0.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general-

purpose I/O port when the corresponding bit in the external address output

control register (HACR) is 1.

P25

Output pin for A21 of the external address bus. When the corresponding bit

in the external address output control register (HACR) is 0, the pin is en-

abled as high address output pin A21.

51

G

A21

IN1

ADTG

P44

Data sample input pin for input capture ICU1.

Trigger input pin for A/D converter.

General purpose I/O port

52

53

SDA0

FRCK0

P45

H

Serial data I/O pin for I²C 0 (devices with C-suffix)

Input pin for the 16-bit I/O Timer 0

General purpose I/O port.

SCL0

FRCK1

Serial clock I/O pin for I²C 0 (devices with C-suffix)

Input for the 16-bit I/O Timer 1

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P30

54

G

Address latch enable output pin. This function is enabled when external bus

is enabled.

ALE

IN4

Data sample input pin for input capture ICU4.

(Continued)

10

MB90350 Series

Pin No.

Circuit

type

Pin name

Function

LQFP64*

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled in single-chip mode.

P31

55

56

G

Read strobe output pin for data bus. This function is enabled when external

bus is enabled.

RD

IN5

Data sample input pin for input capture ICU5.

General purpose I/O port. The register can be set to select whether to use

pull-up resistor. This function is enabled either in single-chip mode or with

the WR/WRL pin output disabled.

P32

Write strobe output pin for the data bus. This function is enabled when both

the external bus and the WR/WRL pin output are enabled. WRL is used to

write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to

write-strobe 8 bits of the data bus in 8-bit access.

G

WR/WRL

INT10R

P33

External interrupt request input pin for INT10.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the WRH pin output disabled.

57

58

G

Write strobe output pin for the 8 higher bits of the data bus. This function is

enabled when the external bus is enabled, when the external bus 16-bit

mode is selected, and when the WRH output pin is enabled.

WRH

P34

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the hold function disabled.

Hold request input pin. This function is enabled when both the external bus

and the hold function are enabled.

HRQ

OUT4

Waveform output pin for output compare OCU4.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the hold function disabled.

P35

59

60

61

G

Hold acknowledge output pin. This function is enabled when both the

external bus and the hold function are enabled.

HAK

OUT5

Waveform output pin for output compare OCU5.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the external ready function disabled.

P36

Ready input pin. This function is enabled when both the external bus and

the external ready function are enabled.

RDY

OUT6

Waveform output pin for output compare OCU6.

General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. This function is enabled either in single-chip mode or with

the CLK output disabled.

P37

CLK output pin. This function is enabled when both the external bus and

CLK output are enabled.

CLK

OUT7

Waveform output pin for output compare OCU7.

(Continued)

11

MB90350 Series

(Continued)

Pin No.

Circuit

type

Pin name

Function

LQFP64*

P60, P61

AN0, AN1

AV^CC

General purpose I/O ports.

62, 63

64

I

Analog input pins for A/D converter.

VCC power input pin for analog circuits.

K

Reference voltage input for the A/D converter. This power supply must be

turned on or off while a voltage higher than or equal to AVRH is applied to

AVCC.

2

AVRH

L

1

AV^SS

K

C

VSS power input pin for analog circuits.

Input pins for specifying the operating mode. The pins must be directly

connected to VCC or VSS.

22, 23

MD1, MD0

Input pins for specifying the operating mode. The pins must be directly

connected to VCC or VSS.

21

MD2

D

49

V^CC

Power (3.5 V to 5.5 V) input pin.

Power (0 V) input pins.

18, 48

VSS

This is the power supply stabilization capacitor pin. It should be connected

to a higher than or equal to 0.1 µF ceramic capacitor.

50

C

K

* : FPT-64P-M09

12

MB90350 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Oscillation circuit

• High-speed oscillation feedback

resistor = approx. 1 MΩ

X1

Xout

A

X0

Standby control signal

Oscillation circuit

X1A

Xout

• Low-speed oscillation feedback

resistor = approx. 10 MΩ

B

X0A

Standby control signal

Mask ROM device:

• CMOS Hysteresis input pin

R

C

D

Hysteresis

Flash device:

inputs

• CMOS input pin

Mask ROM device:

• CMOS Hysteresis input pin

• Pull-down resistor valule: approx. 50 kΩ

Hysteresis

inputs

Pull-down

Resistor

Flash device:

• CMOS input pin

• No Pull-down

CMOS Hysteresis input pin

• Pull-up resistor valule: approx. 50 kΩ

Pull-up

E

Resistor

R

Hysteresis

inputs

(Continued)

13

MB90350 Series

Type

Circuit

Remarks

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

Pout

Nout

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

R

F

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

pull-up control

Pout

pull-up

resistor

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

• TTL input (With the standby-time input

shutdown function)

Nout

R

G

• Programmalble pullup resistor: 50 kΩ

approx.

Hysteresis inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output

(I^OL= 3 mA, IOH = −3 mA)

Pout

Nout

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

R

H

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

(Continued)

14

MB90350 Series

Type

Circuit

Remarks

• CMOS level output(I^OL= 4 mA)

• CMOS hysteresis inputs (With the stand-

by-time input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

• A/D analog input

R

I

Hysteresis inputs

Automotive inputs

Standby control for

input shutdown

Analog input

• Power supply input protection circuit

K

• A/D converter reference voltage power

supply input pin, with the protection cir-

cuit

• Flash devices do not have a protection

circuit against V^CCfor pin AVRH

ANE

AVR

L

ANE

(Continued)

15

MB90350 Series

(Continued)

Type

Circuit

Remarks

• CMOS level output

pull-up control

(I^OL= 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

pull-up

registor

Pout

• Automotive input (With the standby-time

input shutdown function)

• TTL input (With the standby-time input

shutdown function)

Nout

R

N

• Programmable pull-up registor:50 kΩ

approx

CMOS inputs

Automotive inputs

TTL input

Standby control for

input shutdown

• CMOS level output

(I^OL= 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time

input shutdown function)

• Automotive input (With the standby-time

input shutdown function)

Pout

Nout

R

• A/D analog input

O

CMOS inputs

Automotive inputs

Standby control for

input shutdown

Analog input

16

MB90350 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Precautions for when not using a sub clock signal

• Notes on during operation of PLL clock mode

• Power supply pins (V^CC/VSS)

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter

• Notes on Energization

• Stabilization of power supply voltage

• Initialization

• Port0 to port3 output during Power-on (External-bus mode)

• Notes on using CAN Function

• Flash security Function

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than V^CCor lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

• The AV^CCpower supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

2. Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90350 Series

X0

Open

X1

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the

X1A pin open.

17

MB90350 Series

5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

6. Power supply pins (V^CC/V^SS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard for total output current, be sure to connect the V^CCand VSS pins to the power supply

and ground externally.

• Connect V^CCand VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

VCC and VSS in the vicinity of VCC and VSS pins of the device

Vcc

Vss

Vcc

Vss

Vcc

MB90350

Series

Vcc

Vss

Vcc

Vss

7. Pull-up/down resistors

The MB90350 Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).

Use external components where needed.

8. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after

turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

10. Connection of Unused Pins of A/D Converter if A/D Converter is used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.

18

MB90350 Series

11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

or more µs (0.2 V to 2.7 V)

12. Stabilization of power supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply

voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at

commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,

turn on the power again.

14. Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of

Port 0 to Port 3 might be unstable.

1/2 VCC

VCC

Port0 to Port3

Port0 to Port3 outputs Port0 to Port3 outputs = Hi-Z

might be unstable

15. Notes on using CAN Function

To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).

If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.

Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.

16. Flash security Function

The security byte is located in the area of the flash memory.

If protection code 01H is written in the security bit, the flash memory is in the protected state by security.

Therefore please do not write 01H in this address if you do not use the security function.

Please refer to following table for the address of the security bit.

Flash memory size

Address for security bit

MB90F352

Embedded 1 Mbit Flash Memory

FE0001^H

19

MB90350 Series

■ BLOCK DIAGRAMS

• MB90V340/S

X0,X1

X0A,X1A ^*

Clock

16LX

CPU

RST

Controller

FRCK0

IO Timer 0

RAM 30 K

Input

Capture

6 ch

IN7 to IN4,

IN1 to IN0

Output

Compare

4 ch

OUT7 to OUT4

FRCK1

Prescaler

3 ch

IO Timer 1

SOT4 to SOT2

SCK4 to SCK2

SIN4 to SIN2

CAN

Controller

2 ch

UART

3 ch

RX2 to RX1

TX2 to TX1

AVCC

16-bit Reload

Timer 4 ch

TIN3, TIN1

AVSS

TOT3, TOT1

10-bit ADC

15 ch

AN14 to AN0

AVRH

AD15 to AD00

A21 to A16

ALE

ADTG

DA00

RD

10-bit

DAC

1 ch

External

Bus

Interface

WRL

WRH

HRQ

HAK

8/16-bit

PPG

12/8 ch

PPGF to PPG8,

PPG6, PPG4,

PPG2, PPG0

RDY

CLK

I²C

Interface

1 ch

SDA0

SCL0

External

Interrupt

INT15 to INT8

(INT11R to INT9R)

DMAC

* : Only for MB90V340 ( without ‘S’ Suffix )

20

MB90350 Series

• MB90F352/S/C/CS, MB90352/S/C/CS

X0,X1

X0A,X1A ^*1

Clock

16LX

CPU

RST

Controller

FRCK0

IO Timer 0

RAM

4 K

Input

Capture

6 ch

IN7 to IN4,

IN1, IN0

ROM/Flash

128 K

Output

Compare

4 ch

OUT7 to OUT4

FRCK1

Prescaler

2 ch

IO Timer 1

SOT3, SOT2

SCK3, SCK2

SIN3, SIN2

CAN

Controller

1 ch

UART

2 ch

RX1

TX1

AVCC

16-bit Reload

Timer 4 ch

TIN3, TIN1

AVSS

TOT3, TOT1

10-bit ADC

15 ch

AN14 to AN0

AD15 to AD00

A21 to A16

ALE

AVRH

ADTG

RD

External

Bus

Interface

WRL

WRH

8/16-bit

PPG

10/6 ch

HRQ

PPGF to PPG8

PPG6, PPG4

HAK

RDY

CLK

I²C

Interface

1 ch

SDA0^*2

SCL0^*2

INT15 to INT8

External

Interrupt

(INT11R to INT9R)

DMAC

*1 : Only for devices without ‘S’ Suffix

*2 : Only for devices with ‘C’ Suffix

21

MB90350 Series

■ MEMORY MAP

MB90V340

MB90F352/S/C/CS

MB90352/S/C/CS

FFFFFF

H

FFFFFF

H

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

FF0000

FEFFFF

H

FF0000

FEFFFF

H

FE0000

FDFFFF

H

FE0000

FDFFFF

H

External access

area

C00100

C000FF

H

00FFFF

H

00FFFF

H

ROM

(image of FF bank)

008000

007FFF

H

008000

007FFF

H

Peripheral

007900

0078FF

H

007900

H

RAM 30 K

001100

0010FF

H

RAM 4 K

000100

H

000100

H

External access area

0000EF

000000

H

0000EF

000000

H

Peripheral

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFFH is visible only in bank FF.

22

MB90350 Series

■ I/O MAP

Abbrevia-

tion

Address

Register

Port 0 Data Register

Access

Resource name

Initial value

00^H

01H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

XXXXXXXX

Port 1 Data Register

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

02^H

03^H

04H

05^H

06^H

07H to 0AH

0B^H

Reserved

Analog Input Enable Register 5

Analog Input Enable Register 6

ADER5

ADER6

R/W

Port 5, A/D

Port 6, A/D

11111111

0CH

0D^H

Reserved

0EH

Input Level Select Register 0

Input Level Select Register 1

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

ILSR0

ILSR1

R/W

Ports

00000000

XX000000

00000000

XX000000

00000000

0FH

10^H

DDR0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

11H

DDR1

12H

DDR2

13^H

DDR3

14H

DDR4

15^H

DDR5

16H

DDR6

17H to 19H

1A^H

Reserved

DDRA

SIN input Level Setting Register

W

UART2, UART3

X00XXXXX

1BH

Reserved

PUCR0

PUCR1

PUCR2

PUCR3

Reserved

1CH

Port 0 Pull-up Control Register

Port 1 Pull-up Control Register

Port 2 Pull-up Control Register

Port 3 Pull-up Control Register

R/W

Port 0

Port 1

Port 2

Port 3

00000000

1DH

1E^H

1FH

20H to 37H

38^H

PPG 4 Operation Mode Control Register PPGC4

PPG 5 Operation Mode Control Register PPGC5

W, R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator 4/5

39H

3AH

PPG 45 Clock Select Register

PPG45

Program Address Detection Control

Status Register 1

Address Match

Detection 1

3B^H

PACSR1

R/W

00000000

(Continued)

23

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3C^H

3DH

3EH

3F^H

40^H

41^H

42^H

43^H

44H

45H

46H

47^H

48H

49H

4A^H

4BH

4C^H

4DH

4EH

4F^H

PPG 6 Operation Mode Control Register PPGC6

PPG 7 Operation Mode Control Register PPGC7

W, R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator 6/7

PPG 67 Clock Select Register

PPG67

Reserved

PPG 8 Operation Mode Control Register PPGC8

PPG 9 Operation Mode Control Register PPGC9

W, R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator 8/9

PPG 89 Clock Select Register

PPG89

Reserved

PPGCA

PPGCB

PPGAB

Reserved

PPG A operation mode control register

PPG B operation mode control register

PPG AB clock select register

W, R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator A/B

PPG C Operation Mode Control Register PPGCC

PPG D Operation Mode Control Register PPGCD

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator C/D

PPG CD Clock Select Register

PPGCD

Reserved

PPG E Operation Mode Control Register PPGCE

PPG F Operation Mode Control Register PPGCF

W,R/W

R/W

0X000XX1

0X000001

000000X0

16-bit Programable

Pulse Generator E/F

PPG EF Clock Select Register

PPGEF

Reserved

Input Capture Control Status

Register 0/1

50^H

ICS01

R/W

00000000

Input Capture 0/1

51H

Input Capture Edge Register 0/1

ICE01

R/W, R

XXX0X0XX

52^H, 53H

Reserved

Input Capture Control Status

Register 4/5

54H

55^H

56^H

ICS45

ICE45

ICS67

R/W

R

00000000

XXXXXXXX

00000000

Input Capture 4/5

Input Capture 6/7

Input Capture Edge Register 4/5

Input Capture Control Status

Register 6/7

R/W

R/W, R

57H

Input Capture Edge Register 6/7

ICE67

XXX000XX

58H to 5BH

Reserved

Output Compare Control Status

Register 4

5C^H

5D^H

OCS4

OCS5

R/W

0000XX00

Output Compare 4/5

Output Compare Control Status

Register 5

0XX00000

(Continued)

24

MB90350 Series

Abbrevia-

tion

Address

5E^H

Register

Access

R/W

Resource name

Initial value

0000XX00

0XX00000

Output Compare Control Status

Register 6

OCS6

OCS7

Output Compare 6/7

Output Compare Control Status

Register 7

5F^H

R/W

60H

61^H

Timer Control Status Register 0

Timer Control Status Register 1

Timer Control Status Register 2

Timer Control Status Register 3

A/D Control Status Register 0

A/D Control Status Register 1

Data Register 0

TMCSR0

TMCSR1

TMCSR2

TMCSR3

ADCS0

R/W

R

00000000

XXXX0000

00000000

XXXX0000

00000000

XXXX0000

00000000

XXXX0000

000XXXX0

0000000X

00000000

XXXXXX00

00000000

16-bit Reload Timer

0

62^H

16-bit Reload Timer

1

63H

64^H

16-bit Reload Timer

2

65H

66^H

16-bit Reload Timer

3

67H

68H

69^H

ADCS1

6AH

ADCR0

A/D Converter

ROM Mirror

6BH

Data Register 1

ADCR1

R

6C^H

6DH

6E^H

A/D Setting Register 0

ADSR0

R/W

A/D Setting Register 1

ADSR1

Reserved

ROMM

Reserved

6FH

ROM Mirroring Register

W

XXXXXXX1

70H to 7FH

80^Hto 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

90H to 9AH

Reserved

DMA Descriptor Channel Specification

Register

9BH

DCSR

R/W

00000000

DMA

9C^H

9D^H

DMA Status Register L

DMA Status Register H

DSRL

DSRH

R/W

00000000

Program Address Detection Control

Status Register 0

Address Match

Detection 0

9E^H

9F^H

A0H

PACSR0

DIRR

R/W

00000000

00011000

Delayed Interrupt/Release

Delayed Interrupt

Low Power Control

Circuit

Low-power Mode Control Register

LPMCR

W,R/W

Low Power Control

Circuit

A1^H

Clock Selection Register

DMA Stop Status Register

CKSCR

R,R/W

R/W

11111100

A2^H, A3H

A4^H

Reserved

DSSR

DMA

00000000

(Continued)

25

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name Initial value

Automatic Ready Function Selection

Register

A5^H

ARSR

W

0011XX00

External Memory

A6H

A7H

A8^H

A9^H

AAH

AB^H

AC^H

ADH

External Address Output Control Register

Bus Control Signal Selection Register

Watchdog Timer Control Register

Timebase Timer Control Register

Watch Timer Control Register

HACR

ECSR

WDTC

TBTC

W

Access

00000000

0000000X

XXXXX111

1XX00100

1X001000

R,W

Watchdog Timer

Time base timer

Watch timer

W,R/W

R,R/W

WTC

Reserved

DERL

DERH

DMA Enable Register L

DMA Enable Register H

R/W

00000000

DMA

Flash Control Status Register

(Flash Devices only. Otherwise

reserved)

AE^H

FMCS

R,R/W

Flash Memory

000X0000

AF^H

B0^H

Reserved

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Reserved

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

W,R/W

00000111

B1H

B2H

B3^H

B4H

B5^H

B6H

B7H

Interrupt Control

B8^H

B9H

BAH

BBH

BC^H

BDH

BEH

BF^H

C0H to C9H

(Continued)

26

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

External Interrupt Request Enable

Register 1

CA^H

ENIR1

R/W

00000000

CB^H

CCH

CD^H

External Interrupt Request Register 1

External Interrupt Level Register 1

EIRR1

ELVR1

R/W

XXXXXXXX

00000000

External Interrupt 1

External Interrupt Source Select

Register

CE^H

EISSR

R/W

00000000

CFH

D0^H

D1H

D2^H

D3H

D4H

D5^H

D6H

D7H

D8^H

D9H

PLL/Subclock Control register

DMA Buffer Address Pointer L

DMA Buffer Address Pointer M

DMA Buffer Address Pointer H

DMA Control Register

PSCCR

BAPL

BAPM

BAPH

DMACS

IOAL

W

R/W

PLL

XXXX0000

XXXXXXXX

00000000

R/W

DMA

I/O Register Address Pointer L

I/O Register Address Pointer H

Data Counter L

R/W

IOAH

R/W

DCTL

DCTH

SMR2

SCR2

R/W

Data Counter H

R/W

Serial Mode Register 2

W,R/W

Serial Control Register 2

00000000

Reception/Transmission Data Register

2

RDR2/

TDR2

DA^H

DB^H

DCH

R/W

00000000

00001000

000000XX

Serial Status Register 2

SSR2

R,R/W

UART2

Extended Communication Control

Register 2

R,W,

R/W

ECCR2

DD^H

DEH

Extended Status/Control Register 2

Baud Rate Reload Register 20

Baud Rate Reload Register 21

ESCR2

BGR20

BGR21

R/W

00000100

00000000

DFH

E0H to EFH

F0^Hto FFH

Reserved

External

7900H to

7907H

Reserved

(Continued)

27

MB90350 Series

Abbrevia-

tion

Address

Register

Reload Register L4

Access

Resource name

Initial value

7908^H

7909^H

790AH

790B^H

790C^H

790DH

790E^H

790F^H

7910H

7911^H

7912H

7913^H

7914H

7915^H

7916^H

7917H

7918^H

7919^H

791AH

791B^H

791CH

791D^H

791E^H

791F^H

7920H

7921H

7922^H

7923H

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

R/W

R

XXXXXXXX

16-bit Programable

Pulse

Reload Register H4

Reload Register L5

Reload Register H5

Reload Register L6

Reload Register H6

Reload Register L7

Reload Register H7

Reload Register L8

Reload Register H8

Reload Register L9

Reload Register H9

Reload Register LA

Reload Register HA

Reload Register LB

Reload Register HB

Reload Register LC

Reload Register HC

Reload Register LD

Reload Register HD

Reload Register LE

Reload Register HE

Reload Register LF

Reload Register HF

Input Capture Data Register 0

Input Capture Data Register 1

Generator 4/5

16-bit Programable

Pulse

Generator 6/7

16-bit Programable

Pulse

Generator 8/9

16-bit Programable

Pulse

Generator A/B

16-bit Programable

Pulse

Generator C/D

16-bit Programable

Pulse

Generator E/F

R

Input Capture 0/1

R

7924H to

7927H

Reserved

7928H

7929H

792AH

792B^H

Input Capture Data Register 4

Input Capture Data Register 5

IPCP4

IPCP5

R

XXXXXXXX

Input Capture 4/5

XXXXXXXX

(Continued)

28

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

792C^H

792D^H

792E^H

792F^H

Input Capture Data Register 6

Input Capture Data Register 7

IPCP6

IPCP7

R

XXXXXXXX

Input Capture 6/7

7930^Hto

7937H

Reserved

7938^H

7939^H

793A^H

793B^H

793C^H

793D^H

793E^H

793F^H

7940^H

7941^H

7942^H

7943^H

7944^H

7945^H

7946^H

7947^H

7948^H

7949^H

794A^H

794B^H

794C^H

794D^H

794E^H

794F^H

Output Compare Register 4

Output Compare Register 5

Output Compare Register 6

Output Compare Register 7

Data Register 0

OCCP4

OCCP5

OCCP6

OCCP7

TCDT0

TCCSL0

TCCSH0

TCDT1

TCCSL1

TCCSH1

R/W

XXXXXXXX

00000000

Output Compare 4/5

Output Compare 6/7

I/O Timer 0

Data Register 0

00000000

Control status Register 0

Data Register 1

00000000

0XXXXXXX

00000000

Data Register 1

00000000

I/O Timer 1

Control status Register 1

00000000

0XXXXXXX

XXXXXXXX

(Continued)

TMR0/

TMRLR0

16-bit Reload

Timer 0

Timer Register 0/Reload Register 0

Timer Register 1/Reload Register 1

Timer Register 2/Reload Register 2

Timer Register 3/Reload Register 3

TMR1/

TMRLR1

16-bit Reload

Timer 1

TMR2/

TMRLR2

16-bit Reload

Timer 2

TMR3/

TMRLR3

16-bit Reload

Timer 3

29

MB90350 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

7950^H

7951^H

Serial Mode Register 3

Serial Control Register 3

SMR3

SCR3

W, R/W

00000000

Reception/Transmission Data Register

3

RDR3/

TDR3

7952^H

7953^H

7954^H

R/W

00000000

00001000

000000XX

Serial Status Register 3

SSR3

R,R/W

UART3

Extended Communication Control Reg-

ister 3

R,W,

R/W

ECCR3

7955^H

7956^H

7957^H

Extended Status/Control Register 3

Baud Rate Reload Register 30

Baud Rate Reload Register 31

ESCR3

BGR30

BGR31

R/W

00000100

00000000

7958^Hto

796DH

Reserved

796E^H

796F^H

7970^H

7971^H

7972^H

7973^H

7974^H

7975^H

7976^H

7977^H

7978^H

CAN Direct Mode Register

CDMR

R/W

CAN clock sync

XXXXXXX0

Reserved

I²C Bus Status Register 0

I²C Bus Control Register 0

IBSR0

IBCR0

ITBAL0

ITBAH0

ITMKL0

ITMKH0

ISBA0

R

W,R/W

R/W

00000000

11111111

00111111

00000000

01111111

00000000

I²C 10 bit Slave Address Register 0

I²C Interface 0

I²C 10 bit Slave Address Mask Register

0

I²C 7 bit Slave Address Register 0

I²C 7 bit Slave Address Mask Register 0

I²C data register 0

ISMK0

IDAR0

7979^H,

797AH

Reserved

ICCR0

Reserved

CMCR

Reserved

797B^H

I²C Clock Control Register 0

R/W

I²C Interface 0

Clock Modulator

00011111

0001X000

(Continued)

797C^Hto

79C1H

79C2^H

Clock Modulator Control Register

R,R/W

79C3^Hto

79DFH

30

MB90350 Series

(Continued)

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

79E0H

79E1^H

79E2^H

79E3^H

79E4^H

79E5^H

79E6^H

79E7^H

79E8^H

Program Address Detection Register 0 PADR0

Program Address Detection Register 1 PADR1

Program Address Detection Register 2 PADR2

R/W

XXXXXXXX

Address Match

Detection 0

79E9^Hto

79EFH

Reserved

79F0^H

79F1^H

79F2^H

79F3^H

79F4^H

79F5^H

79F6^H

79F7^H

79F8^H

Program Address Detection Register 3 PADR3

Program Address Detection Register 4 PADR4

Program Address Detection Register 5 PADR5

R/W

XXXXXXXX

Address Match

Detection 1

79F9^Hto

7BFFH

Reserved

7C00^Hto

7CFFH

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Reserved

7D00^Hto

7DFFH

7E00^Hto

7FFFH

Notes : • Initial value of “X” represents unknown value.

• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary

functions of the MCU. A read access to these reserved addresses results reading “X” and any write

access should not be performed.

31

MB90350 Series

■ CAN CONTROLLERS

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

• Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

• 29-bit ID and 8-byte data

• Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

• Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)

List of Control Registers (1)

Address

Register

Abbreviation

BVALR

TREQR

TCANR

TCR

Access

R/W

W

Initial Value

CAN1

000080^H

000081^H

000082H

000083^H

000084H

000085^H

000086H

000087^H

000088H

000089^H

00008AH

00008B^H

00008CH

00008D^H

00008EH

00008F^H

00000000

Message buffer enable register

Transmit request register

Transmit cancel register

00000000

Transmission complete register

Receive complete register

Remote request receiving register

Receive overrun register

R/W

00000000

RCR

00000000

RRTRR

ROVRR

RIER

00000000

Reception interrupt

enable register

00000000

32

MB90350 Series

List of Control Registers (2)

Abbreviation

Address

CAN1

Register

Access

Initial Value

007D00^H

007D01^H

007D02H

007D03^H

007D04H

007D05^H

007D06H

007D07^H

007D08H

007D09^H

007D0AH

007D0B^H

007D0CH

007D0D^H

007D0EH

007D0F^H

007D10H

007D11^H

007D12H

007D13^H

007D14H

007D15^H

007D16H

007D17^H

007D18H

007D19^H

007D1AH

007D1B^H

R/W, W

R/W, R

0XXXX0X1

00XXX000

Control status register

Last event indicator register

Receive/transmit error counter

Bit timing register

CSR

LEIR

000X0000

XXXXXXXX

R/W

R

00000000

RTEC

BTR

11111111

X1111111

R/W

XXXXXXXX

IDE register

IDER

00000000

Transmit RTR register

TRTRR

RFWTR

TIER

Remote frame receive waiting

register

XXXXXXXX

Transmit interrupt

enable register

00000000

XXXXXXXX

Acceptance mask

select register

AMSR

AMR0

AMR1

R/W

XXXXXXXX

Acceptance mask register 0

Acceptance mask register 1

XXXXXXXX

33

MB90350 Series

List of Message Buffers (ID Registers) (1)

Address

Register

Abbreviation

Access

Initial Value

CAN1

007C00^H

to

XXXXXXXX

to

General-purpose RAM

R/W

007C1FH

XXXXXXXX

007C20^H

007C21^H

007C22H

007C23^H

007C24H

007C25^H

007C26H

007C27^H

007C28H

007C29^H

007C2AH

007C2B^H

007C2CH

007C2D^H

007C2EH

007C2F^H

007C30H

007C31^H

007C32H

007C33^H

007C34H

007C35^H

007C36H

007C37^H

007C38H

007C39^H

007C3AH

007C3B^H

007C3CH

007C3D^H

007C3EH

007C3F^H

XXXXXXXX

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

R/W

XXXXXXXX

34

MB90350 Series

List of Message Buffers (ID Registers) (2)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C40^H

007C41^H

007C42H

007C43^H

007C44H

007C45^H

007C46H

007C47^H

007C48H

007C49^H

007C4AH

007C4B^H

007C4CH

007C4D^H

007C4EH

007C4F^H

007C50H

007C51^H

007C52H

007C53^H

007C54H

007C55^H

007C56H

007C57^H

007C58H

007C59^H

007C5AH

007C5B^H

007C5CH

007C5D^H

007C5EH

007C5F^H

XXXXXXXX

ID register 8

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

IDR8

R/W

XXXXXXXX

IDR9

IDR10

IDR11

IDR12

IDR13

IDR14

IDR15

XXXXXXXX

35

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (1)

Address

CAN1

Register

Abbreviation

DLCR0

Access

R/W

Initial Value

XXXXXXXX

007C60^H

007C61^H

007C62H

007C63^H

007C64H

007C65^H

007C66H

007C67^H

007C68H

007C69^H

007C6AH

007C6B^H

007C6CH

007C6D^H

007C6EH

007C6F^H

007C70H

007C71^H

007C72H

007C73^H

007C74H

007C75^H

007C76H

007C77^H

007C78H

007C79^H

007C7AH

007C7B^H

007C7CH

007C7D^H

007C7EH

007C7F^H

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

36

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (2)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007C80^H

to

007C87H

XXXXXXXX

to

XXXXXXXX

Data register 0

(8 bytes)

DTR0

R/W

007C88^H

to

007C8FH

XXXXXXXX

to

XXXXXXXX

Data register 1

(8 bytes)

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

007C90^H

to

007C97H

XXXXXXXX

to

XXXXXXXX

Data register 2

(8 bytes)

007C98H

to

007C9FH

XXXXXXXX

to

XXXXXXXX

Data register 3

(8 bytes)

007CA0^H

to

007CA7H

XXXXXXXX

to

XXXXXXXX

Data register 4

(8 bytes)

007CA8H

to

007CAFH

XXXXXXXX

to

XXXXXXXX

Data register 5

(8 bytes)

007CB0^H

to

007CB7H

XXXXXXXX

to

XXXXXXXX

Data register 6

(8 bytes)

007CB8H

to

007CBFH

XXXXXXXX

to

XXXXXXXX

Data register 7

(8 bytes)

007CC0^H

to

007CC7H

XXXXXXXX

to

XXXXXXXX

Data register 8

(8 bytes)

007CC8H

to

007CCFH

XXXXXXXX

to

XXXXXXXX

Data register 9

(8 bytes)

007CD0^H

to

007CD7H

XXXXXXXX

to

XXXXXXXX

Data register 10

(8 bytes)

007CD8^H

to

007CDFH

XXXXXXXX

to

XXXXXXXX

Data register 11

(8 bytes)

007CE0H

to

007CE7^H

XXXXXXXX

to

XXXXXXXX

Data register 12

(8 bytes)

007CE8^H

to

007CEFH

XXXXXXXX

to

XXXXXXXX

Data register 13

(8 bytes)

37

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (3)

Address

CAN1

Register

Abbreviation

Access

Initial Value

007CF0^H

to

007CF7H

XXXXXXXX

to

XXXXXXXX

Data register 14

(8 bytes)

DTR14

R/W

007CF8^H

to

007CFFH

XXXXXXXX

to

XXXXXXXX

Data register 15

(8 bytes)

DTR15

R/W

38

MB90350 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

Interrupt vector

EI²OS

clear

DMA ch

number

register

Interrupt cause

Number

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

Address

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

Number

Address

Reset

N

INT9 instruction

Exception

N

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

Reserved

N

CAN 1 RX / Input Capture 6

CAN 1 TX/NS / Input Capture 7

I²C

Y1

N

Reserved

N

16-bit Reload Timer 0

16-bit Reload Timer 1

16-bit Reload Timer 2

16-bit Reload Timer 3

PPG 4/5

Y1

N

0

1

2

PPG 6/7

N

PPG 8/9/C/D

N

PPG A/B/E/F

N

Time Base Timer

External Interrupt 8 to 11

Watch Timer

N

Y1

N

3

External Interrupt 12 to 15

A/D Converter

Y1

N

4

5

I/O Timer 0 / I/O Timer 1

Input Capture 4/5

Output Compare 4/5

Input Capture 0/1

Output Compare 6/7

Reserved

Y1

N

6

7

8

9

10

11

12

13

Reserved

N

UART 3 RX

Y2

Y1

0000BDH

UART 3 TX

(Continued)

39

MB90350 Series

(Continued)

Interrupt control

register

Interrupt vector

Number Address

EI²OS

clear

DMA ch

number

Interrupt cause

Number

Address

UART 2 RX

Y2

Y1

N

14

15

#39

#40

#41

#42

FFFF60^H

FFFF5CH

FFFF58H

FFFF54H

ICR14

0000BEH

0000BFH

UART 2 TX

Flash Memory

Delayed interrupt

ICR15

N

Y1 : Usable

Y2 : Usable, with EI²OS stop function

N

: Unusable

Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service

at a time.

• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O

Service, the other one cannot use interrupts.

40

MB90350 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

VSS − 0.3 VSS + 6.0

V

Power supply voltage

AVCC

VCC = AVCC*¹

AVRH VSS − 0.3 VSS + 6.0

AVCC ≥ AVRH*¹

Input voltage

VI

VO

VSS − 0.3 VSS + 6.0

*2

Output voltage

Maximum Clamp Current

ICLAMP

Σ|I^CLAMP|

IOL

−4.0

+4.0

40

mA *4

mA *3

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

15

I^OLAV

ΣIOL

4

100

50

ΣI^OLAV

I^OH

−15

−4

IOHAV

ΣI^OH

−100

−50

ΣI^OHAV

+105 °C < Ta ≤ +125 °C,

240

320

mW Normal operation : maximum

frequency 16 MHz

Power consumption

P^D

−40 °C < Ta ≤ +105 °C,

mW Normal operation : maximum

frequency 24 MHz

−40

−55

+105

+125

+150

°C

Operating temperature

Storage temperature

T^A

°C *5

°C

T^STG

(Continued)

41

MB90350 Series

(Continued)

*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun

current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI

rating.

*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67

*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

+B input (0 V to 16 V)

N-ch

R

*5 : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

42

MB90350 Series

2. Recommended Conditions

(VSS = AVSS = 0 V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

Max

4.0

5.0

5.5

V

Under normal operation

Under normal operation, when not using the

A/D converter and not Flash programming.

3.5

5.0

5.5

V^CC,

AVCC

Power supply voltage

4.5

3.0

5.5

V

When External bus is used.

Maintains RAM data in stop mode

Use a ceramic capacitor or capacitor of bet-

Smooth capacitor

C^S

T^A

0.1

1.0

µF ter AC characteristics. Capacitor at the VCC

should be greater than this capacitor.

−40

+105

+125

°C

Operating temperature

°C *

* : If used exceeding T^A= +105 °C, be sure to contact Fujitsu for reliability limitations.

C

CS

C Pin Connection Diagram

Operation guaranteed range

24

16

40

105

125

Operation temperature TA ( C)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

43

MB90350 Series

3. DC Characteristics

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T^A= −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Port inputs if CMOS

hysteresis input levels

are selected (except

P12, P15, P44, P45,

P50)

V^IHS

0.8 VCC

VCC + 0.3

V

Port inputs if

AUTOMOTIVE input

levels are selected

V^IHA

VIHT

V^IHS

0.8 VCC

2.0

VCC + 0.3

V

Input H

voltage

(At V^CC=

5 V ± 10%)

Port inputs if TTL input

levels are selected

P12, P15, P50 inputs if

CMOS input levels are

selected

0.7 VCC

P44, P45 inputs if

CMOS hysteresis input

levels are selected

V^IHI

0.7 VCC

VCC + 0.3

V

RST input pin (CMOS

hysteresis)

V^IHR

V^IHM

0.8 VCC

VCC + 0.3

V

VCC − 0.3

MD input pin

Port inputs if CMOS

hysteresis input levels

are selected (except

P12, P15, P44, P45,

P50)

V^ILS

VSS − 0.3

0.2 VCC

V

Port inputs if

AUTOMOTIVE input

levels are selected

V^ILA

VILT

V^ILS

VSS − 0.3

0.5 VCC

0.8

V

Input L

voltage

(At V^CC=

5 V ± 10%)

Port inputs if TTL

input levels are selected

P12, P15, P50 inputs if

CMOS input levels are

selected

0.3 VCC

P44, P45 inputs if

CMOS hysteresis input

levels are selected

V^ILI

VSS − 0.3

0.3 VCC

V

RST input pin (CMOS

hysteresis)

VILR

V^ILM

V^OH

VSS − 0.3

V^CC− 0.5

0.2 VCC

V

VSS + 0.3

MD input pin

Output H

voltage

Normal

outputs

VCC = 4.5 V,

IOH = −4.0 mA

Output H

voltage

I²Ccurrent VCC = 4.5 V,

V^OHI

V^OL

V^OLI

V^CC− 0.5

V

outputs

IOH = −3.0 mA

Output L

voltage

Normal

outputs

VCC = 4.5 V,

IOL = 4.0 mA

0.4

Output L

voltage

I²Ccurrent VCC = 4.5 V,

outputs IOL = 3.0 mA

(Continued)

44

MB90350 Series

(Continued)

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T^A= −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit Remarks

Min Typ Max

Input leak current

I^IL

VCC = 5.5 V, VSS < VI < VCC

−1

1

µA

P00 to P07,

P10 to P17,

P20 to P25,

P30 to P37,

RST

Pull-up

resistance

R^UP

25

50

100 kΩ

Except

100 kΩ Flash

devices

Pull-down

resistance

R^DOWN

MD2

25

50

65

70

25

0.3

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

65

80

85

35

0.8

mA MB90F352

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At writing FLASH memory.

I^CC

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At erasing FLASH memory.

VCC = 5.0 V,

Internal frequency : 24 MHz,

At Sleep mode.

I^CCS

VCC = 5.0 V,

Internal frequency : 2 MHz,

At Main Timer mode

I^CTS

VCC = 5.0 V,

Power supply

current*

Internal frequency : 24 MHz,

At PLL Timer mode,

external frequency = 4 MHz

VCC

I^CTSPLL6

4

7

mA MB90F352

VCC = 5.0 V,

Internal frequency: 8 kHz,

At sub operation

T^A= +25°C

I^CCL

170

20

360 µA MB90F352

VCC = 5.0 V,

Internal frequency: 8 kHz,

At sub sleep

I^CCLS

50

35

µA MB90F352

TA = +25°C

VCC = 5.0 V,

Internal frequency: 8 kHz,

At watch mode

TA = +25°C

I^CCT

10

VCC = 5.0 V,

At Stop mode,

T^A= +25°C

I^CCH

7

5

25

15

µA MB90F352

Other than C, AVCC, AVSS,

AVRH, VCC, VSS,

Input capacity

C^IN

pF

* : The power supply current is measured with an external clock.

45

MB90350 Series

4. AC Characteristics

(1) Clock Timing

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T^A= −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

16

X0, X1

3

MHz When using an oscillation circuit

f^C

Clock frequency

X0

X0A, X1A

X0, X1

3

—

62.5

24

MHz When using an external clock*

kHz

f^CL

32.768 100

333

ns

µs

ns

µs

When using an oscillation circuit

When using an external clock

t^CYL

Clock cycle time

X0

X0A, X1A

X0

41.67

10

333

t^CYLL

30.5

15.2

—

P^WH, PWL

P^WHL, PWLL

10

Input clock pulse width

Duty ratio is about 30% to 70%.

X0A

5

Input clock rise and fall

time

t^CR, tCF

X0

5

ns

When using external clock

When using main clock at

Ta ≤ +105 °C

24

Internal operating

clock frequency

(machine clock)

f^CP

f^CPL

t^CP

1.5

MHz

When using main clock at

Ta ≤ +125 °C

16

50

8.192

122.1

kHz When using sub clock

When using main clock at

41.67

Ta ≤ +105 °C

ns

Internal operating

clock cycle time

(machine clock)

666

When using main clock at

62.5

20

Ta ≤ +125 °C

t^CPL

µs

When using sub clock

* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as

mentioned in “Relation among external clock frequency and machine clock frequency”.

tCYL

0.8 VCC

X0

0.2 VCC

PWH

PWL

tCF

tCR

tCYLL

0.8 VCC

0.2 VCC

X0A

PWHL

PWLL

tCF

tCR

Clock Timing

46

MB90350 Series

Guaranteed operation range

5.5

4.0

Guaranteed A/D Converter

operation range

3.5

Guaranteed PLL operation range

1.5

24

4

Machine clock f^CP(MHz)

Guaranteed operation range of MB90350 series

Guaranteed oscillation frequency range

x 2

x 1

x 6 x 4

x 3

24

16

12

Internal clock

f^CP(MHz)

x 1/2

(PLL off)

8

4.0

1.5

12

16

3

8

4

24

External clock f^C(MHz) *

* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz

External clock frequency and Machine clock frequency

47

MB90350 Series

(2) Reset Standby Input

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T^A= −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Parameter Symbol

Unit

Remarks

Min

Max

500

ns

Under normal operation

In Stop mode, Sub Clock

mode, Sub Sleep mode

and Watch mode

Oscillation time of oscillator*

Reset input

t^RSTL

µs

RST

+ 100 µs

time

In Main timer mode and

PLL timer mode

100

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators,

the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.

Under normal operation:

t^RSTL

RST

0.2 V^CC

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100

s

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

48

MB90350 Series

(3) Power On Reset

(T^A= −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T^A= −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

Power on rise time

Power off time

t^R

VCC

30

ms

t^OFF

ms Due to repetitive operation

tR

2.7 V

VCC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

Holds RAM data

3 V

VSS

49

MB90350 Series

(4) Bus Timing (Read)

(T^A= –40°C to +85°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 16 MHz)

Value

Sym-

bol

Parameter

ALE pulse width

Valid address

Condition

Unit Remarks

Min

Max

t^LHLL

ALE

tCP/2 − 10

ns

ALE, A21 to

A16, AD15

to AD00

ALE ↓ time

tAVLL

t^LLAX

tAVRL

tCP/2 − 15

tCP − 15

ns

ALE, AD15

to AD00

ALE ↓

Address valid time

A21 toA16,

AD15 to

Valid address

RD ↓ time

AD00, RD

A21 to A16,

AD15 to

AD00

Valid address

input

Valid data

t^AVDV

5 tCP/2 − 40

3 tCP/2 − 50

ns

RD pulse width

tRLRH

tRLDV

RD

3 tCP/2 − 20

ns

RD, AD15 to

AD00

RD ↓

Valid data input

Data hold time

RD, AD15 to

AD00

RD ↑

RD ↓

RD ↑

tRHDX

tRHLH

tRHAX

0

ns

ALE ↑ time

RD, ALE

tCP/2 − 15

tCP/2 − 10

RD, A21 to

A16

Address valid time

A21 to A16,

AD15 to

Valid address

CLK ↑ time

t^AVCH

tCP/2 − 15

ns

AD00, CLK

RD ↓

CLK ↑ time

RD ↓ time

tRLCH

tLLRL

RD, CLK

ALE, RD

tCP/2 − 15

ns

ALE ↓

50

MB90350 Series

t^RLCH

t^AVCH

2.4 V

CLK

ALE

RD

t^LLAX

t^AVLL

t^RHLH

2.4 V

0.8 V

2.4 V

t^LHLL

t^AVRL

t^RLRH

2.4 V

0.8 V

t^LLRL

t^RHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

t^RLDV

t^RHDX

t^AVDV

2.4 V

0.8 V

VIH

VIL

2.4 V

0.8 V

VIH

VIL

AD15 to AD00

Address

Read data

51

MB90350 Series

(5) Bus Timing (Write)

(T^A= –40°C to +85°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 16 MHz)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

A21 to A16,

AD15 to AD00,

WR

Valid address

WR ↓ time

WR ↑

tAVWL

t^CP−15

ns

WR pulse width

tWLWH

tDVWH

WR

3 tCP/2 − 20

ns

Valid data output

time

AD15 to AD00,

WR

AD15 to AD00,

WR

WR ↑

Data hold time

tWHDX

tWHAX

15

ns

A21 to A16,

WR

Address valid time

tCP/2 − 10

WR ↑

WR ↓

ALE ↑ time

CLK ↑ time

tWHLH

tWLCH

WR, ALE

WR, CLK

tCP/2 − 15

ns

t^WLCH

2.4 V

CLK

t^WHLH

2.4 V

ALE

t^AVWL

t^WLWH

2.4 V

WR (WRL, WRH)

0.8 V

t^WHAX

2.4 V

0.8 V

2.4 V

0.8 V

A21 to A16

t^DVWH

t^WHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to AD00

Address

Write data

52

MB90350 Series

(6) Ready Input Timing

Parameter

(T^A= –40°C to +85°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 16 MHz)

Rated Value

Test

Sym-

bol

Units Remarks

Condition

Min

45

0

Max

RDY setup time

RDY hold time

t^RYHS

RDY

ns

tRYHH

Note : If the RDY setup time is insufficient, use the auto-ready function.

2.4 V

CLK

ALE

RD/WR

t^RYHS

t^RYHH

V^IH

RDY

When WAIT is not used.

RDY

V^IL

When WAIT is used.

53

MB90350 Series

(7) Hold Timing

(T^A= –40°C to +85°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 16 MHz)

Value

Parameter

Symbol

Condition

Units

Remarks

Min

Max

Pin floating

time

HAK ↓

tXHAL

tHAHV

HAK

30

t^CP

ns

HAK ↑ time

time

Pin valid

tCP

2 tCP

Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.

2.4V

HAK

0.8V

t^HAHV

t^XHAL

High-Z

2.4V

0.8V

2.4V

0.8V

Each pin

54

MB90350 Series

(8) UART 2/3

(T^A= –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

SCK2, SCK3

8 t^CP*

ns

SCK2, SCK3,

SOT2, SOT3

SCK ↓ → SOT delay time

tSLOV

−80

100

60

+80

Internal clock

operation output

pins are

SCK2, SCK3,

SIN0 to SIN4

Valid SIN → SCK ↑

t^IVSH

t^SHIX

ns

CL = 80 pF + 1 TTL

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

tSLSH

SCK2, SCK3

4 t^CP*

ns

4 tCP*

SCK2, SCK3, External clock

SOT2, SOT3 operation output

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

pins are

CL = 80 pF + 1 TTL

SCK2, SCK3,

SIN2, SIN3

60

SCK2, SCK3,

SIN2, SIN3

SCK ↑ → Valid SIN hold time

* : Refer to “ (1) Clock timing” rating for t^CP(internal operating clock cycle time).

Notes : • AC characteristic in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• tCP is the machine cycle (Unit : ns)

t^SCYC

2.4 V

SCK

0.8 V

t^SLOV

2.4 V

SOT

0.8 V

t^IVSH

V^IH

t^SHIX

V^IH

V^IL

SIN

V^IL

Internal Shift Clock Mode

55

MB90350 Series

t^SLSH

t^SHSL

V^IH

SCK

SOT

V^IL

t^SLOV

V^IL

2.4 V

0.8 V

t^IVSH

t^SHIX

V^IH

V^IL

V^IH

V^IL

SIN

External Shift Clock Mode

(9) Trigger Input Timing

(T^A= –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

INT8 to INT15,

INT9R to INT11R,

ADTG

t^TRGH

tTRGL

Input pulse width

5 tCP

ns

V^IH

INT8 to INT15,

V^IL

INT9R to INT11R,

ADTG

t^TRGH

t^TRGL

56

MB90350 Series

(10) Timer Related Resource Input Timing

(T^A= –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

t^TIWH

t^TIWL

TIN1, TIN3,

IN0, IN1,

IN4 to IN7

Input pulse width

4 tCP

ns

V^IH

TIN1, TIN3,

IN0, IN1,

V^IL

t^TIWH

IN4 to IN7

t^TIWL

(11) Timer Related Resource Output Timing

(T^A= –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(TA = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

TOT1, TOT3,

PPG4, PPG6,

PPG8 to PPGF

CLK ↑

T^OUTchange time

tTO

30

ns

2.4 V

CLK

2.4 V

0.8 V

TOT1, TOT3,

PPG4, PPG6

PPG8 to PPGF

t^TO

57

MB90350 Series

5. A/D Converter

(TA

= −40 °C to +105 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(TA

= −40 °C to +125 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

10

Resolution

Total error

bit

±3.0

±2.5

LSB

Nonlinearity error

Differential

nonlinearity error

±1.9

LSB

Zero reading

voltage

V^OT

AN0 to AN14 AVSS − 1.5

AVSS + 0.5

AVSS + 2.5 LSB

Full scale reading

voltage

V^FST

AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

1.0

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AVCC < 4.5 V

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC< 4.5 V

Compare time

Sampling time

16,500

µs

2.0

0.5

1.2

∞

Analog port input

current

IAIN

AN0 to AN14

AVRH

−0.3

AVSS

+0.3

AVRH

AVCC

µA

V

Analog input

voltage range

V^AIN

Reference

voltage range

AV^SS+ 2.7

V

I^A

I^AH

IR

AVCC

3.5

7.5

5

mA

µA

Power supply

current

*

AVRH

600

900

5

Reference

voltage current

IRH

Offset between

input channels

AN0 to AN14

4

LSB

* : When not operating A/D converter, this is the current (V^CC= AVCC = AVRH = 5.0 V) .

Note : The accuracy gets worse as |AVRH − AVSS| becomes smaller.

58

MB90350 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error

: Difference between an actual value and an ideal value. A total error includes zero transition

error, full-scale transition error, and linear error.

Zero reading

voltage

: Input voltage which results in the minimum conversion value.

Full scale

: Input voltage which results in the maximum conversion value.

reading voltage

Total error

3FF

1.5 LSB

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

VNT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AV^SS

1 LSB = (Ideal value)

[V]

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

V^NT: A voltage at which digital output transitions from (N − 1) to N.

(Continued)

59

MB90350 Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

Actual conversion

characteristics

3FE

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ VOT }

3FD

VFST (actual

measurement

value)

N

VNT (actual

measurement value)

004

003

002

001

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

VOT (actual measurement value)

Analog input

AVSS

AVRH

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (^N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

60

MB90350 Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :

Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AV^CC≤ 5.5 V,

sampling period ≤ 0.5 µs)

If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors

and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high

as internal capacitor.

If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.

• Analog input circuit model

R

Analog input

Comparator

C

4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF

4.0 V ≤ AVCC < 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF

Note : Use the values in the figure only as a guideline.

8. Flash Memory Program/Erase Characteristics

Value

Parameter

Conditions

Unit

Remarks

Min

Typ

Max

Excludes programming

prior to erasure

Sector erase time

Chip erase time

1

15

s

T^A= +25 °C

VCC = 5.0 V

Excludes programming

prior to erasure

9

Word (16 bit width)

programming time

Except for the overhead

time of the system

16

3,600

µs

Program/Erase cycle

10,000

cycle

61

MB90350 Series

■ ORDERING INFORMATION

Part number

MB90F352PFV

Package

Remarks

MB90F352SPFV

MB90F352CPFV

MB90F352CSPFV

MB90352PFV

64-pin Plastic LQFP

(FPT-64P-M09)

MB90352SPFV

MB90352CPFV

MB90352CSPFV

64-pin Plastic LQFP

(FPT-64P-M09)

299-pin Ceramic PGA

(PGA-299C-A01)

MB90V340

For evaluation

62

MB90350 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness including plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

64-pin Plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

*12.00±0.10(.472±.004)SQ

0.145±0.055

(.0057±.0022)

48

33

49

32

0.10(.004)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.25(.010)

INDEX

0~8˚

64

17

0.50±0.20

(.020±.008)

0.10±0.10

(.004±.004)

(Stand off)

"A"

1

16

0.60±0.15

(.024±.006)

0.65(.026)

0.32±0.05

(.013±.002)

M

0.13(.005)

C

2003 FUJITSU LIMITED F64018S-c-3-5

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

63

MB90350 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0309

FUJITSU LIMITED Printed in Japan


型号：	MB90F352CSPFV
厂家：	SPANSION
描述：	Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP64, PLASTIC, LQFP-64 微控制器
文件：	总64页 (文件大小：800K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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