MBM29PL64LM10PCN-E1_技术文档

MBM29PL64LM 90/10

Data Sheet (Retired Product)

MBM29PL64LM 90/10Cover Sheet

This product has been retired and is not recommended for new designs. Availability of this document is retained for reference

and historical purposes only.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been

made are the result of normal data sheet improvement and are noted in the document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number MBM29PL64LM

Revision DS05-20902-2E

Issue Date July 31, 2007

D a t a S h e e t ( R e t i r e d P r o d u c t )

This page left intentionally blank.

2

MBM29PL64LM_DS05-20902-2E July 31, 2007

TM

SPANSION Flash Memory

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20902-2E

FLASH MEMORY

CMOS

64 M (8M × 8/4M × 16) BIT

MirrorFlash^TM*

MBM29PL64LM 90/10

■ DESCRIPTION

The MBM29PL64LM is a 64M-bit, 3.0 V-only Flash memory organized as 8M bytes by 8 bits or 4M words by 16

bits. The MBM29PL64LM is offered in 48-pin, 58-pin TSOP(1) and 80-ball FBGA. The device is designed to be

programmed in-system with the standard 3.0 V V^CCsupply. 12.0 V VPP and 5.0 V VCC are not required for write

or erase operations. The devices can also be reprogrammed in standard EPROM programmers.

(Continued)

■ PRODUCT LINE UP

MBM29PL64LM

Part No.

90

3.0 V to 3.6 V

90 ns

10

3.0 V to 3.6 V

100 ns

V^CC

Max Address Access Time

Max CE Access Time

Max Page Read Access Time

90 ns

100 ns

25 ns

30 ns

■ PACKAGES

48-pin plastic TSOP (1)

56-pin plastic TSOP (1)

80-ball plastic FBGA

(FPT-48P-M19)

(FPT-56P-M01)

(BGA-80P-M01)

* : MirrorFlash^TMis a trademark of Fujitsu Limited.

Notes : • Programming in byte mode ( × 8) is prohibited.

• Programming to the address that already contains data is prohibited.

(It is mandatory to erase data prior to overprogram on the same address.)

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MBM29PL64LM90/10

(Continued)

The standard MBM29PL64LM offers access times of 90 ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE),

and output enable (OE) controls.

The MBM29PL64LM supports command set compatible with JEDEC single-power-supply EEPROMS standard.

Commands are written into the command register. The register contents serve as input to an internal state-

machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and

data needed for the programming and erase operations. Reading data out of the devices is similar to reading

from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29PL64LM is programmed by executing the program command sequence. This will invoke the Em-

bedded Program Algorithm^TMwhich is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will

invoke the Embedded Erase Algorithm^TMwhich is an internal algorithm that automatically preprograms the array

if it is not already programmed before executing the erase operation. During erase, the device automatically

times the erase pulse widths and verifies proper cell margin.

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ⁶. Once the end of a program or erase cycle has been completed, the devices

internally return to the read mode.

Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simulta-

neously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM program-

ming mechanism of hot electron injection.

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MBM29PL64LM90/10

■ FEATURES

• 0.23 μm Process Technology

• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Industry-standard pinouts

48-pin TSOP (1) (Package suffix: TN - Normal Bend Type)

56-pin TSOP (1) (Package suffix: PCN - Normal Bend Type)

80-ball FBGA(Package suffix: PBT)

• Minimum 100,000 program/erase cycles

• High performance Page mode

Fast 8 bytes / 4 words access capablilty

• Sector erase architecture

128 × 64K byte and 32K word sectors

Any combination of sectors can be concurrently erased. Also supports full chip erase

• HiddenROM

256 bytes / 128 words of HiddenROM, accessible through a “HiddenROM Entry” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At V^IL, allows protection of first 64K bytes / 32K words sectors, regardless of sector protection/unprotection

status

At V^ACC, increases program performance

• Embedded Erase^TM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TM* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

• Program Suspend/Resume

Suspends the program operation to allow a read in another address

• Low V^CCwrite inhibit ≤ 2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector Group Protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector protect command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin

This feature allows code changes in previously locked sectors

• In accordance with CFI (Common Flash Memory Interface)

* : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

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MBM29PL64LM90/10

■ PIN ASSIGNMENTS

48 pin TSOP(1)

(Top View)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

BYTE

V^SS

46

1

2

3

4

5

6

7

8

48

47

(Marking Side)

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

45

44

43

42

41

40

39

38

37

36

35

34

9

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

A21

WP/ACC

RY/BY

A¹⁸

DQ2

33

A17

A7

A6

A5

A4

A3

A2

A1

DQ9

32

DQ1

31

DQ8

30

DQ0

29

OE

28

V^SS

27

CE

26

A⁰

25

(FPT-48P-M19)

56 pin TSOP(1)

(Top View)

N.C.

A15

A14

A13

A12

A11

A10

A9

N.C.

56

1

2

3

4

5

6

7

8

(Marking Side)

N.C.

55

A16

BYTE

V^SS

52

54

53

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

51

50

49

48

47

46

45

44

43

42

41

40

9

A8

A19

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

WE

RESET

A²¹

WP/ACC

RY/BY

A¹⁸

DQ2

39

A17

A7

A6

A5

A4

A3

A2

A1

DQ9

38

DQ1

37

DQ8

36

DQ0

35

OE

34

V^SS

33

CE

32

A⁰

31

N.C.

30

V^CCQ

29

(FPT-56P-M01)

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MBM29PL64LM90/10

(Marking side)

FBGA

(Top view)

A8

B8

L8

M8

C8

D8

E8

F8

G8

H8

N.C. N.C.

H7 J7

J8

K8

N.C. N.C.

N.C.

VSS

N.C.

VCCQ

N.C. N.C.

A7

B7

C7

D7

E7

F7

G7

K7

L7

M7

N.C. N.C.

A13

A12

A14

A15

A16 BYTE DQ15/A-1 VSS N.C. N.C.

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7 DQ14 DQ13 DQ6

C5

WE

C4

D5

E5

F5

G5

H5

J5

K5

A21

A19

DQ5 DQ12 VCC DQ4

RESET

D4

E4

F4

G4

H4

J4

K4

RY/BY WP/ACC A18

A20

DQ2 DQ10 DQ11 DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0 DQ8 DQ9 DQ1

A2

N.C. N.C.

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

M2

B2

OE

VSS N.C. N.C.

C1

D1

E1

F1

G1

H1

J1

K1

A1

B1

L1

M1

VCC

N.C.

N.C. N.C. VCCQ VSS

(BGA-80P-M01)

N.C.

N.C. N.C.

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MBM29PL64LM90/10

■ PIN DESCRIPTIONS

MBM29PL64LM Pin Configuration

Function

A²¹to A0, A-1

DQ¹⁵to DQ0

CE

Address Inputs

Data Inputs/Outputs

Chip Enable

OE

Output Enable

Write Enable

WE

WP/ACC

RESET

BYTE

RY/BY

V^CC

Hardware Write Protection/Program Acceleration

Hardware Reset Pin/Temporary Sector Group Unprotection

Select 8-bit or 16-bit mode

Ready/Busy Output

Device Power Supply

V^CCQ

Ouput Voltage

V^SS

Device Ground

N.C.

No Internal Connection

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■ BLOCK DIAGRAM

DQ15 to DQ0

VCC

VSS

V^CCQ

Input/Output

Buffers

Erase Voltage

Generator

WE

State

Control

RESET

WP/ACC

Command

Register

BYTE

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

CE

OE

Y-Gating

Y-Decoder

X-Decoder

STB

Timer for

Program/Erase

Address

Latch

Cell Matrix

A21 to A2

A1, A0

(A- )

1

■ LOGIC SYMBOL

A-1

22

A21 to A0

16 or 8

DQ 15 to DQ 0

CE

OE

WE

WP/ACC

RESET

BYTE

RY/BY

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MBM29PL64LM90/10

■ DEVICE BUS OPERATION

MBM29PL64LM User Bus Operations (Word Mode : BYTE = VIH)

DQ15 to

DQ⁰

WP/

ACC

Operation

CE OE WE A0 A1

A2

A3

A6

A9

RESET

Standby

H

L

X

L

X

H

L

X

L

X

L

X

L

X

L

X

L

X

VID

A9

X

Hi-Z

Code

DOUT

Hi-Z

*4

H

X

Autoselect Manufacture Code*¹

Autoselect Device Code*¹

Read

L

H

A⁰

X

L

H

X

L

A1

X

A2

X

A3

X

A6

X

H

X

Output Disable

H

X

Write (Program/Erase)

Enable Sector Group Protection*²

A⁰

L

A1

H

A2

L

A3

L

A6

L

A9

X

H

*5

H

L

*4

VID

Temporary Sector Group

Unprotection

X

*4

V^ID

H

Reset (Hardware)

Sector Write Protection*³

X

Hi-Z

X

L

X

L

H

Legend : L = V^IL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.

Hi-Z = High-Z, V^ID= 11.5 V to 12.5 V

*1 : Manufacturer and device codes may also be accessed via a command register write sequence.

See “MBM29PL64LM Standard Command Definitions”.

*2 : Refer to Sector Group Protection.

*3 : Protects the first 32K words sector (SA0)

*4 : D^INor DOUT as required by command sequence, data pulling, or sector protect algorithm

*5 : If WP/ACC = VIL, the first sector remain protected.

If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method

specified in "Sector Group Protection".

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MBM29PL64LM90/10

MBM29PL64LM User Bus Operations (Byte Mode : BYTE = VIL)

DQ15/

A^-1

DQ7 to

DQ⁰

WP/

ACC

Operation

CE OE WE

A0

A1 A2 A3 A6 A9

RESET

Standby

H

L

X

L

X

H

L

X

L

X

L

X

L

X

L

X

L

X

L

X

Hi-Z

H

X

Autoselect Manufacture Code*¹

Autoselect Device Code*¹

Read

VID Code

L

H

A0

X

H

X

L

A^-1

X

A1 A2 A3 A6 A9

DOUT

Hi-Z

*4

H

X

Output Disable

H

X

H

X

Write (Erase)

Enable Sector Group Protection*²

A^-1

L

A0

L

A1 A2 A3 A6 A9

H

*5

H

L

H

X

L

X

*4

VID

Temporary Sector Group

Unprotection

X

*4

V^ID

H

Reset (Hardware)

Sector Write Protection*³

X

Hi-Z

X

L

X

L

H

Legend : L = V^IL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.

Hi-Z = High-Z, V^ID= 11.5 V to 12.5 V

*1 : Manufacturer and device codes may also be accessed via a command register write sequence.

See “MBM29PL64LM Standard Command Definitions”.

*2 : Refer to Sector Group Protection.

*3 : Protects the first 64K bytes sector (SA0)

*4 : D^INor DOUT as required by command sequence, data pulling, or sector protect algorithm

*5 : If WP/ACC = VIL, the first sector remain protected.

If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method

specified in "Sector Group Protection".

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MBM29PL64LM90/10

MBM29PL64LM Standard Command Definitions*¹

Fourth Bus

Read/Write

Cycle

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req'd

Command

Sequence

Write Cycle Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Word/

Byte

Reset*²

1

3

XXXh F0h

—

Word

Byte

555h

AAh

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

13

55h

F0h RA*

RD*

AAAh

Word

Byte

555h

AAh

Autoselect

(Device ID)

55h

90h 00h* 04h*¹³

—

3

4

6

AAAh

Word

Byte

555h AAh 2AAh 55h 555h A0h

PA

555h

AAAh

555h

AAAh

—

PD

—

2AAh

555h

2AAh

555h

—

Program

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

—

555h

AAAh

555h

AAAh

—

555h

AAAh

AAh

55h

80h

AAh

55h

10h

Chip Erase

Word

Byte

AAh

55h

SA

30h

Sector Erase

6

Program/Erase Suspend*³

Program/Erase Resume*³

1

XXXh B0h

XXXh 30h

—

Word

Set to Fast Mode*⁴

Byte

555h

AAh

2AAh

555h

PA

555h

AAAh

—

55h

PD

20h

—

3

AAAh

Fast Program*⁴

2

Word

XXXh A0h

—

Reset from Fast

Mode*⁵

Word/

Byte

12

XXXh 90h XXXh 00h*

—

SA

—

Word

Byte

555h

2AAh

555h

AAh

29h

AAh

55h

25h

—

SA

—

0Fh

—

PA

—

PD WBL PD

Write to Buffer

20

1

AAAh

Program Buffer to Flash

(Confirm)

SA

—

Word

555h

2AAh

555h

WritetoBufferAbort

Reset*⁶

3

55h

F0h

—

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

AAAh

Extended Sector

Group Protection* *

SGA

13

XXXh 60h SGA 60h SGA 40h

SD*

—

4

13

7,

8

*

55h

Query*⁹

1

98h

AAh

—

AAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

HiddenROM

Entry*¹⁰

55h

88h

A0h

—

3

4

HiddenROM

PA

PD

Program *^10,*¹¹

HiddenROM Exit*¹¹

90h XXXh 00h

(Continued)

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MBM29PL64LM90/10

(Continued)

Legend : Address bits A²¹to A15 = X = “H” or “L” for all address commands except for Program Address (PA),

Sector Address (SA) and Sector Group Address (SGA).

Bus operations are defined in “MBM29PL64LM User Bus Operations (Word Mode : BYTE = VIH)”

and “MBM29PL64LM User Bus Operations (Byte Mode : BYTE = VIL)”.

RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the write pulse.

SA = Address of the sector to be programmed / erased. The combination of A²¹, A20, A19, A18, A17, A16,

and A¹⁵will uniquely select any sector. See “Sector Address Table (MBM29PL64LM)”.

SGA = Sector Group Address to be protected. See “Sector Group Address Table (MBM29PL64LM)”.

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write plus.

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

WBL = Write Buffer Location

HRA = Address of the HiddenROM area ;

Word Mode : 000000h to 000007h

Byte Mode : 000000h to 0000FFh

*1 : The command combinations not described in “MBM29PL64LM Standard Command Definitions” are

illegal.

*2 : Both of these reset commands are equivalent except for "Write to Buffer Abort" reset.

*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.

*4 : The Set to Fast Mode command is required prior to the Fast Program command.

*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast mode.

*6 : Reset to the read mode. The Write to Buffer Abert Reset command is required after the Write to Buffer

operation was aborted.

*7 : This command is valid while RESET = VID.

*8 : Sector Group Address (SGA) with A⁶= 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0

*9 : The valid address are A⁶to A0.

*10 : The HiddenROM Entry command is required prior to the HiddenROM programming.

*11 : This command is valid during HiddenROM mode.

*12 : The data “F0h” is also acceptable.

*13 : Indicates read cycle.

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Sector Group Protection Verify Autoselect Codes

A-1*¹

VIL

X

Type

A²¹to A15

A6

A3

A2

A1

A0

Code (HEX)

04h

Manufacturer’s Code

X

V^IL

VIL

Word

Byte

Word

Byte

Word

Byte

227Eh

7Eh

Device Code

X

V^IL

VIL

VIH

VIL

VIH

VIL

VIH

VIL

V^IL

X

220Ch

0Ch

V^IL

X

Extended Device Code*²

2201h

01h

V^IL

VIH

VIL

VIH

VIL

VIH

VIL

V^IL

Sector Group

Addresses

Sector Group Protection*⁴

*1 : A^-1is for Byte mode.

VIL

*3

*2 : At Word mode, a read cycle at address 01h ( at Byte mode, 02h ) outputs device code. When 227Eh

( at Byte mode, 7Eh ) is output, it indicates that reading two additional codes, called Extended Device

Codes, will be required. Therefore the system may continue reading out these Extended Device

Codes at the address of 0Eh ( at Byte mode, 1Ch ), as well as at 0Fh ( at Byte mode, 1Eh ).

*3 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*4 : Given CE = Fix, wait for one cycle after the rising edge of WE (the last write command) , then indicate SGA as

(A⁶, A3, A2, A1, A0, A − 1) = (0, 0, 0, 1, 0, 0) .

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Sector Address Table (MBM29PL64LM)

Sector size

(Kbytes/

Kwords)

(×8)

(×16)

Address Range

Sector

A²¹A20 A19 A18 A17 A16 A15

Address Range

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

000000h to 00FFFFh

010000h to 01FFFFh

020000h to 02FFFFh

030000h to 03FFFFh

040000h to 04FFFFh

050000h to 05FFFFh

060000h to 06FFFFh

070000h to 07FFFFh

080000h to 08FFFFh

090000h to 09FFFFh

000000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

100000h to 10FFFFh

110000h to 11FFFFh

120000h to 12FFFFh

130000h to 13FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

(Continued)

16

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MBM29PL64LM90/10

Sector size

(Kbytes/

Kwords)

(×8)

(×16)

Address Range

Sector

A²¹A20 A19 A18 A17 A16 A15

Address Range

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh

210000h to 21FFFFh

220000h to 22FFFFh

230000h to 23FFFFh

240000h to 24FFFFh

250000h to 25FFFFh

260000h to 26FFFFh

270000h to 27FFFFh

280000h to 28FFFFh

290000h to 29FFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

2A0000h to 2AFFFFh 150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

2E0000h to 2EFFFFh 170000h to 177FFFh

2F0000h to 2FFFFFh 178000h to 17FFFFh

300000h to 30FFFFh

310000h to 31FFFFh

320000h to 32FFFFh

330000h to 33FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

(Continued)

17

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MBM29PL64LM90/10

Sector size

(Kbytes/

Kwords)

(×8)

(×16)

Address Range

Sector

A²¹A20 A19 A18 A17 A16 A15

Address Range

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

400000h to 40FFFFh

410000h to 41FFFFh

420000h to 42FFFFh

430000h to 43FFFFh

440000h to 44FFFFh

450000h to 45FFFFh

460000h to 46FFFFh

470000h to 47FFFFh

480000h to 48FFFFh

490000h to 49FFFFh

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

4A0000h to 4AFFFFh 250000h to 257FFFh

4B0000h to 4BFFFFh 258000h to 25FFFFh

4C0000h to 4CFFFFh 260000h to 267FFFh

4D0000h to 4DFFFFh 268000h to 26FFFFh

4E0000h to 4EFFFFh 270000h to 277FFFh

4F0000h to 4FFFFFh 278000h to 27FFFFh

500000h to 50FFFFh

510000h to 51FFFFh

520000h to 52FFFFh

530000h to 53FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

540000h to 54FFFFh 2A0000h to 2A7FFFh

550000h to 55FFFFh 2A8000h to 2AFFFFh

560000h to 56FFFFh 2B0000h to 2B7FFFh

570000h to 57FFFFh 2B8000h to 2BFFFFh

580000h to 58FFFFh 2C0000h to 2C7FFFh

590000h to 59FFFFh 2C8000h to 2CFFFFh

5A0000h to 5AFFFFh 2D0000h to 2D7FFFh

5B0000h to 5BFFFFh 2D8000h to 2DFFFFh

5C0000h to 5CFFFFh 2E0000h to 2EE7FFh

5D0000h to 5DFFFFh 2E8000h to 2EFFFFh

5E0000h to 5EFFFFh 2F0000h to 2F7FFFh

(Continued)

18

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MBM29PL64LM90/10

(Continued)

Sector size

(Kbytes/

Kwords)

(×8)

(×16)

Address Range

Sector

A²¹A20 A19 A18 A17 A16 A15

Address Range

SA95

SA96

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64/32

5F0000h to 5FFFFFh 2F8000h to 2FFFFFh

600000h to 60FFFFh

610000h to 61FFFFh

620000h to 62FFFFh

630000h to 63FFFFh

640000h to 64FFFFh

650000h to 65FFFFh

660000h to 66FFFFh

670000h to 67FFFFh

680000h to 68FFFFh

690000h to 69FFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

6A0000h to 6AFFFFh 350000h to 357FFFh

6B0000h to 6BFFFFh 358000h to 35FFFFh

6C0000h to 6CFFFFh 360000h to 367FFFh

6D0000h to 6DFFFFh 368000h to 36FFFFh

6E0000h to 6EFFFFh 370000h to 377FFFh

6F0000h to 6FFFFFh 378000h to 37FFFFh

700000h to 70FFFFh

710000h to 71FFFFh

720000h to 72FFFFh

730000h to 73FFFFh

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

740000h to 74FFFFh 3A0000h to 3A7FFFh

750000h to 75FFFFh 3A8000h to 3AFFFFh

760000h to 76FFFFh 3B0000h to 3B7FFFh

770000h to 77FFFFh 3B8000h to 3BFFFFh

780000h to 78FFFFh 3C0000h to 3C7FFFh

790000h to 79FFFFh 3C8000h to 3CFFFFh

7A0000h to 7AFFFFh 3D0000h to 3D7FFFh

7B0000h to 7BFFFFh 3D8000h to 3DFFFFh

7C0000h to 7CFFFFh 3E0000h to 3E7FFFh

7D0000h to 7DFFFFh 3E8000h to 3EFFFFh

7E0000h to 7EFFFFh 3F0000h to 3F7FFFh

7F0000h to 7FFFFFh 3F8000h to 3FFFFFh

Note : The address range is A²¹: A-1 if in Byte mode (BYTE = VIL) .

The address range is A²¹: A0 if in Word mode (BYTE = VIH) .

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MBM29PL64LM90/10

Sector Group Address Table (MBM29PL64LM)

Sector group size

(Kbytes/Kwords)

Sector Group

A²¹A20 A19 A18 A17 A16 A15

Sectors

SGA0

SGA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64/32

SA0

64/32

SA1

SGA2

64/32

SA2

SGA3

64/32

SA3

SGA4

256/128

64/32

SA4 to SA7

SA8 to SA11

SA12 to SA15

SA16 to SA19

SA20 to SA23

SA24 to SA27

SA28 to SA31

SA32 to SA35

SA36 to SA39

SA40 to SA43

SA44 to SA47

SA48 to SA51

SA52 to SA55

SA56 to SA59

SA60 to SA63

SA64 to SA67

SA68 to SA71

SA72 to SA75

SA76 to SA79

SA80 to SA83

SA84 to SA87

SA88 to SA91

SA92 to SA95

SA96 to SA99

SA100 to SA103

SA104 to SA107

SA108 to SA111

SA112 to SA115

SA116 to SA119

SA120 to SA123

SA124

SGA5

SGA6

SGA7

SGA8

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

64/32

SA125

64/32

SA126

64/32

SA127

20

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Common Flash Memory Interface Code

Description

A⁰to A6

DQ0 to DQ15

10h

11h

12h

0051h

0052h

0059h

Query-unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

(02h = Fujitsu standard)

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set

(00h = not applicable)

19h

1Ah

0000h

Address for Alternate OEM Extended Table

(00h = not applicable)

V^CCMin (write/erase)

DQ⁷to DQ4: 1 V/bit,

DQ³to DQ0: 100 mV/bit

1Bh

1Ch

0027h

0036h

V^CCMax (write/erase)

DQ⁷to DQ4: 1 V/bit,

DQ³to DQ0: 100 mV/bit

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

0000h

0007h

000Ah

0000h

0001h

0005h

0004h

0000h

0017h

V^PPMin voltage (00h = no Vpp pin)

V^PPMax voltage (00h =no Vpp pin)

Typical timeout per single write 2^Nμs

Typical timeout for Min size buffer write 2^Nμs

Typical timeout per individual sector erase 2^Nms

Typical timeout for full chip erase 2^Nms

Max timeout for write 2^Ntimes typical

Max timeout for buffer write 2^Ntimes typical

Max timeout per individual sector erase 2^Ntimes typical

Max timeout for full chip erase 2^Ntimes typical

Device Size = 2^Nbyte

28h

29h

0002h

0000h

Flash Device Interface description

02h : × 8/ × 16

2Ah

2Bh

0005h

0000h

Max number of byte in multi-byte write = 2^N

2Ch

0002h

Number of Erase Block Regions within device (02h = Boot)

2Dh

2Eh

2Fh

30h

007Fh

0000h

0020h

0000h

Erase Block Region 1 Information

Erase Block Region 2 Information

31h

32h

33h

34h

003Eh

0000h

0001h

(Continued)

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MBM29PL64LM90/10

(Continued)

A⁰to A6

DQ0 to DQ15

Description

35h

36h

37h

38h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

Query-unique ASCII string “PRI”

40h

41h

42h

0050h

0052h

0049h

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock

Required

45h

0008h

Erase Suspend

(02h = To Read & Write)

46h

47h

48h

49h

4Ah

0002h

0004h

0001h

0004h

0000h

Number of sectors in per group

Sector Temporary Unprotection

(01h = Supported)

Sector Protection Algorithm

Dual Operation

(00h = Not Supported)

Burst Mode Type

(00h = Not Supported)

4Bh

4Ch

0000h

0001h

Page Mode Type

(01h = 4-Word Page Supported)

V^ACC(Acceleration) Supply Minimum

DQ⁷to DQ4: 1 V/bit,

DQ³to DQ0: 100 mV/bit

4Dh

4Eh

00B5h

00C5h

V^ACC(Acceleration) Supply Maximum

DQ⁷to DQ4: 1 V/bit,

DQ³to DQ0: 100 mV/bit

Write Protect

(04h = Uniform Sectors Bottom Write Protect)

4Fh

50h

0004h

01h

Program Suspend

(01h = Supported)

22

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

■ FUNCTIONAL DESCRIPTION

Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and

the other via the RESET pin only.

When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ±0.3 V. Under

this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, V^CCactive

current (I^CC2) is required even when CE = "H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ±0.3 V (CE =

“H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,

the device requires t^RHas a wake-up time for output to be valid for read access.

During standby mode, the output is in the high impedance state, regardless of OE input.

Automatic Sleep Mode

Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in

applications such as handy terminal, which requires low power consumption.

To activate this mode, the device automatically switch themselves to low power mode when the device addresses

remain stable after 30 ns from data valid. It is not necessary to control CE, WE, and OE in this mode. The current

consumed is typically 1 μA (CMOS Level).

Since the data are latched during this mode, the data are continuously read out. When the addresses are

changed, the mode is automatically canceled and the device read-out the data for changed addresses.

Autoselect

The Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended

for use by programming equipment for the purpose of automatically matching the device to be programmed with

its corresponding programming algorithm.

To activate this mode, the programming equipment must force V^IDon address pin A9. Two identifier bytes may

then be sequenced from the devices outputs by toggling A⁰. All addresses can be either High or Low except A6,

A³,A2,A1 and A0. See “MBM29PL64LM User Bus Operations (Word Mode : BYTE = VIH)” and “MBM29PL64LM

User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE BUS OPERATION.

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A⁹pin. The command sequence is

illustrated in “MBM29PL64LM Standard Command Definitions” in ■DEVICE BUS OPERATION.Refer to Au-

toselect Command section.

In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at

address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended

Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes

at addresses of 0Eh and 0Fh. Notice that the above applies to Word mode. The addresses and codes differ from

those of Byte mode. Refer to “Sector Group Protection Verify Autoselect Codes” in ■DEVICE BUS OPERATION.

Read Mode

The device has two control functions required to obtain data at the outputs. CE is the power control and used

for a device selection. OE is the output control and used to gate data to the output pins.

Address access time (t^ACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (t^CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the

addresses have been stable for at least t^ACC-tOE time.) When reading out a data without changing addresses after

power-up, input hardware reset or to change CE pin from “H” or “L”.

23

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Page Mode Read

The device is capable of fast read access for random locations within limited address location called Page. The

Page size of the device is 8 bytes / 4 words, within the appropriate Page being selected by the higher address

bits A²¹to A2 and the address bits A1 to A0 in Word mode ( A1 to A-1 in Byte mode) determining the specific word

within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.

The initial page access is equal to the random access (t^ACC) and subsequent Page read access (as long as the

locations specified by the microprocessor fall within that Page) is equivalent to the page address access

time(t^PACC). Here again, CE selects the device and OE is the output control and should be used to gate data to

the output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A²⁰to A2 constant

and changing A¹and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within that Page.

Output Disable

With the OE input at logic high level (VIH), output from the devices are disabled. This may cause the output pins

to be in a high impedance state.

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the device function.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever

starts first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The device features hardware sector group protection. This feature will disable both program and erase opera-

tions in any combination of 38 sector groups of memory.See “Sector Group Address Table (MBM29PL64LM)”

in ■DEVICE BUS OPERATION. The user‘s side can use the sector group protection using programming equip-

ment. The device is shipped with all sector groups that are unprotected.

To activate it, the programming equipment must force V^IDon address pin A9 and control pin OE, CE = VIL and

A⁶= A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, A17, A16, and A15) should be set

to the sector to be protected. “Sector Address Table (MBM29PL64LM)” in ■DEVICE BUS OPERATION defines

the sector address for each of the seventy-one (71) individual sectors, and “Sector Group Address Table

(MBM29PL64LM)” in ■DEVICE BUS OPERATION defines the sector group address for each of the twenty-four

(24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse

and is terminated with the rising edge of the same. Sector group addresses must be held constant during the

WE pulse. See “Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “Sector Group Protection

Algorithm” in ■FLOW CHART for sector group protection timing diagram and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, and A15)

while (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector.

Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order addresses, except

for A⁰, A1, A2, A3, and A6 can be either High or Low. A-1 requires applying to VIL on Byte mode.

Where the higher order addresses(A21, A20, A19, A18, A17, A16, and A15) are the desired sector group address will

produce a logical “1” at DQ⁰for a protected sector group. See “Sector Group Protection Verify Autoselect Codes”

in ■DEVICE BUS OPERATION for Autoselect codes.

24

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the devices in order to

change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID).

During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group

addresses. Once the V^IDis taken away from the RESET pin, all the previously protected sector groups will be

protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in ■TIMING DIAGRAM and

“Temporary Sector Group Unprotection Algorithm” in ■FLOW CHART.

Hardware Reset

The devices may be reset by driving the RESET pin to VIL from VIH. The RESET pin has a pulse requirement

and has to be kept low (V^IL) for at least “tRP” in order to properly reset the internal state machine. Any operation

in the process of being executed will be terminated and the internal state machine will be reset to the read mode

“t^READY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an

additional “t^RH” before it will allow read access. When the RESET pin is low, the devices will be in the standby

mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during

a program or erase operation, the data at that particular location will be corrupted.

Write Protect (WP)

The Write Protection function provides a hardware method of protecting certain first 64K bytes words sectors

without using V^ID. This function is one of two provided by the WP/ACC pin.

If the system asserts V^ILon the WP/ACC pin, the device disables program and erase functions in the first

64K bytes / 32K words sectors independently of whether this sector was protected or unprotected using the

method described in “Sector Group Protection" above.

If the system asserts V^IHon the WP/ACC pin, the device reverts of whether the outermost 8K bytes / 4K words

sectors were last set to be protected to the unprotected status. Sector protection or unprotection for this sector

depends on whether this was last protected or unprotected using the method described in “Sector protection/

unprotection”.

Accelerated Program Operation

Thedevice offersacceleratedprogramoperationwhichenablesprogramminginhighspeed. Ifthesystemasserts

V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program

operation will reduce to about 85%. This function is primarily intended to allow high speed programing, so caution

is needed as the sector group becomes temporarily unprotected.

The system would use a fast program command sequence when programming during acceleration mode. Set

command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device is automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove VACC from the WP/

ACC pin while programming. See “Accelerated Program Timing Diagram” in ■TIMING DIAGRAM.

Enhanced V^CCQFeature

The output voltage generated on the device is determined based on the V^CCQlevel. This feature allows the device

to operate in mixed-voltage environments, driving and receiving signals to and from other devices on the same

bus.

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■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

“MBM29PL64LM Standard Command Definitions” in ■DEVICE BUS OPERATION shows the valid register

command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only

while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h)

commands are valid only while the Program operation is in progress.Moreover Reset commands are functionally

equivalent, resetting the device to the read mode. Please note that commands must be asserted to DQ⁷to DQ0

and DQ15 to DQ8 bits are ignored.

Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read mode, the Reset operation

is initiated by writing the Reset command sequence into the command register. The devices remain enabled for

reads until the command register contents are altered.

The devices will automatically be in the reset state after power-up. In this case, a command sequence is not

required in order to read data.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,

manufacture and device codes must be accessible while the devices reside in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a high voltage. However applying high voltage

onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write

cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be

read from the address, and an actual data of memory cell can be read from the another address.

Following the command write, a read cycle from address 00h returns the manufactures’s code (Fujitsu = 04h).

A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes,

called Extended Device Codes will be required. Therefore the system may continue reading out these Extended

Device Codes at address of 0Eh as well as at 0Fh. Notice that above applies to Word mode. The addresses

and codes differ from those of Byte mode. Refer to “Sector Group Protection Verify Autoselect Codes” in ■DE-

VICE BUS OPERATION.

To terminatetheoperation, itisnecessary to write the Reset command into the register. To execute theAutoselect

command during the operation, Reset command must be written before the Autoselect command.

Programming

The devices are programmed on a word-by-word basis. Programming is a four bus cycle operation. There are

two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses

are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge

of CE or WE, whichever happens first. The rising edge of CEor WE (whichever happens first) starts programming.

Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide

further controls or timings. The device will automatically provide adequate internally generated program pulses

and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit) or

RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.

The programming operation is completed when the data on DQ⁷is equivalent to data written to this bit at which

the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require

that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling

requires the same address which is being programmed.

If hardware reset occurs during the programming operation, the data being written is not guaranteed.

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Programming is allowed in any address sequence and across sector boundaries. Beware that a data “0” cannot

be programmed back to a “1”. Attempting to do so may result in either failure condition or an apparent success

according to the data polling algorithm. But a read from Reset mode will show that the data is still “0”. Only erase

operations can convert “0”s to “1”s.

Note that attempting to program a “1” over a “0” will result in programming failure. This precaution is the same

with Fujitsu standard NOR devices. “Embedded Program^TMAlgorithm” in ■FLOW CHART illustrates the Em-

bedded Program^TMAlgorithm using typical command strings and bus operations.

Program Suspend/Resume

The Program Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during Embedded Program operation imme-

diately suspends the programming. Refer to "Erase Suspend/Resume" for the detail.

When the Program Suspend command is written during a programming process, the device halts the program

operation within 1us and updates the status bits.After the program operation has been suspended, the system

can read data from any address. The data at program-suspended address is not valid. Normal read timing and

command definitions apply.

After the Program Resume command (30h) is written, the device reverts to programming. The system can

determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program

operation. See "Write Operation Status" for more information. When issuing program suspend command in

4 μs after issuing program command, determine the status of program operation by reading status bit at more

4 μs after issuing program resume command.

The system also writes the Autoselect command sequence in the Program Suspend mode. The device allows

reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the

memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend mode, and is

ready for another valid operation. See "Autoselect Command Sequence" for more information.

The system must write the Program Resume command to exit from the Program Suspend mode and continue

the programming operation. Further writes of the Resume command are ignored. Another Program Suspend

command can be written after the device resumes programming. Do not read CFI code after HiddenROM Entry

and Exit in program suspend mode.

Write Buffer Programming Operations

Write Buffer Programming allows the system write to series of 16 words in one programming operation. This

results in faster effective word programming time than the standard programming algorithms. The Write Buffer

Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write

cycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Address

and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming

will occur.

The system then writes the starting address/data combination. This “starting address” must be the same Sector

Address used in third and fourth cycles and its lower addresses of A³to A0 should be 0h. All subsequent address

must be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever happens later

and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE

(whichever happens first) starts programming. Upon executing the Write Buffer Programming Operations com-

mand sequence, the system is not required to provide further controls or timings. The device will automatically

provide adequate internally generated program pulses and verify the programmed cell margin.

DQ⁷(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be mon-

itored to determine the device status during Write Buffer Programming. In addition to these functions, it is also

possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have

been completed by RY/BY. See “Hardware Sequence Flags”.

The Data polling techniques described in “Data Polling Algorithm” in ■FLOW CHART should be used while

monitoring the last address location loaded into the write buffer. In addition, it is not neccessary to specify an

address in Toggle Bit techniques described in “Toggle Bit Algorithm” in ■FLOW CHART. The automatic pro-

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graming operation is completed when the data on DQ7 is equivalent to the data written to this bit at which time

the device returns to the read mode and addresses are no longer latched ( See "Hardware Sequence Flags").

The write-buffer programming operation can be suspended using the standard program suspend/resume com-

mands.

Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command

at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation

and the device will continue busy state.

The Write Buffer Programming Sequence can be ABORTED by doing the following :

• Different Sector Address is asserted.

• Write data other than the “Program Buffer to Flash" command after the specified number of “data load” cycles.

A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See

“MBM29PL64LM Standard Command Definitions” in ■DEVICE BUS OPERATION for details on this command

sequence.)

Chip Erase

Chip erase is a six bus cycle operation. It begins two “unlock” write cycles followed by writing the “set-up”

command, and two “unlock” write cycles followed by the chip erase command which invokes the Embedded

Erase algorithm.

The device does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm the devices automatically programs and verifies the entire memory for an all zero data pattern prior

to electrical erase (Preprogram function). The system is not required to provide any controls or timings during

these operations.

The system can determine the erase operation status by using DQ⁷(Data Polling), DQ6 (Toggle Bit I) and DQ2

(Toggle Bit II) or RY/BY output signal. The chip erase begins on the rising edge of the last CE or WE, whichever

happens first from last command sequence and completes when the data on DQ⁷is “1” (See Write Operation

Status section.) at which time the device returns to read mode.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command.

Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is

followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased.

The time between writes must be less than Erase Time-out time(t^TOW). Otherwise that command will not be

accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to

guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out

of “t^TOW” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector

Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-

out window the timer is reset (monitor DQ³to determine if the sector erase timer window is still open, see section

DQ³, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector.

In that case, restart the erase on those sectors and allow them to complete (refer to the Write Operation Status).

Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 127).

Sector erase does not require the user to program the devices prior to erase. The devices automatically program

all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm.

When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to

provide any controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling), DQ6 (Toggle Bit) or

RY/BY.

The sector erase begins after the “t^TOW” time-out from the rising edge of CE or WE whichever happens first for

the last sector erase command pulse and completes when the data on DQ⁷is “1” (see Write Operation Status

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section), at which the devices return to the read mode. Data polling and Toggle Bit must be performed at an

address within any of the sectors being erased.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read to a

sector not being erased. This command is applicable ONLY during the Sector Erase operation within the time-

out period for sector erase. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results

in immediate termination of the time-out period and suspension of the erase operation.

Writing the "Erase Resume" command (30h) resumes the erase operation.

When the "Erase Suspend" command is written during the Sector Erase operation, the device takes maximum

of “t^SPD” to suspend the erase operation. When the devices enter the erase-suspended mode, the RY/BY output

pin will be at High-Z and the DQ⁷bit will be at logic “1” and DQ6 will stop toggling. The user must use the address

of the erasing sector for reading DQ⁶and DQ7 to determine if the erase operation has been suspended. Further

writes of the Erase Suspend command are ignored.

When the erase operation is suspended, the devices default to the erase-suspend-read mode. Reading data in

this mode is the same as reading from the standard read mode, except that the data must be read from sectors

that have not been erase-suspended. Reading successively from the erase-suspended sector while the device

is in the erase-suspend-read mode will cause DQ²to toggle. See the section on DQ2.

To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the

chip has resumed erasing.

Do not issuing program command after entering erase-suspend-read mode.

Fast Mode Set/Reset

The device has Fast Mode function. It dispenses with the initial two unclock cycles required in the standard

program command sequence by writing Fast Mode command into the command register. In this mode, the

required bus cycle for programming consists of two cycles instead of four bus cycles in standard program

command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any

command other than the Fast program/Fast mode reset command. To exit from this mode, write Fast Mode

Reset command into the command register. (Refer to the “Embedded Program^TMAlgorithm for Fast Mode” in

■FLOW CHART.) The V^CCactive current is required even CE = VIH during Fast Mode.

Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program

Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). See “Embedded

Program^TMAlgorithm for Fast Mode” in ■FLOW CHART.

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Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended

function. This function enables protection of the sector group by forcing V^IDon RESET pin and writes a command

sequence. Unlike conventional procedures, it is not necessary to force V^IDand control timing for control pins.

The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection

requires V^IDon RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)

into the command register. Then the sector group addresses pins (A²¹, A20, A19, A18, A17, A16 and A15) and (A6,

A³, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses

pins is recommended), and write extended sector group protection command (60h). A sector group is typically

protected in 250 μs. To verify programming of the protection circuitry, the sector group addresses pins (A²¹, A20,

A¹⁹, A18, A17, A16 and A15) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h).

Following the command write, a logical “1” at device output DQ⁰will produce for protected sector in the read

operation. If the output data is logical “0”, write the extended sector group protection command (60h) again. To

terminate the operation, set RESET pin to VIH. (Refer to the “Extended Sector Group Protection Timing Diagram”

in ■TIMING DIAGRAM and “Extended Sector Group Protection Algorithm” in ■FLOW CHART.)

Query Command (CFI : Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation

handshake which allows specific vendor-specified software algorithms to be used for entire families of devices.

This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software sup-

port for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. Following the command

write, a read cycle from specific address retrieves device information. Please note that output data of upper byte

(DQ¹⁵to DQ8) is “0”. Refer to the CFI code table. To terminate operation, it is necessary to write the Reset

command sequence into the register. (See “Common Flash Memory Interface Code” in ■DEVICE BUS OPER-

ATION.)

HiddenROM Mode

(1) HiddenROM Region

The HiddenROM (HiddenROM) feature provides a Flash memory region that the system may access through

a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number

(ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any

further modification of that region is impossible. This ensures the security of the ESN once the product is shipped

to the field.

The HiddenROM region is 256 bytes / 128 words in length. After the system writes the HiddenROM Entry

command sequence, it may read the HiddenROM region by using device addresses A⁶to A0 (A21 to A15 are all

“0”). That is, the device sends only program command that would normally be sent to the address to the

HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command

sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device

reverts to sending commands to the address.

If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more

information.

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(2) HiddenROM Entry Command

The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and

to unable the change of the code once set. Programming is allowed in this area until it is protected. However,

once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.

The HiddenROM area is 256 bytes / 128 words. This area is in SA0 . Therefore, write the HiddenROM entry

command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area

appears.

Sectors other than the block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM

area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the Hidden-

ROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/reset

commands during the HiddenROM mode. When you issue the other commands including the suspend resume

capability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each com-

mand.

(3) HiddenROM Program Command

To program the data to the HiddenROM area, write the HiddenROM program command sequence during Hid-

denROM mode. This command is the same as the usual program command, except that it needs to write the

command during HiddenROM mode. Therefore the detection of completion method is the same as in the past,

using the DQ⁷data pooling, DQ6 Toggle bit or RY/BY. You should pay attention to the address to be programmed.

If an address not in the HiddenROM area is selected, the previous data will be deleted.

During the write into the HiddenROM region, the program suspend command issuance is prohibited.

(4) HiddenROM Protect Command

There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command

(60h) , set the sector address in the HiddenROM area and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the

sector group protect command (60h) during the HiddenROM mode. The same command sequence may be used

because it is the same as the extension sector group protect in the past, except that it is in the HiddenROM

mode and does not apply high voltage to the RESET pin. Please refer to above mentioned “Extended Sector

Group Protection” for details of sector group protect setting.

The other method is to apply high voltage (V^ID) to A9 and OE, set the sector address in the HiddenROM area

and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the

protect circuit, apply high voltage (V^ID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address

in the HiddenROM area, and read. When “1” appears on DQ⁰, the protect setting is completed. “0” will appear

on DQ⁰if it is not protected. Apply write pulse again. The same command sequence could be used for the above

method because other than the HiddenROM mode, it is the same as the sector group protect previously men-

tioned.

Take note that other sector groups will be affected if an address other than those for the HiddenROM area is

selected for the sector group address, soplease be careful. Pay close attentionthat once it is protected, protection

CANNOT BE CANCELLED.

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Write Operation Status

Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the device for

current mode operation. When checking Hardware Sequence Flags during program operation, it should be

checked 4 μs after issuing program command. During sector erase, the part provides the status flags automat-

ically to the I/O ports. The information on DQ²is address sensitive. If an address from an erasing sector is

consecutively read, then the DQ²bit will toggle. However DQ2 will not toggle if an address from a non-erasing

sector is consecutively read. This allows the user to determine which sectors are erasing.

Once erase suspend is entered address sensitivity still applies. If the address of a non-erasing sector (one

available for read) is provided, then stored data can be read from the device. If the address of an erasing sector

(one unavailable for read) is applied, the device will output its status bits.

Hardware Sequence Flags

DQ1*³

Status

DQ⁷

0

DQ6

DQ5

0

DQ3

0

DQ2

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspend-Read

Toggle

1

0

1

Toggle*¹N/A

Data

1

Data

1

Data

0

Data

0

Data

Program

Suspend

(Program Suspended Sector)

Program-Suspend-Read

Mode

In

(Non-Program Suspended Sector)

Progress

Erase-Suspend-Read

(Erase Suspended Sector)

Toggle*¹N/A

Erase

Erase-Suspend-Read

Suspend

Data

DQ7

Data

Toggle

Data

0

Data

0

Data

1*²

Data

N/A

(Non-Erase Suspended Sector)

Mode

Erase-Suspend-Program

(Non-Erase Suspended Sector)

Embedded Program Algorithm

DQ⁷

0

Toggle

1

0

1

N/A

Exceeded Embedded Erase Algorithm

N/A

Time

Limits

Erase

Suspend

Mode

Erase-Suspend-Program

(Non-Erase Suspended Sector)

DQ⁷

Toggle

1

0

N/A

BUSY State

DQ7

DQ⁷

N/A

Toggle

0

1

0

N/A

0

1

Write to

Buffer*⁴

Exceeded Timing Limits

ABORT State

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ²bit.

*3 : DQ¹indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations.

*4 : The Data Polling algorithm detailed in “Data Polling Algorithm” in ■FLOW CHART should be used for Write-

Buffer-Programming operations. Note that DQ⁷during Write-Buffer-Programming indicates the data-bar for

DQ⁷data for the LAST LOADED WRITE-BUFFER ADDRESS location.

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DQ⁷

Data Polling

The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce

reverse data last written to DQ⁷. Upon completion of the Embedded Program Algorithm, an attempt to read the

device will produce true data last written to DQ⁷. During the Embedded Erase Algorithm, an attempt to read the

device will produce a “0” at the DQ⁷output. Upon completion of the Embedded Erase Algorithm, an attempt to

read device will produce a “1” at the DQ⁷output. The flowchart for Data Polling (DQ7) is shown in “Data Polling

Algorithm” in ■FLOW CHART.

For programming, the Data Polling is valid after the rising edge of fourth write pulse in the four write pulse

sequence.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequence. DataPolling must be performed at sector addresses of sectors being erased, not protected

sectors. Otherwise, the status may become invalid.

If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1 μs, then

the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing

are protected, Data Polling on DQ7 is active for approximately 100 μs, then the device returns to read mode. If

not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ⁷) may change

asynchronously while the output enable (OE) is asserted low. This means that the device is driving status

information on DQ⁷at one instant of time, and then that byte’s valid data the next. Depending on when the system

samples the DQ⁷output, it may read the status or valid data. Even if the device completes the Embedded

Algorithm operation and DQ⁷has a valid data, the data outputs on DQ6 to DQ0 may still be invalid. The valid data

on DQ⁷to DQ0 will be read on the successive read attempts.

The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-

rithm, Erace Suspendmode or sector erase time-out.

See “Data Polling during Embedded Algorithm Operation Timing Diagram” in ■TIMING DIAGRAM for the Data

Polling timing specifications and diagram.

DQ⁶

Toggle Bit I

The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms

are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data

from the devices will result in DQ⁶toggling between one and zero. Once the Embedded Program or Erase

Algorithm cycle is completed, DQ⁶will stop toggling and valid data will be read on the next successive attempts.

During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1 μs and

then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for

the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 100 μs and

then drop back into read mode, having data kept remained.

Either CE or OE toggling will cause the DQ6 to toggle. See “Toggle Bit l Timing Diagramduring Embedded

Algorithm Operations” in ■TIMING DIAGRAM for the Toggle Bit I timing specifications and diagram.

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DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ⁵will produce a “1”. This is a failure condition indicating that the program or erase cycle was

not successfully completed. Data Polling is the only operating function of the device under this condition. The

CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE

pins will control the output disable functions as described in “MBM29PL64LM User Bus Operations (Word

Mode : BYTE = VIH)” and “MBM29PL64LM User Bus Operations (Byte Mode : BYTE = VIL)” in ■DEVICE BUS

OPERATION.

The DQ⁵failure condition may also appear if a user tries to program a non blank location without pre-erase. In

this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads a valid data on DQ⁷bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1”. Note that this is not a device failure condition since the device was incorrectly used. If this

occurs, reset the device with command sequence.

DQ³

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ³will

remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase

command sequence.

If Data Polling or the Toggle Bit I indicates a valid erase command has been written, DQ3 may be used to

determine whether the sector erase timer window is still open. If DQ³is “1” the internally controlled erase cycle

has begun. If DQ³is “0”, the device will accept additional sector erase commands. To insure the command has

been accepted, the system software should check the status of DQ³prior to and following each subsequent

SectorErasecommand. IfDQ³were highonthe second statuscheck, thecommandmaynothave been accepted.

See “Hardware Sequence Flags”.

DQ²

Toggle Bit II

This Toggle bit II, along with DQ⁶, can be used to determine whether the devices are in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ²to toggle during the Embedded Erase Algorithm. If the

devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ²to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector will indicate a logic “1” at the DQ²bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ⁷, is summarized

as follows:

For example, DQ²and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ²toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “DQ2 vs. DQ6” in ■TIMING DIA-

GRAM.

Furthermore, DQ²can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles

if this bit is read from an erasing sector.

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Reading Toggle Bits DQ⁶/ DQ2

Whenever the system initially begins reading Toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a Toggle bit is toggling. Typically a system would note and store the value of the Toggle

bit after the first read. After the second read, the system would compare the new value of the Toggle bit with the

first. If the Toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ⁷to DQ0 on the following read cycle.

However, if, after the initial two read cycles, the system determines that the Toggle bit is still toggling, the system

also should note whether the value of DQ⁵is high (see the section on DQ5) . If it is, the system should then

determine again whether the Toggle bit is toggling, since the Toggle bit may have stopped toggling just as DQ⁵

went high. If the Toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the Toggle bit is toggling and DQ⁵has not

gone high. The system may continue to monitor the Toggle bit and DQ⁵through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status

of the operation. (Refer to “Toggle Bit Algorithm” in ■FLOW CHART.)

Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

Toggle ^*1

Erase-Suspend-Read

(Erase-Suspended Sector)

1

Toggle ^*1

1 ^*2

Erase-Suspend-Program

DQ7

Toggle

*1 : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2 : Reading from the non-erase suspend sector address will indicate logic “1” at the DQ²bit.

DQ¹

Write-to-Buffer Abort

DQ¹indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1".

The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array

data. See "Write Buffer Programming Operations" section for more details.

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin to indicate to the host system that the Embedded Algorithms

are either in progress or has been completed. If the output is low, the device is busy with either a program or

erase operation. If the output is high, the device is ready to accept any read/write or erase operation. If the

device is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-

up resister to V^CC.

During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a

busy condition during the RESET pulse. See “RY/BY Timing Diagram during Program/Erase Operation Timing

Diagram” and “RESET Timing Diagram ( During Embedded Algorithms )” in ■TIMING DIAGRAM for a detailed

timing diagram. The RY/BY pin is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

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Word/Byte Configuration

BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the

device operates in the word (16-bit) mode. Data is read and programmed at DQ¹⁵to DQ0. When this pin is driven

low, the device operates in byte (8-bit) mode. In this mode, DQ¹⁵/A-1 pin becomes the lowest address bit, and

DQ¹⁴to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence

commands are written at DQ⁷to DQ0 and DQ15 to DQ8 bits are ignored.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power up the device automatically reset the internal

state machine in Read mode. Also, with its control register architecture, alteration of memory contents only

occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting form V^CCpower-up

and power-down transitions or system noise.

(1) Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than V^LKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.

Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V^CClevel

is greater than V^LKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent

unintentional writes when V^CCis above VLKO.

If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.

(2) Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.

(3) Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must

be a logical zero while OE is a logical one.

(4) Power-up Write Inhibit

Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

(5) Sector Protection

Device user is able to protect each sector group individually to store and protect data. Protection circuit voids

both write and erase commands that are addressed to protected sectors.

Any commands to write or erase addressed to protected sector are ignored .

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■ ABSOLUTE MAXIMUM RATINGS

Rating

Unit

Parameter

Symbol

Min

–55

–20

Max

+125

+85

Storage Temperature

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All Pins Except

A⁹, OE, and RESET *^1,*²

VIN, VOUT

–0.5

VCC +0.5

V

Power Supply Voltage *¹

A⁹, OE, and RESET *^1,*³

WP/ACC *^1,*³

VCC

VIN

–0.5

+4.0

+12.5

V

VACC

*1 : Voltage is defined on the basis of VSS = GND = 0 V.

*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot

V^SSto –0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage

transitions, input or I/O pins may overshoot to V^CC+2.0 V for periods of up to 20 ns

*3 : Minimum DC input voltage is –0.5 V. During voltage transitions, these pins may undershoot V^SSto –0.2 V for

periods of up to 20 ns.Voltage difference between input and supply voltage ( V^IN–VCC) dose not exceed to

+9.0 V. Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of up to 20 ns .

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES*¹

Value

Parameter

Symbol

Unit

Min

–20

+3.0

Max

+70

+85

+3.6

90

10

Ambient Temperature

V^CCSupply Voltage *^2,*³

T^A

°C

VCC

V

V^CCQSupply Voltage *^2,*³*⁴

VCCQ

VCC

*1 : Operating ranges define those limits between which the functionality of the device is guaranteed.

*2 : Voltage is defined on the basis of V^SS= GND = 0 V.

*3 : V^CCand VCCQ supply voltage must be on the same level.

*4 : V^CCQsupply voltage is only for MBM29PL64LMxxPCN : 56 pin TSOP

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

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■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.6 V

–0.5 V

–2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

VCC +2.0 V

VCC +0.5 V

0.7 × VCC

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+12.5 V

VCC +0.5 V

20 ns

Note: This waveform is applied for A9, OE, RESET, and ACC.

Maximum Overshoot Waveform 2

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■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Unit

Parameter

Symbol

Conditions

Min

–2.0

–1.0

Typ

—

Max

+2.0

+1.0

WP/ACC pin

Others

VIN = VSS to VCC,

V^CC= VCC Max

Input Leakage Current

Output Leakage Current

I^LI

µA

—

I^LO

I^LIT

VOUT = VSS to VCC, VCC = VCC Max

—

µA

A⁹, OE, RESET Inputs Leakage

Current

VCC = VCC Max,

A⁹, OE, RESET = 12.5 V

—

35

Word

Byte

Word

Byte

—

15

35

25

50

CE = VIL, OE = VIH,

f = 5 MHz

V^CCActive Current

(Read ) *^1,*²

ICC1

mA

CE = VIL, OE = VIH,

f = 10 MHz

V^CCActive Current

CE = VIL, OE = VIH, tPRC = 25 ns,

4-Word

ICC2

ICC3

—

10

50

20

60

mA

(Intra-Page Read ) *²

V^CCActive Current

CE = VIL, OE = VIH

(Program / Erase) *^2,*³

CE = VCC ±0.3 V,

RESET = VCC ±0.3 V,

OE = VIH, WP/ACC = VCC ±0.3 V

V^CCStandby Current *²

V^CCReset Current *²

ICC4

ICC5

—

1

5

µA

RESET = VCC ±0.3 V,

WP/ACC = VCC ±0.3 V

CE = VSS ±0.3 V,

RESET = VCC ±0.3 V,

V^IN= VCC ±0.3 V or Vss ±0.3 V,

WP/ACC = VCC ±0.3 V

V^CCAutomatic Sleep Current *⁴

ICC6

ICC7

I^ACC

—

1

5

µA

mA

V^CCActive Current

CE = VIL, OE = VIH

—

50

—

60

45

(Erase-Suspend-Program) *²

CE = VIL, OE = VIH, WP/ACC pin

Vcc = Vcc Max,

ACC Accelerated Program

Current

WP/ACC =VACC

Max

Vcc Pin

—

60

Input Low Level

Input High Level

V^IL

V^IH

—

–0.5

—

0.6

V

0.7×VCC

VCC + 0.3

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration

V^ACC

VCC = 3.0 V to 3.6 V

11.5

12.0

12.5

V

Voltage for Autoselect, and

Temporary Sector Unprotected

V^ID

VCC = 3.0 V to 3.6 V

11.5

12.0

12.5

V

Output Low Voltage Level

Output High Voltage Level

Low V^CCLock-Out Voltage

V^OL

V^OH

VLKO

IOL = 4.0 mA, VCC = VCC Min

IOH = –2.0 mA, VCC = VCC Min

—

0.85×VCC

2.3

—

0.45

—

V

2.5

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*1 : The l^CCcurrent listed includes both the DC operating current and the frequency dependent component.

*2 : Maximum I^CCvalues are tested with VCC = VCC Max, and VCCQ = VCCQ Max.

V^CCQis only for MBM29PL64LMxxPCN : 56 pin TSOP.

*3 : I^CCactive while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.

*4 : Automatic sleep mode enables the low power mode when address remain stable for t^ACC+ 30 ns.

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2. AC Characteristics

• Read Only Operations Characteristics

Value*

Symbols

Parameter

Condition

90

10

Unit

JEDEC Standard

Min Max Min Max

Read Cycle Time

t^AVAV

tRC

—

90

⎯

100

⎯

ns

CE = VIL,

OE = VIL

Address to Output Delay

t^AVQV

tACC

⎯

90

⎯

100

Chip Enable to Output Delay

Page Read Cycle Time

t^ELQV

—

tCE

OE = VIL

—

⎯

90

⎯

100

ns

t^PRC

25

⎯

30

⎯

CE = VIL,

OE = VIL

Page Address to Output Delay

—

t^PACC

⎯

25

⎯

30

ns

Output Enable to Output Delay

Chip Enable to Output High-Z

t^GLQV

t^EHQZ

tOE

tDF

—

⎯

0

25

⎯

25

⎯

0

30

⎯

30

ns

Read

Output Enable

Hold Time

—

t^OEH

Toggle and Data Polling

10

⎯

10

⎯

Output Enable to Output High-Z

t^GHQZ

t^AXQX

—

tDF

tOH

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

—

0

⎯

0

⎯

ns

µs

RESET Pin Low to Read Mode

tREADY

⎯

20

⎯

20

* : Test Conditions :

Output Load

: 1 TTL gate and 30 pF

Input rise and fall times : 5 ns

Input pulse levels

: 0.0 V or V^CC

Timing measurement reference level

Input

: V^CC/ 2

Output : V^CC/ 2

3.3 V

Diode = 1N3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diode = 1N3064

or Equivalent

Test Conditions

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• Write (Erase/Program) Operations

Parameter

Value

Symbol

90

10

Unit

JEDEC Standard Min Typ Max Min Typ Max

Write Cycle Time

t^AVAV

t^AVWL

tWC

tAS

90

0

⎯

100

0

⎯

ns

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

—

t^WLAX

—

t^ASO

tAH

15

45

0

⎯

15

45

0

⎯

ns

Address Hold Time

Address Hold Time from CE or OE High

During Toggle Bit Polling

t^AHT

Data Setup Time

t^DVWH

t^WHDX

—

tDS

tDH

35

0

⎯

35

0

⎯

ns

Data Hold Time

Output Enable Setup Time

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

t^OES

tCEPH

tOEPH

0

—

20

—

Read Recover Time Before Write

(OE High to WE Low)

t^GHWL

t^GHEL

tGHWL

tGHEL

0

⎯

0

⎯

ns

Read Recover Time Before Write

(OE High to CE Low)

⎯

CE Setup Time

tELWL

tWLEL

tWHEH

tEHWH

tELEH

tCS

tWS

tCH

0

⎯

0

ns

WE Setup Time

CE Hold Time

0

⎯

WE Hold Time

tWH

tCP

0

CE Pulse Width

Write Pulse Width

CE Pulse Width High

Write Pulse Width High

Effective Page

35

25

30

35

25

30

t^WLWH

tEHEL

t^WHWL

tWP

tCPH

tWPH

Programming Time

(Write Buffer Programming)

Per Word

Word

⎯

23.5

⎯

23.5

⎯

µs

t^WHWH1

tWHWH1

Programming Time

⎯

100

1.0

⎯

90

⎯

100

1.0

⎯

90

⎯

µs

s

Sector Erase Operation *¹

tWHWH2

—

tWHWH2

tVCS

V^CCSetup Time

50

0

50

0

µs

ns

µs

Recovery Time From RY/BY

—

tPB

⎯

Erase/Program Valid to RY/BY Delay

Rise Time to V^ID*²

Rise Time to V^ACC*³

—

tBUSY

tVIDR

tVACCR

tVLHT

⎯

—

500

4

⎯

500

4

⎯

—

⎯

Voltage Transition Time *²

—

⎯

(Continued)

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(Continued)

Value

Symbol

Parameter

90

JEDEC Standard Min Typ Max Min Typ Max

10

Unit

Write Pulse Width *²

—

tWPP

tOESP

tCSP

tRP

100

4

⎯

100

4

⎯

µs

ns

OE Setup Time to WE Active *²

CE Setup Time to WE Active *²

RESET Pulse Width

4

500

100

500

100

RESET High Time Before Read

tRH

Delay Time from Embedded Output

Enable

—

t^EOE

⎯

90

⎯

100

ns

Erase Time-out Time

—

t^TOW

t^SPD

50

⎯

50

⎯

µs

Erase Suspend Transition Time

⎯

20

⎯

20

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Group Protection operation.

*3 : This timing is for Accelerated Program operation.

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■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Remarks

Min

—

Typ

1

Max

15

Excludes programming time prior to

erasure

Sector Erase Time

Programming Time

s

—

100

3000

µs

Effective Page Programming

Time

—

23.5

—

µs

Excludes system-level overhead

(Write Buffer Programming)

Chip Programming Time

—

600

6

s

Absolute Maximum

Programming Time (16 words)

Non programming within the same

page

ms

Erase/Program Cycle

100,000

—

cycle

—

■ TSOP (1) PIN CAPACITANCE

Value

Unit

Parameter

Symbol

Test Setup

Typ

8

Max

Input Capacitance

C^IN

C^OUT

C^IN2

VIN = 0

10

pF

Output Capacitance

Control Pin Capacitance

VOUT = 0

VIN = 0

8.5

8

12

10

Reset pin and WP/ACC Pin

Capacitance

C^IN3

VIN = 0

20

25

pF

Notes : • Test conditions TA = +25°C, f = 1.0 MHz

• DQ¹⁵/A-1 pin capacitance is stipulated by output capacitance.

■ FBGA PIN CAPACITANCE

Value

Parameter

Input Capacitance

Symbol

Test Setup

Unit

Typ

8

Max

10

C^IN

C^OUT

C^IN2

VIN = 0

pF

Output Capacitance

VOUT = 0

VIN = 0

8.5

8

12

Control Pin Capacitance

10

Reset pin and WP/ACC Pin

Capacitance

C^IN3

VIN = 0

15

20

pF

Notes : • Test conditions TA = +25°C, f = 1.0 MHz

• DQ¹⁵/A-1 pin capacitance is stipulated by output capacitance.

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■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will Be

Changing

from H to L

May

Change

from L to H

Will Be

Changing

from L to H

“H” or “L”

Any Change

Permitted

Changing

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

“Off” State

t

RC

Address

Address Stable

tACC

CE

OE

t

OE

t

DF

t

OEH

WE

t

CE

t

OH

High-Z

Data

Output Valid

Read Operation Timing Diagram

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A21 to A2

Address Valid

A1 to A0

(A-1)

Aa

Ab

Ac

t^RC

tPRC

tACC

CE

OE

tCE

tOEH

tOE

tDF

tPACC

tOH

tPACC

tOH

WE

tOH

High-Z

Data

Da

Db

Dc

Page Read Operation Timing Diagram

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Data

tOH

High-Z

Output Valid

Hardware Reset/Read Operation Timing Diagram

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3rd Bus Cycle

Data Polling

555h

PA

Address

CE

tWC

tRC

tAS

tAH

tCH

tCS

tCE

OE

tOE

tWP

tWPH

tGHWL

tWHWH1

WE

tOH

tDF

tDS

tDH

PD

DOUT

A0h

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

Alternate WE Controlled Program Operation Timing Diagram

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3rd Bus Cycle

Data Polling

Address

WE

PA

555h

PA

tWC

tAS

tAH

tWS

tWH

OE

CE

tGHEL

tCP

tCPH

tWHWH1

tDS

tDH

A0h

PD

DQ 7

D ^OUT

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ⁷is the output of the complement of the data written to the device.

• D^OUTis the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

Alternate CE Controlled Program Operation Timing Diagram

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555h

2AAh

555h

2AAh

SA*

Address

CE

t

WC

t

AS

t

AH

t

CS

t

CH

OE

t

WP

tWPH

t

GHWL

t

TOW

WE

DS

tDH

10h for Chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

t

BUSY

RY/BY

t

VCS

V

CC

* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.

Chip/Sector Erase Operation Timing Diagram

49

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

XXXh

tWC

Address

CE

tCS

tCH

tWP

tDS

WE

tSPD

B0h

Data

RY/BY

Erase Suspend Operation Timing Diagram

50

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

VA

Address

CE

tCH

tDF

tOE

OE

tOEH

WE

4 μs

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ⁶to DQ0 =

Output Flag

DQ⁶to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tBUSY

tEOE

* : DQ7 = Valid Data (The device has completed the Embedded operation.)

Note : When checking Hardware Sequence Flags program operations, it should be checked 4 μs

after issuing program command.

Data Polling during Embedded Algorithm Operation Timing Diagram

51

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Address

CE

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

4 μs

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

RY/BY

Data

Toggling

tBUSY

* : DQ6 stops toggling (The device has completed the Embedded operation).

Note : When checking Hardware Sequence Flags program operations, it should be checked 4 μs

after issuing program command.

Toggle Bit l Timing Diagram during Embedded Algorithm Operations

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

WE

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase Suspend

Read

Erase

Complete

DQ⁶

DQ2*

Toggle

DQ and DQ

with OE or CE

2

6

* : DQ2 is read from the erase-suspended sector.

DQ2 vs. DQ6

52

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CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

CE, OE

RESET

tRH

tRP

tREADY

RESET Timing Diagram (Not during Embedded Algorithms)

53

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

WE

RESET

tRP

tRB

RY/BY

tREADY

RESET Timing Diagram (During Embedded Algorithms)

54

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

A

21, A19, A18

17, A16, A15

,

SGAX

SGAY

A

6, A

3, A

2, A

0

A

1

V

ID

IH

V

A

9

tVLHT

V

ID

IH

V

OE

WE

CE

tVLHT

tWPP

tOESP

tCSP

Data

01h

tVCS

tOE

VCC

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

Sector Group Protection Timing Diagram

55

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MBM29PL64LM90/10

tVIDR

tVCS

VCC

tVLHT

VID

VSS, VIL or VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Temporary Sector Group Unprotection Timing Diagram

56

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MBM29PL64LM90/10

VCC

tVCS

RESET

Add

tVLHT

tVIDR

SGAX

SGAY

A6, A3, A2, A0

A1

CE

OE

TIME-OUT

WE

Data

60h

40h

01h

60h

t

OE

SGAX: Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 μs (Min)

Extended Sector Group Protection Timing Diagram

57

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MBM29PL64LM90/10

V

CC

t

VACCR

t

VCS

t

VLHT

V

ACC

CE

WE

t

VLHT

t

VLHT

Program Command Sequence

Acceleration period

Accelerated Program Timing Diagram

58

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■ FLOW CHART

EMBEDDED ALGORITHMS

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in progress

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Note : The sequence is applied for Word ( ×16 ) mode.

The addresses differ from Byte ( × 8 ) mode.

Embedded Program^TMAlgorithm

59

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EMBEDDED ALGORITHMS

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Note : The sequence is applied for Word ( ×16 ) mode.

The addresses differ from Byte ( × 8 ) mode.

Embedded Erase^TMAlgorithm

60

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Start

Wait 4 μs

after issuing

Program Command

Read Byte

(DQ 7 to DQ 0)

Addr. = VA

VA = Valid address for programming

= Any of the sector addresses within

the sector being erased during

sector erase or multiple sector

erases operation

Yes

DQ 7 = Data?

No

= Any of the sector addresses within

the sector not being protected

during chip erase operation

No

DQ 5 = 1?

Yes

Read Byte

(DQ ⁷to DQ 0)

Addr. = VA

Yes

DQ 7 = Data?

*

No

Fail

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Data Polling Algorithm

61

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Start

Wait 4 μs

after issuing

Program Command

*1

Read DQ

Addr. = "H" or "L"

7 to DQ0

Read DQ7 to DQ0

Addr. = "H" or "L"

No

DQ6

= Toggle

?

Yes

No

DQ5

= 1?

Yes

*1, *2

Read DQ

Addr. = "H" or "L"

7 to DQ0

Read DQ7 to DQ0

Addr. = "H" or "L"

No

DQ6

= Toggle

?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read Toggle bit twice to determine whether it is toggling.

*2 : Recheck Toggle bit because it may stop toggling as DQ⁵changes to “1”.

Toggle Bit Algorithm

62

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Start

Setup Sector Group Addr.

(A21, A20, A19, A18,

A¹⁷, A16, A15)

PLSCNT = 1

OE = V^ID, A9 = VID

CE = VIL, RESET = VIH

A6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 100 μs

WE = V^IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SGA, A¹= VIH

A6 = A3 = A2 = A0 = VIL

(

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove V^IDfrom A9

Write Reset Command

Protect Another Sector

Group?

No

Remove V^IDfrom A9

Write Reset Command

Device Failed

Sector Group Protection

Completed

* : A-1 is VIL in Byte ( × 8 ) mode.

Sector Group Protection Algorithm

63

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1 : All protected sector groups are unprotected.

*2 : All previously protected sector groups are protected.

Temporary Sector Group Unprotection Algorithm

64

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Start

RESET = VID

Wait to 4 μs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group

Protection Write XXXh/60h

PLSCNT = 1

To Protect Sector Group

Write 60h to Sector Address

(A6 = A3 = A2 = A0 =VIL, A1 = VIH)

Time Out 250 μs

Increment PLSCNT

Setup Next Sector Group

Address

To Verify Sector Group Protection

Write 40h to Sector Address

(A⁶= A3 = A2 = A0 =VIL, A1 = VIH)

Read from Sector Group

Address

(A6 = A3 = A2 = A0 =VIL, A1 = VIH

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from RESET

Write Reset Command

Protection Other Sector

Group ?

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group Protection

Completed

Extended Sector Group Protection Algorithm

65

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

FAST MODE ALGORITHM

Start

555h/AAh

Set Fast Mode

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling

No

In Fast Program

Verify Data?

Yes

No

Last Address

?

Increment Address

Yes

Programming Completed

XXXh/90h

XXXh/F0h

Reset Fast Mode

Notes : • The sequence is applied for Word ( ×16 ) mode.

• The addresses differ from Byte ( × 8 ) mode.

Embedded Program^TMAlgorithm for Fast Mode

66

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

■ ORDERING INFORMATION

Part No.

Package

Access Time (ns)

Remarks

MBM29PL64LM90TN

MBM29PL64LM10TN

MBM29PL64LM90PCN

MBM29PL64LM10PCN

48-pin, plastic TSOP (1)

(FPT-48P-M19)

90 ns

100 ns

90 ns

(Normal Bend)

56-pin, plastic TSOP (1)

(FPT-56P-M01)

100 ns

(Normal Bend)

MBM29PL64LM90PBT

MBM29PL64LM10PBT

90 ns

80-ball, plastic FBGA

(BGA-80P-M01)

100 ns

MBM29PL64LM

90

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP(1)) Standard Pinout

PCN = 56-Pin Thin Small Outline Package

(TSOP(1)) Standard Pinout

PBT = 80-Ball Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

90 = 90ns access time

10 = 100ns access time

DEVICE NUMBER/DESCRIPTION

64 Mega-bit (8M × 8/4M × 16) MirrorFlash with Page Mode,

Boot Sector

3.0 V-only Read, Program, and Erase

67

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

■ PACKAGE DIMENSIONS

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP(1)

(FPT-48P-M19)

Resin protrusion and gate protrusion are +0.15(.006)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8˚

0.60 0.15

(.024 .006)

24

25

*

20.00 0.20

(.787 .008)

12.00 0.20

(.472 .008)

*18.40 0.20

(.724 .008)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting

height)

0.10 0.05

(.004 .002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ⁺^–0⁰^.^.⁰⁰⁸³

0.22 0.05

(.009 .002)

M

0.10(.004)

.007 –⁺.^.0⁰0⁰3¹

C

2003 FUJITSU LIMITED F48029S-c-6-7

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

68

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Note 1) *1 : Resn protrusion. (Each side : +0.15 (.006) Max).

Note 2) *2 : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

56-pin plastic TSOP(1)

(FPT-56P-M01)

0.10 0.05

(.004 .002)

(Stand off)

LEAD No.

1

56

INDEX

0.22 0.05

(.009 .002)

M

0.10(.004)

¹14.00 0.10

(.551 .004)

*

0.50(.020)

28

29

Details of "A" part

1.10 –⁺0⁰.^.0¹5⁰

20.00 0.20(.787 .008)

²18.40 0.10(.724 .004)

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

(Mounting height)

0˚~8˚

*

0.17 0.03

.007 .001

0.60 0.15

(.024 .006)

0.25(.010)

"A"

0.08(.003)

C

2002 FUJITSU LIMITED F56001S-c-4-5

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

69

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

(Continued)

80-ball plastic FBGA

(BGA-80P-M01)

11.00 0.10(.433 .004)

1.08 –⁺0⁰.^.1¹3²

.043 –⁺.^.0⁰0⁰5⁵

(Mounting height)

(Stand off)

B

0.38 0.10

(.015 .004)

0.40(.016)

REF

0.80(.031)

REF

8

7

6

5

4

3

2

1

A

7.00 0.10

(.276 .004)

0.10(.004)

S

(INDEX AREA)

M

L K J H G F E D C B A

S

INDEX AREA

80-ø0.45 0.05

M

0.08(.003)

S A B

(80-ø.018 .002)

C

2003 FUJITSU LIMITED B80001S-c-1-1

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

70

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

Revision History

Revision DS05-20902-2E（July 31, 2007）

The following comment is added.

This product has been retired and is not recommended for new designs. Availability of this

document is retained for reference and historical purposes only.

71

Retired ProductꢀDS05-20902-2E_July 31, 2007

MBM29PL64LM90/10

FUJITSU LIMITED

For further information please contact:

Japan

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

FUJITSU LIMITED

Marketing Division

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94088-3470, U.S.A.

Tel: +1-408-737-5600

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fme.fujitsu.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Tel: +65-6281-0770

Fax: +65-6281-0220

http://www.fmal.fujitsu.com/

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

http://www.fmk.fujitsu.com/

F0311

Retired ProductꢀDS05-20902-2E_July 31, 2007


型号：	MBM29PL64LM10PCN-E1
厂家：	SPANSION
描述：	Flash, 4MX16, 100ns, PDSO56, PLASTIC, TSOP1-56 光电二极管
文件：	总72页 (文件大小：489K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29PL64LM10PCN-E1 [SPANSION]

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