S29CD016J0JFAM020 [SPANSION]
Flash, 512KX32, 54ns, PBGA80, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80;
| 型号： | S29CD016J0JFAM020 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 512KX32, 54ns, PBGA80, 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件： | 总81页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29CD-J and S29CL-J Flash Family
S29CD032J, S29CD016J, S29CL032J, S29CL016J
32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-Only
Simultaneous Read/Write, Dual Boot, Burst Mode
Flash Memory with VersatileI/O™
S29CD-J and S29CL-J Flash Family Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29CD-J_CL-J_00
Revision B
Amendment 7
Issue Date October 11, 2012
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
S29CD-J and S29CL-J Flash Family
S29CD032J, S29CD016J, S29CL032J, S29CL016J
32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-Only
Simultaneous Read/Write, Dual Boot, Burst Mode
Flash Memory with VersatileI/O™
Data Sheet
General Description
The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process
technology. These burst-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks, using separate data and address pins. These products
can operate up to 75 MHz (32 Mb) or 66 MHz (16 Mb), and use a single VCC of 2.5V to 2.75V (S29CD-J) or
3.0V to 3.6V (S29CL-J) that make them ideal for today’s demanding automotive applications.
Distinctive Characteristics
Single 2.6V (S29CD-J) or 3.3V (S29CL-J) for read/program/
Supports Common Flash Interface (CFI)
Extended Temperature range
erase
110 nm Floating Gate Technology
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Persistent and Password methods of Advanced Sector
Protection
Unlock Bypass program command to reduce programming
time
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
ACC input pin to reduce factory programming time
Data Polling bits indicate program and erase operation
– CD016J and CL016J: Eight 2k Double word, Thirty 16k Double
word, and Eight 2k Double Word sectors
completion
– CD032J and CL032J: Eight 2k Double word, Sixty-two 16k Double
Word, and Eight 2k Double Word sectors
Hardware (WP#) protection of two outermost sectors in the
large bank
VersatileI/O™ control (1.65V to 3.6V)
Ready/Busy (RY/BY#) output indicates data available to
Programmable Burst Interface
system
– Linear for 2, 4, and 8 double word burst with wrap around
Suspend and Resume commands for Program and Erase
Operation
Secured Silicon Sector that can be either factory or customer
locked
Offered Packages
20 year data retention (typical)
– 80-pin PQFP
– 80-ball Fortified BGA (13 x 11 mm and 11 x 9mm versions)
– Pb-free package option available
– Known Good Die
Cycling Endurance: 1 million write cycles per sector (typical)
Command set compatible with JEDEC (JC42.4) standard
Performance Characteristics
Read Access Times
Current Consumption (Max values)
75
Continuous Burst Read @ 75 MHz
90 mA
50 mA
50 mA
60 µA
Speed Option (MHz)
66
56
40
(32 Mb only)
Program
Max Asynch. Access Time, ns (t
)
54
8
54
8
54
8
54
8
ACC
Erase
Max Synch. Burst Access, ns (t
)
BACC
Standby Mode
Min Initial Clock Delay (clock cycles)
Max CE# Access Time, ns (t
5
5
5
4
)
54
20
54
20
54
20
54
20
CE
Typical Program and Erase Times
Max OE# Access time, ns (t
)
OE
Double Word Programming
Sector Erase
18 µs
1.0 s
Notice for the 32Mb S29CD-J and S29CL-J devices only:
Please refer to the application note “Recommended Mode of Operation for Spansion® 110 nm S29CD032J/S29CL032J Flash
Memory” publication number S29CD-CL032J_Recommend_AN for programming best practices.
Publication Number S29CD-J_CL-J_00
Revision B
Amendment 7
Issue Date October 11, 2012
D a t a S h e e t
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.
3.
4.
5.
Input/Output Descriptions and Logic Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram of Simultaneous Read/Write Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
5.2
5.3
5.4
5.5
5.6
80-Pin PQFP Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions . . . . . . . . . . . . . . . . . . 14
80-Ball Fortified BGA Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions. . . . . . . . . . . . 16
LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm) Physical Dimensions . . . . . . . . . . . . 17
6.
Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
6.2
6.3
6.4
Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specification Bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Hardware and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.
8.
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Synchronous (Burst) Read Mode and Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . 26
Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VersatileI/O (VIO) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
9.2
9.3
9.4
9.5
9.6
Advanced Sector Protection Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dynamic Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10. Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1 Secured Silicon Sector Protection Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.2 Secured Silicon Sector Entry and Exit Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11. Electronic Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12. Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
14. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
15. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
15.1 Zero Power Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
16. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
17. Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
17.1 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
18. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
18.1
VCC and VIO Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
18.2 Asynchronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
18.3 Synchronous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
18.4 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
18.5 Write Protect (WP#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
18.6 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
18.7 Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
18.8 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
18.9 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
19. Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
19.1 Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
20. Appendix 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
20.1 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
21. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
5
D a t a S h e e t
Figures
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 9.1
Figure 9.2
Figure 9.3
Asynchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Synchronous/Asynchronous State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation . . . . 28
Initial Burst Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Advanced Sector Protection/Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PPB Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PPB Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15.1
I
CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) . . . . . . . . . . . . . . . . 55
Figure 15.2 Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 17.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18.1
VCC and VIO Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18.2 Conventional Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 18.3 Asynchronous Command Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18.4 Burst Mode Read (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18.5 Synchronous Command Write/Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18.6 RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 18.7 WP# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 18.8 Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 18.9 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 18.10 Back-to-back Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 18.11 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 18.12 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 18.15 Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 18.16 Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Tables
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 8.8
Table 8.9
Table 8.10
Table 9.1
Table 10.1
Table 13.1
Table 14.1
Table 15.1
Table 17.1
Table 17.2
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 19.1
Table 19.2
Table 19.3
Table 19.4
Table 20.1
Table 20.2
S29CD016J/CL016J (Top Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . .20
S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . .21
S29CD032J/CL032J (Top Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . .22
S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map . . . . . . . . . . . . . . . . .23
Device Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
32-Bit Linear and Burst Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Valid Configuration Register Bit Definition for IND/WAIT# . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Burst Initial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Configuration Register After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage Method) . . . . . . . . . .31
DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Reset Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sector Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DC Characteristic, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
V
CC and VIO Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Asynchronous Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Burst Mode for 32 Mb and 16 Mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Memory Array Command Definitions (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Sector Protection Command Definitions (x32 Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
7
D a t a S h e e t
1. Ordering Information
The order number (Valid Combination) is formed by the following:
S29CD032J
S29CL032J
0
J
F
A
I
0
0
0
Packing Type
0
=
Tray, FBGA: 180 per tray, min. 10 trays per box
Tray, PQFP: 66 per tray, min. 10 trays per box
2
3
=
=
7” Tape and Reel, FBGA: 400 per reel
13” Tape and Reel, FBGA: 1600 per reel
13” Tape and Reel, PQFP: 500 per reel
Boot Sector Option (16th Character)
0
1
2
3
=
=
=
=
Top Boot with Simultaneous Operation
Bottom Boot with Simultaneous Operation
Top Boot without Simultaneous Operation
Bottom Boot without Simultaneous Operation
Autoselect ID Option (15th Character)
0
1
0
0
0
=
=
=
=
=
7E, 08, 01/00 Autoselect ID
7E, 36, 01/00 Autoselect ID
7E, 46, 01/00 Autoselect ID
7E, 09, 01/00 Autoselect ID
7E, 49, 01/00 Autoselect ID
S29CD016J only
S29CL016J only
S29CD032J only
S29CL032J only
Temperature Range
I
M
=
=
Industrial (–40°C to +85°C)
Extended (–40°C to +125°C)
Material Set
A
F
=
=
Standard
Pb-free Option
Package Type
Q
F
B
=
=
=
Plastic Quad Flat Package (PQFP)
Fortified Ball Grid Array, 1.0 mm pitch package, 13 x 11 mm package
Fortified Ball Grid Array, 1.0 mm pitch package, 11 x 9 mm package
Clock Frequency (11th Character)
J
=
=
=
=
40 MHz
56 MHz
66 MHz
75 MHz
M
P
R
Initial Burst Access Delay (10th Character)
0
1
=
=
5-1-1-1, 6-1-1-1, and above
4-1-1-1 (40 MHz only)
Device Number/Description
S29CD032J/S29CD016J (2.5 volt-only), S29CL032J/S29CL016J (3.3 volt-only)
32 or 16 Megabit (1M or 512k x 32-Bit) CMOS Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
Manufactured on 110 nm floating gate technology
8
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
1.1
Valid Combinations
Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
S29CD-J/CL-J Valid Combinations
Device
Number
Initial Burst
Access Delay
Clock
Frequency
Package Material Temperature
Autoselect ID
Option
Boot Sector
Option
Packing
Type
Type
Set
Range
Q
0, 3
0, 2, 3
0, 3
0, 1
0
J
B, F
Q
S29CD016J
S29CL016J
0, 1
M, P
J
B, F
Q
0, 2, 3
0, 3
0, 1
0
B, F
Q
0, 2, 3
0, 3
0, 1, 2, 3
M, P
J
B, F
Q
0, 2, 3
0, 3
0, 1
B, F
Q
0, 2, 3
0, 3
M, P
B, F
0, 2, 3
S29CD032J
A, F
I, M
0, 1 (2)
2, 3
0
0, 1
0
Q
0, 3
R
0
0, 1 (2)
2, 3
B, F
0, 2, 3
Q
0, 3
0, 2, 3
0, 3
J
B, F
Q
0, 1, 2, 3
M, P
B, F
0, 2, 3
S29CL032J
0, 1 (2)
2, 3
Q
0, 3
R
0, 1 (2)
2, 3
B, F
0, 2, 3
Notes:
1. The ordering part number that appears on BGA packages omits the leading “S29”.
2. Contact factory for availability.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
9
D a t a S h e e t
2. Input/Output Descriptions and Logic Symbols
Table identifies the input and output package connections provided on the device.
Symbol
Type
Description
Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb).
A9 supports 12V autoselect input.
A19-A0
Input
DQ31-DQ0
CE#
I/O
Input
Data input/output
Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
OE#
Input
Output Enable. This signal is asynchronous relative to CLK for the burst mode.
WE#
VCC
Input
Write Enable
Supply
Supply
Supply
No Connect
Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VersatileI/OTM Input.
VIO
VSS
Ground
NC
Not connected internally
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = VOH, the device is ready to accept read operations and commands.
When RY/BY# = VOL, the device is either executing an embedded algorithm or the
device is executing a hardware reset operation.
RY/BY#
Output
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
CLK
Input
Input
Load Burst Address input. Indicates that the valid address is present on the address
inputs.
ADV#
End of burst indicator for finite bursts only. IND is low when the last word in the burst
sequence is at the data outputs.
IND#
WAIT#
WP#
Output
Output
Input
Provides data valid feedback only when the burst length is set to continuous.
Write Protect Input. At VIL, disables program and erase functions in two outermost
sectors of the large bank.
Acceleration input. At VHH, accelerates erasing and programming. When not used for
ACC
Input
Input
acceleration, ACC = VSS or VCC
.
RESET#
Hardware Reset.
10
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
3. Block Diagram
VCC
VSS
DQmax–DQ0
Erase Voltage
Generator
Input/Output
Buffers
VIO
WE#
RESET#
State
ACC
WP#
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
VCC
Detector
Timer
Cell Matrix
Burst
State
Control
Burst
Address
Counter
ADV#
CLK
IND/
WAIT#
Amax-A0
Amax-A0
Note
Address bus is A19–A0 for 32 Mb device, A18–A0 for 16 Mb device. Data bus is D31–DQ0.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
11
D a t a S h e e t
4. Block Diagram of Simultaneous Read/Write Circuit
OE#
V
V
CC
SS
Upper Bank Address
A
–A0
max
Upper Bank
X-Decoder
A
–A0
max
STATE
CONTROL
&
COMMAND
REGISTER
RESET#
WE#
Status
DQ
–DQ0
max
CE#
Control
ADV#
DQ
–DQ0
max
X-Decoder
Lower Bank
A
–A0
max
Lower Bank Address
12
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
5. Physical Dimensions/Connection Diagrams
5.1
80-Pin PQFP Connection Diagram
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DQ16
DQ17
DQ18
DQ19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DQ15
DQ14
DQ13
DQ12
V
V
V
IO
SS
IO
V
SS
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
80-Pin PQFP
V
V
V
IO
SS
IO
V
SS
DQ28
DQ29
DQ30
DQ31
NC
DQ3
DQ2
DQ1
DQ0
A19
A18
A17
A16
A0
A1
A2
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Notes
1. On 16 Mb device, pin 44 (A19) is NC.
2. Pin 69 (RY/BY#) is Open Drain and requires an external pull-up resistor.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
13
D a t a S h e e t
5.2
PQR080–80-Lead Plastic Quad Flat Package Physical Dimensions
6
D
3
D1
0.20 MIN. FLAT SHOULDER
PIN S
D3
PIN R
7˚
TYP.
0˚MIN.
0.30 ± 0.05 R
PIN ONE I.D.
A
4
GAGE
0.25
PLANE
7˚
TYP.
L
E3
3
ccc
C
b
0˚-7˚
E1
6
-A-
-B-
aaa
M
A B S D S
C
E
DETAIL X
SEE NOTE 3
b
PIN P
-D-
SEE DETAIL X
PIN Q
c
e
BASIC
SECTION S-S
2
S
A2
A
-A-
-C-
A1
SEATING PLANE
S
NOTES:
PACKAGE
PQR 080
JEDEC
MO-108(B)CB-1
NOTES
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1982.
SYMBOL
MIN
--
NOM
--
MAX
3.35
--
2. DATUM PLANE -A- IS LOCATED AT THE MOLD PARTING LINE
AND IS COINCIDENT WITH THE BOTTOM OF THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY.
A
A1
A2
b
0.25
2.70
0.30
0.15
17.00
13.90
--
--
2.80
--
2.90
0.45
0.23
17.40
14.10
--
3. DIMENSIONS "D1" AND "E1" DO NOT INCLUD MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE.
SEE NOTE 4
DIMENSIONS "D1" AND "E1" INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE -A-
c
--
D
17.20
14.00
12.0
0.80
23.20
20.00
18.40
0.20
0.10
0.88
24
4. DIMENSION "B" DOES NOT INCLUDE DAMBAR PROTRUSION.
5. CONTROLLING DIMENSIONS: MILLIMETER.
D1
D3
e
SEE NOTE 3
REFERENCE
6. DIMENSIONS "D" AND "E" ARE MEASURED FROM BOTH
INNERMOST AND OUTERMOST POINTS.
--
--
BASIC, SEE NOTE 7
7. DEVIATION FROM LEAD-TIP TRUE POSITION SHALL BE WITHIN
±0.0076 mm FOR PITCH > 0.5 mm AND WITHIN ±0.04 FOR
PITCH < 0.5 mm.
E
23.00
19.90
--
23.40
20.10
--
E1
E3
aaa
ccc
L
SEE NOTE 3
REFERENCE
8. LEAD COPLANARITY SHALL BE WITHIN: (REFER TO 06-500)
1 - 0.10 mm FOR DEVICES WITH LEAD PITCH OF 0.65 - 0.80 mm
2 - 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm.
COPLANARITY IS MEASURED PER SPECIFICATION 06-500.
---
---
0.73
1.03
9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE
WITHIN ±0.0085".
P
Q
40
R
64
S
80
3213\38.4C
14
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
5.3
80-Ball Fortified BGA Connection Diagrams
A8
B8
C8
D8
E8
F8
G8
H8
J8
K8
A2
A1
A0
DQ29
VIO
VSS
VIO
DQ20
DQ16
NC
A7
B7
A4
C7
D7
E7
F7
G7
H7
J7
K7
A3
NC
DQ30
DQ26
DQ24
DQ23
DQ18 IND/WAIT#
NC
A6
A6
B6
A5
C6
A7
D6
E6
F6
G6
H6
J6
K6
DQ19
OE#
WE#
DQ31
DQ28
DQ25
DQ21
A5
B5
C5
D5
E5
F5
G5
H5
J5
K5
VSS
A8
NC
NC
DQ27
RY/BY#
DQ22
DQ17
CE#
VCC
A4
B4
A9
C4
D4
E4
F4
G4
H4
J4
K4
ACC
A10
NC
DQ1
DQ5
DQ9
WP#
NC
VSS
A3
B3
C3
D3
E3
F3
G3
H3
J3
K3
VCC
A12
A11
A19
DQ2
DQ6
DQ10
DQ11
ADV#
CLK
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
A14
A13
A18
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14
RESET#
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
A15
A16
A17
DQ3
VIO
VSS
VIO
DQ13
DQ15
VIO
Notes
1. On 16 Mb device, ball D3 (A19) is NC.
2. Ball F5 (RY/BY#) is Open Drain and requires an external pull-up resistor.
5.4
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
15
D a t a S h e e t
5.5
LAA080–80-ball Fortified Ball Grid Array (13 x 11 mm) Physical Dimensions
D1
D
A
0.20
2X
C
eD
K
J
H
G
F
E
D
C
B
A
8
7
6
5
4
3
2
1
7
SE
eE
E
E1
A1 CORNER ID.
(INK OR LASER)
B
A1
CORNER
6
NXφb
SD
0.20
2X
C
7
1.00±0.5
TOP VIEW
φ0.25
φ0.10
M
C
C
A B
A1
CORNER
M
BOTTOM VIEW
0.25
C
A
A2
A1
SEATING PLANE
C
0.15
C
SIDE VIEW
NOTES:
PACKAGE
JEDEC
LAA 080
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
NOTE
13.00 x 11.00 mm
PACKAGE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010
(EXCEPT AS NOTED).
SYMBOL
A
MIN
--
NOM
--
MAX
1.40
--
PROFILE HEIGHT
STANDOFF
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A1
0.40
0.60
--
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX
SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF
SOLDER BALLS.
A2
--
--
BODY THICKNESS
BODY SIZE
D
13.00 BSC.
11.00 BSC.
9.00 BSC.
7.00 BSC.
10
E
BODY SIZE
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW , SD OR SE = e/2
E1
MD
ME
N
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
80
φb
0.50
0.60
0.70
BALL DIAMETER
8. N/A
eD
1.00 BSC.
1.00 BSC.
0.50 BSC
BALL PITCH - D DIRECTION
BALL PITCH - E DIRECTION
SOLDER BALL PLACEMENT
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
eE
SD/SE
3214\38.12C
16
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
5.6
LAD080–80-ball Fortified Ball Grid Array (11 x 9 mm) Physical Dimensions
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
PACKAGE
JEDEC
LAD 080
N/A
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
11.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
0.55
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
0.35
0.45
BALL HEIGHT
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
D
11.00 BSC
9.00 BSC
9.00 BSC
7.00 BSC
10
BODY SIZE
E
BODY SIZE
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
MD
ME
N
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
8
80
b
0.55
0.65
0.75
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW SD OR SE = 0.000.
eE
1.00 BSC
1.00 BSC
0.50 BSC
N/A
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eD
SD / SE
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. “+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g1064 \ f16-038.12 \ 01.31.12
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
17
D a t a S h e e t
6. Additional Resources
Visit www.spansion.com to obtain the following related documents:
6.1
Application Notes
The following is a list of application notes related to this product. All Spansion application notes are available
at http://www.spansion.com/Support/TechnicalDocuments/Pages/ApplicationNotes.aspx
Using the Operation Status Bits in AMD Devices
Understanding Page Mode Flash Memory Devices
Common Flash Interface Version 1.4 Vendor Specific Extensions
6.2
6.3
Specification Bulletins
Contact your local sales office for details.
Hardware and Software Support
Downloads and related information on Flash device support is available at
http://www.spansion.com/SUPPORT/Pages/Support.aspx
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
Downloads and related information on simulation modeling and CAD modeling support is available at
http://www.spansion.com/Support/Pages/SimulationModels.aspx
VHDL and Verilog
IBIS
ORCAD
6.4
Contacting Spansion
Obtain the latest list of company locations and contact information on our web site at
http://www.spansion.com/About/Pages/Locations.aspx
18
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
7. Product Overview
The S29CD-J and S29CL-J families consist of 32 Mb and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J),
simultaneous read/write, dual boot burst mode Flash devices optimized for today's automotive designs.
These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are
capable of linear burst read (2, 4, or 8 double words) with wraparound. (Note that 1 double word = 32 bits.)
These products also offer single word programming with program/erase suspend and resume functionality.
Additional features include:
Advanced Sector Protection methods for protecting sectors as required.
256 bytes of Secured Silicon area for storing customer or factory secured information. The Secured Silicon
Sector is One-Time Programmable.
Electronic marking.
7.1
Memory Map
The S29CD-J and S29CL-J devices consist of two banks organized as shown in Table 7.1, Table 7.2,
Table 7.3 and Table 7.4.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
19
D a t a S h e e t
Table 7.1 S29CD016J/CL016J (Top Boot) Sector and Memory Address Map
Sector
Group
x32 Address
Range (A18:A0)
Sector Size
(KDwords)
Sector
Group
x32AddressRange Sector Size
Sector
Sector
(A18:A0)
(KDwords)
SA0
SG0
00000h–007FFh
2
SA15
20000h–23FFFh
16
(Note 1)
SA1
SA2
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
2
2
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7C7FFh
7C800h–7CFFFh
7D000h–7D7FFh
7D800h–7DFFFh
7E000h–7E7FFh
7E800h–7EFFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
SG10
SA3
2
SA4
2
SA5
2
SG11
SG12
SG13
SA6
2
SA7
2
SA8
16
16
16
16
16
16
16
SA9
SG8
SA10
SA11
SA12
SA13
SA14
SG9
SG14
SG15
SG16
SG17
SG18
SG19
SG20
SG21
2
2
2
2
2
SA44
(Note 3)
SG22
SG23
7F000h–7F7FFh
7F800h–7FFFFh
2
2
SA45
(Note 3)
Notes
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
3. This sector has the additional WP# pin sector protection feature.
20
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Table 7.2 S29CD016J/CL016J (Bottom Boot) Sector and Memory Address Map
x32
Sector
Group
x32 Address
Range (A18:A0)
Sector Size
(KDwords)
Sector
Group
Address Range
(A18:A0)
Sector Size
(KDwords)
Sector
SA0 (Note 1)
SA1 (Note 1)
SA2
Sector
SA31
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
2
2
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7C7FFh
7C800h–7CFFFh
7D000h–7D7FFh
7D800h–7DFFFh
7E000h–7E7FFh
7E800h–7EFFFh
7F000h–7F7FFh
16
16
16
16
16
16
16
2
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SG14
2
SA3
2
SA4
2
SA5
2
SG15
SA6
2
SA7
2
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SA8
16
16
16
16
16
16
2
SA9
SG8
2
SA10
SA11
SA12
SA13
2
2
2
SG9
2
SA45
(Note 3)
SA14
1C000h–1FFFFh
16
SG23
7F800h–7FFFFh
2
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SG10
SG11
SG12
SG13
Notes
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
3. Secured Silicon Sector overlays this sector when enabled.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
21
D a t a S h e e t
Table 7.3 S29CD032J/CL032J (Top Boot) Sector and Memory Address Map
Sector
Group
x32 Address Range
(A19:A0)
Sector Size
(KDwords)
Sector
Group
x32 Address Range
(A19:A0)
Sector Size
(KDwords)
Sector
Sector
Bank 0 (Note 2)
Bank 1 continued (Note 2)
80000h–83FFFh
SA0 (Note 1)
SA1
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
2
SA39
SA40
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
84000h–87FFFh
SG16
SA2
2
SA41
88000h–8BFFFh
8C000h–8FFFFh
90000h–93FFFh
94000h–97FFFh
98000h–9BFFFh
9C000h–9FFFFh
A0000h–A3FFFh
A4000h–A7FFFh
A8000h–ABFFFh
AC000h–AFFFFh
B0000h–B3FFFh
B4000h–B7FFFh
B8000h–BBFFFh
BC000h–BFFFFh
C0000h–C3FFFh
C4000h–C7FFFh
C8000h–CBFFFh
CC000h–CFFFFh
D0000h–D3FFFh
D4000h–D7FFFh
D8000h–DBFFFh
DC000h–DFFFFh
E0000h–E3FFFh
E4000h–E7FFFh
E8000h–EBFFFh
EC000h–EFFFFh
F0000h–F3FFFh
F4000h–F7FFFh
F8000h–FBFFFh
FC000h–FC7FFh
FC800h–FCFFFh
FD000h–FD7FFh
FD800h–FDFFFh
FE000h–FE7FFh
FE800h–FEFFFh
FF000h–FF7FFh
FF800h–FFFFFh
SA3
2
SA42
SA4
2
SA43
SA5
2
SA44
SG17
SG18
SG19
SG20
SG21
SA6
2
SA45
SA7
2
SA46
SA8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SA47
SA9
SG8
SA48
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA49
SA50
SA51
SG9
SA52
SA53
SA54
SA55
SG10
SG11
SA56
SA57
SA58
SA59
SA60
SA61
Bank 1 (Note 2)
SA62
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7FFFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SA63
SA64
SG12
SG13
SG14
SG15
SG22
SG23
SA65
SA66
SA67
SA68
SA69
SA70
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SA71
2
SA72
2
SA73
2
SA74
2
SA75
2
SA76 (Note 3)
SA77 (Note 3)
2
2
Notes
1. Secured Silicon Sector overlays this sector when enabled.
2. The bank address is determined by A19 and A18. BA = 00 for Bank 0 and BA = 01, 10, or 11 for Bank 1.
3. This sector has the additional WP# pin sector protection feature.
22
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Table 7.4 S29CD032J/CL032J (Bottom Boot) Sector and Memory Address Map
Sector Size
(KDwords)
Sector
Group
x32 Address Range
(A19:A0)
Sector Size
(KDwords)
Sector
Group
x32 Address Range
(A19:A0)
Sector
Sector
Bank 0 (Note 2)
Bank 0 continued (Note 2)
SA0 (Note 3)
SA1 (Note 3)
SA2
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
00000h–007FFh
00800h–00FFFh
01000h–017FFh
01800h–01FFFh
02000h–027FFh
02800h–02FFFh
03000h–037FFh
03800h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
20000h–23FFFh
24000h–27FFFh
28000h–2BFFFh
2C000h–2FFFFh
30000h–33FFFh
34000h–37FFFh
38000h–3BFFFh
3C000h–3FFFFh
40000h–43FFFh
44000h–47FFFh
48000h–4BFFFh
4C000h–4FFFFh
50000h–53FFFh
54000h–57FFFh
58000h–5BFFFh
5C000h–5FFFFh
60000h–63FFFh
64000h–67FFFh
68000h–6BFFFh
6C000h–6FFFFh
70000h–73FFFh
74000h–77FFFh
78000h–7BFFFh
7C000h–7FFFFh
2
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
80000h–83FFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
84000h–87FFFh
SG16
2
88000h–8BFFFh
SA3
2
8C000h–8FFFFh
90000h–93FFFh
SA4
2
SA5
2
94000h–97FFFh
SG17
SA6
2
98000h–9BFFFh
SA7
2
9C000h–9FFFFh
A0000h–A3FFFh
SA8
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SA9
SG8
A4000h–A7FFFh
SG18
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
A8000h–ABFFFh
AC000h–AFFFFh
B0000h–B3FFFh
SG9
B4000h–B7FFFh
SG19
B8000h–BBFFFh
BC000h–BFFFFh
Bank 1 (Note 2)
SG10
SG11
SG12
SG13
SG14
SG15
SA55
SA56
C0000h–C3FFFh
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2
C4000h–C7FFFh
SG20
SA57
C8000h–CBFFFh
SA58
CC000h–CFFFFh
D0000h–D3FFFh
SA59
SA60
D4000h–D7FFFh
SG21
SA61
D8000h–DBFFFh
SA62
DC000h–DFFFFh
E0000h–E3FFFh
SA63
SA64
E4000h–E7FFFh
SG22
SA65
E8000h–EBFFFh
SA66
EC000h–EFFFFh
F0000h–F3FFFh
SA67
SA68
SG23
F4000h–F7FFFh
F8000h–FBFFFh
FC000h–FC7FFh
FC800h–FCFFFh
FD000h–FD7FFh
FD800h–FDFFFh
FE000h–FE7FFh
FE800h–FEFFFh
FF000h–FF7FFh
FF800h–FFFFFh
SA69
SA70
SG24
SG25
SG26
SG27
SG28
SG29
SG30
SG31
SA71
2
SA72
2
SA73
2
SA74
2
SA75
2
SA76
2
SA77 (Note 1)
2
Notes
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A19 and A18. BA = 00, 01, or 10 for Bank 0 and BA = 11 for Bank 1.
3. The Secured Silicon Sector overlays this sector when enabled.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
23
D a t a S h e e t
8. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset features of
the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command register (see Table 8.1). The command register itself does not occupy any addressable
memory location; rather, it is composed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve as input to the internal state
machine; the state machine outputs dictate the function of the device. Writing incorrect address and data
values or writing them in an improper sequence may place the device in an unknown state, in which case the
system must write the reset command in order to return the device to the reading array data mode.
8.1
Device Operation Table
The device must be set up appropriately for each operation. Table 8.1 describes the required state of each
control pin for any particular operation.
Table 8.1 Device Bus Operation
Data
Operation
CE# OE# WE# RESET#
CLK
X
ADV#
Addresses
AIN
(DQ0–DQ31)
Read
L
L
L
H
L
H
H
X
X
DOUT
Asynchronous Write
Synchronous Write
H
X
AIN
DIN
L
H
L
H
AIN
DIN
Standby (CE#)
Output Disable
Reset
H
L
X
H
X
X
H
X
H
H
L
H
X
X
X
X
X
X
High-Z
X
High-Z
High-Z
High-Z
X
00000001h, (protected)
A6 = H
Sector Address,
A9 = VID,
A7 – A0 = 02h
PPB Protection Status (Note 2)
L
L
H
H
X
X
00000000h (unprotect)
A6 = L
Burst Read Operations
Load Starting Burst Address
L
L
X
L
H
H
H
H
AIN
X
X
Advance Burst to next address
with appropriate Data presented
on the Data bus
H
Burst Data Out
Terminate Current Burst Read Cycle
H
X
L
X
X
H
H
H
H
H
L
X
X
X
X
High-Z
High-Z
X
Terminate Current Burst
Read Cycle with RESET#
X
Terminate Current Burst Read Cycle;
Start New Burst Read Cycle
H
AIN
Legend
L = Logic Low = V , H = Logic High = V , X = Don’t care.
IL
IH
Notes
1. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
2. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB.
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S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
8.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
The internal state machine is set for asynchronously reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the
power control and should be used for device selection (CE# must be set to VIL to read data). OE# is the
output control and should be used to gate data to the output pins if the device is selected (OE# must be set to
VIL in order to read data). WE# should remain at VIH (when reading data).
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output pins. The
output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least a period of tACC-tOE and CE# has been asserted for at
least tCE-tOE time). Figure 8.1 shows the timing diagram of an asynchronous read operation.
Figure 8.1 Asynchronous Read Operation
CE#
CLK
ADV#
Addresses
Data
Address 0
Address 1
Address 2
Address 3
D0
D1
D2
D3
D3
OE#
WE#
VIH
Float
Float
VOH
IND/WAIT#
Note
Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Refer to Asynchronous Operations on page 58 for timing specifications and to Figure 18.2, Conventional
Read Operations Timings on page 58 for another timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading array data.
8.3
Hardware Reset (RESET#)
The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0”
on this input forces the device out of any mode that is currently executing back to the reset state. RESET#
may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential
bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data
outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset
operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is
complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a
period of tREADY2, if the bank was in the read/reset mode at the time RESET# was asserted. If one of the
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
25
D a t a S h e e t
banks was in the middle of either a program or erase operation when RESET# was asserted, the user must
wait a period of tREADY before accessing that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address
locations being operated on at the time of device reset. These locations need updating after the reset
operation is complete. See Hardware Reset (RESET#) on page 62 for timing specifications.
Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device initialization
until VCC and VIO have reached their steady state voltages. See VCC and VIO Power-up on page 57.
8.4
Synchronous (Burst) Read Mode and Configuration Register
When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode
can be used to significantly reduce the overall time needed for the device to output array data. After an initial
access time required for the data from the first address location, subsequent data is output synchronized to a
clock input provided by the system.
The device offers a linear method of burst read operation which is discussed in 2-, 4-, 8- Double Word Linear
Burst Operation on page 27.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration
register must be set in order to enable the burst read mode. Other Configuration Register settings include the
number of wait states to insert before the initial word (tIACC) of each burst access and when RDY indicates
that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration
register settings (and read the current register settings if desired via the Read Configuration Register
command sequence), then write the configuration register command sequence. See Configuration Register
on page 29, and Table 20.1 on page 75 for further details. Once the configuration register is written to enable
burst mode operation, all subsequent reads from the array are returned using the burst mode protocols.
Figure 8.2 Synchronous/Asynchronous State Diagram
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(D15 = 0)
Asynchronous Mode
(D15 = 1)
Synchronous Read
Mode Only
The device outputs the initial word subject to the following operational conditions:
tIACC specification: The time from the rising edge of the first clock cycle after addresses are latched to valid
data on the device outputs.
Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before
valid data appears on the device outputs. The effect is that tIACC is lengthened.
Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or
asynchronous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
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Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection
bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations
results in the data remaining valid while OE# is at VIL, regardless of the number of CLK cycles applied to the
device.
8.4.1
2-, 4-, 8- Double Word Linear Burst Operation
In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive
addresses that are determined by the group within which the starting address falls. Note that 1 double word =
32 bits. See Table 8.2 for all valid burst output sequences.
The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (VIL) during the last transfer of data
in a linear burst read before a wrap around. This transition indicates that the system should initiate another
ADV# to start the next burst access. If the system continues to clock the device, the next access wraps
around to the starting address of the previous burst access. The IND/WAIT# signal is floating when not active.
Table 8.2 32-Bit Linear and Burst Data Order
Output Data Sequence
Data Transfer Sequence
(Initial Access Address)
0-1 (A0 = 0)
1-0 (A0 = 1)
Two Linear Data Transfers
0-1-2-3 (A1-A0 = 00)
1-2-3-0 (A1-A0 = 01)
2-3-0-1 (A1-A0 = 10)
3-0-1-2 (A1-A0 = 11)
Four Linear Data Transfers
0-1-2-3-4-5-6-7 (A2-A0 = 000)
1-2-3-4-5-6-7-0 (A2-A0 = 001)
2-3-4-5-6-7-0-1 (A2-A0 = 010)
3-4-5-6-7-0-1-2 (A2-A0 = 011)
4-5-6-7-0-1-2-3 (A2-A0 = 100)
5-6-7-0-1-2-3-4 (A2-A0 = 101)
6-7-0-1-2-3-4-5 (A2-A0 = 110)
7-0-1-2-3-4-5-6 (A2-A0 = 111)
Eight Linear Data Transfers
Notes
1. The default configuration in the Control Register for Bit 6 is “1,” indicating that the device delivers data on the rising edge of the CLK
signal.
2. The device is capable of holding data for one CLK cycle.
3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to
asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register contents are reset to their
default conditions.
4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to V at any time during the burst linear or
IH
burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal.
5. Restarting a burst cycle is accomplished by taking CE# and ADV# to V
.
IL
6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge,
whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and
subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions back to V before a clock edge.
IH
7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to V during a
IH
burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst sequence, The DQ bus remains in the float state until OE# is taken to V
.
IL
8. Halting the burst sequence is accomplished by either taking CE# to V or re-issuing a new ADV# pulse.
IH
The IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/WAIT# signal floats and is not
driven. If OE# is at VIL, the IND/ WAIT# signal is driven at VIH until it transitions to VIL, indicating the end of
the burst sequence. Table 8.3 lists the valid combinations of the Configuration Register bits that impact the
IND/WAIT# timing. See Figure 8.3 for the IND/WAIT# timing diagram.
October 11, 2012 S29CD-J_CL-J_00_B7
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D a t a S h e e t
Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT#
CR9
CR8
CR6
(DOC)
(WC)
(CC)
Definition
0
0
0
1
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising
CLK edge
1
Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation
V
IH
IL
CE#
CLK
V
3 Clock Delay
ADV#
Addresses
Data
Address 1 Latched
Address 2
Address 1
Invalid
D1
D2
D3
D0
OE#
IND/WAIT#
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst,
output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.
8.4.2
Initial Burst Access Delay
Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon
a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration
Register (CR13-CR10). Refer to Table 8.5 for the initial access delay configurations under CR13-CR10. See
Figure 8.4 for the Initial Burst Delay Control timing diagram. Note that the Initial Access Delay for a burst
access has no effect on asynchronous read operations.
Table 8.4 Burst Initial Access Delay
CR13
CR12
CR11
CR10
Initial Burst Access (CLK cycles)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
3
4
5
6
7
8
9
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Figure 8.4 Initial Burst Delay Control
1st CLK
2nd CLK
3rd CLK
4th CLK
5th CLK
CLK
ADV#
Address 1 Latched
Valid Address
Addresses
Three CLK Delay
DQ31-DQ03
DQ31-DQ04
D0
D1
D0
D2
D1
D3
D4
Four CLK Delay
D2
D3
Five CLK Delay
DQ31-DQ05
D0
D1
D2
Notes
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles.
4. CR [13-10] = 2 or four clock cycles.
5. CR [13-10] = 3 or five clock cycles.
8.4.3
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up
or hardware reset, the device defaults to the asynchronous read mode and the configuration register settings
are in their default state. (See Table 8.6 for the default Configuration Register settings.) The host system
determines the proper settings for the entire configuration register, and then execute the Set Configuration
Register command sequence before attempting burst operations. The configuration register is not reset after
deasserting CE#.
The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the
Configuration Register commands. The Configuration Register is readable at any time, however, writing the
Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If the user
attempts to write the Configuration Register while the Embedded Algorithm is active, the write operation is
ignored and the contents of the Configuration Register remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation,
DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the same as the Autoselect
command reads. When the command is issued, the bank address is latched along with the command. Read
operations to the bank that was specified during the Configuration Register read command return
Configuration Register contents. Read operations to the other bank return flash memory data. Either bank
address is permitted when writing the Configuration Register read command.
The configuration register can be read with a four-cycle command sequence. See Command Definitions
on page 75 for sequence details.
Table 8.5 describes the Configuration Register settings.
October 11, 2012 S29CD-J_CL-J_00_B7
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D a t a S h e e t
Table 8.5 Configuration Register
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to 0.
CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC)
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)
0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)
These bits are reserved for future use. Set these bits to 0.
CR2–CR0 = Burst Length (BL2–BL0)
000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)
100 = Reserved, burst accesses disabled (asynchronous reads only)
101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)
Table 8.6 Configuration Register After Device Reset
CR15
RM
1
CR14
Reserve
0
CR13
IAD3
0
CR12
IAD2
1
CR11
IAD1
1
CR10
IAD0
1
CR9
DOC
0
CR8
Reserve
0
CR7
BS
1
CR6
CC
1
CR5
Reserve
0
CR4
Reserve
0
CR3
Reserve
0
CR2
BL2
1
CR1
BL1
0
CR0
BL0
0
8.5
Autoselect
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-dress pins A6,
A1, and A0 must be as shown in Table 8.7. In addition, when verifying sector protection, the sector address
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
must appear on the appropriate highest order address bits. Table 8.7 shows the remaining address bits that
are don’t care. When all necessary bits have been set as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command. This method does not require VID. See Command Definitions on page 75 for details on using the
autoselect mode. Autoselect mode can be used in either synchronous (Burst) mode or asynchronous (Non
Burst) mode.
The system must write the reset command to exit the autoselect mode and return to reading the array data.
See Table 8.7 for command sequence details.
Table 8.7 S29CD-J and S29CL-J Flash Family Autoselect Codes (High Voltage Method)
A19
to
A5
to
DQ7
Description
Manufacturer ID: Spansion
Read Cycle 1
CE# OE# WE# A11 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0
to DQ0
L
L
L
L
H
H
X
X
X
X
V
X
X
X
L
L
L
X
X
X
L
X
L
L
L
L
0001h
007Eh
ID
ID
V
H
08h or 36h for CD016J
46h for CL016J
Read Cycle 2
Read Cycle 3
L
L
H
X
X
V
X
L
L
L
H
H
H
L
ID
09h for CD032J
49h for CL032J
0000h
Top Boot Option
L
L
L
L
H
H
X
X
X
V
V
X
X
L
L
L
L
L
L
H
L
H
L
H
H
H
L
ID
0001h
Bottom Boot Option
0000h (unprotected)
0001h (protected)
PPB Protection Status
SA
ID
Legend
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
Note
The autoselect codes can also be accessed in-system via command sequences. See Table 20.2.
8.6
8.7
VersatileI/O (V ) Control
IO
The VersatileI/O (VIO) control allows the host system to set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO
pin. The output voltage generated on the device is determined based on the VIO level. For the 2.6 V (CD-J), a
VIO of 1.65 V–3.6 V (CD032J has a VIO of 1.65 V to 2.75 V) allows the device to interface with I/Os lower than
2.5 V. For a 3.3 V VCC (CL-J), a VIO of 1.65 V–3.60 V allows the device to interface with I/Os lower than 3.0 V.
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in
detail in the following sections. However, prior to any programming and or erase operation, devices must be
set up appropriately as outlined in the configuration register (Table 8.5 on page 30). During a synchronous
write operation, to write a command or command sequence (including programming data to the device and
erasing sectors of memory), the system must drive ADV# and CE# to VIL, and OE# to VIH when providing an
address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or
programming data.
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D a t a S h e e t
8.7.1
Programming
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program setup command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically generates the program pulses and verifies the programmed cell
margin. Command Definitions on page 75 shows the address and data requirements for the program
command sequence.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode and address are
no longer latched. An address change is required to begin reading valid array data.
The system can determine the status of the program operation by using DQ7, DQ6 or RY/BY#. Refer to
Write Operation Status on page 36 for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so may halt the operation and set DQ5 to 1, or
cause the Data# Polling algorithm to indicate the operation was successful. A succeeding read shows that
the data is still “0.” Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ignored except the
Program Suspend command.
A hardware reset immediately terminates the program operation; the program command sequence should
be re-initiated once the device has returned to the read mode, to ensure data integrity.
For the 32Mb S29CD-J and S29CL-J devices only:
Please refer to the application note “Recommended Mode of Operation for Spansion® 110 nm
S29CD032J/S29CL032J Flash Memory” publication number S29CD-CL032J_Recommend_AN for
programming best practices.
Figure 8.5 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note
See Table 19.1 and Table 20.2 for program command sequence.
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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8.7.2
Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 20.1, Memory Array
Command Definitions (x32 Mode) on page 75 and Figure 8.6, Erase Operation on page 34.) The device
does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all-zero data pattern prior to electrical erase. After a
successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than 80 µs occurs. During the time-
out period, additional sector addresses and sector erase commands may be written. Loading the sector erase
buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 80 µs. Any sector erase address and command
following the exceeded time-out (80 µs) may or may not be accepted. A time-out of 80 µs from the rising edge
of the last WE# (or CE#) initiates the execution of the Sector Erase command(s). If another falling edge of the
WE# (or CE#) occurs within the 80 µs time-out window, the timer is reset. Any command other than Erase
Suspend during the time-out period will be interpreted as an additional sector to erase. The device does not
decode the data bus, but latches the address. (See S29CD016J Sector Erase Time-Out Functionality
Application Note for further information.). The system can monitor DQ3 to determine if the sector erase timer
has timed out (See DQ3: Sector Erase Timer on page 42.) The time-out begins from the rising edge of the
final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data; addresses are no
longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in
the erasing bank. Refer to Write Operation Status on page 36 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be re-initiated once that bank has returned to reading array
data, in order to ensure data integrity.
Figure 8.6 on page 34 illustrates the algorithm for the erase operation. Refer to Program/Erase Operations
on page 31 for parameters and timing diagrams.
8.7.3
Chip Erase
Chip erase is a six-bus cycle operation as indicated by Command Definitions on page 75. The Chip Erase
command is used to erase the entire flash memory contents of the chip by issuing a single command.
However, chip erase does not erase protected sectors.
This command invokes the Embedded Erase algorithm, which does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for
an all-zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain
FFFFh. The system is not required to provide any controls or timings during these operations. Command
Definitions on page 75 in the appendix shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6 or the RY/
BY#. Refer to Write Operation Status on page 36 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
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33
D a t a S h e e t
Figure 8.6 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Command Definitions on page 75 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 42 for more information.
8.7.4
Erase Suspend / Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. When the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation. The bank address is required when writing this command. This command is valid only during
the sector erase operation, including the minimum 80-µs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the 80-µs time-out period has expired and during the
sector erase operation, the device takes 20 µs maximum to suspend the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system
can read data from or program data to any sector that is not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Note that when the device is in the Erase Suspend mode, the
Reset command is not required for read operations and is ignored.
Further nesting of erase operation is not permitted. Reading at any address within erase suspended sectors
produces status information on DQ7-DQ0. The system can use DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer to Table 8.8 on page 40 for information on these
status bits.
A read operation from the erase-suspended bank returns polling data during the first 8 µs after the erase
suspend command is issued; read operations thereafter return array data. Read operations from the other
bank return array data with no latency.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend read mode.
The system can determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status
bits, just as in the standard program operation.
To resume the sector erase operation, the system must write the Erase Resume command. The bank
address of the erase-suspended bank is required when writing this command. Further writes of the Resume
command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
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The following are the allowable operations when Erase Suspend is issued under certain conditions:
For the Busy Sectors, the host system may
Read status
Write the Erase Resume command
For the Non Busy Sectors, the system may
Read data
Program data or write the Suspend/Resume Erase command
8.7.5
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation so that
data can read from any non-suspended sector. When the Program Suspend command is written during a
programming process, the device halts the programming operation and updates the status bits.
After the programming operation has been suspended, the system can read array data from any non-
suspended sector. If a read is needed from the Secured Silicon Sector area, then user must use the proper
command sequences to enter and exit this region. The Sector Erase and Program Resume Command is
ignored if the Secured Silicon sector is enabled.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the DQ7, DQ6, and/or RY/BY# status bits, just as in the
standard program operation. See Write Operation Status on page 36 for more information.
The system must write the Program Resume command in order to exit the Program Suspend mode, and
continue the programming operation. Further writes of the Program Resume command are ignored. Another
Program Suspend command can be written after the device has resumed programming.
The following are the allowable operations when Program Suspend is issued under certain conditions:
For the Busy Sectors, the host system may write the Program Resume command
For the Non Busy Sectors, the system may read data
8.7.6
Accelerated Program Operations
Accelerated programming is enabled through the ACC function. This method is faster than the standard
program command sequences.
The device offers accelerated program operations through the ACC pin. When the system asserts VHH (12V)
on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command sequence to do accelerated programming. The device uses the
higher voltage on the ACC pin to accelerate the operation. Any sector that is being protected with the WP#
pin is still protected during accelerated program. Removing VHH from the ACC input, upon completion of the
embedded program operation, returns the device to normal operation.
Notes
In this mode, the write protection function is bypassed unless the PPB Lock Bit = 1.
The ACC pin must not be at VHH for operations other than accelerated programming or device damage
may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
The Accelerated Program command is not permitted if the Secured Silicon sector is enabled.
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D a t a S h e e t
8.7.7
Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster programming, erasing (Chip Erase), as well
as CFI commands. Once the device enters the Unlock Bypass mode, only two write cycles are required to
program or erase data, instead of the normal four cycles for program or 6 cycles for erase. This results in
faster total programming/erasing time.
Command Definitions on page 75 shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode only the Read, Unlock Bypass Program and Unlock Bypass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass
reset command sequence, which returns the device to read mode.
Notes
1. The Unlock Bypass Command is ignored if the Secured Silicon sector is enabled.
2. Unlike the standard program or erase commands, there is no Unlock Bypass Program/Erase
Suspend or Program/Erase Resume command.
8.7.8
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while
programming or erasing in another bank of memory.
The Simultaneous Read/Write feature can be used to perform the following:
Programming in one bank, while reading in the other bank
Erasing in one bank, while reading in the other bank
Programming a PPB, while reading data from the large bank or status from the small bank
Erasing a PPB, while reading data from the large bank or status from the small bank
Any of the above situations while in the Secured Silicon Sector Mode
The Simultaneous R/W feature can not be performed during the following modes:
CFI Mode
Password Program operation
Password Verify operation
As an alternative to using the Simultaneous Read/Write feature, the user may also suspend an erase or
program operation to read in another location within the same bank (except for the sector being erased).
Restrictions
The Simultaneous Read/Write function is tested by executing an embedded operation in the small (busy)
bank while performing other operations in the big (non-busy) bank. However, the opposite case is neither
tested nor valid. That is, it is not tested by executing an embedded operation in the big (busy) bank while
performing other operations in the small (non-busy) bank.
8.8
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ7, DQ6, DQ2, DQ5, DQ3, and RY/BY#.
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8.8.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence. Note that Data# Polling returns invalid data for the
address being programmed or erased.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately 1 µs,
then that bank returns to the read mode without programming the sector. If an erase address falls within a
protected sector, Toggle BIT (DQ6) is active for 150 s, then the device returns to the read mode without
erasing the sector. Please note that Data# polling (DQ7) may give misleading status when an attempt is
made to program or erase a protected sector.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete Data# Polling produces a “1” on DQ7. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
In asynchronous mode, just prior to the completion of an Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase
operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
See the following for more information: Table 8.9, Write Operation Status on page 42 shows the outputs for
Data# Polling on DQ7. Figure 8.7, Data# Polling Algorithm on page 38 shows the Data# Polling timing
diagram.
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D a t a S h e e t
Figure 8.7 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for
erasure. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5
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8.8.2
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE#
pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation, two immediate consecutive read cycles to any
address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. For asynchronous mode,
either OE# or CE# can be used to control the read cycles. For synchronous mode, the rising edge of ADV# is
used or the rising edge of clock while ADV# is Low.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
Algorithm is complete.
See Figure 18.12, Toggle Bit Timings (During Embedded Algorithms) on page 66 for additional information.
8.8.3
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system
performs two consecutive reads at addresses within those sectors that have been selected for erasure. But
DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison,
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to
Table 8.8 to compare outputs for DQ2 and DQ6. See DQ6: Toggle Bit I on page 39 for additional information.
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D a t a S h e e t
8.8.4
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must perform two consecutive reads of DQ7-
DQ0 in a row in order to determine whether a toggle bit is toggling. Typically, the system notes and stores the
value of the toggle bit after the first read. After the second read, the system compares the new value of the
toggle bit with the first. If the toggle bit is not toggling, the device completes the program or erases operation.
The system can read array data on DQ7-DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also notes whether the value of DQ5 is high (see the section on DQ5). If it is, the system then
determines again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erases operation. If it is still toggling, the device had not completed the operation successfully, and the
system writes the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, the system may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation. Refer to Figure 8.8 for more on the Toggle Bit Algorithm.
Table 8.8 DQ6 and DQ2 Indications
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
at an address within a sector selected
for erasure,
toggles,
toggles,
also toggles.
does not toggle
toggles.
actively erasing,
at an address within sectors not
selected for erasure,
at an address within sectors selected
for erasure,
does not
toggle,
erase suspended,
returns array data. The system can
read from any sector not selected for
erasure.
at an address within sectors not
selected for erasure,
returns array
data,
programming in erase
suspend,
at any address,
toggles,
is not applicable.
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Figure 8.8 Toggle Bit Algorithm
START
Read Byte
(DQ0-DQ7)
Address = VA
(Note 1)
Read Byte
(DQ0-DQ7)
Address = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ0-DQ7)
(Notes 1, 2)
Adrdess = VA
No
DQ6 = Toggle?
Yes
FAIL
PASS
Notes
1. Read toggle bit with two immediately consecutive reads to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1.
8.8.5
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device halts
the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system issues the reset command to return the device to reading array data.
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D a t a S h e e t
8.8.6
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
Sector Erase on page 33 for more details.
After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands.
To ensure the command has been accepted, the system software check the status of DQ3 prior to and
following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Table 8.9 shows the status of DQ3 relative to the other status bits.
8.8.7
RY/BY#: Ready/Busy#
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or have been completed. If the output of RY/BY# is low, the
device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to
accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any
additional program or erase commands with the exception of the Erase suspend command. If the device has
entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY#
= 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/
BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the
RY/BY# is also valid after the rising edge of the sixth WE# pulse.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is
completed in a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-
up resistor to VCC. An external pull-up resistor is required to take RY/BY# to a VIH level since the output is an
open drain.
Table 8.9 shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2. Figure 18.2, Figure 18.6,
Figure 18.8 and Figure 18.9 show RY/BY# for read, reset, program, and erase operations, respectively.
Table 8.9 Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5:
Exceeded Timing Limits on page 41 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. See DQ7: Data# Polling on page 37 and DQ2: Toggle Bit II
on page 39 for further details.
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8.9
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the cycles in an erase command sequence before erasing
begins. This resets the device to the read mode. However, once erasure begins, the device ignores the reset
commands until the operation is complete.
The reset command may be written between the cycles in a program command sequence before
programming begins. This resets the device to the read mode. If the program command sequence is written
while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-
suspend-read mode. However, once programming begins, the device ignores the reset commands until the
operation is complete.
The reset command may be written between the cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to exit the autoselect mode and return to the read
mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the
read mode or erase-suspend-read-mode if the device was in Erase Suspend. When the reset command is
written, before the embedded operation starts, the device requires tRR before it returns to the read or erase-
suspend-read mode.
Table 8.10 Reset Command Timing
Parameter
Description
Reset Command to Read Mode
or Erase-Suspend-Read Mode
Max.
Unit
tRR
250
ns
9. Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations
in any or all sectors and can be implemented through software and/or hardware methods, which are
independent of each other. This section describes the various methods of protecting data stored in the
memory array. An overview of these methods in shown in Figure 9.1.
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Figure 9.1 Advanced Sector Protection/Unprotection
Hardware Methods
Software Methods
WP# = VIL
(Two outermost sectors
locked in large bank)
Persistent Method
Password Method
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “0” on reset.
PPB Lock Bit1,2,3
2. Programming to “1” locks all PPBs to their
current state.
0 = PPBs Unlocked
1 = PPBs Locked
3. Once programmed to “1”, requires hardware
reset to unlock.
Persistent
Protection Bit
(PPB)5,6
Dynamic
Protection Bit
(DYB)7,8,9
Memory Array
Sector Group 0
Sector Group 1
Sector Group 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector Group N-2
Sector Group N-1
Sector Group N4
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
4. N = 23 for S29CD016J/CL016J,
31 for S29CD032J/CL032J.
5. PPBs programmed individually,
but cleared collectively.
7. Protect effective only if PPB Lock Bit is
unlocked and corresponding PPB is “0”
(unprotected).
6. 0 = Sector Group Unprotected;
1 = Sector Group Protected
8. Volatile Bits.
9. 0 = Sector Group Unprotected;
1 = Sector Group Protected
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9.1
Advanced Sector Protection Overview
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sector
groups are unprotected. The device programmer or host system must then choose which sector group
protection method to use. Programming (setting to “0”) any one of the following two one-time programmable,
non-volatile bits locks the device permanently in that mode:
Persistent Protection Mode Lock Bit
Password Protection Mode Lock Bit
After selecting a sector group protection method, each sector group can operate in any of the following three
states:
1. Persistently Locked. A sector group is protected and cannot be changed.
2. Dynamically locked. The selected sector groups are protected and can be altered via software
commands.
3. Unlocked. The sector groups are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in sections Persistent Protection Bits on page 45 to
Hardware Data Protection Methods on page 49.
Notes
1. If the password mode is chosen, the password must be programmed before setting the
corresponding lock register bit. The user must be sure that the password is correct when the
Password Mode Locking Bit is set, as there is no means to verify the password afterwards.
2. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.
3. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode
Lock Bit is programmed, the Password Mode is permanently disabled.
4. It is important that the mode is explicitly selected when the device is first programmed, rather than
relying on the default mode alone. This is so that it is impossible for a system program or virus to
later set the Password Mode Locking Bit, which would cause an unexpected shift from the default
Persistent Sector Protection Mode into the Password Protection Mode.
5. If the user attempts to program or erase a protected sector, the device ignores the command and
returns to read mode. A program command to a protected sector enables status polling for
approximately 1 µs before the device returns to read mode without modifying the contents of the
protected sector. An erase command to a protected sector enables status polling for approximately
50 µs, after which the device returns to read mode without having erased the protected sector.
6. For the command sequence required for programming the lock register bits, refer to Command
Definitions on page 75.
9.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile. A single Persistent Protection Bit is assigned to a
maximum for four sectors (see the sector address tables for specific sector protection groupings). All eight-
Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility.
Notes
1. Each PPB is individually programmed and all are erased in parallel. There are no means for
individually erasing a specific PPB and no specific sector address is required for this operation.
2. If a PPB requires erasure, all of the sector PPBs must first be programmed prior to PPB erasing. It
is the responsibility of the user to perform the preprogramming operation. Otherwise, an already
erased sector PPB has the potential of being over-erased. There is no hardware mechanism to
prevent sector PPB over-erasure.
3. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out
without programming or erasing the PPB.
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9.2.1
Programming PPB
The PPB Program Command is used to program, or set, a given PPB. The first three cycles in the PPB
Program Command are standard unlock cycles. The fourth cycle in the PPB Program Command executes the
pulse which programs the specified PPB. The user must wait either 100 µs or until DQ6 stops toggling before
executing the fifth cycle, which is the read verify portion of the PPB Program Command. The sixth cycle
outputs the status of the PPB Program operation.
In the event that the program PPB operation was not successful, the user can loop directly to the fourth cycle
of the PPB Program Command to perform the program pulse and read verification again. After four
unsuccessful loops through the program pulse and read verification cycles the PPB programming operation
should be considered a failure.
Figure 9.2 PPB Program Operation
Write 0xAA to 0x555
Write 0x55 to 0x2AA
Write 0x60 to 0x555
Write 0x68 to SG+WP
Note: Reads from the
Either poll DQ6 in the
small bank and wait for
it to stop toggling OR
wait 100 µs
small bank at this point
return the status of the
operation, not read array
data.
Write 0x48 to SG+WP
Read from SG+WP
NO
NO
5th attempt?
YES
DQ0 = 1?
YES
Error
Done
9.2.2
Erasing PPB
The All PPB Erase command is used to erase all the PPBs in bulk. There are no means for individually
erasing a specific PPB. The first three cycles of the PPB Erase command are standard unlock cycles. The
fourth cycle executes the erase pulse to all the PPBs. The user must wait either 20 ms or until DQ6 stops
toggling before executing the fifth cycle, which is the read verify portion of the PPB Erase Command. The
sixth cycle outputs the status of the PPB Erase operation.
In the event that the erase PPB operation was not successful, the user can loop directly to the fourth cycle of
the All PPB Erase Command to perform the erase pulse and read verification again. After four unsuccessful
loops through the erase pulse and read verification cycles, the PPB erasing operation should be considered a
failure.
Note
All PPB must be preprogrammed prior to issuing the All PPB Erase Command.
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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Figure 9.3 PPB Erase Operation
Write 0xAA to 0x555
Write 0x55 to 0x2AA
Write 0x60 to 0x555
Write 0x60 to WP
Note: Reads from the
small bank at this point
return the status of the
operation, not read array
data.
Either poll DQ6 in the
small bank and wait for
it to stop toggling OR
wait 20 ms
Write 0x40 to WP
Read from WP
NO
NO
5th attempt?
YES
DQ0 = 0?
YES
Error
Done
9.3
9.4
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set to “1”, it locks all PPBs;
when set to “0”, it allows the PPBs to be changed. There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password protection
mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set only after all PPBs are configured to the desired settings.
Dynamic Protection Bits
A Dynamic Protection Bit (DYB) is volatile and unique for each sector group and can be individually modified.
DYBs only control the protection scheme for unprotected sector groups that have their PPBs set to “0”. By
issuing the DYB Set or Clear command sequences, the DYBS are set or cleared, thus placing each sector
group in the protected or unprotected state respectively. This feature allows software to easily protect sector
groups against inadvertent changes, yet does not prevent the easy removal of protection when changes are
needed.
Notes
1. The DYBs can be set or cleared as often as needed with the DYB Write Command.
2. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is
defaulted to power up in the cleared state – meaning the PPBs are changeable. The DYB are also
always cleared after a power-up or reset.
3. It is possible to have sector groups that are persistently locked with sector groups that are left in
the dynamic state.
October 11, 2012 S29CD-J_CL-J_00_B7
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47
D a t a S h e e t
4. The DYB Set or Clear commands for the dynamic sector groups signify the protected or
unprotected state of the sector groups respectively. However, if there is a need to change the
status of the persistently locked sector groups, a few more steps are required. First, the PPB Lock
Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The
PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again
locks the PPBs, and the device operates normally again.
Table 9.1 Sector Protection Schemes
DYB
0
PPB
PPB Lock
Sector State
Unprotected—PPB and DYB are changeable
0
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
Unprotected—PPB not changeable, DYB is changeable
0
1
Protected—PPB and DYB are changeable
1
0
1
Protected—PPB not changeable, DYB is changeable
1
9.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection
Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password
requirement, after power-up and reset, the PPB Lock Bit is set “1” in order to maintain the password mode of
operation. Successful execution of the Password Unlock command by entering the entire password clears the
PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the password
is written and verified, the Password Mode Locking Bit must be set in order to prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a
cell is programmed as a “0” results in a time-out with the cell as a “0”. (This is an OTP area).
3. The password is all “1”s when shipped from the factory.
4. When the password is undergoing programming, Simultaneous Read/Write operation is disabled.
Read operations to any memory location returns the programming status. Once programming is
complete, the user must issue a Read/Reset command to return the device to normal operation.
5. All 64-bit password combinations are valid as a password.
6. There is no means to read, program or erase the password is after it is set.
7. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and
further password programming.
8. The Password Mode Lock Bit is not erasable.
9. The exact password must be entered in order for the unlocking function to occur.
10.There is a built-in 2-µs delay for each password check. This delay is intended to stop any efforts to
run a program that tries all possible combinations in order to crack the password.
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9.6
Hardware Data Protection Methods
The device offers several methods of data protection by which intended or accidental erasure of any sectors
can be prevented via hardware means. The following subsections describe these methods.
9.6.1
WP# Method
The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large
bank.
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the two
“outermost” boot sectors (8-Kbyte sectors) in the large bank. If the system asserts VIH on the WP# pin, the
device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector
protection or unprotection for these sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may
result.
The WP# pin must be held stable during a command sequence execution
9.6.2
Low V Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO
.
9.6.3
9.6.4
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power-up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9.6.5
9.6.6
V
and V Power-up And Power-down Sequencing
CC IO
The device imposes no restrictions on VCC and VIO power-up or power-down sequencing. Asserting RESET#
to VIL is required during the entire VCC and VIO power sequence until the respective supplies reach the
operating voltages. Once VCC and VIO attain the operating voltages, deassertion of RESET# to VIH is
permitted. Refer to timing in VCC and VIO Power-up on page 57.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero (VIL) while OE# is a logical one (VIH).
October 11, 2012 S29CD-J_CL-J_00_B7
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D a t a S h e e t
10. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification
through an Electronic Serial Number (ESN). The Secured Silicon Sector is a 256-byte flash memory area that
is either programmable at the customer, or by Spansion at the request of the customer. See Table 10.1 for
the Secured Silicon Sector address ranges.
All Secured Silicon reads outside of the 256-byte address range return invalid data.
Table 10.1 Secured Silicon Sector Addresses
Ordering Option
Sector Size (Bytes)
Address Range
Top Boot
256
00000h-0003Fh (16 Mb and 32 Mb)
FFFC0h–FFFFFh (32 Mb)
7FFC0h–7FFFFh (16 Mb)
Bottom Boot
256
The device allows Simultaneous Read/Write operation while the Secured Silicon Sector is enabled. However,
several restrictions are associated with Simultaneous Read/Write operation and device operation when the
Secured Silicon Sector is enabled:
1. The Secured Silicon Sector is not available for reading while the Password Unlock, any PPB
program/erase operation, or Password programming are in progress. Reading to any location in
the small bank will return the status of these operations until these operations have completed
execution.
2. Programming the DYB associated with the overlaid boot-block sector results in the DYB NOT being
updated. This occurs only when the Secured Silicon sector is not enabled.
3. Reading the DYB associated with the overlaid boot-block sector when the PPB Lock/DYB Verify
command is issued, causes the read command to return invalid data. This function occurs only
when the Secured Silicon Sector is not enabled.
4. All commands are available for execution when the Secured Silicon Sector is enabled, except the
following:
a. Any Unlock Bypass command
b. CFI
c. Accelerated Program
d. Program and Sector Erase Suspend
e. Program and Sector Erase Resume
Issuing the above commands while the Secured Silicon Sector is enabled results in the command being
ignored.
5. It is valid to execute the Sector Erase command on any sector other than the Secured Silicon
Sector when the Secured Silicon Sector is enabled. However, it is not possible to erase the
Secured Silicon Sector using the Sector Erase Command, as it is a one-time programmable (OTP)
area that can not be erased.
6. Executing the Chip Erase command is permitted when the Secured Silicon Sector is enabled. The
Chip Erase command erases all sectors in the memory array, except for sector 0 in top-boot block
configuration, or sector 45 in bottom-boot block configuration. The Secured Silicon Sector is a one-
time programmable memory area that cannot be erased.
7. Executing the Secured Silicon Sector Entry command during program or erase suspend mode is
allowed. The Sector Erase/Program Resume command is disabled when the Secured Silicon
sector is enabled; the user cannot resume programming of the memory array until the Exit Secured
Silicon Sector command is written.
8. Address range 00040h–007FFh for the top bootblock, and FF00h–FFF7Fh return invalid data
when addressed with the Secured Silicon sector enabled.
9. The Secured Silicon Sector Entry command is allowed when the device is in either program or
erase suspend modes. If the Secured Silicon sector is enabled, the program or erase suspend
command is ignored. This prevents resuming either programming or erasure on the Secured
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Silicon sector if the overlayed sector was undergoing programming or erasure. The host system
must ensure that the device resume any suspended program or erase operation after exiting the
Secured Silicon sector.
10.1 Secured Silicon Sector Protection Bit
The Secured Silicon Sector can be shipped unprotected, allowing customers to utilize that sector in any
manner they choose.
Please note the following:
The Secured Silicon Sector can be read any number of times, but can be programmed and locked only
once. The Secured Silicon Sector Protection Bit must be used with caution as once locked, there is no
procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured
Silicon Sector memory space can be modified in any way.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon
Sector Region command sequence to return the device to the memory array.
10.2 Secured Silicon Sector Entry and Exit Commands
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon Sector region until the
system issues the four-cycle Exit Secured Silicon Sector command sequence. See the Table 20.1, Memory
Array Command Definitions (x32 Mode) on page 75 and Table 20.2, Sector Protection Command Definitions
(x32 Mode) on page 76 for address and data requirements for both command sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read Secured Silicon areas
Program Secured Silicon Sector (only once)
After the system has written the Enter Secured Silicon Sector command sequence, it can read the Secured
Silicon Sector by using the addresses listed in Table 10.1, Secured Silicon Sector Addresses on page 50.
This mode of operation continues until the system issues the Exit Secured Silicon Sector command
sequence, or until power is removed from the device.
11. Electronic Marking
Electronic marking has been programmed into the device, prior to shipment from Spansion, to ensure
traceability of individual products. The electronic marking is stored and locked within a one-time
programmable region. Detailed information on Electronic Marking will be provided in a data sheet
supplement.
12. Power Conservation Modes
12.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in standby mode. In this mode,
current consumption is greatly reduced, and outputs are placed in a high impedance state, independent of
OE# input. The device enters CMOS standby mode when the CE# and RESET# inputs are both held at
VCC ± 10%. The device requires standard access time (tCE) for read access before it is ready to read data. If
the device is deselected during erasure or programming, the device draws active current until the operation is
completed.
ICC5 in DC Characteristic, CMOS Compatible on page 54 represents the standby current specification.
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D a t a S h e e t
Caution
Entering standby mode via the RESET# pin also resets the device to read mode and floats the data I/O pins.
Furthermore, entering ICC7 during a program or erase operation leaves erroneous data in the address
locations being operated on at the time of the RESET# pulse. These locations require updating after the
device resumes standard operations. See Hardware RESET# Input Operation on page 52for further
discussion of the RESET# pin and its functions.
12.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. While in sleep mode, output data is latched and
always available to the system.
While in asynchronous mode, the device automatically enables this mode when addresses remain stable for
tACC + 60 ns. Standard address access timings provide new data when addresses are changed. While in
synchronous mode, the device automatically enables this mode when either the first active CLK level is
greater than tACC or the CLK runs slower than 5 MHz. A new burst operation is required to provide new data.
ICC8 in DC Characteristic, CMOS Compatible on page 54 represents the automatic sleep mode current
specification.
12.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array data. Any operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity.
When RESET# is held at VSS ±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at
VIL but not within VSS ±0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry, thus a system reset would also reset the Flash memory,
enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset
operation is internally complete. This action requires between 1 µs and 7 µs for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine whether the reset operation is complete. Otherwise, allow
for the maximum reset time of 11 µs.
If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation
completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank
after 500 ns if the bank is in the read/reset mode at the time RESET# is asserted. If one of the banks is in the
middle of either a program or erase operation when RESET# is asserted, the user must wait 11 µs before
accessing that bank.
Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization
until VCC and VIO have reached steady state voltages.
12.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high
impedance state.
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13. Electrical Specifications
13.1 Absolute Maximum Ratings
Table 13.1 Absolute Maximum Ratings
Parameter
Rating
–65 °C to +150 °C
–65 °C to +145 °C
–0.5V to +3.6V
–0.5V to +3.6V
Storage Temperature, Plastic Packages
Ambient Temperature with Power Applied
VCC, VIO (Note 1) for 2.6 V devices (S29CD-J)
VCC, VIO (Note 1) for 3.3 V devices (S29CL-J)
ACC, A9, and RESET# (Note 2)
–0.5V to +13.0V
–0.5V to +3.6V (CL016J)
–0.5V to +2.75V (CD016J)
–0.5V to +3.6V (CL032J)
–0.5V to +2.75V (CD032J)
200 mA
(with the exception of CLK)
All other pins (Note 1)
Address, Data, Control Signals (Note 1)
Output Short Circuit Current (Note 3)
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input at I/O pins may overshoot V to –2.0V for periods of
SS
up to 20 ns. See Figure 13.2. Maximum DC voltage on output and I/O pins is 3.6V. During voltage transitions output pins may overshoot
to V + 2.0V for periods up to 20 ns. See Figure 13.2.
CC
2. Minimum DC input voltage on pins ACC, A9, and RESET# is -0.5V. During voltage transitions, A9 and RESET# may overshoot
V
to –2.0V for periods of up to 20 ns. See Figure 13.1. Maximum DC input voltage on pin A9 is +13.0V which may overshoot to 14.0V
SS
for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 13.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2 V
20 ns
Figure 13.2 Maximum Positive Overshoot Waveform
20 ns
V
CC +2.0 V
CC+0.5 V
2.0 V
V
20 ns
20 ns
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D a t a S h e e t
14. Operating Ranges
Table 14.1 Operating Ranges
Parameter
Range
Industrial Devices
Extended Devices
CC for 2.6V regulated voltage range (S29CD-J devices)
–40°C to +85°C
–40°C to +125°C
2.50V to 2.75V
3.00V to 3.60V
1.65V to 2.75V
1.65V to 3.6V
Ambient Temperature (TA)
V
V
CC Supply Voltages
VCC for 3.3V regulated voltage range (S29CL-J devices)
VIO (S29CD-J devices)
VIO Supply Voltages
VIO (S29CL-J devices)
Note
Operating ranges define those limits between which the functionality of the device is guaranteed.
15. DC Characteristics
Table 15.1 DC Characteristic, CMOS Compatible
Parameter Description
Test Conditions
VIN = VSS to VIO, VIO = VIO max
VIN = VSS to VIO, VIO = VIO max
VCC = VCCmax; A9 = 12.5V
Min
Typ
Max
± 1.0
–25
35
Unit
ILI
ILIWP
ILIT
Input Load Current
µA
µA
µA
µA
mA
mA
WP# Input Load Current
A9, ACC Input Load Current
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC max
± 1.0
55
S29CD-J
S29CL-J
45
65
CE# = VIL, OE# = VIL, 8 Double
Word
ICCB
VCC Active Burst Read Current (1)
90
VCC Active Asynchronous
Read Current (1)
ICC1
ICC3
CE# = VIL, OE# = VIL
1 MHz
10
50
mA
mA
VCC Active Program Current
(2, 3, 4)
CE# = VIL, OE# = VIH, ACC = VIH
40
20
ICC4
ICC5
VCC Active Erase Current (2, 3, 4)
VCC Standby Current (CMOS)
CE# = VIL, OE# = VIH, ACC = VIH
50
60
mA
µA
VCC= VCC max, CE# = VCC ± 0.3V
VCC Active Current
(Read While Write) (3)
ICC6
CE# = VIL, OE# = VIL
30
90
mA
ICC7
ICC8
IACC
VIL
VCC Reset Current
RESET# = VIL
60
60
µA
µA
mA
V
Automatic Sleep Mode Current
VACC Acceleration Current
Input Low Voltage
VIH = VCC ± ± 0.3 V, VIL = VSS ± ± 0.3V
ACC = VHH
20
–0.5
0.7 x VIO
–0.2
0.3 x VIO
VCC
VIH
Input High Voltage
V
VILCLK
VIHCLK
VIHCLK
VID
CLK Input Low Voltage
CLK Input High Voltage (CD-J)
CLK Input High Voltage (CL-J)
Voltage for Autoselect
0.3 x VIO
2.75
V
0.7 x VCC
0.7 x VCC
11.5
V
3.6
V
VCC = 2.5V
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
VOL = 0.4V
0.45
V
IOLRB
VHH
RY/BY#, Output Low Current
Accelerated (ACC pin) High Voltage
Output High Voltage
8
mA
V
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
0.85 x VCC
VIO –0.1
1.6
VOH
V
VLKO
Low VCC Lock-Out Voltage (3)
2.0
V
Notes
1. The I current listed includes both the DC operating current and the frequency dependent component.
CC
2.
3. Not 100% tested.
4. Maximum I specifications are tested with V = V .
CCmax
I
active while Embedded Erase or Embedded Program is in progress.
CC
CC
CC
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15.1 Zero Power Flash
Figure 15.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
4
3
2
1
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz
Figure 15.2 Typical ICC1 vs. Frequency
5
4
3
2
1
2.7 V
0
1
2
3
4
5
Frequency in MHz
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55
D a t a S h e e t
16. Test Conditions
Figure 16.1 Test Setup
Device
Under
Test
C
L
17. Test Specifications
Table 17.1 Test Specifications
Test Condition
All Options
1 TTL gate
Unit
Output Load
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
30
5
pF
ns
V
Input Pulse Levels
0.0V – VIO
VIO/2
Input timing measurement reference levels
Output timing measurement reference levels
V
V
IO/2
V
Table 17.2 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High-Z)
17.1 Switching Waveforms
Figure 17.1 Input Waveforms and Measurement Levels
Measurement Level
VIO
VIO/2 V
VIO/2 V
Input
Output
VSS
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18. AC Characteristics
18.1
V
and V Power-up
CC
IO
Table 18.1 VCC and VIO Power-up
Parameter
tVCS
Description
VCC Setup Time
Test Setup
Speed
50
Unit
µs
Min
Min
Min
tVIOS
VIO Setup Time
50
µs
tRSTH
RESET# Low Hold Time
50
µs
Figure 18.1 VCC and VIO Power-up Diagram
tVCS
VCC
tVIOS
VIOP
tRSTH
RESET#
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18.2 Asynchronous Operations
Table 18.2 Asynchronous Read Operations
Parameter
Speed Options
75 MHz 66 MHz 56 MHz 40 MHz
JEDEC Std.
Description
Test Setup
Min
0R 0P 0M 0J/1J
Unit
tAVAV
tAVQV
tRC Read Cycle Time (Note 1)
tACC Address to Output Delay
54
54
ns
CE# = VIL
OE# = VIL
Max
ns
tELQV
tGLQV
tCE Chip Enable to Output Delay
tOE Output Enable to Output Delay
OE# = VIL
Max
Max
54
20
ns
ns
Chip Enable to Output High-Z
(Note 1)
tEHQZ
tDF
Max
10
ns
Min
Max
Min
2
10
0
ns
ns
ns
tGHQZ
tDF Output Enable to Output High-Z (Note 1)
Read
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
2
ns
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
tAXQX
tOH
Notes
1. Not 100% tested.
2. See Figure 16.1 and Table 17.1 for test specifications.
3. TOE during Read Array.
Figure 18.2 Conventional Read Operations Timings
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
High Z
High Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Figure 18.3 Asynchronous Command Write Timing
CLK
ADV#
tCS
CE#
tCH
tWC
Stable Address
Addresses
Data
Valid Data
tAH
tAS
tDH
tDS
WE#
OE#
tWEH
tOEP
IND/WAIT#
Notes
1. All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command.
Only a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode
option is enabled in the Configuration Register.
2. Refer to Table 18.5 for write timing parameters.
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18.3 Synchronous Operations
Table 18.3 Burst Mode for 32 Mb and 16 Mb
Parameter
Speed Options
66 MHz, 56 MHz,
Description
75 MHz,
40 MHz,
0J/1J
JEDEC
Std.
tBACC
0R
0P 0M
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Burst Access Time Valid Clock to Output Delay
Max
Min
Min
Min
Min
Min
Max
Min
Max
Min
Max
Max
Max
Min
Min
Max
Min
Max
Max
Min
Max
8
8
8
8
tADVCS ADV# Setup Time to Rising Edge of CLK
tADVCH ADV# Hold Time from Rising Edge of CLK
6
1.5
tADVP
ADV# Pulse Width
7.5
2
8.5
2
9.5
3
10.5
3
16 Mb
32 Mb
tBDH
Valid Data Hold from CLK (Note 2)
0
0
0
0
tINDS
tINDH
tIACC
CLK to Valid IND/WAIT# (Note 2)
8
IND/WAIT# Hold from CLK (Note 2)
CLK to Valid Data Out, Initial Burst Access
2
2
3
3
48
54
54
54
25
13.3
15.15
17.85
tCLK
CLK Period
60
3
tCR
tCF
CLK Rise Time (Note 2)
CLK Fall Time (Note 2)
CLK High Time (Note 3)
CLK Low Time (Note 3)
Output Enable to Output Valid
ns
ns
ns
ns
ns
ns
3
tCLKH
tCLKL
tOE
6.65
6.65
6.8
6.8
8.0
8.0
11.25
11.25
20
2
2
10
10
4
3
15
15
5
3
17
17
6
tDF
tOEZ
Output Enable to Output High-Z (Note 2)
7.5
7.5
4
tEHQZ
tCEZ
tCES
Chip Enable to Output High-Z (Note 2)
CE# Setup Time to Clock
ns
ns
ns
tAAVS
ADV# Falling Edge to Address Valid (Note 1)
6.5
1
CLK
cycle
tAAVH
tRSTZ
Address Hold Time from Rising Edge of ADV#
RESET# Low to Output High-Z (Note 2)
Min
Max
Min
Min
Min
7.5
10
15
17
ns
ns
ns
ns
tWADVH1 ADV# Falling Edge to WE# Falling Edge
tWADVH2 ADV# Rising Edge to WE# Rising Edge
tWADVS WE# Rising Edge Setup to ADV# Falling Edge
0
10
11.75
Notes
1. Using the max t
and min t
specs together will result in incorrect data output.
ADVCS
AAVS
2. Not 100% tested
3. Recommended 50% Duty Cycle
60
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Figure 18.4 Burst Mode Read (x32 Mode)
tCES
tCEZ
CE#
CLK
tADVCS
ADV#
tAAVH
Aa
Addresses
Data
tBDH
tBACC
Da
Da+1
Da+2
Da + 3
Da + 7
tIACC
tAAVS
tOE
tOEZ
OE#
IND#
tINDS
tINDH
Figure 18.5 Synchronous Command Write/Read Timing
CE#
tCES
CLK
tADVCS
tADVP
ADV#
Valid Address
Addresses
Valid Address
tWC
Valid Address
tEHQZ
tADVCH
Data In
tWADVH1
Data Out
Data
tDF
tWADVH2
tOE
tDH
OE#
WE#
tDS
tWP
10 ns
tWADVS
IND/WAIT#
Note
All commands have the same number of cycles in both asynchronous and synchronous modes, including the READ/RESET command. Only
a single array access occurs after the F0h command is entered. All subsequent accesses are burst mode when the burst mode option is
enabled in the Configuration Register.
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18.4 Hardware Reset (RESET#)
Table 18.4 Hardware Reset (RESET#)
Parameter
JEDEC
Test
Setup
All Speed
Options
Std.
Description
Unit
RESET# Pin Low (During embedded Algorithms) to Read or
Write (See Note)
tREADY
Max
Min
11
µs
RESET# Pin Low (Not during embedded Algorithms) to Read or
Write (See Note)
tREADY2
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
Min
500
50
ns
ns
µs
ns
ns
RESET# High time Before Read (See Note)
RESET# Low to Standby Mode
20
RY/BY # Recovery Time
0
tREADY3
RESET # Active for Bank NOT Executing Algorithm
500
Note
Not 100% tested.
Figure 18.6 RESET# Timings
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tREADY2
Reset Timing to Bank NOT Executing Embedded Algorithm
Reset Timing to Bank Executing Embedded Algorithm
tREADY
RY/BY#
tRB
CE#, OE#
RESET#
tRP
62
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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18.5 Write Protect (WP#)
Figure 18.7 WP# Timing
Program/Erase Command
Data
WE#
tDS
tDH
tWP
tWPWS
Valid WP#
WP#
tBUSY
tWPRH
RY/BY#
18.6 Erase/Program Operations
Table 18.5 Erase/Program Operations
Parameter
All Speed
JEDEC
tAVAX
Std.
tWC
tAS
Description
Options
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
Min
Min
60
0
tAVWL
tWLAX
tDVWH
tWHDX
Address Setup Time
ns
tAH
tDS
tDH
Address Hold Time from WE# Falling Edge
Data Setup to WE# Rising Edge
Data Hold from WE# Rising Edge
11.75
18
ns
ns
2
ns
Read Recovery Time Before Write
(OE# High to WE# Low, WE# Hold Time) (Note 1)
tGHWL
tWEH
Min
0
ns
tOEP
tCS
OE# Pulse Width (Note 1)
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
Min
Min
Max
Min
Max
16
0
ns
ns
ns
ns
ns
µs
sec.
µs
ns
ns
ns
ns
tELWL
tWHEH
tCH
CE# Hold Time
0
tWLWH
tWHWL
tWHWH1
tWHWH2
tWP
tWPH
WE# Width
25
30
9
Write Pulse Width High
tWHWH1 Programming Operation (Note 2), Double-Word
tWHWH2 Sector Erase Operation (Note 2)
0.5
50
0
tVCS
tRB
VCC Setup Time (Note 1)
Recovery Time from RY/BY# (Note 1)
tBUSY
tWPWS
tWPRH
RY/BY# Delay After WE# Rising Edge (Note 1)
WP# Setup to WE# Rising Edge with Command (Note 1)
WP# Hold after RY/BY# Rising Edge (Note 1)
90
20
2
Notes
1. Not 100% tested.
2. See Command Definitions on page 75 for more information.
3. Program Erase Parameters are the same, regardless of Synchronous or Asynchronous mode.
October 11, 2012 S29CD-J_CL-J_00_B7
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D a t a S h e e t
Figure 18.8 Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
CE#
OE#
tCH
tAH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
tVCS
Note
PA = program address, PD = program data, D
is the true data at the program address.
OUT
64
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Figure 18.9 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tCH
OE#
tAH
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
tDH
In
Data
Complete
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Note
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 36).
Figure 18.10 Back-to-back Cycle Timings
tWC
Valid PA
tWC
tRC
tWC
Valid PA
Valid PA
Valid RA
Addresses
tAH
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
tWPH
WE#
tDF
tWPH
tDS
tOH
Valid
tDH
Valid
In
Valid
In
Valid
In
Data
Out
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
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Figure 18.11 Data# Polling Timings (During Embedded Algorithms)
‘
tWC
VA
tRC
Addresses
VA
tACC
tCE
VA
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Valid Data
Complement
Complement
True
Data
Status Data
True
Status Data
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 18.12 Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
tACC
tCE
VA
VA
VA
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
tBUSY
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
66
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations
Enter Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
WE#
Erase Suspend
Read
Erase Suspend
Program
Erase Suspend
Read
Erase
Erase
Erase
Complete
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings
CE#
CLK
ADV#
Addresses
OE#
VA
VA
tOE
tOE
Data
Status Data
Status Data
RDY
Notes
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
4. Data polling requires burst access time delay.
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Figure 18.15 Sector Protect/Unprotect Timing Diagram
V
IH
RESET#
SA, A6,
Valid*
Valid*
Valid*
A1, A0
Sector Protect/Unprotect
Verify
Data
60h
60h/68h**
40h/48h***
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Notes
* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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18.7 Alternate CE# Controlled Erase/Program Operations
Table 18.6 Alternate CE# Controlled Erase/Program Operations
Parameter
All Speed
Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Min
65
0
tAVEL
tELAX
tDVEH
tAH
tDS
45
35
2
16 Mb
32 Mb
tEHDX
tDH
Data Hold Time
5
tGHEL
tWLEL
tEHWH
tGHEL Read Recovery Time Before Write (OE# High to WE# Low)
0
tWS
tWH
tWP
tCP
WE# Setup Time
WE# Hold Time
WE# Width
0
0
25
20
30
9
tELEH
tEHEL
CE# Pulse Width
CE# Pulse Width High
tCPH
tWHWH1 tWHWH1 Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
tWCKS WE# Rising Edge Setup to CLK Rising Edge
Double-Word
0.5
5
Notes
1. Not 100% tested.
2. See Command Definitions on page 75 for more information.
October 11, 2012 S29CD-J_CL-J_00_B7
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Figure 18.16 Alternate CE# Controlled Write Operation Timings
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
PA
Addresses
tAS
tWC
tAH
tWH
tWP
WE#
OE#
tWPH
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
= data written to the device.
OUT
2. Figure indicates the last two bus cycles of the command sequence.
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S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
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18.8 Erase and Programming Performance
Table 18.7 Erase and Programming Performance
Typ
(Note 1)
Max
(Note 2)
Parameter
Sector Erase Time
Unit
Comments
0.5
5
s
Excludes 00h programming prior to erasure
16 Mb = 23
32 Mb = 46
16 Mb = 230
32 Mb = 460
(Note 4)
Chip Erase Time
s
Double Word Program Time
8
8
130
130
µs
µs
Accelerated Double Word Program Time
16 Mb = 5
32 Mb = 10
16 Mb = 50
32 Mb = 100
Excludes system level overhead (Note 5)
Accelerated Chip Program Time
s
s
16 Mb = 12
32 Mb = 24
16 Mb = 120
32 Mb = 240
Chip Program Time, x32 (Note 3)
Notes
1. Typical program and erase times assume the following conditions: 25°C, 2.5V V , 100K cycles. Additionally, programming typicals assume checkerboard
CC
pattern.
2. Under worst case conditions of 145°C, V = 2.5V, 1M cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20.1 and Table 20.2 for further
information on command definitions.
6. PPBs have a program/erase cycle endurance of 100 cycles.
7. Guaranteed cycles per sector is 100K minimum.
18.9 PQFP and Fortified BGA Pin Capacitance
Table 18.8 PQFP and Fortified BGA Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
7.5
12
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
8.5
7.5
pF
9
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
October 11, 2012 S29CD-J_CL-J_00_B7
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19. Appendix 1
19.1 Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system
can read CFI information at the addresses given in Table 19.1-Table 19.3. In order to terminate reading CFI
data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Table 19.1-
Table 19.3. The system must write the reset command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact a Spansion
representative for copies of these documents.
Table 19.1 CFI Query Identification String
Addresses
Data
Description
Query Unique ASCII string QRY
10h
11h
12h
0051h
0052h
0059h
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
0000h
0000h
Table 19.2 CFI System Interface String
Addresses
Data
Description
V
CC Min. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Bh
1Ch
(see description)
0025h = S29CD-J devices
0030h = S29CL-J devices
V
CC Max. (write/erase)
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
(see description)
0027h = S29CD-J devices
0036h = S29CL-J devices
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
0000h
0000h
0004h
0000h
0009h
0000h
0005h
0000h
0007h
0000h
V
PP Min. voltage (00h = no VPP pin present)
PP Max. voltage (00h = no VPP pin present)
V
Typical timeout per single word/doubleword program 2N µs
Typical timeout for Min. size buffer program 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for word/doubleword program 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
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Table 19.3 Device Geometry Definition
Addresses
Data
Description
Device Size = 2N byte
0015h = 16 Mb device
0016h = 32 Mb device
27h
(see description)
Flash Device Interface description (for complete description, please refer to CFI
publication 100)
0000 = x8-only asynchronous interface
28h
29h
0003h
0000h
0001 = x16-only asynchronous interface
0002 = supports x8 and x16 via BYTE# with asynchronous interface
0003 = x 32-only asynchronous interface
0005 = supports x16 and x32 via WORD# with asynchronous interface
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte program = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
31h
32h
33h
34h
(See description)
0000h
(refer to the CFI specification or CFI publication 100)
Address 31h data:
0000h
0001h
001Dh = 16 Mb device
003Dh = 32 Mb device
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Table 19.4 CFI Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string PRI
43h
44h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (DQ1, DQ0)
00 = Required, 01 = Not Required
Silicon Revision Number (DQ5–DQ2)
0000 = CS49
0001 = CS59
45h
000Ch
0010 = CS99
0011 = CS69
0100 = CS119
Erase Suspend (1 byte)
00 = Not Supported
01 = To Read Only
46h
0002h
02 = To Read and Write
Sector Protect (1 byte)
00 = Not Supported, X = Number of sectors in per group
47h
48h
0001h
0000h
Temporary Sector Unprotect
00h = Not Supported, 01h = Supported
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Table 19.4 CFI Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Addresses
Data
Description
Sector Protect/Unprotect scheme (1 byte)
01 =29F040 mode, 02 = 29F016 mode
03 = 29F400 mode, 04 = 29LV800 mode
49h
0006h
05 = 29BDS640 mode (Software Command Locking)
06 = BDD160 mode (New Sector Protect)
07 = 29LV800 + PDL128 (New Sector Protect) mode
Simultaneous Read/Write (1 byte)
00h = Not Supported, X = Number of sectors in all banks except Bank 1
4Ah
4Bh
4Ch
4Dh
4Eh
0037h
0001h
0000h
00B5h
00C5h
Burst Mode Type
00h = Not Supported, 01h = Supported
Page Mode Type
00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
ACC (Acceleration) Supply Maximum
00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
Top/Bottom Boot Sector Flag (1 byte)
00h = Uniform device, no WP# control,
01h = 8 x 8 Kb sectors at top and bottom with WP# control
02h = Bottom boot device
4Fh
0001h
03h = Top boot device
04h = Uniform, Bottom WP# Protect
05h = Uniform, Top WP# Protect
If the number of erase block regions = 1, then ignore this field
Program Suspend
00 = Not Supported
01 = Supported
50h
51h
57h
0001h
0000h
0002h
Write Buffer Size
2(N+1) word(s)
Bank Organization (1 byte)
00 = If data at 4Ah is zero
XX = Number of banks
Bank 1 Region Information (1 byte)
XX = Number of Sectors in Bank 1
58h
59h
0017h
0037h
Bank 2 Region Information (1 byte)
XX = Number of Sectors in Bank 2
Bank 3 Region Information (1 byte)
XX = Number of Sectors in Bank 3
5Ah
5Bh
0000h
0000h
Bank 4 Region Information (1 byte)
XX = Number of Sectors in Bank 4
74
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
20. Appendix 2
20.1 Command Definitions
Table 20.1 Memory Array Command Definitions (x32 Mode)
Bus Cycles (Notes 1–4)
Third Fourth
Addr
First
Addr
Second
Fifth
Addr
Sixth
Addr
Command (Notes)
Read (5)
Data
RD
F0
Addr
Data
Addr
Data
Data
Data
Data
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
RA
XXX
555
555
555
555
555
BA
Reset (6)
Manufacturer ID
Device ID (8)
AA
AA
AA
AA
AA
B0
30
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
555
555
555
555
555
90
90
A0
80
80
BA+X00
BA+X01
PA
01
7E
PD
AA
AA
Autoselect
(7)
BA+X0E
09
BA+X0F
00/01
Program
Chip Erase
Sector Erase
555
2AA
2AA
55
55
555
SA
10
30
555
Program/Erase Suspend (9)
Program/Erase Resume (10)
CFI Query (11, 12)
BA
55
98
Accelerated Program (13)
Configuration Register Verify (12)
Configuration Register Write (14)
Unlock Bypass Entry (15)
Unlock Bypass Program (15)
Unlock Bypass Erase (15)
Unlock Bypass CFI (11, 15)
Unlock Bypass Reset (15)
Legend
XX
A0
AA
AA
AA
A0
80
PA
2AA
2AA
2AA
PA
PD
55
55
55
PD
10
555
555
555
XX
BA+555
555
C6
D0
20
BA+XX
XX
RD
WD
555
XX
XX
XX
98
XX
90
XX
00
BA = Bank Address. The set of addresses that comprise a bank. The system may RA = Read Address (Amax–A0).
write any address within a bank to identify that bank for a command.
PA = Program Address (Amax–A0). Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
RD = Read Data. Data DQmax–DQ0 at address location RA.
SA = Sector Address. The set of addresses that comprise a sector. The system
may write any address within a sector to identify that sector for a command.
WD = Write Data. See “Configuration Register” definition for specific write data.
Data latched on rising edge of WE#.
PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
Notes
1. See Table 8.1 for description of bus operations.
2. All values are in hexadecimal.
8. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in
the sixth cycle indicates ordering option 00, 01h indicates ordering option 01.
9. The system may read and program in non-erasing sectors when in the
Program/Erase Suspend mode. The Program/Erase Suspend command is
valid only during a sector erase operation, and requires the bank address.
3. Shaded cells in table denote read cycles. All other cycles are write
operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table)
address bits higher than A11 (except where BA is required) and data bits
higher than DQ7 are don’t cares.
10. The Program/Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
11. Command is valid when device is ready to read array data.
12. Asynchronous read operations.
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to the read mode (or to the erase-
suspend-read mode if previously in Erase Suspend) when a bank is in the
autoselect mode, or if DQ5 goes high (while the bank is providing status
information).
13. ACC must be at V during the entire operation of this command.
ID
14. Command is ignored during any Embedded Program, Embedded Erase, or
Suspend operation.
7. The fourth cycle of the autoselect command sequence is a read cycle. The
system must provide the bank address to obtain the manufacturer ID or
device ID information. See Autoselect on page 30 for more information.
15. The Unlock Bypass Entry command is required prior to any Unlock Bypass
operation. The Unlock Bypass Reset command is required to return to the
read mode.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
75
D a t a S h e e t
Table 20.2 Sector Protection Command Definitions (x32 Mode)
Bus Cycles (Notes 1–4)
First
Second
Third
Addr
Fourth
Fifth
Addr
Sixth
Addr
Command (Notes)
Addr Data Addr Data
Data
Addr
Data
Data
Data
Reset
1
3
4
XXX
555
555
F0
AA
AA
Secured Silicon Sector Entry
Secured Silicon Sector Exit
2AA
2AA
55
55
555
555
88
90
XX
00
68
Secured Silicon Protection
Bit Program (5, 6)
6
6
555
555
AA
AA
2AA
2AA
55
55
555
555
60
60
OW
OW
48
OW
RD(0)
Secured Silicon Protection Bit
Status
OW
RD(0)
Password Program (5, 7, 8)
Password Verify
4
4
5
6
6
4
3
4
4
4
4
6
6
6
6
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
38
C8
28
60
60
90
78
58
48
48
58
60
60
60
60
PWA[0-1]
PWA[0-1]
PWA[0-1]
SG+WP
WP
PWD[0-1]
PWD[0-1]
PWD[0-1]
68
Password Unlock (7, 8)
PPB Program (5, 6)
All PPB Erase (5, 9, 10)
PPB Status (11, 12)
PPB Lock Bit Set
PPB Lock Bit Status
DYB Write (7)
555
555
SG+WP
WP
48
40
SG+WP RD(0)
555
60
WP
RD(0)
BA+555
555
SA+X02
00/01
BA+555
555
SA
SA
SA
SA
PL
PL
SL
SL
RD(1)
X1
DYB Erase (7)
555
X0
DYB Status (12)
BA+555
555
RD(0)
68
PPMLB Program (5, 6)
PPMLB Status (5)
SPMLB Program (5, 6)
SPMLB Status (5)
Legend
PL
SL
48
48
PL
SL
RD(0)
RD(0)
555
RD(0)
68
555
555
RD(0)
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PPB = Persistent Protection Bit
SA = Sector Address. The set of addresses that comprise a sector. The system
may write any address within a sector to identify that sector for a command.
SG = Sector Group Address
BA = Bank Address. The set of addresses that comprise a bank. The system may
write any address within a bank to identify that bank for a command.
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111010)
PWA = Password Address. A0 selects between the low and high 32-bit portions
of the 64-bit Password
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, if
unprotected, DQ0 = 0.
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 = 1, if
unprotected, DQ1 = 0.
SPMLB = Persistent Protection Mode Locking Bit
Notes
1. See Table 8.1 for description of bus operations.
2. All values are in hexadecimal.
8. The entire four bus-cycle sequence must be entered for each portion of the
password.
9. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to
validate whether the bits have been fully erased. If DQ0 (in the sixth cycle)
reads 1, the erase command must be issued and verified again.
3. Shaded cells in table denote read cycles. All other cycles are write
operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table)
address bits higher than A11 (except where BA is required) and data bits
higher than DQ7 are don’t cares.
10. Before issuing the erase command, all PPBs should be programmed in order
to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set.
5. The reset command returns the device to reading the array.
12. The status of additional PPBs and DYBs may be read (following the fourth
cycle) without reissuing the entire command sequence.
6. The fourth cycle programs the addressed locking bit. The fifth and sixth
cycles are used to validate whether the bit has been fully programmed. If DQ0
(in the sixth cycle) reads 0, the program command must be issued and
verified again.
7. Data is latched on the rising edge of WE#.
76
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
21. Revision History
Section
Description
Revision A0 (March 1, 2005)
Initial release.
Revision A1 (April 15, 2005)
Ordering Information and Valid
Combinations tables
Updated to include lead Pb-free options.
Revision A2 (January 20, 2006)
Added “Contact factory” for 75 MHz. Modified Ordering Options for Characters 15 and 16 to reflect
autoselect ID and top/bottom boot. Changed “N” for Extended Temperature Range to “M”.
Ordering Information
Input/Output Descriptions
Additional Resources
Removed Logic Symbol Diagrams.
Added section.
Memory Address Map
Changed “Bank 2” to “Bank 1”.
Removed Ordering Options Table (Tables 3 and 4).
Simultaneous Read/Write Operation
Advanced Sector Protection/
Unprotection
Added Advanced Sector Protection/Unprotection figure. Added figures for PPB Erase and Program
Algorithm.
Electronic Marking
Added in Electronic Marking section.
Modified VCC Ratings to reflect 2.6 V and 3.6 V devices. Modified VCC Ratings to reflect 16 Mb and
32 Mb devices.
Absolute Maximum Ratings
AC Characteristics
Added Note “tOE during Read Array”.
Asynchronous Read Operation
Conventional Read Operation Timings
Changed values of tAVAV, tAVQV, tELQV, tGLQV in table.
Moved tDF line to 90% on the high-Z output in figure.
Added tAAVS and tAAVH timing parameters to table. Changed tCH to tCLKH. Changed tCL to tCLKL
Removed the following timing parameters:
.
• tDS (Data Setup to WE# Rising Edge)
• tDH (Data Hold from WE# Rising Edge)
• tAS (Address Setup to Falling Edge of WE#)
• tAH (Address Hold from Falling Edge of WE#)
• tCS (CE# Setup Time)
Burst Mode Read for 32 Mb and 16 Mb
• tCH (CE# Hold Time)
• tACS (Address Setup Time to CLK)
• tACH (Address Hold Time from ADV# Rising Edge of CLK while ADV# is Low)
Added the following timing parameters:
• tAAVS
• tDVCH
• tINDS
• tINDH
Burst Mode Read (x32 Mode)
Asynchronous Command Write Timing In figure, changed tOEH to tWEH; changed tWPH to tOEP
.
Synchronous Command Write/Read
Timing
Removed tWADVH and tWCKS from figure.
In figure, changed tCH to tBUSY
WP# Timing
In table, added Note 3: Program/Erase parameters are the same regardless of synchronous or
asynchronous mode. Added tOEP (OE# High Pulse)
Erase/Program Operations
Alternative CE# Controlled Erase/
Program Operations
Removed tOES from table. Added tWADVS and tWCKS
Appendix 2: Command Definitions
Revision B0 (June 12, 2006)
Global
Removed “or when device is in autoselect mode” from Note 14.
Changed document status to Preliminary.
Distinctive Characteristics
Performance Characteristics
Ordering Information
Changed cycling endurance from typical to guaranteed.
Updated Max Asynch. Access Time, Max CE# Access Time, and Max OE# Access time in table.
Updated additional ordering options in designator breakout table. Updated valid combination tables.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
77
D a t a S h e e t
Section
Description
Input/Output Descriptions and Logic
Symbols
Changed RY/BY# description.
Physical Dimensions/Connection
Diagrams
Changed note on connection diagrams.
Additional Resources
Hardware Reset (RESET#)
Autoselect
Updated contact information.
Added section.
Updated third and fourth paragraphs in section. Updated Autoselect Codes table.
Modified second paragraph. Replaced allowable operations table with bulleted list.
Erase Suspend / Erase Resume
Commands
Program Suspend / Program Resume
Commands
Replaced allowable operations table with bulleted list.
Added section.
Reset Command
Secured Silicon Sector Flash Memory
Region
Modified Secured Silicon Sector Addresses table.
Absolute Maximum Ratings
Operating Ranges
Modified VCC and VIO ratings. Modified Note 1.
Modified specification titles and descriptions (no specification value changes).
DC Characteristics, CMOS Compatible
table
Modified ICCB specification. Deleted Note 5. Added Note 3 references to table.
Burst Mode Read for 32 Mb and 16 Mb Modified tADVCS, tCLKH, tCLKL, tAAVS specifications. Added tRSTZ, tWADVH1, and tWADVH2
table
specifications. Added Notes 2 and 3, and note references to table.
Synchronous Command Write/Read
Timing figure
Added tWADVH1 and tWADVH2 to figure. Deleted tACS and tACH from figure.
Hardware Reset (RESET#)
Added table to section.
Erase/Program Operations table
Erase and Programming Performance
Added note references. Deleted tOEP specification.
Changed Double Word Program Time specification.
CFI System Interface String table: Changed description and data for addresses 1Bh and 1Ch.
Device Geometry Definition table: Changed description and data for address 27h.
Common Flash Memory Interface (CFI)
Revision B1 (September 27, 2006)
Global
Data sheet format reorganized.
Distinctive Characteristics
Performance Characteristics
Ordering Information
Changed cycling endurance specification to typical.
Changed tBACC specifications for 66 MHz, 56 MHz, 40 MHz speed options.
Added quantities to packing type descriptions, restructured table for easier reference.
S29CD-J and S29CL-J Flash Family
Autoselect Codes (High Voltage
Method)
In table, modified description of read cycle 3 DQ7–DQ0.
DQ6 and DQ2 Indications
In table, corrected third column heading
Added table.
Section 8.9, Reset Command
Section 13.1, Absolute Maximum
Ratings
Deleted OE# from section.
Table 18.3, Burst Mode Read for 32 Mb In table, changed tADVCS, tBDH specifications. Modified description for tIACC. Deleted minimum
and 16 Mb
specifications for tAAVH.
Burst Mode Read (x32 Mode)
Revision B2 (March 7, 2007)
Distinctive Characteristics
In figure, modified period for tIACC in drawing.
Corrected number of 16K sectors in 16 Mb devices. Modified read access times table.
Changed boot sector option part number designators. Changed valid combinations. Modified 10th
character option descriptions.
Ordering Information
Block Diagram
Deleted WORD# input.
2-, 4-, 8- Double Word Linear Burst
Operation
In 32- Bit Linear and Burst Data Order table, deleted reference to WORD# input.
Modified second paragraph; added reference to application note.
Sector Erase
78
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Section
Description
Advanced Sector Protection/
Unprotection
Modified Advanced Sector Protection/Unprotection figure and notes. In some subsections, changed
“sector” to “sector group”.
DC Characteristics
Test Specifications
Changed ICCB test conditions and ICC1 maximum specification.
Changed CL.
Asynchronous Command Write Timing figure: Added note.
Asynchronous Operations
Synchronous Operations
Asynchronous Read Operations table: Changed tRC, tACC, tCE for 75 MHz device.
Burst Mode Read for 32 Mb and 16 Mb table: Changed tINDS, tCLKL, tAAVH, and tWADVH1
specifications.
Burst Mode Read figure: Modified period lengths for several specifications.
Added tWEH and tOEP specifications to table.
Deleted section.
Erase/Program Operations
Latchup Characteristics
CFI System Interface String table: Modified description of address 1Bh.
Common Flash Memory Interface (CFI)
Revision B3 (March 30, 2009)
Global
CFI Primary Vendor-Specific Extended Query table: Modified data at address 45h.
Removed “Preliminary”
Changed all instances of VCCQ to VIO
Distinctive Characteristics
Performance Characteristics
Removed “or without” (wrap around) from Programmable Burst Interface bullet
Added notice to refer to programming best practices application note for 32 Mb devices.
Added S29CL032J to valid OPN diagram.
Corrected valid combinations table.
Ordering Information
Subscript CC for VCC, IO for VIO, SS for VSS in table.
Changed type for VIO to “Supply”
Input/Output Descriptions and Logic
Symbols
Changed type for VSS to “Supply”
Removed DQmax-DQ0 label from inputs to Burst Address Counter and Address Latch.
Removed Amax-A0 label from I/O Buffers.
Block Diagram
Table: S29CD016J/CL016J (Top Boot)
Sector and Memory Address Map
Changed Note 2 to refer to Bank 0 and 1 instead of Bank 1 and 2.
Removed “x16”
Table: 32-Bit Linear and Burst Data
Order
Removed “A0:A-1” from Output Data Sequence column for Four Linear Data Transfers.
Removed “A1:A-1” from Output Data Sequence column for Eight Linear Data Transfers.
Programming
Added notice to refer to programming best practices application note for 32 Mb devices.
Changed Max ICCB for S29CL-J to 90 mA.
Table: DC Characteristic, CMOS
Compatible
Corrected values for tBDH with separate values for 16Mb and 32Mb.
Added tWADVS parameter to table.
Table: Burst Mode for 32 Mb and 16 Mb
Figure: Synchronous Command Write/
Read Timing
Added timing definition for tWADVS
.
Appended “from WE# Rising Edge” to tAH description.
Changed tAH Min to 11.75 ns.
Table: Erase/Program Operations
Figure: Program Operation Timings
Updated timing diagram to reflect new tAH value.
Updated timing diagram to reflect new tAH value.
Figure: Chip/Sector Erase Operation
Timings
Table: Alternate CE# Controlled Erase/
Program Operations
Removed tWADVS parameter.
Product Overview
Removed “or without”.
Table: Device Bus Operation
Changed “X” to “H” under CLK column for CE# row.
Accelerated Program and Erase
Operations
Removed all mention of accelerated erase.
Unlock Bypass
Removed mention of unlock bypass sector erase.
Simultaneous Read/Write
Added in warning to indicate restrictions on Simultaneous Read/Write conditions.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
79
D a t a S h e e t
Section
Description
VCC and VIO Power-up And Power-
down Sequencing
Added reference to timing section.
Changed Vcc ± 0.2V to Vcc ± 10%.
Standby Mode
Figure: Test Setup
Removed Note “Diodes are IN3064 or equivalent”.
Table: Alternate CE# Controlled Erase/
Program Operations
Corrected values for tDH with separate values for 16 Mb and 32 Mb.
Table: Memory Array Command
Definitions (x32 Mode)
Cleaned up Notes.
Revision B4 (October 30, 2009)
Absolute Maximum Ratings
DC Characteristics
Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings
between CL016L, CL032J, CD016J, and CD032J.
Added line item to distinguish VIHCLK value differences between CL-J and CD-J.
Corrected Figure “Burst Mode Read (x32 Mode)” to reflect max linear burst length of 8 double words
instead of 32.
Synchronous Operation
Corrected Table “Burst Initial Access Delay”: changed tREADY2, tRP, and tREADY3 set up to Min
instead of Max.
Hardware Reset (RESET#)
Corrected Figure “RESET# Timings” to add tREADY2 to timing diagram for bank not executing
embedded algorithm.
Revision B5 (May 25, 2011)
Physical Dimensions/Connection
Diagrams
On the 80-ball Fortified BGA Connection Diagram, corrected the K1 pin name from VCCQ to VIO
.
Revision B6 (March 15, 2012)
Global
Added LAD080 Fortified BGA package option and drawing.
Updated relevant application note links.
Additional Resources
Revision History
Corrected heading for May 25, 2011 edits from revision B4 to B5.
Revision B7 (October 11, 2012)
Updated Valid Combinations table to add clarity and make explicit which offerings require a
customer to “contact factory for availability”.
Valid Combinations
In Figure 18.3, “Asynchronous Command Write Timing”, corrected the tWC measurement to be of
the Stable Address period, not the Valid Data period.
Asynchronous Operations
In Table 18.5, “Erase/Program Operations”, corrected JEDEC symbol tAVAV to tAVAX
In Table 18.5, merged redundant rows tGHWL and tWEH
.
.
Erase/Program Operations
In Figures 18.8 “Program Operation Timings” and 18.9 “Chip/Sector Erase Operation Timings”,
corrected tAH measurement to be from the falling edge of WE#.
80
S29CD-J and S29CL-J Flash Family
S29CD-J_CL-J_00_B7 October 11, 2012
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2005–2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and
combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used
are for informational purposes only and may be trademarks of their respective owners.
October 11, 2012 S29CD-J_CL-J_00_B7
S29CD-J and S29CL-J Flash Family
81
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