S29GL032M10TFIR53 [SPANSION]
MirrorBit Flash Family; 的MirrorBit闪存系列
| 型号： | S29GL032M10TFIR53 |
| 厂家： | 
SPANSION |
| 描述： | MirrorBit Flash Family |
| 文件： | 总159页 (文件大小：5249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29GLxxxM MirrorBitTM Flash Family
S29GL256M, S29GL128M, S29GL064M, S29GL032M
256 Megabit, 128 Megabit, 64 Megabit, and 32Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
0.23 um MirrorBit process technology
Datasheet
DATASHEET
Distinctive Characteristics
Package options
— 40-pin TSOP
— 48-pin TSOP
— 56-pin TSOP
— 64-ball Fortified BGA
— 48-ball fine-pitch BGA
— 63-ball fine-pitch BGA
Architectural Advantages
Single power supply operation
— 3 volt read, erase, and program operations
Manufactured on 0.23 um MirrorBit process
technology
SecSi™ (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
Software & Hardware Features
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— 256Mb: 512 32 Kword (64 Kbyte) sectors
— 128Mb: 256 32 Kword (64 Kbyte) sectors
— 64Mb (uniform sector models): 128 32 Kword (64
Kbyte) sectors or 128 32 Kword sectors
— Unlock Bypass Program command reduces overall
multiple-word programming time
— 64Mb (boot sector models): 127 32 Kword (64 Kbyte)
sectors + 8 4Kword (8Kbyte) boot sectors
Hardware features
— 32Mb (uniform sector models): 64 32Kword (64
Kbyte) sectors of 64 32Kword sectors
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
— 32Mb (boot sector models): 63 32Kword (64 Kbyte)
sectors + 8 4Kword (8Kbyte) boot sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
100,000 erase cycles typical per sector
20-year data retention typical
Performance Characteristics
High performance
— 90 ns access time (128Mb, 64Mb, 32Mb),
100 ns access time (256Mb)
— 4-word/8-byte page read buffer
— 25 ns page read times (128Mb, 64Mb, 32Mb)
— 30 ns page read times (256Mb)
— 16-word/32-byte write buffer
— 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Low power consumption (typical values at 3.0 V, 5
MHz)
— 18 mA typical active read current (64 Mb, 32 Mb)
— 25 mA typical active read current (256 Mb, 128 Mb)
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Publication Number S29GLxxxM Revision B Amendment 3 Issue Date Octorber 18, 2004
D a t a s h e e t
General Description
The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufactured using 0.23
um MirrorBit technology. The S29GL256M is a 256 Mbit, organized as 16,777,216 words or 33,554,432 bytes. The
S29GL128M is a 128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The S29GL064M is a 64 Mbit, or-
ganized as 4,194,304 words or 8,388,608 bytes. The S29GL032M is a 32 Mbit, organized as 2,097,152 words or
4,194,304 bytes. Depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide data
bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The
devices can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M) are available. Note
that each access time has a specific operating voltage range (V ) as specified in the Product Selector Guide and
CC
the Ordering Information sections. Package offerings include 40-pin TSOP, 48-pin TSOP, 56-pin TSOP, 48-ball fine-
pitch BGA, 63-ball fine-pitch BGA and 64-ball Fortified BGA, depending on model number. Each device has sepa-
rate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V
CC
input, a high-voltage accelerated program (ACC) feature provides shorter programming times through in-
creased current on the WP#/ACC input. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com-
mands are written to the device using standard microprocessor write timing. Write cycles also internally latch
addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation
starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the
Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an
Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data
instead of four.
Hardware data protection measures include a low V detector that automatically inhibits write operations dur-
CC
ing power transitions. The hardware sector protection feature disables both program and erase operations in any
combination of sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector
to read or program any other sector and then complete the erase operation. The Program Suspend/Program
Resume feature enables the host system to pause a program operation in a given sector to read any other sector
and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus
also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and
RESET#, or when addresses are stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin
or WP# pin, depending on model number. The protected sector is still protected even during accelerated
programming.
The SecSi™ (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be perma-
nently protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
2
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
Table of Contents
Table 17. S29GL256M Sector Address Table ..........................68
Autoselect Mode ................................................................................................ 79
Table 18. Autoselect Codes, (High Voltage Method) ...............80
Sector Group Protection and Unprotection .............................................. 81
Table 19. S29GL032M (Model R0) Sector Group Protection/Unpro-
tection Address Table .........................................................81
Table 20. S29GL032M (Models R1, R2) Sector Group Protection/Un-
protection Address Table .....................................................81
Table 21. S29GL032M (Models R3, R5) Sector Group Protection/Un-
protection Address Table .....................................................82
Table 22. S29GL032M (Models R4, R6) Sector Group Protection/Un-
protection Address Table .....................................................83
Table 23. S29GL064M (Model 00) Sector Group Protection/Unpro-
tection Address Table ........................................................84
Table 24. S29GL064M (Models R1, R2, R8, R9) Sector Group Protec-
tion/Unprotection Address Table ..........................................85
Table 25. S29GL064M (Model R3) Sector Group Protection/Uprotec-
tion Address Table .............................................................86
Table 26. S29GL064M (Model R4) Sector Group Protection/Unpro-
tection Address Table .........................................................87
Table 27. S29GL064M (Model R5) Sector Group Protection/Unpro-
tection Address Table ........................................................88
Table 28. S29GL064M (Models R6, R7) Sector Group Protection/Un-
protection Address Table ....................................................89
Table 29. S29GL128M Sector Group Protection/Unprotection
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
S29GL256M .............................................................................................................5
S29GL128M ..............................................................................................................5
S29GL064M .............................................................................................................5
S29GL032M .............................................................................................................5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7
For S29GL064M (model R0) only. ...................................................................9
For S29GL064M (model R0) only. ..................................................................13
Logic Symbol-S29GL032M (Model R0) ..........................................................17
Logic Symbol-S29GL032M (Models R1, R2) ..................................................17
Logic Symbol-S29GL032M (Models R3, R4, R5, R6) ..................................17
Logic Symbol-S29GL064M (Models R0) .......................................................18
Logic Symbol-S29GL064M (Models R1, R2, R8, R9) .................................18
Logic Symbol-S29GL064M (Models R3, R4) ...............................................18
Logic Symbol-S29GL064M (Model R5) ......................................................... 19
Logic Symbol-S29GL064M (Model R6, R7) ................................................. 19
Logic Symbol-S29GL128M ................................................................................. 19
Logic Symbol-S29GL256M ...............................................................................20
Ordering Information-S29GL032M . . . . . . . . . . . . 21
S29GL032M Standard Products ...................................................................... 21
Table 1. S29GL032M Ordering Options ................................. 22
Ordering Information-S29GL064M . . . . . . . . . . . .23
S29GL064M Standard Products ......................................................................23
Table 2. S29GL064M Ordering Options ................................. 24
Ordering Information-S29GL128M . . . . . . . . . . . .25
S29GL128M Standard Products .......................................................................25
Table 3. S29GL128M Ordering Options ................................. 26
Ordering Information-S29GL256M . . . . . . . . . . . .27
S29GL256M Standard Products ......................................................................27
Table 4. S29GL256M Ordering Options ................................. 28
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .29
Table 5. Device Bus Operations ........................................... 29
Word/Byte Configuration ................................................................................30
Requirements for Reading Array Data ........................................................ 30
Page Mode Read ............................................................................................. 30
Writing Commands/Command Sequences ................................................ 30
Write Buffer .................................................................................................... 30
Accelerated Program Operation ................................................................31
Autoselect Functions ......................................................................................31
Standby Mode ........................................................................................................31
Automatic Sleep Mode .......................................................................................31
RESET#: Hardware Reset Pin ..........................................................................31
Address Table ....................................................................90
Table 30. S29GL256M Sector Group Protection/Unprotection
Address Table ....................................................................92
Temporary Sector Group Unprotect ..........................................................95
Figure 1. Temporary Sector Group Unprotect Operation.......... 95
Figure 2. In-System Sector Group Protect/Unprotect Algorithms 96
SecSi (Secured Silicon) Sector Flash Memory Region ............................. 97
Write Protect (WP#) .......................................................................................98
Hardware Data Protection .............................................................................98
Low VCC Write Inhibit ...............................................................................98
Write Pulse “Glitch” Protection ...............................................................98
Logical Inhibit ...................................................................................................98
Power-Up Write Inhibit ...............................................................................98
Common Flash Memory Interface (CFI) . . . . . . . 99
Table 32. System Interface String...................................... 100
Command Definitions . . . . . . . . . . . . . . . . . . . . . .103
Reading Array Data ..........................................................................................103
Reset Command ................................................................................................103
Autoselect Command Sequence ..................................................................104
Enter SecSi Sector/Exit SecSi Sector Command Sequence ..................104
Word Program Command Sequence .....................................................104
Unlock Bypass Command Sequence .......................................................105
Write Buffer Programming ........................................................................105
Accelerated Program ...................................................................................106
Figure 3. Write Buffer Programming Operation..................... 107
Figure 4. Program Operation ............................................. 108
Program Suspend/Program Resume Command Sequence .................. 108
Figure 5. Program Suspend/Program Resume...................... 109
Chip Erase Command Sequence ..................................................................109
Sector Erase Command Sequence ................................................................110
Figure 6. Erase Operation ................................................. 111
Erase Suspend/Erase Resume Commands ...................................................111
Output Disable Mode ........................................................................................32
Table 6. S29GL032M (Model R0) Sector Address Table ........... 32
Table 7. S29GL032M (Models R1, R2) Sector Address Table .... 34
Table 8. S29GL032M (Models R3, R5) Top Boot Sector Architecture
36
Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Architec-
ture ................................................................................. 38
Table 10. S29GL064M (Model R0) Sector Address Table ......... 40
Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Address Table
44
Table 12. S29GL064M (Model R3) Top Boot Sector Architecture 48
Table 13. S29GL064M (Model R4) Bottom Boot Sector Architecture
52
Table 14. S29GL064M (Model R5) Sector Address Table ......... 56
Table 15. S29GL064M (Model R6, R7) Sector Address Table .... 59
Table 16. S29GL128M Sector Address Table ......................... 62
Command Definitions ........................................................................................113
Table 35. Command Definitions (x16 Mode, BYTE# = VIH) ....113
Table 36. Command Definitions (x8 Mode, BYTE# = VIL) .......114
Write Operation Status ................................................................................... 115
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
3
133
DQ7: Data# Polling ........................................................................................... 115
Figure 7. Data# Polling Algorithm....................................... 116
RY/BY#: Ready/Busy# ......................................................................................116
DQ6: Toggle Bit I ...............................................................................................117
Figure 8. Toggle Bit Algorithm............................................ 118
DQ2: Toggle Bit II ...............................................................................................119
Reading Toggle Bits DQ6/DQ2 .....................................................................119
DQ5: Exceeded Timing Limits .......................................................................119
DQ3: Sector Erase Timer ................................................................................119
DQ1: Write-to-Buffer Abort .........................................................................120
Table 37. Write Operation Status ........................................120
Figure 9. Maximum Negative Overshoot Waveform............... 121
Figure 10. Maximum Positive
Figure 20. Toggle Bit Timings (During Embedded Algorithms) 134
Figure 21. DQ2 vs. DQ6.................................................... 134
Temporary Sector Unprotect .......................................................................134
Figure 22. Temporary Sector Group Unprotect Timing Diagram 135
Figure 23. Sector Group Protect and Unprotect Timing Diagram 135
Alternate CE# Controlled Erase and Program Operations-S29GL256M
136
Alternate CE# Controlled Erase and Program Operations-S29GL128M
137
Alternate CE# Controlled Erase and Program Operations-S29GL064M
138
Alternate CE# Controlled Erase and Program Operations-S29GL032M
139
Overshoot Waveform........................................................ 121
Figure 24. Alternate CE# Controlled Write (Erase/
Program) Operation Timings.............................................. 140
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 121
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 122
Erase and Programming Performance . . . . . . . . 141
TSOP Pin and BGA Package Capacitance . . . . .142
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . .143
TS040—40-Pin Standard Thin Small Outline Package ...........................143
TSR040—40-Pin Standard/Reverse Thin Small Outline Package (TSOP)
144
TS048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)
145
TSR048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)
146
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package
(TSOP) ..................................................................................................................147
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ..............................148
LAC064—64-Pin 18 x 12 mm package .........................................................149
FBA048—48-Pin 6.15 x 8.15 mm package ...................................................150
FBC048—48-Pin 8 x 9 mm package ............................................................151
FBE063—63-Pin 12 x 11 mm package ............................................................152
FPT-48P-M19 ....................................................................................................... 153
FPT-56P-M01 ....................................................................................................... 153
FBG048—48-pin 8 x 6 mm package ...........................................................154
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .155
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 11. Test Setup ....................................................... 123
Table 38. Test Specifications ..............................................123
Key to Switching Waveforms . . . . . . . . . . . . . . 123
Figure 12. Input Waveforms and
Measurement Levels......................................................... 123
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 124
Read-Only Operations-S29GL256M only ..................................................124
Read-Only Operations-S29GL128M only ...................................................124
Read-Only Operations-S29GL064M only .................................................. 125
Read-Only Operations-S29GL032M only .................................................. 125
Figure 13. Read Operation Timings..................................... 126
Figure 14. Page Read Timings............................................ 126
Hardware Reset (RESET#) ............................................................................. 127
Figure 15. Reset Timings................................................... 127
Erase and Program Operations-S29GL256M only ..................................128
Erase and Program Operations-S29GL128M Only .................................129
Erase and Program Operations-S29GL064M Only ................................130
Erase and Program Operations-S29GL032M only ....................................131
Figure 16. Program Operation Timings................................ 132
Figure 17. Accelerated Program Timing Diagram .................. 132
Figure 18. Chip/Sector Erase Operation Timings................... 133
Figure 19. Data# Polling Timings (During Embedded Algorithms) .
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S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Product Selector Guide
S29GL256M
Part Number
S29GL256M
Speed Option
10
100
100
30
11
110
110
30
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
30
S29GL128M
Part Number
S29GL128M
Speed Option
90
90
90
25
25
10
100
100
30
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
S29GL064M
Part Number
S29GL064M
Speed Option
90
90
90
25
25
10
100
100
30
11
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
110
110
30
30
30
S29GL032M
Part Number
S29GL032M
Speed Option
90
90
90
25
25
10
100
100
30
11
110
110
30
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
30
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
5
D a t a s h e e t
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
AMax**–A0
** AMax GL256M = A23
A
A
A
Max GL128M = A22
Max GL064M = A21 (AMax GL064M-00 = A22)
Max GL032M = A20 (AMax GL032M-00 = A21)
6
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Connection Diagrams
A17
VSS
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
40-Pin Standard TSOP
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
7
D a t a s h e e t
Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
A8
48-Pin Standard TSOP
2
A19
9
A20
WE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RESET#
1,2
A21
2
2
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Notes:
1. Pin 13 is NC on S29GL032M.
2. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is VIO on S29GL064M (models R6, R7).
8
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Connection Diagrams
For S29GL064M (model R0) only.
NC
NC
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
NC
A22
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin Standard TSOP
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
ACC
RY/BY#
A18
A7
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
NC
NC
A6
A5
A4
A3
A2
A1
NC
NC
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
9
D a t a s h e e t
Connection Diagrams
1
2
A23
A22
1
2
3
4
5
6
7
8
9
56 NC
55 NC
54 A16
53 BYTE#
52 VSS
A15
A14
A13
A12
A11
A10
A9
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
56-Pin Standard TSOP
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A213 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
A1 26
32 CE#
31 A0
NC 27
30 NC
NC 28
29 VIO
Notes:
1. Pin 1 is NC on S29GL128M, 29GL064M, and S29GL032M.
2. Pin 2 is NC on S29GL064M, and S29GL032M.
3. Pin 15 is NC on S29GL032M.
10
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Connection Diagrams
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
4
A222
A233
VIO
VSS
NC
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
BYTE#5 DQ15/A-1
VSS
A13
A12
A14
A15
A16
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET# A211
A19
DQ5
DQ12
DQ4
VCC
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
B1
C1
D1
E1
F1
G1
NC
H1
4
NC
NC
NC
NC
NC
NC
VIO
Notes:
1. Ball C5 is NC on S29GL032M.
2. Ball B8 is NC on S29GL064M and S29GL032M.
3. Ball C8 is NC on S29GL128M, S29GL064M and S29GL032M.
4. Ball D8 and Ball F1 are NC on S29GL064M (models R3, R4) and S29GL032M (models R3, R4, R5, R6).
5. Ball F7 is NC on S29GL064M (model R5).
Special Package Handling Instructions
Special handling is required for Flash Memory products in moulded packages (TSOP and BGA). The package and/
or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
11
D a t a s h e e t
Connection Diagrams
63-Ball Fine-Pitch BGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC*
NC*
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
BYTE#1 DQ15/A
-1
VSS
NC*
NC*
NC*
NC*
A13
A12
A14
A15
A16
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
C4 D4
E4
F4
G4
H4
J4
K4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A17
DQ0
DQ8
DQ9
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
L2
M2
A2
VSS
CE#
OE#
NC*
NC*
NC*
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Notes:
1. Ball H7 is VIO on S29GL064M (model R5).
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/
or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
12
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Connection Diagrams
For S29GL064M (model R0) only.
63-Ball Fine-Pitch BGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC*
NC*
NC*
NC*
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
A7
B7
A14
A13
A15
A16
A17
NC
A20
V
SS
NC*
NC*
NC*
NC*
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A11
A12
A19
A10
DQ6
DQ7
C5
D5
E5
F5
G5
H5
J5
K5
WE# RESET# A22
NC
DQ5
NC
V
DQ4
CC
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY# ACC
NC
NC
DQ2
DQ3
V
A21
IO
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A18
DQ0
NC
NC
DQ1
A2
L2
M2
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
NC*
CE#
OE#
V
NC*
NC*
SS
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/
or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
13
D a t a s h e e t
Connection Diagrams
48-ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
VCC
WE# RESET#
NC
A19
DQ5
DQ12
DQ4
A3 B3
C3
D3
E3
F3
G3
H3
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
VSS
CE#
OE#
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/
or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
14
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Connection Diagrams
For S29GL032M (model R0) only.
48-Ball Fine-Pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A14
A13
A15
A16
A17
NC
A20
V
SS
A5
A9
B5
A8
C5
D5
E5
F5
G5
D6
H5
D7
A11
A12
A19
A10
A4
B4
C4
D4
E4
D5
F4
G4
H4
D4
WE# RESET#
A3 B3
RY/BY# ACC
NC
NC
NC
V
CC
C3
D3
E3
D2
F3
D3
G3
H3
NC
NC
V
A21
IO
A2
A7
B2
C2
A6
D2
A5
E2
D0
F2
G2
NC
H2
D1
A18
NC
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
V
SS
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/
or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged
periods of time.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
15
D a t a s h e e t
Pin Description
A23–A0
A22–A0
A21–A0
A20–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
=
=
24 Address inputs
23 Address inputs
22 Address inputs
21 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
CE#
OE#
WE#
WP#/ACC
=
=
=
=
Hardware Write Protect input/Programming
Acceleration input
ACC
WP#
RESET#
RY/BY#
BYTE#
=
=
=
=
=
=
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Device Ground
V
CC
V
=
=
=
SS
NC
Pin Not Connected Internally
Output Buffer Power
V
IO
16
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Logic Symbol-S29GL032M (Model R0)
22
A21–A0
8
DQ7–DQ0
CE#
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol-S29GL032M (Models R1, R2)
21
A20–A0
16 or 8
DQ15–DQ0
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Logic Symbol-S29GL032M (Models R3, R4, R5, R6)
21
A20–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
RY/BY#
BYTE#
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
17
D a t a s h e e t
Logic Symbol-S29GL064M (Models R0)
23
A22–A0
8
DQ7–DQ0
(A-1)
CE#
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol-S29GL064M (Models R1, R2, R8, R9)
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
VIO
RY/BY#
Logic Symbol-S29GL064M (Models R3, R4)
22
A21–A0
16 or 8
DQ15–DQ0
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
BYTE#
RY/BY#
18
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Logic Symbol-S29GL064M (Model R5)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
ACC
RESET#
VIO
RY/BY#
Logic Symbol-S29GL064M (Model R6, R7)
22
A21–A0
16
DQ15–DQ0
CE#
OE#
WE#
WP#
ACC
RESET#
VIO
Logic Symbol-S29GL128M
23
A22–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
VIO
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
19
D a t a s h e e t
Logic Symbol-S29GL256M
24
A23–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
VIO
RY/BY#
20
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Ordering Information-S29GL032M
S29GL032M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL032M
10
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R0
R1
=
=
x8, VCC=3.0-3.6V, Uniform sector device
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#/ACC=VIL
R2
R3
R4
R5
R6
=
=
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL, FBG048 package only
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL FBG048 package only
TEMPERATURE RANGE
I
=
=
Industrial (–40
°
C to +85
°
C)
C)
C
Commercial (0°C to +70
°
PACKAGE MATERIAL SET
A
F
B
C
=
=
=
=
Standard
Pb-Free
Standard
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL032M
32 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
21
D a t a s h e e t
Table 1. S29GL032M Ordering Options
S29GL032M Valid Combinations
Package Description
Device
Number
Speed
Option
Package, Material, &
Temperature Range
Model
Number
Packing
Type
TAC,TFC
BAC,BFC
TAC,TFC
FAC,FFC
TAC,TFC
BAC,BFC
FAC,FFC
TAI,TFI
TS040 (note 2, 3, 5)
TSOP
Fine-Pitch BGA
TSOP
R0
FBC048 (note 4)
TS056 (note 2, 3, 5)
LAA064 (note 4)
TS048 (note 2, 3, 5)
FBC048 ((note 4)
LAA064 (note 4)
TS040 (note 2, 3, 5)
FBC048 (note 4)
TS056 (note 2, 3, 5)
LAA064 (note 4)
TS048 (note 2, 3, 5)
FBC048 (note 4)
LAA064 (note 4)
FPT-48P-M19 (note 3, 6)
FBG048 (note 4)
R1,R2
90
Fortified BGA
TSOP
R3,R4
Fine-Pitch BGA
Fortified BGA
TSOP
0,2,3
(note 1)
S29GL032M
R0
BAI,BFI
Fine-Pitch BGA
TSOP
TAI,TFI
R1,R2
FAI,FFI
Fortified BGA
TSOP
90, 10, 11
TAI,TFI
BAI,BFI
Fine-Pitch BGA
Fortified BGA
TSOP
R3,R4
R5,R6
FAI,FFI
TBI,TCI
BAI,BFI
Fine-Pitch BGA
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types
0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales
office to confirm availability of specific valid combinations and to check on newly released combinations.
22
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Ordering Information-S29GL064M
S29GL064M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL064M
90
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R0
R1
=
=
x8, VCC=3.0-3.6V, Uniform sector device
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
R2
R3
R4
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address
sectors protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
R5
R6
=
=
x16, VCC=3.0-3.6V, Uniform sector device
x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#=VIL
R7
R8
R9
=
=
=
x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL, FPT-56P-M01 package only
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL, FPT-56P-M01 package only
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85 C)
°
PACKAGE MATERIAL SET
A
F
B
C
D
=
=
=
=
=
Standard
Pb-Free
Standard
Pb-Free
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL064M
64 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales
office to confirm availability of specific valid combinations and to check on newly released combinations.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
23
D a t a s h e e t
Table 2. S29GL064M Ordering Options
S29GL064M Valid Combinations
Package Description
Device
Number
Speed
Option
Package, Material, &
Temperature Range
Model
Number
Packing
Type
R0,R3,R4,R6,R7
R1,R2
TS048 (note 2, 3, 5)
TAI, TFI
TS056 (note 2, 3, 5)
FPT-48P-M19 (note 3, 6)
FPT-56P-M01 (note 3, 6)
FBE063 (note 4)
TSOP
TBI, TCI
TAI, TDI
BAI, BFI
FAI, FFI
R2,R7
0,2,3
(note 1)
S29GL064M
90, 10, 11
R9
R0,R3,R4,R5
R1,R2,R3,R4,R5
Fine-Pitch BGA
Fortified BGA
LAA064 (note 4)
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types
0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
24
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Ordering Information-S29GL128M
S29GL128M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL128M
90
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
Model Number
R1
R2
R8
R9
=
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL, FPT-56P-M01 package only
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL, FPT-56P-M01 package only
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85 C)
°
PACKAGE MATERIAL SET
A
F
D
=
=
=
Standard
Pb-Free
Pb-Free
PACKAGE TYPE
T
F
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL128M
128 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
25
D a t a s h e e t
Table 3. S29GL128M Ordering Options
S29GL128M Valid Combinations
Package Description
Device
Number
Speed
Option
Package, Material, &
Temperature Range
Model
Number
Packing
Type
TAI,TFI
FAI,FFI
TS056 (note 2, 3, 5)
TSOP
Fortified BGA
TSOP
R1,R2
R9
0,2,3
(note 1)
S29GL128M
90, 10, 11
LAA064 (note 4)
TAI,TDI
FPT-56P-M01 (note 3, 6)
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types
0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to con-
firm availability of specific valid combinations and to check on newly released combinations.
26
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Ordering Information-S29GL256M
S29GL256M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL256M
10
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
Model Number
R1
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
R2
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
=
Industrial (–40
°
C to +85 C)
°
PACKAGE MATERIAL SET
A
F
=
=
Standard
Pb-Free
PACKAGE TYPE
T
F
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL1256M
256 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
27
D a t a s h e e t
Table 4. S29GL256M Ordering Options
S29GL256M Valid Combinations
Package Description
Device
Number
Speed
Option
Package, Material, &
Temperature Range
Model
Number
Packing
Type
TAI,TFI
FAI,FFI
TS056 (note 2, 3, 4)
LAC064 (note 3)
TSOP
0,2,3
(note 1)
S29GL256M
10, 11
R1,R2
Fortified BGA
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types
0, 2, or 3.
2. TSOP package marking omits the packing type designator from the ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
4. 100% Matte Sn is used for Pb-free TSOP plating.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to con-
firm availability of specific valid combinations and to check on newly released combinations.
28
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the in-
ternal command register. The command register itself does not occupy any addressable memory location. The
register is a latch used to store the commands, along with the address and data information needed to execute
the command. The contents of the register serve as inputs to the internal state machine. The state machine out-
puts dictate the function of the device. Table 5 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 5. Device Bus Operations
DQ8–DQ15
WE
#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Operation
CE# OE#
RESET#
WP#
ACC
Read
L
L
L
H
L
H
X
X
A
D
D
OUT
IN
IN
OUT
(Note
3)
(Note
4)
(Note DQ8–DQ14
4)
Write (Program/Erase)
Accelerated Program
H
H
H
X
A
= High-Z,
DQ15 = A-1
(Note
3)
(Note
4)
(Note
4)
L
H
X
L
V
A
HH
IN
V
CC
V
CC
0.3 V
Standby
0.3
V
X
X
H
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L,A2=L,
A1=H, A0=L
Sector Group Protect
(Note 2)
(Note
X
L
H
L
V
H
X
X
ID
4)
Sector Group
Unprotect
(Note 2)
SA, A6=H,
A3=L,A2=L,
A1=H, A0=L
(Note
X
L
H
X
L
V
V
H
H
X
X
X
ID
ID
4)
Temporary Sector
Group Unprotect
(Note
4)
(Note
4)
X
X
A
High-Z
IN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5V, VHH = 11.5–12.5V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors
are protected (for boot sector devices). If WP# = VIH, the first or last sector, or the two outer boot sectors are
protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”.
All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending
on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, on page 96).
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
29
D a t a s h e e t
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE#
pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active
and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input
for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V . CE# is the power control
IL
and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at
V
.
IH
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device data outputs. The device remains enabled for read
access until the command register contents are altered.
See ““Reading Array Data” on page 103” for more information. Refer to “AC Characteristics” on page 124 for tim-
ing specifications and the timing diagram. Refer to “DC Characteristics” on page 122 for the active current
specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation.
This mode provides faster read access speed for random locations within a page. The page size of the device is 4
words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in
word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation;
the microprocessor supplies the specific word location.
The random or initial page access is equal to t
or t and subsequent page read accesses (as long as the lo-
CE
ACC
cations specified by the microprocessor falls within that page) is equivalent to t
. When CE# is deasserted and
PACC
reasserted for a subsequent access, the access time is t
or t . Fast page mode accesses are obtained by keep-
CE
ACC
ing the “read-page addresses” constant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors
of memory), the system must drive WE# and CE# to V , and OE# to V
.
IH
IL
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Program Com-
mand Sequence” on page 104” section contains details on programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 6 on page 32 and Table 17
on page 68 indicates the address space that each sector occupies.
Refer to “DC Characteristics” on page 122 for the active current specification for the write mode. The “AC Char-
acteristics” on page 124 section contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming op-
eration. This results in faster effective programming time than the standard programming algorithms. See ““Write
Buffer Programming” on page 105” for more information.
30
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions provided
by the WP#/ACC or ACC pin, depending on model number. This function is primarily intended to allow faster man-
ufacturing throughput at the factory.
If the system asserts V
on this pin, the device automatically enters the aforementioned Unlock Bypass mode,
HH
temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time
required for program operations. The system would use a two-cycle program command sequence as required by
the Unlock Bypass mode. Removing V from the WP#/ACC or ACC pin, depending on model number, returns the
HH
device to normal operation. Note that the WP#/ACC or ACC pin must not be at V
for operations other than ac-
HH
celerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is
at V
.
IH
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0.
Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 79 and “Autoselect Com-
mand Sequence” on page 104 sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V ± 0.3 V. (Note
IO
that this is a more restricted voltage range than V .) If CE# and RESET# are held at V , but not within V ±
IO
IH
IH
0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access
time (t ) for read access when the device is in either of these standby modes, before it is ready to read data.
CE
If the device is deselected during erasure or programming, the device draws active current until the operation is
completed.
Refer to “DC Characteristics” on page 122 for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this
mode when addresses remain stable for t
+ 30 ns. The automatic sleep mode is independent of the CE#, WE#,
ACC
and OE# control signals. Standard address access timings provide new data when addresses are changed. While
in sleep mode, output data is latched and always available to the system. Refer to “DC Characteristics” on
page 122 for the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin
is driven low for at least a period of t , the device immediately terminates any operation in progress, tristates all
RP
output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets
the internal state machine to reading array data. The operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V ±0.3 V, the device draws
SS
CMOS standby current (I
). If RESET# is held at V but not within V ±0.3 V, the standby current is greater.
IL SS
CC5
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the Flash memory.
Refer to “AC Characteristics” on page 124 for RESET# parameters and to Figure 15, on page 127 for the timing
diagram.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
31
D a t a s h e e t
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins are placed in the high impedance
IH
state.
Table 6. S29GL032M (Model R0) Sector Address Table (Sheet 1 of 2)
8-bit Address Range
Sector
SA0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
32
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 6. S29GL032M (Model R0) Sector Address Table (Sheet 2 of 2)
8-bit Address Range
Sector
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
33
D a t a s h e e t
Table 7. S29GL032M (Models R1, R2) Sector Address Table (Sheet 1 of 2)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector Size
(Kbytes/Kwords)
Sector
A20-A15
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
34
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 7. S29GL032M (Models R1, R2) Sector Address Table (Sheet 2 of 2)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector Size
(Kbytes/Kwords)
Sector
A20-A15
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
35
D a t a s h e e t
Table 8. S29GL032M (Models R3, R5) Top Boot Sector Address Table (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
101011xxx
36
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 8. S29GL032M (Models R3, R5) Top Boot Sector Address Table (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA36
SA37
SA38
SA39
SA40
SA41
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
3F6000h–3F7FFFh
3F8000h–3F9FFFh
3FA000h–3FBFFFh
3FC000h–3FDFFFh
3FE000h–3FFFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
8/4
111111010
8/4
111111011
8/4
111111100
8/4
111111101
8/4
111111110
8/4
111111111
8/4
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
37
D a t a s h e e t
Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Address Table (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001101xxx
001111xxx
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
SA1
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
011000xxx
011001xxx
011010xxx
011011xxx
011000xxx
38
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Address Table (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA36
SA37
SA38
SA39
SA40
SA41
011101xxx
011110xxx
011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
100000xxx
100001xxx
100010xxx
101011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
110000xxx
110001xxx
110010xxx
110011xxx
100100xxx
110101xxx
110110xxx
110111xxx
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
39
D a t a s h e e t
Table 10. S29GL064M (Model R0) Sector Address Table (Sheet 1 of 4)
8-bit Address Range
Sector
SA0
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(in hexadecimal)
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
40
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 10. S29GL064M (Model R0) Sector Address Table (Sheet 2 of 4)
8-bit Address Range
Sector
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
A22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A19
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
A18
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
A17
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A16
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
41
D a t a s h e e t
Table 10. S29GL064M (Model R0) Sector Address Table (Sheet 3 of 4)
8-bit Address Range
Sector
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
A22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
A19
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
A18
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
A17
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(in hexadecimal)
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
42
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 10. S29GL064M (Model R0) Sector Address Table (Sheet 4 of 4)
8-bit Address Range
Sector
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
A22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A21
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A20
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(in hexadecimal)
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
43
D a t a s h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Address Table (Sheet 1 of 4)
8-bit
Address Range
(in
16-bit
Address Range
(in
Sector Size
(Kbytes/
Kwords)
Sector
A21–A15
hexadecimal)
hexadecimal)
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
44
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Address Table (Sheet 2 of 4)
8-bit
16-bit
Sector Size
(Kbytes/
Kwords)
Address Range
(in
hexadecimal)
Address Range
(in
hexadecimal)
Sector
A21–A15
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
45
D a t a s h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Address Table (Sheet 3 of 4)
8-bit
16-bit
Sector Size
(Kbytes/
Kwords)
Address Range
(in
hexadecimal)
Address Range
(in
hexadecimal)
Sector
A21–A15
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
46
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Address Table (Sheet 4 of 4)
8-bit
16-bit
Sector Size
(Kbytes/
Kwords)
Address Range
(in
hexadecimal)
Address Range
(in
hexadecimal)
Sector
A21–A15
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
47
D a t a s h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Address Table (Sheet 1 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
0100000xxx
0100001xxx
0100010xxx
0101011xxx
48
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Address Table (Sheet 2 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA36
SA37
SA38
SA39
SA40
SA41
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
0111110xxx
0111111xxx
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
49
D a t a s h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Address Table (Sheet 3 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
50
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Address Table (Sheet 4 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA108
SA109
SA110
SA111
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
8/4
1111111010
8/4
1111111011
8/4
1111111100
8/4
1111111101
8/4
1111111110
8/4
1111111111
8/4
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
51
D a t a s h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Address Table (Sheet 1 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA0
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
SA1
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
52
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Address Table (Sheet 2 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA36
SA37
SA38
SA39
SA40
SA41
0011101xxx
0011110xxx
0011111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
400000h–40FFFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
200000h–207FFFh
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0100100xxx
0110101xxx
0110110xxx
0110111xxx
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
1000000xxx
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
53
D a t a s h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Address Table (Sheet 3 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
54
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Address Table (Sheet 4 of 4)
Sector Address
A21–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
Sector
SA108
SA109
SA110
SA111
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7FFFFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3FFFFFh
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
55
D a t a s h e e t
Table 14. S29GL064M (Model R5) Sector Address Table (Sheet 1 of 3)
16-bit
Address Range
(in hexadecimal)
Sector
A21–A15
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
56
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 14. S29GL064M (Model R5) Sector Address Table (Sheet 2 of 3)
16-bit
Address Range
Sector
A21–A15
(in hexadecimal)
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
57
D a t a s h e e t
Table 14. S29GL064M (Model R5) Sector Address Table (Sheet 3 of 3)
16-bit
Address Range
Sector
A21–A15
(in hexadecimal)
SA58
SA59
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
58
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 15. S29GL064M (Model R6, R7) Sector Address Table (Sheet 1 of 3)
16-bit
Address Range
(in hexadecimal)
Sector
A21–A15
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
59
D a t a s h e e t
Table 15. S29GL064M (Model R6, R7) Sector Address Table (Sheet 2 of 3)
16-bit
Address Range
Sector
A21–A15
(in hexadecimal)
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
60
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 15. S29GL064M (Model R6, R7) Sector Address Table (Sheet 3 of 3)
16-bit
Address Range
Sector
A21–A15
(in hexadecimal)
SA58
SA59
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
SA60
SA61
SA62
SA63
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
61
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 1 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
62
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 2 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
63
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 3 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA90
SA91
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
800000–80FFFF
810000–81FFFF
820000–82FFFF
830000–83FFFF
840000–84FFFF
850000–85FFFF
860000–86FFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
400000–407FFF
408000–40FFFF
410000–417FFF
418000–41FFFF
420000–427FFF
428000–42FFFF
430000–437FFF
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
64
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 4 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
870000–87FFFF
880000–88FFFF
890000–89FFFF
8A0000–8AFFFF
8B0000–8BFFFF
8C0000–8CFFFF
8D0000–8DFFFF
8E0000–8EFFFF
8F0000–8FFFFF
900000–90FFFF
910000–91FFFF
920000–92FFFF
930000–93FFFF
940000–94FFFF
950000–95FFFF
960000–96FFFF
970000–97FFFF
980000–98FFFF
990000–99FFFF
9A0000–9AFFFF
9B0000–9BFFFF
9C0000–9CFFFF
9D0000–9DFFFF
9E0000–9EFFFF
9F0000–9FFFFF
A00000–A0FFFF
A10000–A1FFFF
A20000–A2FFFF
A30000–A3FFFF
A40000–A4FFFF
A50000–A5FFFF
A60000–A6FFFF
A70000–A7FFFF
A80000–A8FFFF
A90000–A9FFFF
AA0000–AAFFFF
AB0000–ABFFFF
AC0000–ACFFFF
AD0000–ADFFFF
AE0000–AEFFFF
AF0000–AFFFFF
B00000–B0FFFF
B10000–B1FFFF
B20000–B2FFFF
B30000–B3FFFF
438000–43FFFF
440000–447FFF
448000–44FFFF
450000–457FFF
458000–45FFFF
460000–467FFF
468000–46FFFF
470000–477FFF
478000–47FFFF
480000–487FFF
488000–48FFFF
490000–497FFF
498000–49FFFF
4A0000–4A7FFF
4A8000–4AFFFF
4B0000–4B7FFF
4B8000–4BFFFF
4C0000–4C7FFF
4C8000–4CFFFF
4D0000–4D7FFF
4D8000–4DFFFF
4E0000–4E7FFF
4E8000–4EFFFF
4F0000–4F7FFF
4F8000–4FFFFF
500000–507FFF
508000–50FFFF
510000–517FFF
518000–51FFFF
520000–527FFF
528000–52FFFF
530000–537FFF
538000–53FFFF
540000–547FFF
548000–54FFFF
550000–557FFF
558000–55FFFF
560000–567FFF
568000–56FFFF
570000–577FFF
578000–57FFFF
580000–587FFF
588000–58FFFF
590000–597FFF
598000–59FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
65
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 5 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
B40000–B4FFFF
B50000–B5FFFF
B60000–B6FFFF
B70000–B7FFFF
B80000–B8FFFF
B90000–B9FFFF
BA0000–BAFFFF
BB0000–BBFFFF
BC0000–BCFFFF
BD0000–BDFFFF
BE0000–BEFFFF
BF0000–BFFFFF
C00000–C0FFFF
C10000–C1FFFF
C20000–C2FFFF
C30000–C3FFFF
C40000–C4FFFF
C50000–C5FFFF
C60000–C6FFFF
C70000–C7FFFF
C80000–C8FFFF
C90000–C9FFFF
CA0000–CAFFFF
CB0000–CBFFFF
CC0000–CCFFFF
CD0000–CDFFFF
CE0000–CEFFFF
CF0000–CFFFFF
D00000–D0FFFF
D10000–D1FFFF
D20000–D2FFFF
D30000–D3FFFF
D40000–D4FFFF
D50000–D5FFFF
D60000–D6FFFF
D70000–D7FFFF
D80000–D8FFFF
D90000–D9FFFF
DA0000–DAFFFF
DB0000–DBFFFF
DC0000–DCFFFF
DD0000–DDFFFF
DE0000–DEFFFF
DF0000–DFFFFF
E00000–E0FFFF
5A0000–5A7FFF
5A8000–5AFFFF
5B0000–5B7FFF
5B8000–5BFFFF
5C0000–5C7FFF
5C8000–5CFFFF
5D0000–5D7FFF
5D8000–5DFFFF
5E0000–5E7FFF
5E8000–5EFFFF
5F0000–5F7FFF
5F8000–5FFFFF
600000–607FFF
608000–60FFFF
610000–617FFF
618000–61FFFF
620000–627FFF
628000–62FFFF
630000–637FFF
638000–63FFFF
640000–647FFF
648000–64FFFF
650000–657FFF
658000–65FFFF
660000–667FFF
668000–66FFFF
670000–677FFF
678000–67FFFF
680000–687FFF
688000–68FFFF
690000–697FFF
698000–69FFFF
6A0000–6A7FFF
6A8000–6AFFFF
6B0000–6B7FFF
6B8000–6BFFFF
6C0000–6C7FFF
6C8000–6CFFFF
6D0000–6D7FFF
6D8000–6DFFFF
6E0000–6E7FFF
6E8000–6EFFFF
6F0000–6F7FFF
6F8000–6FFFFF
700000–707FFF
66
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 16. S29GL128M Sector Address Table (Sheet 6 of 6)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A22–A15
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
E10000–E1FFFF
E20000–E2FFFF
E30000–E3FFFF
E40000–E4FFFF
E50000–E5FFFF
E60000–E6FFFF
E70000–E7FFFF
E80000–E8FFFF
E90000–E9FFFF
EA0000–EAFFFF
EB0000–EBFFFF
EC0000–ECFFFF
ED0000–EDFFFF
EE0000–EEFFFF
EF0000–EFFFFF
F00000–F0FFFF
F10000–F1FFFF
F20000–F2FFFF
F30000–F3FFFF
F40000–F4FFFF
F50000–F5FFFF
F60000–F6FFFF
F70000–F7FFFF
F80000–F8FFFF
F90000–F9FFFF
FA0000–FAFFFF
FB0000–FBFFFF
FC0000–FCFFFF
FD0000–FDFFFF
FE0000–FEFFFF
FF0000–FFFFFF
708000–70FFFF
710000–717FFF
718000–71FFFF
720000–727FFF
728000–72FFFF
730000–737FFF
738000–73FFFF
740000–747FFF
748000–74FFFF
750000–757FFF
758000–75FFFF
760000–767FFF
768000–76FFFF
770000–777FFF
778000–77FFFF
780000–787FFF
788000–78FFFF
790000–797FFF
798000–79FFFF
7A0000–7A7FFF
7A8000–7AFFFF
7B0000–7B7FFF
7B8000–7BFFFF
7C0000–7C7FFF
7C8000–7CFFFF
7D0000–7D7FFF
7D8000–7DFFFF
7E0000–7E7FFF
7E8000–7EFFFF
7F0000–7F7FFF
7F8000–7FFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
67
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 1 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0000000–000FFFF
0010000–001FFFF
0020000–002FFFF
0030000–003FFFF
0040000–004FFFF
0050000–005FFFF
0060000–006FFFF
0070000–007FFFF
0080000–008FFFF
0090000–009FFFF
00A0000–00AFFFF
00B0000–00BFFFF
00C0000–00CFFFF
00D0000–00DFFFF
00E0000–00EFFFF
00F0000–00FFFFF
0100000–010FFFF
0110000–011FFFF
0120000–012FFFF
0130000–013FFFF
0140000–014FFFF
0150000–015FFFF
0160000–016FFFF
0170000–017FFFF
0180000–018FFFF
0190000–019FFFF
01A0000–01AFFFF
01B0000–01BFFFF
01C0000–01CFFFF
01D0000–01DFFFF
01E0000–01EFFFF
01F0000–01FFFFF
0200000–020FFFF
0210000–021FFFF
0220000–022FFFF
0230000–023FFFF
0240000–024FFFF
0250000–025FFFF
0260000–026FFFF
0270000–027FFFF
0280000–028FFFF
0290000–029FFFF
02A0000–02AFFFF
02B0000–02BFFFF
02C0000–02CFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
68
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 2 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
02D0000–02DFFFF
02E0000–02EFFFF
02F0000–02FFFFF
0300000–030FFFF
0310000–031FFFF
0320000–032FFFF
0330000–033FFFF
0340000–034FFFF
0350000–035FFFF
0360000–036FFFF
0370000–037FFFF
0380000–038FFFF
0390000–039FFFF
03A0000–03AFFFF
03B0000–03BFFFF
03C0000–03CFFFF
03D0000–03DFFFF
03E0000–03EFFFF
03F0000–03FFFFF
0400000–040FFFF
0410000–041FFFF
0420000–042FFFF
0430000–043FFFF
0440000–044FFFF
0450000–045FFFF
0460000–046FFFF
0470000–047FFFF
0480000–048FFFF
0490000–049FFFF
04A0000–04AFFFF
04B0000–04BFFFF
04C0000–04CFFFF
04D0000–04DFFFF
04E0000–04EFFFF
04F0000–04FFFFF
0500000–050FFFF
0510000–051FFFF
0520000–052FFFF
0530000–053FFFF
0540000–054FFFF
0550000–055FFFF
0560000–056FFFF
0570000–057FFFF
0580000–058FFFF
0590000–059FFFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
69
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 3 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA90
SA91
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
05A0000–05AFFFF
05B0000–05BFFFF
05C0000–05CFFFF
05D0000–05DFFFF
05E0000–05EFFFF
05F0000–05FFFFF
0600000–060FFFF
0610000–061FFFF
0620000–062FFFF
0630000–063FFFF
0640000–064FFFF
0650000–065FFFF
0660000–066FFFF
0670000–067FFFF
0680000–068FFFF
0690000–069FFFF
06A0000–06AFFFF
06B0000–06BFFFF
06C0000–06CFFFF
06D0000–06DFFFF
06E0000–06EFFFF
06F0000–06FFFFF
0700000–070FFFF
0710000–071FFFF
0720000–072FFFF
0730000–073FFFF
0740000–074FFFF
0750000–075FFFF
0760000–076FFFF
0770000–077FFFF
0780000–078FFFF
0790000–079FFFF
07A0000–07AFFFF
07B0000–07BFFFF
07C0000–07CFFFF
07D0000–07DFFFF
07E0000–07EFFFF
07F0000–07FFFFF
0800000–080FFFF
0810000–081FFFF
0820000–082FFFF
0830000–083FFFF
0840000–084FFFF
0850000–085FFFF
0860000–086FFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
400000–407FFF
408000–40FFFF
410000–417FFF
418000–41FFFF
420000–427FFF
428000–42FFFF
430000–437FFF
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
70
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 4 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA135
SA136
SA137
SA138
SA139
SA140
SA141
SA142
SA143
SA144
SA145
SA146
SA147
SA148
SA149
SA150
SA151
SA152
SA153
SA154
SA155
SA156
SA157
SA158
SA159
SA160
SA161
SA162
SA163
SA164
SA165
SA166
SA167
SA168
SA169
SA170
SA171
SA172
SA173
SA174
SA175
SA176
SA177
SA178
SA179
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0870000–087FFFF
0880000–088FFFF
0890000–089FFFF
08A0000–08AFFFF
08B0000–08BFFFF
08C0000–08CFFFF
08D0000–08DFFFF
08E0000–08EFFFF
08F0000–08FFFFF
0900000–090FFFF
0910000–091FFFF
0920000–092FFFF
0930000–093FFFF
0940000–094FFFF
0950000–095FFFF
0960000–096FFFF
0970000–097FFFF
0980000–098FFFF
0990000–099FFFF
09A0000–09AFFFF
09B0000–09BFFFF
09C0000–09CFFFF
09D0000–09DFFFF
09E0000–09EFFFF
09F0000–09FFFFF
0A00000–0A0FFFF
0A10000–0A1FFFF
0A20000–0A2FFFF
0A30000–0A3FFFF
0A40000–0A4FFFF
0A50000–0A5FFFF
0A60000–0A6FFFF
0A70000–0A7FFFF
0A80000–0A8FFFF
0A90000–0A9FFFF
0AA0000–0AAFFFF
0AB0000–0ABFFFF
0AC0000–0ACFFFF
0AD0000–0ADFFFF
0AE0000–0AEFFFF
0AF0000–0AFFFFF
0B00000–0B0FFFF
0B10000–0B1FFFF
0B20000–0B2FFFF
0B30000–0B3FFFF
438000–43FFFF
440000–447FFF
448000–44FFFF
450000–457FFF
458000–45FFFF
460000–467FFF
468000–46FFFF
470000–477FFF
478000–47FFFF
480000–487FFF
488000–48FFFF
490000–497FFF
498000–49FFFF
4A0000–4A7FFF
4A8000–4AFFFF
4B0000–4B7FFF
4B8000–4BFFFF
4C0000–4C7FFF
4C8000–4CFFFF
4D0000–4D7FFF
4D8000–4DFFFF
4E0000–4E7FFF
4E8000–4EFFFF
4F0000–4F7FFF
4F8000–4FFFFF
500000–507FFF
508000–50FFFF
510000–517FFF
518000–51FFFF
520000–527FFF
528000–52FFFF
530000–537FFF
538000–53FFFF
540000–547FFF
548000–54FFFF
550000–557FFF
558000–55FFFF
560000–567FFF
568000–56FFFF
570000–577FFF
578000–57FFFF
580000–587FFF
588000–58FFFF
590000–597FFF
598000–59FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
71
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 5 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA180
SA181
SA182
SA183
SA184
SA185
SA186
SA187
SA188
SA189
SA190
SA191
SA192
SA193
SA194
SA195
SA196
SA197
SA198
SA199
SA200
SA201
SA202
SA203
SA204
SA205
SA206
SA207
SA208
SA209
SA210
SA211
SA212
SA213
SA214
SA215
SA216
SA217
SA218
SA219
SA220
SA221
SA222
SA223
SA224
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0B40000–0B4FFFF
0B50000–0B5FFFF
0B60000–0B6FFFF
0B70000–0B7FFFF
0B80000–0B8FFFF
0B90000–0B9FFFF
0BA0000–0BAFFFF
0BB0000–0BBFFFF
0BC0000–0BCFFFF
0BD0000–0BDFFFF
0BE0000–0BEFFFF
0BF0000–0BFFFFF
0C00000–0C0FFFF
0C10000–0C1FFFF
0C20000–0C2FFFF
0C30000–0C3FFFF
0C40000–0C4FFFF
0C50000–0C5FFFF
0C60000–0C6FFFF
0C70000–0C7FFFF
0C80000–0C8FFFF
0C90000–0C9FFFF
0CA0000–0CAFFFF
0CB0000–0CBFFFF
0CC0000–0CCFFFF
0CD0000–0CDFFFF
0CE0000–0CEFFFF
0CF0000–0CFFFFF
0D00000–0D0FFFF
0D10000–0D1FFFF
0D20000–0D2FFFF
0D30000–0D3FFFF
0D40000–0D4FFFF
0D50000–0D5FFFF
0D60000–0D6FFFF
0D70000–0D7FFFF
0D80000–0D8FFFF
0D90000–0D9FFFF
0DA0000–0DAFFFF
0DB0000–0DBFFFF
0DC0000–0DCFFFF
0DD0000–0DDFFFF
0DE0000–0DEFFFF
0DF0000–0DFFFFF
0E00000–0E0FFFF
5A0000–5A7FFF
5A8000–5AFFFF
5B0000–5B7FFF
5B8000–5BFFFF
5C0000–5C7FFF
5C8000–5CFFFF
5D0000–5D7FFF
5D8000–5DFFFF
5E0000–5E7FFF
5E8000–5EFFFF
5F0000–5F7FFF
5F8000–5FFFFF
600000–607FFF
608000–60FFFF
610000–617FFF
618000–61FFFF
620000–627FFF
628000–62FFFF
630000–637FFF
638000–63FFFF
640000–647FFF
648000–64FFFF
650000–657FFF
658000–65FFFF
660000–667FFF
668000–66FFFF
670000–677FFF
678000–67FFFF
680000–687FFF
688000–68FFFF
690000–697FFF
698000–69FFFF
6A0000–6A7FFF
6A8000–6AFFFF
6B0000–6B7FFF
6B8000–6BFFFF
6C0000–6C7FFF
6C8000–6CFFFF
6D0000–6D7FFF
6D8000–6DFFFF
6E0000–6E7FFF
6E8000–6EFFFF
6F0000–6F7FFF
6F8000–6FFFFF
700000–707FFF
72
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 6 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA225
SA226
SA227
SA228
SA229
SA230
SA231
SA232
SA233
SA234
SA235
SA236
SA237
SA238
SA239
SA240
SA241
SA242
SA243
SA244
SA245
SA246
SA247
SA248
SA249
SA250
SA251
SA252
SA253
SA254
SA255
SA256
SA257
SA258
SA259
SA260
SA261
SA262
SA263
SA264
SA265
SA266
SA267
SA268
SA269
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0E10000–0E1FFFF
0E20000–0E2FFFF
0E30000–0E3FFFF
0E40000–0E4FFFF
0E50000–0E5FFFF
0E60000–0E6FFFF
0E70000–0E7FFFF
0E80000–0E8FFFF
0E90000–0E9FFFF
0EA0000–0EAFFFF
0EB0000–0EBFFFF
0EC0000–0ECFFFF
0ED0000–0EDFFFF
0EE0000–0EEFFFF
0EF0000–0EFFFFF
0F00000–0F0FFFF
0F10000–0F1FFFF
0F20000–0F2FFFF
0F30000–0F3FFFF
0F40000–0F4FFFF
0F50000–0F5FFFF
0F60000–0F6FFFF
0F70000–0F7FFFF
0F80000–0F8FFFF
0F90000–0F9FFFF
0FA0000–0FAFFFF
0FB0000–0FBFFFF
0FC0000–0FCFFFF
0FD0000–0FDFFFF
0FE0000–0FEFFFF
0FF0000–0FFFFFF
1000000–100FFFF
1010000–101FFFF
1020000–102FFFF
1030000–103FFFF
1040000–104FFFF
1050000–105FFFF
1060000–106FFFF
1070000–107FFFF
1080000–108FFFF
1090000–109FFFF
10A0000–10AFFFF
10B0000–10BFFFF
10C0000–10CFFFF
10D0000–10DFFFF
708000–70FFFF
710000–717FFF
718000–71FFFF
720000–727FFF
728000–72FFFF
730000–737FFF
738000–73FFFF
740000–747FFF
748000–74FFFF
750000–757FFF
758000–75FFFF
760000–767FFF
768000–76FFFF
770000–777FFF
778000–77FFFF
780000–787FFF
788000–78FFFF
790000–797FFF
798000–79FFFF
7A0000–7A7FFF
7A8000–7AFFFF
7B0000–7B7FFF
7B8000–7BFFFF
7C0000–7C7FFF
7C8000–7CFFFF
7D0000–7D7FFF
7D8000–7DFFFF
7E0000–7E7FFF
7E8000–7EFFFF
7F0000–7F7FFF
7F8000–7FFFFF
800000–807FFF
808000–80FFFF
810000–817FFF
818000–81FFFF
820000–827FFF
828000–82FFFF
830000–837FFF
838000–83FFFF
840000–847FFF
848000–84FFFF
850000–857FFF
858000–85FFFF
860000–867FFF
868000–86FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
73
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 7 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA270
SA271
SA272
SA273
SA274
SA275
SA276
SA277
SA278
SA279
SA280
SA281
SA282
SA283
SA284
SA285
SA286
SA287
SA288
SA289
SA290
SA291
SA292
SA293
SA294
SA295
SA296
SA297
SA298
SA299
SA300
SA301
SA302
SA303
SA304
SA305
SA306
SA307
SA308
SA309
SA310
SA311
SA312
SA313
SA314
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
10E0000–10EFFFF
10F0000–10FFFFF
1100000–110FFFF
1110000–111FFFF
1120000–112FFFF
1130000–113FFFF
1140000–114FFFF
1150000–115FFFF
1160000–116FFFF
1170000–117FFFF
1180000–118FFFF
1190000–119FFFF
11A0000–11AFFFF
11B0000–11BFFFF
11C0000–11CFFFF
11D0000–11DFFFF
11E0000–11EFFFF
11F0000–11FFFFF
1200000–120FFFF
1210000–121FFFF
1220000–122FFFF
1230000–123FFFF
1240000–124FFFF
1250000–125FFFF
1260000–126FFFF
1270000–127FFFF
1280000–128FFFF
1290000–129FFFF
12A0000–12AFFFF
12B0000–12BFFFF
12C0000–12CFFFF
12D0000–12DFFFF
12E0000–12EFFFF
12F0000–12FFFFF
1300000–130FFFF
1310000–131FFFF
1320000–132FFFF
1330000–133FFFF
1340000–134FFFF
1350000–135FFFF
1360000–136FFFF
1370000–137FFFF
1380000–138FFFF
1390000–139FFFF
13A0000–13AFFFF
870000–877FFF
878000–87FFFF
880000–887FFF
888000–88FFFF
890000–897FFF
898000–89FFFF
8A0000–8A7FFF
8A8000–8AFFFF
8B0000–8B7FFF
8B8000–8BFFFF
8C0000–8C7FFF
8C8000–8CFFFF
8D0000–8D7FFF
8D8000–8DFFFF
8E0000–8E7FFF
8E8000–8EFFFF
8F0000–8F7FFF
8F8000–8FFFFF
900000–907FFF
908000–90FFFF
910000–917FFF
918000–91FFFF
920000–927FFF
928000–92FFFF
930000–937FFF
938000–93FFFF
940000–947FFF
948000–94FFFF
950000–957FFF
958000–95FFFF
960000–967FFF
968000–96FFFF
970000–977FFF
978000–97FFFF
980000–987FFF
988000–98FFFF
990000–997FFF
998000–99FFFF
9A0000–9A7FFF
9A8000–9AFFFF
9B0000–9B7FFF
9B8000–9BFFFF
9C0000–9C7FFF
9C8000–9CFFFF
9D0000–9D7FFF
74
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 8 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA315
SA316
SA317
SA318
SA319
SA320
SA321
SA322
SA323
SA324
SA325
SA326
SA327
SA328
SA329
SA330
SA331
SA332
SA333
SA334
SA335
SA336
SA337
SA338
SA339
SA340
SA341
SA342
SA343
SA344
SA345
SA346
SA347
SA348
SA349
SA350
SA351
SA352
SA353
SA354
SA355
SA356
SA357
SA358
SA359
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
13B0000–13BFFFF
13C0000–13CFFFF
13D0000–13DFFFF
13E0000–13EFFFF
13F0000–13FFFFF
1400000–140FFFF
1410000–141FFFF
1420000–142FFFF
1430000–143FFFF
1440000–144FFFF
1450000–145FFFF
1460000–146FFFF
1470000–147FFFF
1480000–148FFFF
1490000–149FFFF
14A0000–14AFFFF
14B0000–14BFFFF
14C0000–14CFFFF
14D0000–14DFFFF
14E0000–14EFFFF
14F0000–14FFFFF
1500000–150FFFF
1510000–151FFFF
1520000–152FFFF
1530000–153FFFF
1540000–154FFFF
1550000–155FFFF
1560000–156FFFF
1570000–157FFFF
1580000–158FFFF
1590000–159FFFF
15A0000–15AFFFF
15B0000–15BFFFF
15C0000–15CFFFF
15D0000–15DFFFF
15E0000–15EFFFF
15F0000–15FFFFF
1600000–160FFFF
1610000–161FFFF
1620000–162FFFF
1630000–163FFFF
1640000–164FFFF
1650000–165FFFF
1660000–166FFFF
1670000–167FFFF
9D8000–9DFFFF
9E0000–9E7FFF
9E8000–9EFFFF
9F0000–9F7FFF
9F8000–9FFFFF
A00000–A07FFF
A08000–A0FFFF
A10000–A17FFF
A18000–A1FFFF
A20000–A27FFF
A28000–A2FFFF
A30000–A37FFF
A38000–A3FFFF
A40000–A47FFF
A48000–A4FFFF
A50000–A57FFF
A58000–A5FFFF
A60000–A67FFF
A68000–A6FFFF
A70000–A77FFF
A78000–A7FFFF
A80000–A87FFF
A88000–A8FFFF
A90000–A97FFF
A98000–A9FFFF
AA0000–AA7FFF
AA8000–AAFFFF
AB0000–AB7FFF
AB8000–ABFFFF
AC0000–AC7FFF
AC8000–ACFFFF
AD0000–AD7FFF
AD8000–ADFFFF
AE0000–AE7FFF
AE8000–AEFFFF
AF0000–AF7FFF
AF8000–AFFFFF
B00000–B07FFF
B08000–B0FFFF
B10000–B17FFF
B18000–B1FFFF
B20000–B27FFF
B28000–B2FFFF
B30000–B37FFF
B38000–B3FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
75
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 9 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA360
SA361
SA362
SA363
SA364
SA365
SA366
SA367
SA368
SA369
SA370
SA371
SA372
SA373
SA374
SA375
SA376
SA377
SA378
SA379
SA380
SA381
SA382
SA383
SA384
SA385
SA386
SA387
SA388
SA389
SA390
SA391
SA392
SA393
SA394
SA395
SA396
SA397
SA398
SA399
SA400
SA401
SA402
SA403
SA404
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1680000–168FFFF
1690000–169FFFF
16A0000–16AFFFF
16B0000–16BFFFF
16C0000–16CFFFF
16D0000–16DFFFF
16E0000–16EFFFF
16F0000–16FFFFF
1700000–170FFFF
1710000–171FFFF
1720000–172FFFF
1730000–173FFFF
1740000–174FFFF
1750000–175FFFF
1760000–176FFFF
1770000–177FFFF
1780000–178FFFF
1790000–179FFFF
17A0000–17AFFFF
17B0000–17BFFFF
17C0000–17CFFFF
17D0000–17DFFFF
17E0000–17EFFFF
17F0000–17FFFFF
1800000–180FFFF
1810000–181FFFF
1820000–182FFFF
1830000–183FFFF
1840000–184FFFF
1850000–185FFFF
1860000–186FFFF
1870000–187FFFF
1880000–188FFFF
1890000–189FFFF
18A0000–18AFFFF
18B0000–18BFFFF
18C0000–18CFFFF
18D0000–18DFFFF
18E0000–18EFFFF
18F0000–18FFFFF
1900000–190FFFF
1910000–191FFFF
1920000–192FFFF
1930000–193FFFF
1940000–194FFFF
B40000–B47FFF
B48000–B4FFFF
B50000–B57FFF
B58000–B5FFFF
B60000–B67FFF
B68000–B6FFFF
B70000–B77FFF
B78000–B7FFFF
B80000–B87FFF
B88000–B8FFFF
B90000–B97FFF
B98000–B9FFFF
BA0000–BA7FFF
BA8000–BAFFFF
BB0000–BB7FFF
BB8000–BBFFFF
BC0000–BC7FFF
BC8000–BCFFFF
BD0000–BD7FFF
BD8000–BDFFFF
BE0000–BE7FFF
BE8000–BEFFFF
BF0000–BF7FFF
BF8000–BFFFFF
C00000–C07FFF
C08000–C0FFFF
C10000–C17FFF
C18000–C1FFFF
C20000–C27FFF
C28000–C2FFFF
C30000–C37FFF
C38000–C3FFFF
C40000–C47FFF
C48000–C4FFFF
C50000–C57FFF
C58000–C5FFFF
C60000–C67FFF
C68000–C6FFFF
C70000–C77FFF
C78000–C7FFFF
C80000–C87FFF
C88000–C8FFFF
C90000–C97FFF
C98000–C9FFFF
CA0000–CA7FFF
76
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 10 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA405
SA406
SA407
SA408
SA409
SA410
SA411
SA412
SA413
SA414
SA415
SA416
SA417
SA418
SA419
SA420
SA421
SA422
SA423
SA424
SA425
SA426
SA427
SA428
SA429
SA430
SA431
SA432
SA433
SA434
SA435
SA436
SA437
SA438
SA439
SA440
SA441
SA442
SA443
SA444
SA445
SA446
SA447
SA448
SA449
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1950000–195FFFF
1960000–196FFFF
1970000–197FFFF
1980000–198FFFF
1990000–199FFFF
19A0000–19AFFFF
19B0000–19BFFFF
19C0000–19CFFFF
19D0000–19DFFFF
19E0000–19EFFFF
19F0000–19FFFFF
1A00000–1A0FFFF
1A10000–1A1FFFF
1A20000–1A2FFFF
1A30000–1A3FFFF
1A40000–1A4FFFF
1A50000–1A5FFFF
1A60000–1A6FFFF
1A70000–1A7FFFF
1A80000–1A8FFFF
1A90000–1A9FFFF
1AA0000–1AAFFFF
1AB0000–1ABFFFF
1AC0000–1ACFFFF
1AD0000–1ADFFFF
1AE0000–1AEFFFF
1AF0000–1AFFFFF
1B00000–1B0FFFF
1B10000–1B1FFFF
1B20000–1B2FFFF
1B30000–1B3FFFF
1B40000–1B4FFFF
1B50000–1B5FFFF
1B60000–1B6FFFF
1B70000–1B7FFFF
1B80000–1B8FFFF
1B90000–1B9FFFF
1BA0000–1BAFFFF
1BB0000–1BBFFFF
1BC0000–1BCFFFF
1BD0000–1BDFFFF
1BE0000–1BEFFFF
1BF0000–1BFFFFF
1C00000–1C0FFFF
1C10000–1C1FFFF
CA8000–CAFFFF
CB0000–CB7FFF
CB8000–CBFFFF
CC0000–CC7FFF
CC8000–CCFFFF
CD0000–CD7FFF
CD8000–CDFFFF
CE0000–CE7FFF
CE8000–CEFFFF
CF0000–CF7FFF
CF8000–CFFFFF
D00000–D07FFF
D08000–D0FFFF
D10000–D17FFF
D18000–D1FFFF
D20000–D27FFF
D28000–D2FFFF
D30000–D37FFF
D38000–D3FFFF
D40000–D47FFF
D48000–D4FFFF
D50000–D57FFF
D58000–D5FFFF
D60000–D67FFF
D68000–D6FFFF
D70000–D77FFF
D78000–D7FFFF
D80000–D87FFF
D88000–D8FFFF
D90000–D97FFF
D98000–D9FFFF
DA0000–DA7FFF
DA8000–DAFFFF
DB0000–DB7FFF
DB8000–DBFFFF
DC0000–DC7FFF
DC8000–DCFFFF
DD0000–DD7FFF
DD8000–DDFFFF
DE0000–DE7FFF
DE8000–DEFFFF
DF0000–DF7FFF
DF8000–DFFFFF
E00000–E07FFF
E08000–E0FFFF
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
77
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 11 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA450
SA451
SA452
SA453
SA454
SA455
SA456
SA457
SA458
SA459
SA460
SA461
SA462
SA463
SA464
SA465
SA466
SA467
SA468
SA469
SA470
SA471
SA472
SA473
SA474
SA475
SA476
SA477
SA478
SA479
SA480
SA481
SA482
SA483
SA484
SA485
SA486
SA487
SA488
SA489
SA490
SA491
SA492
SA493
SA494
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1C20000–1C2FFFF
1C30000–1C3FFFF
1C40000–1C4FFFF
1C50000–1C5FFFF
1C60000–1C6FFFF
1C70000–1C7FFFF
1C80000–1C8FFFF
1C90000–1C9FFFF
1CA0000–1CAFFFF
1CB0000–1CBFFFF
1CC0000–1CCFFFF
1CD0000–1CDFFFF
1CE0000–1CEFFFF
1CF0000–1CFFFFF
1D00000–1D0FFFF
1D10000–1D1FFFF
1D20000–1D2FFFF
1D30000–1D3FFFF
1D40000–1D4FFFF
1D50000–1D5FFFF
1D60000–1D6FFFF
1D70000–1D7FFFF
1D80000–1D8FFFF
1D90000–1D9FFFF
1DA0000–1DAFFFF
1DB0000–1DBFFFF
1DC0000–1DCFFFF
1DD0000–1DDFFFF
1DE0000–1DEFFFF
1DF0000–1DFFFFF
1E00000–1E0FFFF
1E10000–1E1FFFF
1E20000–1E2FFFF
1E30000–1E3FFFF
1E40000–1E4FFFF
1E50000–1E5FFFF
1E60000–1E6FFFF
1E70000–1E7FFFF
1E80000–1E8FFFF
1E90000–1E9FFFF
1EA0000–1EAFFFF
1EB0000–1EBFFFF
1EC0000–1ECFFFF
1ED0000–1EDFFFF
1EE0000–1EEFFFF
E10000–E17FFF
E18000–E1FFFF
E20000–E27FFF
E28000–E2FFFF
E30000–E37FFF
E38000–E3FFFF
E40000–E47FFF
E48000–E4FFFF
E50000–E57FFF
E58000–E5FFFF
E60000–E67FFF
E68000–E6FFFF
E70000–E77FFF
E78000–E7FFFF
E80000–E87FFF
E88000–E8FFFF
E90000–E97FFF
E98000–E9FFFF
EA0000–EA7FFF
EA8000–EAFFFF
EB0000–EB7FFF
EB8000–EBFFFF
EC0000–EC7FFF
EC8000–ECFFFF
ED0000–ED7FFF
ED8000–EDFFFF
EE0000–EE7FFF
EE8000–EEFFFF
EF0000–EF7FFF
EF8000–EFFFFF
F00000–F07FFF
F08000–F0FFFF
F10000–F17FFF
F18000–F1FFFF
F20000–F27FFF
F28000–F2FFFF
F30000–F37FFF
F38000–F3FFFF
F40000–F47FFF
F48000–F4FFFF
F50000–F57FFF
F58000–F5FFFF
F60000–F67FFF
F68000–F6FFFF
F70000–F77FFF
78
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 17. S29GL256M Sector Address Table (Sheet 12 of 12)
Sector Size
(Kbytes/
Kwords)
8-bit
Address Range
(in hexadecimal)
16-bit
Address Range
(in hexadecimal)
Sector
A23–A15
SA495
SA496
SA497
SA498
SA499
SA500
SA501
SA502
SA503
SA504
SA505
SA506
SA507
SA508
SA509
SA510
SA511
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
1EF0000–1EFFFFF
1F00000–1F0FFFF
1F10000–1F1FFFF
1F20000–1F2FFFF
1F30000–1F3FFFF
1F40000–1F4FFFF
1F50000–1F5FFFF
1F60000–1F6FFFF
1F70000–1F7FFFF
1F80000–1F8FFFF
1F90000–1F9FFFF
1FA0000–1FAFFFF
1FB0000–1FBFFFF
1FC0000–1FCFFFF
1FD0000–1FDFFFF
1FE0000–1FEFFFF
1FF0000–1FFFFFF
F78000–F7FFFF
F80000–F87FFF
F88000–F8FFFF
F90000–F97FFF
F98000–F9FFFF
FA0000–FA7FFF
FA8000–FAFFFF
FB0000–FB7FFF
FB8000–FBFFFF
FC0000–FC7FFF
FC8000–FCFFFF
FD0000–FD7FFF
FD8000–FDFFFF
FE0000–FE7FFF
FE8000–FEFFFF
FF0000–FF7FFF
FF8000–FFFFFF
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to au-
tomatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V on address pin A9. Address pins A6, A3,
ID
A2, A1, and A0 must be as shown in Table 18 on page 80. In addition, when verifying sector protection, the sector
address must appear on the appropriate highest order address bits (see Table 6 on page 32 through Table 17 on
page 68). Table 18 on page 80 shows the remaining address bits that are don’t care. When all necessary bits are
set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the command
register, as shown in Table 35 on page 113 and Table 36 on page 114. This method does not require V . Refer to
ID
the “Autoselect Command Sequence” on page 104 section for more information.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
79
D a t a s h e e t
Table 18. Autoselect Codes, (High Voltage Method)
DQ7 to DQ0
Model Number
A22
to
A15
A14
to
A10
A8
to A6
A7
A5 A3
DQ8 to DQ15
Description CE# OE# WE#
A9
to
to A1 A0
BYTE# BYTE#=
R1, R2,
R0 R8, R9
R5, R6,
R7
A4 A2
= V
V
R3,R4
IH
IL
Manufacture
r ID:
Spansion
Products
L
L
L
L
H
H
X
X
X
X
V
X
X
L
L
X
X
L
L
L
00
X
01h
01h
01h
01h
ID
ID
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
Cycle 3
Cycle 1
Cycle 2
L
H
H
L
L
H
H
L
H
L
22
22
22
22
22
22
22
22
X
X
X
X
X
X
X
X
7Eh
12h
01h
7Eh
12h
00h
7Eh
0Ch
V
H
H
L
L
L
L
L
H
H
X
X
X
X
V
X
X
L
L
X
X
H
H
L
H
H
L
ID
ID
H
H
L
7Eh
13h
7Eh
10h
7Eh
13h
H
H
V
00h (-R4,
bottom boot)
01h (-R3, top
boot)
Cycle 3
H
H
H
22
X
00h
01h
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
1Ch
7Eh
1Dh
7Eh
1Ah
7Eh
1Ah
H
H
00h(-R6
bottom
L
L
H
X
X
V
X
L
X
ID
00h (-R4,
bottom boot) boot)
01h (-R3, top 01h (-
Cycle 3
H
L
H
H
H
L
22
X
X
X
00h
00h
boot)
R5, top
boot)
Sector
Group
Protection
Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
V
V
X
X
L
L
X
X
ID
SecSi Sector
Indicator Bit
(DQ7), WP#
protects
highest
address
98h (factory locked),
18h (not factory locked)
L
L
H
H
H
H
X
X
X
X
ID
sector
SecSi Sector
Indicator Bit
(DQ7), WP#
protects
lowest
address
88h (factory locked),
08h (not factory locked)
L
L
H
X
X
V
X
L
X
ID
sector
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
80
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group.
In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time
(see Table 4 on page 28). The hardware sector group unprotection feature re-enables both program and erase
operations in previously protected sector groups. Sector group protection/unprotection can be implemented via
two methods.
Sector protection/unprotection requires V on the RESET# pin only, and can be implemented either in-system or
ID
via programming equipment. Figure 2, on page 96 shows the algorithms and Figure 24, on page 140 shows the
timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all un-
protected sector groups must first be protected prior to the first sector group unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of programming and protect-
ing sector groups at its factory prior to shipping the device through Spansion Programming Service. Contact a
Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected. See the “Autoselect Mode” on
page 79 section for details.
Table 19. S29GL032M (Model R0) Sector Group Protection/Unprotection Address Table
Sector Group
SA0–SA3
A22–A18
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
Note: All sector groups are 256 Kbytes in size
.
Table 20. S29GL032M (Models R1, R2) Sector Group Protection/Unprotection Address Table (Sheet 1 of 2)
Sector Group
SA0
A20–A15
000000
000001
000010
000011
0001xx
0010xx
0011xx
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
81
D a t a s h e e t
Table 20. S29GL032M (Models R1, R2) Sector Group Protection/Unprotection Address Table (Sheet 2 of 2)
Sector Group
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60
A20–A15
0100xx
0101xx
0110xx
0111xx
1000xx
1001xx
1010xx
1011xx
1100xx
1101xx
1110xx
111100
111101
111110
111111
SA61
SA62
SA63
Table 21. S29GL032M (Models R3, R5) Sector Group Protection/Unprotection Address Table
Sector/
Sector
SA0-SA3
A20–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
0000XXXXXh
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh,
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52-SA55
SA56-SA59
111100XXXh
111101XXXh
111110XXXh
SA60-SA62
192 (3x64) Kbytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
82
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 22. S29GL032M (Models R4, R6) Sector Group Protection/Unprotection Address Table
Sector/
Sector
SA0
SA1
A20–A12
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
Sector Block Size
8 Kbytes
8 Kbytes
SA2
SA3
8 Kbytes
8 Kbytes
SA4
SA5
8 Kbytes
8 Kbytes
SA6
SA7
8 Kbytes
8 Kbytes
000001XXXh,
000010XXXh,
000011XXXh,
SA8–SA10
192 (3x64) Kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
0001XXXXXh
0010XXXXXh
0011XXXXXh
0100XXXXXh
0101XXXXXh
0110XXXXXh
0111XXXXXh
1000XXXXXh
1001XXXXXh
1010XXXXXh
1011XXXXXh
1100XXXXXh
1101XXXXXh
1110XXXXXh
1111XXXXXh
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
83
D a t a s h e e t
Table 23. S29GL064M (Model 00) Sector Group Protection/Unprotection Address Table
Sector Group
SA0–SA3
A22–A18
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Note: All sector groups are 256 Kbytes in size.
84
S29GLxxxM MirrorBitTM Flash Family
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D a t a s h e e t
Table 24. S29GL064M (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Address Table
Sector Group
SA0
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
10000xx
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
11010xx
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
SA125
SA126
SA127
Octorber 18, 2004 S29GLxxxM_00_B3
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85
D a t a s h e e t
Table 25. S29GL064M (Model R3) Sector Group Protection/Uprotection Address Table
Sector/
Sector
SA0-SA3
A21–A12
Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
00000XXXXX
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
SA60-SA63
SA64-SA67
SA68-SA71
SA72-SA75
SA76-SA79
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
SA100-SA103
SA104-SA107
SA108-SA111
SA112-SA115
SA116-SA119
SA120-SA123
1111100XXX
1111101XXX
1111110XXX
SA124-SA126
192 (3x64) Kbytes
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
86
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 26. S29GL064M (Model R4) Sector Group Protection/Unprotection Address Table
Sector/
Sector
SA0
SA1
A21–A12
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
Sector Block Size
8 Kbytes
8 Kbytes
SA2
SA3
8 Kbytes
8 Kbytes
SA4
SA5
8 Kbytes
8 Kbytes
SA6
SA7
8 Kbytes
8 Kbytes
0000001XXX,
0000010XXX,
0000011XXX,
SA8–SA10
192 (3x64) Kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
11111XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
SA131–SA134
Octorber 18, 2004 S29GLxxxM_00_B3
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87
D a t a s h e e t
Table 27. S29GL064M (Model R5) Sector Group Protection/Unprotection Address Table
Sector Group
SA0–SA3
A21–A17
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Note: All sector groups are 128 Kwords in size.
88
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 28. S29GL064M (Models R6, R7) Sector Group Protection/Unprotection Address Table
Sector Group
SA0–SA3
A21–A17
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
Note: All sector groups are 128 Kwords in size.
Octorber 18, 2004 S29GLxxxM_00_B3
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89
D a t a s h e e t
Table 29. S29GL128M Sector Group Protection/Unprotection Address Table (Sheet 1 of 2)
Sector Group
SA0
A22–A15
00000000
00000001
00000010
00000011
000001xx
000010xx
000011xx
000100xx
000101xx
000110xx
000111xx
001000xx
001001xx
001010xx
001011xx
001100xx
001101xx
001110xx
001111xx
010000xx
010001xx
010010xx
010011xx
010100xx
010101xx
010110xx
010111xx
011000xx
011001xx
011010xx
011011xx
011100xx
011101xx
011110xx
011111xx
100000xx
100001xx
100010xx
100011xx
100100xx
100101xx
100110xx
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
SA128–SA131
SA132–SA135
SA136–SA139
SA140–SA143
SA144–SA147
SA148–SA151
SA152–SA155
90
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 29. S29GL128M Sector Group Protection/Unprotection Address Table (Sheet 2 of 2)
Sector Group
SA156–SA159
SA160–SA163
SA164–SA167
SA168–SA171
SA172–SA175
SA176–SA179
SA180–SA183
SA184–SA187
SA188–SA191
SA192–SA195
SA196–SA199
SA200–SA203
SA204–SA207
SA208–SA211
SA212–SA215
SA216–SA219
SA220–SA223
SA224–SA227
SA228–SA231
SA232–SA235
SA236–SA239
SA240–SA243
SA244–SA247
SA248–SA251
SA252
A22–A15
100111xx
101000xx
101001xx
101010xx
101011xx
101100xx
101101xx
101110xx
101111xx
110000xx
110001xx
110010xx
110011xx
110100xx
110101xx
110110xx
110111xx
111000xx
111001xx
111010xx
111011xx
111100xx
111101xx
111110xx
11111100
11111101
11111110
11111111
SA253
SA254
SA255
Octorber 18, 2004 S29GLxxxM_00_B3
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91
D a t a s h e e t
Table 30. S29GL256M Sector Group Protection/Unprotection Address Table (Sheet 1 of 4)
Sector Group
SA0
A23–A15
000000000
000000001
000000010
000000011
0000001xx
0000010xx
0000011xx
0000100xx
0000101xx
0000110xx
0000111xx
0001000xx
0001001xx
0001010xx
0001011xx
0001100xx
0001101xx
0001110xx
0001111xx
0010000xx
0010001xx
0010010xx
0010011xx
0010100xx
0010101xx
0010110xx
0010111xx
0011000xx
0011001xx
0011010xx
0011011xx
0011100xx
0011101xx
0011110xx
0011111xx
0100000xx
0100001xx
0100010xx
0100011xx
0100100xx
0100101xx
0100110xx
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
SA128–SA131
SA132–SA135
SA136–SA139
SA140–SA143
SA144–SA147
SA148–SA151
SA152–SA155
92
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 30. S29GL256M Sector Group Protection/Unprotection Address Table (Sheet 2 of 4)
Sector Group
SA156–SA159
SA160–SA163
SA164–SA167
SA168–SA171
SA172–SA175
SA176–SA179
SA180–SA183
SA184–SA187
SA188–SA191
SA192–SA195
SA196–SA199
SA200–SA203
SA204–SA207
SA208–SA211
SA212–SA215
SA216–SA219
SA220–SA223
SA224–SA227
SA228–SA231
SA232–SA235
SA236–SA239
SA240–SA243
SA244–SA247
SA248–SA251
SA252–SA255
SA256–SA259
SA260–SA263
SA264–SA267
SA268–SA271
SA272–SA275
SA276–SA279
SA280–SA283
SA284–SA287
SA288–SA291
SA292–SA295
SA296–SA299
SA300–SA303
SA304–SA307
SA308–SA311
SA312–SA315
SA316–SA319
SA320–SA323
A23–A15
0100111xx
0101000xx
0101001xx
0101010xx
0101011xx
0101100xx
0101101xx
0101110xx
0101111xx
0110000xx
0110001xx
0110010xx
0110011xx
0110100xx
0110101xx
0110110xx
0110111xx
0111000xx
0111001xx
0111010xx
0111011xx
0111100xx
0111101xx
0111110xx
0111111xx
1000000xx
1000001xx
1000010xx
1000011xx
1000100xx
1000101xx
1000110xx
1000111xx
1001000xx
1001001xx
1001010xx
1001011xx
1001100xx
1001101xx
1001110xx
1001111xx
1010000xx
Octorber 18, 2004 S29GLxxxM_00_B3
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93
D a t a s h e e t
Table 30. S29GL256M Sector Group Protection/Unprotection Address Table (Sheet 3 of 4)
Sector Group
SA324–SA327
SA328–SA331
SA332–SA335
SA336–SA339
SA340–SA343
SA344–SA347
SA348–SA351
SA352–SA355
SA356–SA359
SA360–SA363
SA364–SA367
SA368–SA371
SA372–SA375
SA376–SA379
SA380–SA383
SA384–SA387
SA388–SA391
SA392–SA395
SA396–SA399
SA400–SA403
SA404–SA407
SA408–SA411
SA412–SA415
SA416–SA419
SA420–SA423
SA424–SA427
SA428–SA431
SA432–SA435
SA436–SA439
SA440–SA443
SA444–SA447
SA448–SA451
SA452–SA455
SA456–SA459
SA460–SA463
SA464–SA467
SA468–SA471
SA472–SA475
SA476–SA479
SA480–SA483
SA484–SA487
SA488–SA491
A23–A15
1010001xx
1010010xx
1010011xx
1010100xx
1010101xx
1010110xx
1010111xx
1011000xx
1011001xx
1011010xx
1011011xx
1011100xx
1011101xx
1011110xx
1011111xx
1100000xx
1100001xx
1100010xx
1100011xx
1100100xx
1100101xx
1100110xx
1100111xx
1101000xx
1101001xx
1101010xx
1101011xx
1101100xx
1101101xx
1101110xx
1101111xx
1110000xx
1110001xx
1110010xx
1110011xx
1110100xx
1110101xx
1110110xx
1110111xx
1111000xx
1111001xx
1111010xx
94
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Table 30. S29GL256M Sector Group Protection/Unprotection Address Table (Sheet 4 of 4)
Sector Group
SA492–SA495
SA496–SA499
SA500–SA503
SA504–SA507
SA508
A23–A15
1111011xx
1111100xx
1111101xx
1111110xx
111111100
111111101
111111110
111111111
SA509
SA510
SA511
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The
Sector Group Unprotect mode is activated by setting the RESET# pin to V . During this mode, formerly protected
ID
sector groups can be programmed or erased by selecting the sector group addresses. Once V is removed from
ID
the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm,
and Figure 23, on page 135 shows the timing diagrams, for this feature.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = VIL, the highest or lowest address sector remains protected for
uniform sector devices, the top or bottom two address sectors remains protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
Octorber 18, 2004 S29GLxxxM_00_B3
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95
D a t a s h e e t
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 µs
Wait 1 µs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Unprotect Algorithms
96
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identi-
fication through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi
Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory.
This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part.
This ensures the security of the ESN once the product is shipped to the field.
The factory offers the device with the SecSi Sector either customer lockable (standard shipping option) or factory
locked (contact a Spansion sales representative for ordering information). The customer-lockable version is
shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device.
The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a “0.” The factory-locked
version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator
Bit permanently set to a “1.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being
used to replace devices that are factory locked.
Notes: The ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
The SecSi sector address space in this device is allocated as follows:
SecSi Sector Address
Range
ExpressFlash
Factory Locked
Customer Lockable ESN Factory Locked
ESN or determined by
customer
000000h–000007h
000008h–00007Fh
ESN
Determined by
customer
Determined by
customer
Unavailable
The system accesses the SecSi Sector through a command sequence (see “Write Protect (WP#)” on page 98).
After the system writes the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the
addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following
a hardware reset, the device reverts to sending commands to sector SA0.
Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte
SecSi sector.
The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in
addition to the standard programming command sequence. See “Command Definitions” on page 103.
Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no pro-
cedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space
can be modified in any way.
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, on page 96, except that RESET# may be at either V
IH
or V . This allows in-system protection of the SecSi Sector without raising any device pin to a high
ID
voltage. Note that this method is only applicable to the SecSi Sector.
Write the three-cycle Enter SecSi Sector Region command sequence and then use the alternate
method of sector protection described in the “Sector Group Protection and Unprotection” section.
Once the SecSi Sector is programmed, locked, and verified, the system must write the Exit SecSi Sector Region
command sequence to return to reading and writing within the remainder of the array.
Octorber 18, 2004 S29GLxxxM_00_B3
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97
D a t a s h e e t
Factory Locked: SecSi Sector Programmed and Protected At the Factory
In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sec-
tor cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses
000000h–000007h. Please contact your sales representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion programming service
(Customer Factory Locked). The devices are then shipped from the factory with the SecSi Sector permanently
locked. Contact your sales representative for details on using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group without using
V
. Write Protect is one of two functions provided by the WP#/ACC input.
ID
If the system asserts V on the WP#/ACC pin, the device disables program and erase functions in the first or last
IL
sector group independently of whether those sector groups were protected or unprotected. Note that if WP#/ACC
is at V when the device is in the standby mode, the maximum input load current is increased. See Table 22 on
IL
page 83.
Note: If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was
previously set to be protected or unprotected using the method described in “Sector Group Protection and
Unprotection”. Note that WP# has an internal pullup; when unconnected, WP# is at VIH
.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 35 on page 113 and Table 36 on page 114 for command definitions). In
addition, the following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level signals during V power-up and power-down transitions, or
CC
from system noise.
Low V Write Inhibit
CC
When V is less than V , the device does not accept any write cycles. This protects data during V power-up
CC
LKO
CC
and power-down. The command register and all internal program/erase circuits are disabled, and the device re-
sets to the read mode. Subsequent writes are ignored until V is greater than V . The system must provide
CC
LKO
the proper signals to the control pins to prevent unintentional writes when V is greater than V
.
CC
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the device does not accept commands on the rising edge
IL
IH
of WE#. The internal state machine is automatically reset to the read mode on power-up.
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation hand-
shake, which allows specific vendor-specified software algorithms to be used for entire families of devices.
Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compat-
ible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h,
any time the device is ready to read array data. The system can read CFI information at the addresses given in
Table 31 on page 99 through Table 34 on page 102. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device enters
the CFI query mode, and the system can read CFI data at the addresses given in Table 31 on page 99 through
Table 34 on page 102. The system must write the reset command to return the device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Alternatively, contact your
sales representative for copies of these documents.
Table 31. CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
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Table 32. System Interface String
Addresses
(x16)
Addresses
(x8)
Data
Description
VCC Min. (write/erase)
0027h
1Bh
1Ch
36h
38h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0007h
0007h
000Ah
0000h
0001h
0005h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Reserved for future use
Typical timeout for Min. size buffer write 2N
µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Reserved for future use
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering
Information tables to obtain the VCC range for particular part numbers. Please see the “Erase and Programming Performance” on
page 141 table for typical timeout specifications.
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Table 33. Device Geometry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
0019h
0018h
0017h
0016h
Device Size = 2N byte
27h
4Eh
19 = 256 Mb, 18 = 128 Mb, 17 = 64 Mb, 16 = 32 Mb
Flash Device Interface description (refer to CFI publication 100)
28h
29h
50h
52h
000xh
0000h
0000h = x8-only bus devices
0001h = x16-only bus devices
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
0001h
0002h
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Ch
58h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
003Fh, 0000h, 0001h = 32 Mb (-R0, -R3, -R4, R5, R6)
007Fh, 0000h, 0020h, 0000h = 32 Mb (-R1, -R2), 64 Mb (-R1, -R2)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R0, -R3, -R4, -R5, -R6, -R7)
00FFh, 0000h, 0000h, 0001h = 128 Mb
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
00FFh, 0001h, 0000h, 0001h = 256 Mb
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
Erase Block Region 2 Information (refer to CFI publication 100)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2)
0000h, 0000h, 0000h, 0000h = all others
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
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Table 34. Primary Vendor-Specific Extended Query
Addresses
(x16)
Addresses
(x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
000xh
Process Technology (Bits 7-2) 0010b = 0.23
0009h = x8-only bus devices
µm MirrorBit
0008h = all other devices
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0001h
0004h
0000h
0000h
0001h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect, 02h = Bottom Boot
Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP#
protect, 05h = Uniform sectors top WP# protect
4Fh
50h
9Eh
A0h
00xxh
0001h
Program Suspend
00h = Not Supported, 01h = Supported
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Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations.
Table 35 on page 113 and Table 36 on page 114 define the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence may place the device in an unknown state. A
reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the
rising edge of WE# or CE#, whichever happens first. Refer to the “AC Characteristics” on page 124 section for
timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve
data. The device is ready to read array data after completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after
which the system can read data from any non-erase-suspended sector. After completing a programming operation
in the Erase Suspend mode, the system may once again read array data with the same exception. See the “Erase
Suspend/Erase Resume Commands” on page 111 section for more information.
The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next
section, Reset Command, for more information.
See also “Requirements for Reading Array Data” on page 30 in the Device Bus Operations section for more infor-
mation. The Read-Only Operations–“AC Characteristics” on page 124 provides the read parameters, and
Figure 13, on page 126 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing
begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset com-
mands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before pro-
gramming begins. This resets the device to the read mode. If the program command sequence is written while
the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-
read mode. Once programming begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in
the autoselect mode, the reset command must be written to return to the read mode. If the device entered the
autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-
suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read
mode (or erase-suspend-read mode if the device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Write-to-
Buffer-Abort Reset command sequence to reset the device for the next operation.
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D a t a s h e e t
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at specific addresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
SecSi Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
Note: The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read
at any address any number of times without initiating another autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device
was previously in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial
Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector com-
mand sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal
operation. Table 35 on page 113 and Table 36 on page 114 show the address and data requirements for both com-
mand sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that
the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command. The program address and data are written next, which in
turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings.
The device automatically provides internally generated program pulses and verifies the programmed cell margin.
Table 35 on page 113 and Table 36 on page 114 show the address and data requirements for the word program
command sequence, respectively.
When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are
no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to
the Write Operation Status section for information on these status bits. Any commands written to the device dur-
ing the Embedded Program Algorithm are ignored. Note that the SecSi Sector, autoselect, and CFI functions are
unavailable when a program operation is in progress. Note that a hardware reset immediately terminates the
program operation. The program command sequence should be reinitiated once the device returns to the read
mode, to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector boundaries. Programming to the
same word address multiple times without intervening erases (incremental bit programming) requires a modified
programming method. For such application requirements, please contact your local Spansion representative.
Word programming is supported for backward compatibility with existing Flash driver software and for occasional
writing of individual words. Use of write buffer programming (see below) is strongly recommended for general
programming use when more than a few words are to be programmed. The effective word programming time
using write buffer programming is approximately four times shorter than the single word programming time.
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Any bit in a word cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device
to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding
read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard pro-
gram command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles.
This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the
unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to program in
this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle
contains the program address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting in faster total
programming time. Table 35 on page 113 and Table 36 on page 114 show the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence.
The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns
to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming op-
eration. This results in faster effective programming time than the standard programming algorithms. The Write
Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs.
The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For
example, if the system programs six unique address locations, then 05h should be written to the device. This tells
the device how many write buffer addresses are loaded with data and therefore when to expect the Program
Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by
address bits A
–A . All subsequent address/data pairs must fall within the selected-write-buffer-page. The sys-
4
MAX
tem then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in
any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This
means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means that
Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load program-
ming data outside of the selected write-buffer page, the operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decremented
for every data load operation. The host system must therefore account for loading a write-buffer location more
than once. The counter decrements for each data load operation, not for each unique write-buffer-address loca-
tion. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that
address is programmed.
Once the specified number of write buffer locations are loaded, the system must then write the Program Buffer
to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Pro-
gramming operation. The device then begins programming. Data polling should be used while monitoring the
last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine
the device status during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume com-
mands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute
the next command.
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D a t a s h e e t
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to Program
step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load com-
mand.
Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting
Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle,
and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next
operation.
Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in
progress.This flash device is capable of handling multiple write buffer programming operations on the same write
buffer address range without intervening erases. For applications requiring incremental bit programming, a mod-
ified programming method is required; please contact your local Spansion representative. Any bit in a write
buffer address range cannot be programmed from “0” back to a “1.” Attempting to do so may cause the
device to set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a
succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC pin depending on the particular
product. When the system asserts V
on the WP#/ACC or ACC pin. The device uses the higher voltage on the
HH
WP#/ACC or ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V
for operations
HH
other than accelerated programming, or device damage may result. WP# has an internal pullup; when uncon-
nected, WP# is at V
.
IH
Figure 3, on page 107 illustrates the algorithm for the program operation. Refer to the “Erase and Program Op-
erations-S29GL032M only” on page 131 and “AC Characteristics” on page 124 section for parameters, and
Figure 14, on page 126 for timing diagrams.
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Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
(Note 1)
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Yes
DQ7 = Data?
No
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
No
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this
flowchart location was reached because DQ1=
“1”, then the Write to Buffer operation was
ABORTED. In either case, the proper reset
command must be written before the device can
begin another operation. If DQ1=1, write the
Write-Buffer-Programming-Abort-Reset
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
command. if DQ5=1, write the Reset command.
4. See Table 35 and Table 36 for command
Yes
(Note 2)
DQ7 = Data?
No
FAIL or ABORT
PASS
(Note 3)
Figure 3. Write Buffer Programming Operation
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START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 35 and Table 36 for program com-
mand sequence.
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer pro-
gramming operation so that data can be read from any non-suspended sector. When the Program Suspend
command is written during a programming process, the device halts the program operation within 15 µs maximum
(5µs typical) and updates the status bits. Addresses are not required when writing the Program Suspend
command.
After the programming operation is suspended, the system can read array data from any non-suspended sector.
The Program Suspend command may also be issued during a programming operation while an erase is suspended.
In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed
from the SecSi Sector area (One-time Program area), then user must use the proper command sequences to enter
and exit this region. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program
operation is in progress.
The system may also write the autoselect command sequence when the device is in the Program Suspend mode.
The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device
reverts to the Program Suspend mode, and is ready for another valid operation. See “Autoselect Command Se-
quence” on page 104 for more information.
After the Program Resume command is written, the device reverts to programming. The system can determine
the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
See “Write Operation Status” on page 115 for more information.
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The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend
mode and continue the programming operation. Further writes of the Resume command are ignored. Another Pro-
gram Suspend command can be written after the device resumes programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations. Table 35 on page 113 and Table 36 on page 114 show the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to
the “Write Operation Status” on page 115 section for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated
once the device returns to reading array data, to ensure data integrity.
Figure 6, on page 111 illustrates the algorithm for the erase operation. Refer to the “Erase and Programming Per-
formance” on page 141 in the “AC Characteristics” on page 124 section for parameters, and Figure 18, on
page 133 for timing diagrams.
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D a t a s h e e t
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the
address of the sector to be erased, and the sector erase command. Table 35 on page 113 and Table 36 on
page 114 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automati-
cally programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, ad-
ditional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these
additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to the read mode. Note that the SecSi Sector, autoselect, and CFI func-
tions are unavailable when an erase operation is in progress. The system must rewrite the command sequence
and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector
Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no
longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the
erasing sector. Refer to the “Write Operation Status” on page 115 section for information on these status bits.
Once the sector erase operation starts, only the Erase Suspend command is valid. All other commands are ig-
nored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the
sector erase command sequence should be reinitiated once the device returns to reading array data, to ensure
data integrity.
Figure 6, on page 111 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations
table in the “AC Characteristics” on page 124 section for parameters, and Figure 18, on page 133 for timing
diagrams.
110
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D a t a s h e e t
l
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 35 on page 113 and Table 36 on
page 114 for program command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 6. Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase
operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend
command is ignored if written during the chip erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device requires a typical of
5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors se-
lected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–
DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-
suspended. Refer to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode.
The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the
standard word program operation. Refer to the Write Operation Status section for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Au-
toselect Mode” on page 79 and “Autoselect Command Sequence” on page 104 sections for details.
Octorber 18, 2004 S29GLxxxM_00_B3
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D a t a s h e e t
To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written after the chip resumes erasing.
Notes:
During an erase operation, this flash device performs multiple internal operations which are invisible to the system. When an
erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As such, if this flash
device is continually issued suspend/resume commands in rapid succession, erase progress are impeded as a function of the
number of suspends. The result is a longer cumulative erase time than without suspends. Note that the additional suspends do
not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases,
erase performance is not significantly impacted.
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D a t a s h e e t
Command Definitions
Table 35. Command Definitions (x16 Mode, BYTE# = VIH
)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Manufacturer ID
4
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
(Note
18)
(Note
18)
Device ID (Note 9)
4
4
4
555
555
555
AA
AA
AA
X0E
X0F
SecSi‰ Sector Factory Protect
(Note 10)
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify (Note
12)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
1
555
555
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
555
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
555
SA
WC
PA
PD
WBL
PD
SA
3
3
2
2
6
6
1
555
AA
AA
A0
90
2AA
2AA
PA
55
55
555
555
F0
20
555
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
XXX
555
PD
00
55
XXX
2AA
2AA
AA
AA
B0
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
Sector Erase
555
55
30
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
XXX
XXX
55
1
30
1
98
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 on page 22 for description of bus operations.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
18. Refer to Table 18 on page 80, AutoSelect Codes for individual
Device IDs per device density and model number.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
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D a t a s h e e t
Table 36. Command Definitions (x8 Mode, BYTE# = VIL)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
RD
F0
XXX
AAA
Manufacturer ID
4
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
(Note
17)
(Note
17)
Device ID (Note 9)
4
AAA
AA
7E
X1C
X1E
SecSi‰ Sector Factory Protect
(Note 10)
4
4
AAA
AAA
AA
AA
555
555
55
55
AAA
AAA
90
90
X06
(Note 10)
00/01
Sector Group Protect Verify (Note
12)
(SA)X04
Enter SecSi Sector Region
Exit SecSi Sector Region
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Chip Erase
3
4
3
1
AAA
AAA
AAA
SA
AA
AA
AA
29
555
555
555
55
55
55
AAA
AAA
SA
88
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
3
6
6
1
AAA
AAA
AAA
XXX
XXX
AA
AA
AA
AA
B0
555
555
555
55
55
55
AAA
AAA
AAA
F0
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
Sector Erase
30
Program/Erase Suspend (Note 14)
Program/Erase Resume (Note 15)
CFI Query (Note 16)
1
30
1
98
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 on page 22 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or AAA as shown in table, address bits above A11 are don’t
care.
10. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determined by
number of bytes written to write buffer. Maximum number of
cycles in command sequence is 37, including “Program Buffer to
Flash” command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
7. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
17. Refer to Table 18 on page 80, AutoSelect Codes for individual
Device IDs per device density and model number.
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D a t a s h e e t
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6,
and DQ7. Table 37 on page 120 and the following subsections describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a program or erase operation is complete or in progress. The device
also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase
operation is in progress or is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of
the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algo-
rithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program
address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling
on DQ7 is active for approximately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algo-
rithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The
system must provide an address within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on
DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that
are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be
valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status in-
formation to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status
or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data
outputs on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 37 on page 120 shows the outputs for Data# Polling on DQ7. Figure 7, on page 116 shows the Data# Polling
algorithm. Figure 17, on page 132 shows the Data# Polling timing diagram.
Octorber 18, 2004 S29GLxxxM_00_B3
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D a t a s h e e t
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence.
Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor
to V
.
CC
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-
suspend-read mode. Table 37 on page 120 shows the outputs for RY/BY#.
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D a t a s h e e t
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or
whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after
the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to
toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6
stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-sus-
pended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles.
When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2
to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the sub-
section on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program com-
mand sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program al-
gorithm is complete.
Table 37 on page 120 shows the outputs for Toggle Bit I on DQ6. Figure 8, on page 118 shows the toggle bit al-
gorithm. Figure 20, on page 134 shows the toggle bit timing diagrams. Figure 21, on page 134 shows the
differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Octorber 18, 2004 S29GLxxxM_00_B3
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D a t a s h e e t
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Operation Complete
Complete, Write
Reset Command
Note:
The system should recheck the toggle bit even if DQ5 = “1”
because the toggle bit may stop toggling as DQ5 changes
to “1.” See the subsections on DQ6 and DQ2 for more
information.
Figure 8. Toggle Bit Algorithm
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S29GLxxxM MirrorBitTM Flash Family
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D a t a s h e e t
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is,
the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively
erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for
sector and mode information. Refer to Table 37 on page 120 to compare outputs for DQ2 and DQ6.
Figure 8, on page 118 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” ex-
plains the algorithm. See also the “RY/BY#: Ready/Busy#” on page 116 subsection. Figure 20, on page 134
shows the toggle bit timing diagram. Figure 21, on page 134 shows the differences between DQ2 and DQ6 in
graphical form.
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then de-
termine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went
high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation.
If it is still toggling, the device did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 did not go
high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining
the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the algorithm when it returns to determine the status of the
operation (top of Figure 6, on page 111).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading the array (or to
erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure
started. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the
system can be assumed to be less than 50 µs, the system need not monitor DQ3. See the “Sector Erase Command
Sequence” on page 110 section.
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D a t a s h e e t
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Tog-
gle Bit I) to ensure that the device accepted the command sequence, and then reads DQ3. If DQ3 is “1,” the
Embedded Erase algorithm started; all further commands (except Erase Suspend) are ignored until the erase op-
eration is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command
was accepted, the system software should check the status of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status check, the last command might not have been accepted.
Table 37 on page 120 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The
system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array data.
See “Write Buffer” on page 30 for more details.
Table 37. Write Operation Status
DQ7
(Note 2)
DQ5
(Note 1) DQ3
DQ2
(Note 2)
RY/
BY#
Status
DQ6
DQ1
0
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program Program-
Suspend
Mode
Sector
Suspend
Read
Non-Program
Suspended Sector
Erase-Suspended
Sector
1
No toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Read
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation exceeded the
maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device aborts the write-to-buffer operation
120
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Absolute Maximum Ratings
Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
V
(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
CC
. . . . . . . . . . . . A9, OE#, ACC and RESET# (Note 2)–0.5 V to +12.5 V
All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs
or I/Os may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9, on
page 121. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage
transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods up to 20
ns. See Figure 10, on page 121.
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During
voltage transitions, A9, OE#, ACC, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. See Figure 9, on page 121. Maximum DC input voltage on
pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0V for
periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to
absolute maximum rating conditions for extended periods may affect device
reliability.
20 ns
20 ns
20 ns
VCC
+2.0 V
+0.8 V
VCC
–0.5 V
–2.0 V
+0.5 V
2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative
Overshoot Waveform
Figure 10. Maximum Positive
Overshoot Waveform
Operating Ranges
Industrial (I) Devices
Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A
Supply Voltages
V
V
for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V
for regulated voltage range. . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V
CC
CC
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IO
CC
Notes:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
121
D a t a s h e e t
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
(Notes)
V
V
= V to V
,
IN
CC
SS
CC
I
Input Load Current (1)
1.0
µA
LI
= V
= V
= V
CC max
CC max
CC max
I
A9, ACC Input Load Current
Reset Leakage Current
V
V
; A9 = 12.5 V
35
35
µA
µA
LIT
CC
I
; RESET# = 12.5 V
LR
CC
V
V
= V to V
SS
CC max
,
CC
OUT
CC
I
Output Leakage Current
1.0
µA
LO
= V
1 MHz
5
20
25
35
50
60
20
40
60
5 MHz (4)
5 MHz (5)
10 MHz (4)
10 MHz (5)
10 MHz
18
25
35
40
5
I
V
Initial Read Current (2), (3)
CE# = V OE# = V
,
mA
CC1
CC
IL,
IH
I
V
Intra-Page Read Current (2), (3)
CE# = V OE# = V
mA
CC2
CC
IL,
IH
40 MHz
10
50
I
I
I
I
V
V
V
Active Write Current (3), (4)
Standby Current (3)
Reset Current (3)
CE# = V OE# = V
mA
µA
µA
µA
CC3
CC4
CC5
CC6
CC
CC
CC
IL,
IH
CE#, RESET# = V
0.3 V,
CC
1
1
1
5
5
WP# = V
IH
RESET# = V
0.3 V, WP# = V
IH
SS
V
= V
0.3 V;
IH
CC
IL
Automatic Sleep Mode (3), (7)
5
-0.1< V ≤ 0.3 V, WP# = V
IH
V
Input Low Voltage 1(8)
–0.5
0.8
V
V
V
IL
V
Input High Voltage 1 (8)
0.7 V
V
+ 0.5
CC
IH
CC
V
Voltage for ACC Program Acceleration
V
V
= 2.7 –3.6 V
= 2.7 –3.6 V
11.5
11.5
12.0
12.0
12.5
12.5
0.45
HH
CC
Voltage for Autoselect and Temporary
Sector Unprotect
V
V
ID
CC
V
Output Low Voltage (8)
I
I
I
= 4.0 mA, V = V
CC min
V
V
V
V
OL
OL
OH
OH
CC
V
V
= –2.0 mA, V = V
0.85 V
CC
OH1
OH2
CC
CC min
CC min
Output High Voltage
= –100 µA, V = V
V
–0.4
CC
CC
V
Low V Lock-Out Voltage (9)
2.3
2.5
LKO
CC
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 2.0 µA.
2. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. S29GL032M, S29GL064M
.
5. S29GL128M, S29GL256M
6. ICC active while Embedded Erase or Embedded Program is in progress.
7. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
8. VCC voltage requirements.
9. Not 100% tested.
122
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Test Conditions
Table 38. Test Specifications
3.3 V
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
C
L
6.2 kΩ
0.0 or V
CC
Input timing measurement
reference levels (See Note)
0.5 V
0.5 V
V
V
CC
Output timing measurement
reference levels
CC
Note: Diodes are IN3064 or equivalent
Figure 11. Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
Figure 12. Input Waveforms and
Measurement Levels
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
123
D a t a s h e e t
AC Characteristics
Read-Only Operations-S29GL256M only
Parameter
Speed Options
Description
Test Setup
Unit
JEDEC
Std.
10
11
tAVAV
tRC
Read Cycle Time (Note 1)
Min
CE#, OE# = VIL Max
100
100
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tACC Address to Output Delay
tCE Chip Enable to Output Delay
tPACC Page Access Time
100
100
30
100
100
30
OE# = VIL
Max
Max
Max
Max
Max
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
30
30
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
(Note 1)
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 38 for test specifications.
Read-Only Operations-S29GL128M only
Parameter
Speed Options
Description
Test Setup
Unit
JEDEC
Std.
90
10
tAVAV
tRC
Read Cycle Time (Note 1)
Min
90
100
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tACC Address to Output Delay
tCE Chip Enable to Output Delay
tPACC Page Access Time
CE#, OE# = VIL Max
90
90
25
25
100
100
30
OE# = VIL
Max
Max
Max
Max
Max
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
30
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
(Note 1)
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 38 for test specifications.
124
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Read-Only Operations-S29GL064M only
Parameter
Speed Options
Description
Test Setup
Unit
JEDEC
Std.
90
10
11
tAVAV
tRC Read Cycle Time (Note 1)
Min
CE#, OE# = VIL Max
90
100 110
100 110
100 110
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tACC Address to Output Delay
90
90
25
25
tCE Chip Enable to Output Delay
tPACC Page Access Time
OE# = VIL
Max
Max
Max
Max
Max
30
30
30
30
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
tDF Output Enable to Output High Z (Note 1)
16
16
0
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
ns
ns
ns
Read
0
Output Enable Hold
tOEH
Toggle and
Time (Note 1)
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 38 for test specifications.
Read-Only Operations-S29GL032M only
Parameter
Speed Options
Description
Test Setup
Unit
JEDEC
Std.
90
10
11
tAVAV
tRC Read Cycle Time (Note 1)
Min
CE#, OE# = VIL Max
90
100
110
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tACC Address to Output Delay
90
90
25
25
100
100
30
110
110
30
tCE
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Max
tPACC Page Access Time
tGLQV
tEHQZ
tGHQZ
tOE Output Enable to Output Delay
tDF Chip Enable to Output High Z (Note 1)
tDF Output Enable to Output High Z (Note 1)
30
30
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
tOEH
Toggle and
Time (Note 1)
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 38 for test specifications.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
125
D a t a s h e e t
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
Same Page
A23-A2
A1-A0*
Ad
Aa
tACC
Ab
tPACC
Ac
tPACC
tPACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
* Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
126
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
t
t
Max
Max
20
µs
Ready
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
500
ns
Ready
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
Reset High Time Before Read (See Note)
RESET# Input Low to Standby Mode (See Note)
RY/BY# Output High to CE#, OE# pin Low
RH
t
RPD
t
RB
Notes:
1. Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRH
tRP
Figure 15. Reset Timings
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
127
D a t a s h e e t
Erase and Program Operations-S29GL256M only
Parameter
Speed Options
Unit
JEDEC
Std.
Description
Write Cycle Time (Note 1)
10
11
t
t
Min
Min
Min
Min
100
110
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
0
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
ASO
t
t
WLAX
AH
Address Hold Time From CE# or OE# high during toggle bit
polling
t
Min
0
ns
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
DVWH
DS
t
Data Hold Time
WHDX
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
100
110
BUSY
t
Program Valid before Status Polling
4
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes
POLL
POLL
(that is, the program resume command is written). If the suspend command was issued after t
after programming resumes. See Figure 16, on page 132.
, status data is available immediately
POLL
128
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Erase and Program Operations-S29GL128M Only
Parameter
Speed Options
Unit
JEDEC
Std.
Description
Write Cycle Time (Note 1)
90
10
t
t
Min
Min
Min
Min
90
100
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
0
AVWL
WLAX
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
ASO
t
t
AH
Address Hold Time From CE# or OE# high during toggle bit
polling
t
Min
0
ns
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
DVWH
DS
t
Data Hold Time
WHDX
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
100
BUSY
t
Program Valid before Status Polling
4
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 16, on page 132.
, status data is available immediately
POLL
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
129
D a t a s h e e t
Erase and Program Operations-S29GL064M Only
Parameter
Speed Options
10
Unit
JEDEC Std.
Description
Write Cycle Time (Note 1)
90
11
t
t
Min
Min
Min
Min
90
100
0
110
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
AVWL
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
ASO
t
t
WLAX
AH
Address Hold Time From CE# or OE# high during toggle bit
polling
t
Min
0
ns
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
DVWH
WHDX
DS
t
Data Hold Time
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 16, on page 132.
, status data is available immediately
POLL
130
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Erase and Program Operations-S29GL032M only
Parameter
Speed Options
10
Unit
JEDEC
Std.
Description
Write Cycle Time (Note 1)
90
11
t
t
Min
Min
Min
Min
90
100
0
110
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
AVWL
WLAX
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
ASO
t
t
AH
Address Hold Time From CE# or OE# high during toggle bit
polling
t
Min
0
ns
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Min
Max
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
DVWH
WHDX
DS
t
Data Hold Time
DH
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
µs
ns
µs
WHWH2
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within t , the device requires t before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 16, on page 132.
, status data is available immediately
POLL
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
131
D a t a s h e e t
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tCS
tWHWH1
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Figure 16. Program Operation Timings
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
V
HH
V
or V
IL IH
V
or V
IL IH
ACC
t
t
VHH
VHH
Figure 17. Accelerated Program Timing Diagram
132
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tPOLL
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
133
D a t a s h e e t
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6 / DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
Description
JEDEC
Std
All Speed Options
Unit
t
VID Rise and Fall Time (See Note)
Min
Min
500
ns
VIDR
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note:Not 100% tested.
134
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
V
V
ID
IH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
135
D a t a s h e e t
Alternate CE# Controlled Erase and Program Operations-S29GL256M
Parameter
Speed Options
Unit
JEDEC Std.
Description
10
11
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
0
45
45
0
AVWL
AS
AH
DS
DH
t
t
ELAX
DVEH
EHDX
t
t
t
t
Data Hold Time
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
WLEL
GHEL
t
t
t
0
WS
WH
t
WE# Hold Time
0
EHWH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
CP
t
t
CE# Pulse Width High
EHEL
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resume (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 24, on page 140.
, status data is available immediately
POLL
136
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Alternate CE# Controlled Erase and Program Operations-S29GL128M
Parameter
Speed Options
Unit
JEDEC Std.
Description
10
11
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
0
45
45
0
AVWL
AS
AH
DS
DH
t
t
ELAX
DVEH
EHDX
t
t
t
t
Data Hold Time
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
WLEL
GHEL
t
t
t
0
WS
WH
t
WE# Hold Time
0
EHWH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH1
sec
ns
WHWH2
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 24, on page 140.
, status data is available immediately
POLL
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
137
D a t a s h e e t
Alternate CE# Controlled Erase and Program Operations-S29GL064M
Parameter
Speed Options
Unit
JEDEC Std.
Description
Write Cycle Time (Note 1)
90
10
11
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
90
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
0
45
35
0
AVWL
AS
AH
DS
DH
t
t
Address Hold Time
ELAX
DVEH
EHDX
t
t
t
t
Data Setup Time
Data Hold Time
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
WLEL
GHEL
t
t
t
0
WS
WH
t
WE# Hold Time
0
EHWH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
CP
t
t
CE# Pulse Width High
EHEL
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 5)
t
t
t
t
µs
WHWH1
WHWH1
sec
ns
WHWH2
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 24, on page 140.
, status data is available immediately
POLL
138
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Alternate CE# Controlled Erase and Program Operations-S29GL032M
Parameter
Speed Options
Unit
JEDEC Std.
Description
Write Cycle Time (Note 1)
90
10
11
t
t
Min
Min
Min
Min
Min
90
100
110
ns
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
0
45
35
0
AVWL
AS
AH
DS
DH
t
t
ELAX
DVEH
EHDX
t
t
t
t
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WLEL
WS
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See “Erase and Programming Performance” on page 141 for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading status data, once programming resumes (that
POLL
POLL
is, the program resume command has been written). If the suspend command was issued after t
after programming resumes. See Figure 24, on page 140.
, status data is available immediately
POLL
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
139
D a t a s h e e t
PBA for program
2AA for erase
SA for program buffer to flash
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
PBD for program 29 for program buffer to flash
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
140
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Erase and Programming Performance
Max
Parameter
Typ (Note 1)
(Note 2)
Unit
Comments
Sector Erase Time
0.5
32
3.5
64
sec
Excludes
00h
programm
ingpriorto
erasure
S29GL032M
S29GL064M
S29GL128M
S29GL256M
64
128
256
512
Chip Erase Time
sec
128
256
240
Note (6)
Total Write Buffer Program Time Notes (3), (5)
µs
µs
Total Accelerated Effective Write Buffer Program Time Notes (4),
(5)
200
Excludes
system
level
overhead
Note (7)
S29GL032M
31.5
63
S29GL064M
Chip Program Time
S29GL128M
sec
126
252
S29GL256M
Notes:
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V, 10,000 cycles; checkerboard data pattern.
CC
2. Under worst case conditions of 90°C; Worst case V , 100,000 cycles.
CC
3. Effective programming time (typ) is 15 µs (per word), 7.5 µs (per byte).
4. Effective accelerated programming time (typ) is 12.5 µs (per word), 6.3 µs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 35 on page 113 and
Table 36 on page 114 for further information on command definitions.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
141
D a t a s h e e t
TSOP Pin and BGA Package Capacitance
For package types TA, TF, BA, BF, FA, FF (refer to Ordering Information Pages):
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
TSOP
BGA
C
Input Capacitance
V
= 0
IN
IN
4.2
8.5
5.4
7.5
3.9
pF
TSOP
BGA
pF
C
Output Capacitance
V
= 0
= 0
OUT
OUT
6.5
9
pF
TSOP
BGA
pF
C
Control Pin Capacitance
V
IN
IN2
4.7
pF
For package types TB, TC, BB, BC, (refer to Ordering Information Pages):
Parameter Symbol
Parameter Description
Test Setup
Typ
8
Max
10
10
12
12
10
10
25
20
Unit
pF
pF
pF
pF
pF
pF
pF
pF
TSOP
BGA
C
Input Capacitance
V
= 0
IN
IN
8
TSOP
BGA
8.5
8.5
8
C
Output Capacitance
V
= 0
= 0
= 0
OUT
OUT
TSOP
BGA
C
C
Control Pin Capacitance
V
IN2
IN3
IN
IN
8
TSOP
BGA
20
15
RESET# and WP#/ACC Pin
Capacitance
V
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
142
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Physical Dimensions
TS040—40-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
143
D a t a s h e e t
TSR040—40-Pin Standard/Reverse Thin Small Outline Package (TSOP)
REVERSE PIN OUT (TOP VIEW)
A2
3
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TSR 040
MO-142 (B) EC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
NOT APPLICABLE.
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
9.90 10.00 10.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
40
3324 \ 16-038.10a
144
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
TS048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW)
A2
2
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TS 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (B) EC
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
NOT APPLICABLE.
A
A1
A2
b1
b
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3325 \ 16-038.10a
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
145
D a t a s h e e t
TSR048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)
REVERSE PIN OUT (TOP VIEW)
A2
3
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TSR 048
MO-142 (B) EC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
NOT APPLICABLE.
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
c1
c
D
D1
E
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
e
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3326 \ 16-038.10a
146
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)
NOTES:
PACKAGE
TS/TSR 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
4
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
---
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
D
19.90
18.30
20.00
18.40
20.20
18.50
D1
E
e
13.90
14.00
14.10
7
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
0.50 BASIC
L
0.50
0˚
0.60
3˚
0.70
5˚
8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
O
R
N
0.08
---
0.20
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
56
3160\38.10A
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
147
D a t a s h e e t
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
148
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
LAC064—64-Pin 18 x 12 mm package
D1
D
A
0.20
2X
C
eD
H
G
F
E
D
C
B
A
8
7
6
5
4
3
2
1
7
SE
eE
E
E1
A1 CORNER ID.
(INK OR LASER)
A1
CORNER
1.00±0.5
B
6
SD
0.20
2X
C
NXφb
φ 0.25 M C A
7
TOP VIEW
B
A1
φ 0.10 M
C
CORNER
BOTTOM VIEW
0.25
C
A
A2
A1
SEATING PLANE
C
0.15
C
SIDE VIEW
NOTES:
PACKAGE
JEDEC
LAC 064
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
18.00 mm x 12.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
NOM
---
MAX
NOTE
PROFILE HEIGHT
STANDOFF
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.40
0.60
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
---
BODY THICKNESS
BODY SIZE
D
18.00 BSC.
12.00 BSC.
7.00 BSC.
7.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MD
ME
N
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
64
φb
0.50
0.60
0.70
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eD
eE
1.00 BSC.
1.00 BSC.
0.50 BSC.
NONE
BALL PITCH - D DIRECTION
BALL PITCH - E DIRECTION
SOLDER BALL PLACEMENT
8. NOT USED.
SD / SE
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
DEPOPULATED SOLDER BALLS
3243 \ 16-038.12d
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
149
D a t a s h e e t
FBA048—48-Pin 6.15 x 8.15 mm package
Dwg rev AF; 10/99
150
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
FBC048—48-Pin 8 x 9 mm package
Dwg rev AF; 10/99
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
151
D a t a s h e e t
FBE063—63-Pin 12 x 11 mm package
Dwg rev AF; 10/99
152
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
FPT-48P-M19
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60 0.15
(.024 .006)
24
25
*
20.00 0.20
(.787 .008)
12.00 0.20
(.472 .008)
*
18.40 0.20
(.724 .008)
1.10 –+00..0150
.043 –+..000024
(Mounting
height)
0.10 0.05
(.004 .002)
(Stand off height)
0.50(.020)
"A"
0.10(.004)
0.17 –+00..0083
.007 –+..000031
0.22 0.05
(.009 .002)
M
0.10(.004)
FPT-56P-M01
0.10±0.05
(.004±.002)
(Stand off)
LEAD No.
1
56
INDEX
0.22±0.05
(.009±.002)
M
0.10(.004)
1 14.00±0.10
*
(.551±.004)
0.50(.020)
28
29
Details of "A" part
1.10 –+00..0150
20.00±0.20(.787±.008)
2 18.40±0.10(.724±.004)
.043 +–..000024
(Mounting height)
0˚~8˚
*
0.17±0.03
.007±.001
0.60±0.15
(.024±.006)
0.25(.010)
"A"
0.08(.003)
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
153
D a t a s h e e t
FBG048—48-pin 8 x 6 mm package
NOTES:
PACKAGE
JEDEC
FBG 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.00 mm x 6.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
0.95
0.28
---
NOM
1.08
MAX
1.20
0.48
---
NOTE
OVERALL THICKNESS
BALL HEIGHT
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
A2
D
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.38
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
---
BODY THICKNESS
7.80
5.80
8.00
8.20
6.20
BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
6.00
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MD
ME
N
5.60 BSC.
4.00 BSC.
8
BALL FOOTPRINT
BALL FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
6
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
48
φb
0.40
0.45
0.50
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
e
0.80 BSC.
0.40 BSC.
NONE
BALL PITCH
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3422\ 16-038.9m
154
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Revision Summary
Revision A (January 29, 2004)
Initial Release.
Revision A+1 (February 23, 2004)
Connection Diagrams
Removed 80-ball Fine-pitch BGA pinout.
Ordering Information
Added additional packing type.
Removed frame description from package material set.
Updated valid combinations to reflect the addition of new package type.
Added marking descriptions to all valid combination tables.
Word Program Command Sequence and Unlock Bypass Command Sequence
Added these sections.
Figure 3, on page 107, Figure 4, on page 108
Updated figure.
Table 35, “Command Definitions (x16 Mode, BYTE# = V ),”
IH
Updated table.
Added note 19.
Table 36, “Command Definitions (x8 Mode, BYTE# = V ),”
IL
Updated table.
Added note 17.
Figure 7, on page 116
Updated figure.
Erase and Program Operations and Alternate CE# Controlled Erase and Program Operations
Updated T
description
WHWHI
Added Note 4.
Figure 16, Figure 18, Figure 20, Figure 24
Updated figure.
Physical Dimensions
Removed BGA-63P-M02 and BGA-80P-M01
Added the TS040 package
Revision A+2 (February 25, 2004)
Connection Diagrams
Removed the 40-pin reverse TSOP diagram.
Updated the 48-pin standard TSOP diagram.
Removed the 48-pin reverse TSOP diagram.
Removed the 56-pin reverse TSOP diagram.
Ordering Information
Removed all references to package type R.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
155
D a t a s h e e t
Table 18 Autoselect Codes, (High Voltage Method)
Updated the R3, R4 column replacing -04 and -03 designators with -R4 and -R3 respectively.
Word Program Command Sequence
Included statements documenting word programming support for backward compatibility with existing Flash
drivers.
Physical Dimensions
Removed the BGA-80P-M02 diagram.
Revision A+3 (February 26, 2004)
Distinctive Characteristics
Corrected typo in the Flexible Sector Architecture section.
Revision A+4 (March 24, 2004)
CMOS Compatible
Removed V from Max for V
.
CC
OL
Erase and Program Operations-S29GL256M only
Corrected unit typos.
Erase and Program Operations-S29GL128M only
Corrected the minimum Data Setup Time.
Alternate CE# Controlled Erase and Program Operations-S29GL128M
Corrected the minimum CE# Pulse width.
TSOP Pin and BGA Package Capacitance: Pkg types TB, TC, BB, BC
Added C
IN3.
Connection Diagrams
40-pin standard TSOP: Corrected pin 30 to be V
.
IO
48-pin standard TSOP: Added superscripts to designators for pin 9, 13, 14, 15 and 47. Changed pin 13 to A21.
Added two notes below illustration.
56-pin standard TSOP: Added superscripts to designators for pin 1, 2 and 12. Changed pin 56 to NC. Added three
notes below illustration.
64-ball Fortified BGA: Corrected ball D8 to be V . Added superscripts to designators for ball D8, F7, and F1.
IO
Added two notes below illustration.
63-ball Fine-pitch BGA: Added superscript to designator for Ball H7. Added one note below illustration. Added con-
nection diagrams for S29GL064M (model R0) and S29GL032M (model R0).
Pin Description
Added V description.
IO
Logic Symbols
Added V on all models except R3 and R4.
IO
Figure 3 Write Buffer Programming Operation
Corrected the DQ locations and added callouts to notes one through three.
DC Characteristics
Corrected test conditions for I
.
CC6
156
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Revision A+5 (April 30, 2004)
Ordering Information - S29GL032M
Added R5 and R6 model numbers to the breakout table.
Updated the Valid Combinations for BGA packages table to reflect model numbers R5 and R6.
Ordering Information - S29GL064M
Revised R8 and R9 model numbers on the breakout table.
Updated the Valid Combinations for TSOP packages table.
Ordering Information - S29GL0128M
Added R8 and R9 model numbers to the breakout table.
Revised the Package Material Set options on the breakout table.
Updated the Valid Combinations for TSOP packages table.
Ordering Information - S29GL256M
Revised the Package Material Set options on the breakout table.
Connection Diagrams (56-Pin TSOP)
Added a callout to Note 3 for pin 15.
Device Geometry Definition table
Revised the data and description information for addresses: 28h/50h and
29h/52h.
Primary Vendor Specific Extended Query table
Revised the data and description information for addresses: 45h/8Ah (x16/x8)
Revised the data information for addresses: 4Ch/98h (x16/x8)
Erase and Programming Performance table
Revised notes 1 and 2 below the table.
Revision B0 (May 24, 2004)
Global
Converted to full datasheet status.
Figure 18, on page 80
Corrected typos in description.
Added values for R5, R6, R7 description for cycle 1-3.
Added R8 and R9 to Model Number.
Revision B1 (August 2, 2004)
“Ordering Information-S29GL032M” on page 21
Added the following temperature range: “C = Commercial (0°C to +70°C)'.
Commercial temperature range options added for 90ns speeds.
Global Change
S29GL032M, S29GL064M, S29GL128M, S29GL236M ordering options pages:
Updated note 3 with the following “...TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2,
or 3.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
157
D a t a s h e e t
Revision B2 (September 8, 2004)
Connection Diagram - 64-ball Fortified BGA
Modified note 4.
Logic Symbol-S29GL032M (Models R3, R4)
Added models R5 and R6 to the logic symbol.
Logic Symbol-S29GL064M (Models R1, R2)
Added models R8 & R9 to the logic symbol.
S29GL032M Valid Combinations
Corrected ordering part numbers for LAA064 packages.
Physical Dimensions
Renamed the BGA-48P-M20 package as the FBG048 package.
Ordering Information
Added footnotes to indicate TSOP Pb-free leadframe plating.
Revision B3 (October 9, 2004)
General
Updated all references to Figures, Tables, and Headings to reflect page number (active link)
Updated tables 20, 21, and 22
Updated tables 24, 25, and 26
S29GL064M Valid combination
Corrected ordering part numbers for TS056 packages
S29GL032M Sector Protection/Uprotection Address Tables
Corrected table titles
S29GL064M Sector Protection/Uprotection Address Tables
Corrected table titles
Primary Vendor-Specific Extended Query
Corrected CFI data at address 48h/90h to be 0001h
DC Characteristics
Updated note 2
Figure 15, “Reset Timing”
Added t
RH
158
S29GLxxxM MirrorBitTM Flash Family
S29GLxxxM_00_B3 Octorber 18, 2004
D a t a s h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-
vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-
sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004 Spansion LLC. All rights reserved.
Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in
this publication are for identification purposes only and may be trademarks of their respective companies.
Octorber 18, 2004 S29GLxxxM_00_B3
S29GLxxxM MirrorBitTM Flash Family
159
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