S29GL032M11BAIR42 [SPANSION]
Flash, 2MX16, 110ns, PBGA48, 8 X 9 MM, FBGA-48;
| 型号： | S29GL032M11BAIR42 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 2MX16, 110ns, PBGA48, 8 X 9 MM, FBGA-48 |
| 文件： | 总116页 (文件大小：4729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29GL-M MirrorBitTM Flash Family
S29GL256M, S29GL128M, S29GL064M, S29GL032M
256 Megabit, 128 Megabit, 64 Megabit, and 32 Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
0.23 µm MirrorBit Process Technology
Data Sheet
This product family has been retired and is not recommended for designs. For
new and current designs, S29GL032A, S29GL064A, S29GL128P, and
S29GL256P supersede S29GL032M, S29GL064M, S29GL128M, and
S29GL256M respectively. These are the factory-recommended migration
paths. Please refer to the S29GL-A and S29GL-P Datasheets for specifications
and ordering information. Availability of this document is retained for reference
and historical purposes only.
Notice to Readers: This document states the current technical specifications
regarding the Spansion product(s) described herein. Spansion Inc. deems the
products to have been in sufficient production volume such that subsequent
versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered
may occur.
Publication Number S29GL-M_00 Revision B Amendment 8 Issue Date February 7, 2007
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise
readers of product information or intended specifications throughout the product life cycle, in-
cluding development, qualification, initial production, and full production. In all cases, however,
readers are encouraged to verify that they have the latest information before finalizing their de-
sign. The following descriptions of Spansion data sheet designations are presented here to high-
light their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more
specific products, but has not committed any design to production. Information presented in a
document with this designation is likely to change, and in some cases, development on the prod-
uct may discontinue. Spansion Inc. therefore places the following conditions upon Advance Infor-
mation content:
“This document contains information on one or more products under development at Spansion Inc. The
information is intended to help you evaluate this product. Do not design in this product without con-
tacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the prod-
uct life cycle, including product qualification, initial production, and the subsequent phases in the
manufacturing process that occur before full production is achieved. Changes to the technical
specifications presented in a Preliminary document should be expected while keeping these as-
pects of production under consideration. Spansion places the following conditions upon Prelimi-
nary content:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. The Preliminary status of this document indicates that product qualification has been completed,
and that initial production has begun. Due to the phases of the manufacturing process that require
maintaining efficiency and quality, this document may be revised by subsequent versions or modifica-
tions due to changes in technical specifications.”
Combination
Some data sheets will contain a combination of products with different designations (Advance In-
formation, Preliminary, or Full Production). This type of document will distinguish these products
and their designations wherever necessary, typically on the first page, the ordering information
page, and pages with DC Characteristics table and AC Erase and Program table (in the table
notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal
changes may include those affecting the number of ordering part numbers available, such as the
addition or deletion of a speed option, temperature range, package type, or V range. Changes
IO
may also include those needed to clarify a description or to correct a typographical error or incor-
rect specification. Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s) described
herein. Spansion Inc. deems the products to have been in sufficient production volume such that sub-
sequent versions of this document are not expected to change. However, typographical or specification
corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
S29GL-M MirrorBitTM Flash Family
S29GL256M, S29GL128M, S29GL064M, S29GL032M
256 Megabit, 128 Megabit, 64 Megabit, and 32 Megabit,
3.0 Volt-only Page Mode Flash Memory featuring
0.23 µm MirrorBit Process Technology
Data Sheet
This product family has been retired and is not recommended for designs. For new and current designs, S29GL032A,
S29GL064A, S29GL128P, and S29GL256P supersede S29GL032M, S29GL064M, S29GL128M, and S29GL256M respectively.
These are the factory-recommended migration paths. Please refer to the S29GL-A and S29GL-P Datasheets for specifications
and ordering information. Availability of this document is retained for reference and historical purposes only.
Distinctive Characteristics
—
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
Architectural Advantages
Single power supply operation
3 volt read, erase, and program operations
Low power consumption (typical values at 3.0 V,
5 MHz)
—
—
—
—
—
Manufactured on 0.23 µm MirrorBit process
technology
18 mA typical active read current (64 Mb, 32 Mb)
25 mA typical active read current (256 Mb, 128 Mb)
50 mA typical erase/program current
Secured Silicon Sector region
—
128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
1 µA typical standby mode current
Package options
—
—
—
—
—
—
40-pin TSOP
48-pin TSOP
56-pin TSOP
64-ball Fortified BGA
48-ball fine-pitch BGA
63-ball fine-pitch BGA
—
May be programmed and locked at the factory or by
the customer
Flexible sector architecture
—
—
—
256 Mb: 512 32-Kword (64 Kbyte) sectors
128 Mb: 256 32-Kword (64 Kbyte) sectors
Software & Hardware Features
64 Mb (uniform sector models): 128 32-Kword
(64-Kbyte) sectors or 128 32 Kword sectors
Software features
—
—
Program Suspend & Resume: read other sectors
before programming operation is completed
Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
Data# polling & toggle bits provide status
CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
—
—
—
64 Mb (boot sector models): 127 32-Kword
(64-Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors
32 Mb (uniform sector models): 64 32-Kword
(64-Kbyte) sectors of 64 32-Kword sectors
—
—
32 Mb (boot sector models): 63 32-Kword (64 Kbyte)
sectors + 8 4-Kword (8-Kbyte) boot sectors
Compatibility with JEDEC standards
—
Provides pinout and software compatibility for single-
power supply flash, and superior inadvertent write
protection
—
Unlock Bypass Program command reduces overall
multiple-word programming time
Hardware features
100,000 erase cycles typical per sector
20-year data retention typical
—
—
—
Sector Group Protection: hardware-level method of
preventing write operations within a sector group
Temporary Sector Unprotect: VID-level method of
charging code in locked sectors
WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings on uniform
sector models
Performance Characteristics
High performance
—
90 ns access time (128 Mb, 64 Mb, 32 Mb),
100 ns access time (256 Mb)
4-word/8-byte page read buffer
25 ns page read times (128 Mb, 64 Mb, 32 Mb)
30 ns page read times (256 Mb)
16-word/32-byte write buffer
—
—
—
—
—
—
Hardware reset input (RESET#) resets device
Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
Publication Number S29GL-M_00 Revision B Amendment 8 Issue Date February 7, 2007
D a t a S h e e t
General Description
The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufac-
tured using 0.23 µm MirrorBit technology. The S29GL256M is a 256†Mbit, organized as 16,777,216
words or 33,554,432 bytes. The S29GL128M is a 128 Mbit, organized as 8,388,608 words or
16,777,216 bytes. The S29GL064M is a 64 Mbit, organized as 4,194,304 words or 8,388,608 bytes.
The S29GL032M is a 32 Mbit, organized as 2,097,152 words or 4,194,304 bytes. Depending on the
model number, the devices have an 8-bit wide data bus only, 16-bit wide data bus only, or a 16-bit
wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The devices
can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M) are
available. Note that each access time has a specific operating voltage range (V ) as specified in
CC
Product Selector Guide and the Ordering Information sections starting on page 16. Package offer-
ings include 40-pin TSOP, 48-pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA, 63-ball fine-pitch BGA
and 64-ball Fortified BGA, depending on model number. Each device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In
addition to a V input, a high-voltage accelerated program (ACC) feature provides shorter pro-
CC
gramming times through increased current on the WP#/ACC input. This feature is intended to
facilitate factory throughput during system production, but may also be used in the field if desired.
The device is entirely command set compatible with the JEDEC single-power-supply Flash stan-
dard. Commands are written to the device using standard microprocessor write timing. Write cycles
also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without
affecting the data contents of other sectors. The device is fully erased when shipped from the
factory.
Device programming and erasure are initiated through command sequences. Once a program or
erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) sta-
tus bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is
complete. To facilitate programming, an Unlock Bypass mode reduces command sequence over-
head by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low V detector that automatically inhibits write
CC
operations during power transitions. The hardware sector protection feature disables both program
and erase operations in any combination of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation
in a given sector to read or program any other sector and then complete the erase operation. The
Program Suspend/Program Resume feature enables the host system to pause a program op-
eration in a given sector to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after
which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the host system to read boot-up firmware
from the Flash memory device.
The device reduces power consumption in the standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses are stable for a specified period of time.
The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the
WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected even
during accelerated programming.
The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be per-
manently protected. Once this sector is protected, no further changes within the sector can occur.
Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to
produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases
all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using
hot electron injection.
2
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table of Contents
Unprotection Address Table ................................................. 49
Table 23. S29GL064M (Models R1, R2, R8, R9) Sector Group
Protection/Unprotection Addresses ....................................... 49
Table 24. S29GL064M (Model R3) Sector Group Protection/
Unprotection Address Table ................................................. 50
Table 26. S29GL064M (Model R5) Sector Group Protection/
Unprotection Addresses ...................................................... 51
Table 27. S29GL064M (Models R6, R7) Sector Group Protection/
Unprotection Address ......................................................... 51
Table 28. S29GL128M Sector Group Protection/Unprotection
Addresses ......................................................................... 51
Table 29. S29GL256M Sector Group Protection/Unprotection
Addresses ......................................................................... 52
Temporary Sector Group Unprotect .......................................................... 53
Figure 1. Temporary Sector Group Unprotect Operation.......... 53
Figure 2. In-System Sector Group Protect/Sector Group Unprotect
Algorithms........................................................................ 54
Secured Silicon Sector Flash Memory Region ........................................... 55
Write Protect (WP#) .......................................................................................56
Hardware Data Protection .............................................................................56
Low VCC Write Inhibit ................................................................................56
Write Pulse “Glitch” Protection ...............................................................56
Logical Inhibit ...................................................................................................56
Power-Up Write Inhibit ...............................................................................56
Common Flash Memory Interface (CFI) . . . . . . . 57
Table 30. CFI Query Identification String .............................. 57
Table 31. System Interface String ........................................ 57
Table 32. Device Geometry Definition ................................... 58
Table 33. Primary Vendor-Specific Extended Query ................ 59
Command Definitions . . . . . . . . . . . . . . . . . . . . . .60
Reading Array Data ...........................................................................................60
Reset Command .................................................................................................60
Autoselect Command Sequence .....................................................................61
Enter/Exit Secured Silicon Sector Command Sequence ..........................61
Word Program Command Sequence .......................................................61
Unlock Bypass Command Sequence ........................................................62
Write Buffer Programming ..........................................................................62
Accelerated Program .................................................................................... 63
Figure 3. Write Buffer Programming Operation ...................... 64
Figure 4. Program Operation............................................... 65
Program Suspend/Program Resume Command Sequence ....................65
Figure 5. Program Suspend/Program Resume........................ 66
Chip Erase Command Sequence ...................................................................66
Sector Erase Command Sequence ................................................................66
Figure 6. Erase Operation................................................... 67
Erase Suspend/Erase Resume Commands ..................................................68
Command Definitions .......................................................................................69
Table 34. Command Definitions( x16 Mode, BYTE# = VIH) ...... 69
Table 35. Command Definitions (x8 Mode, BYTE# = VIL) ........ 70
Write Operation Status ....................................................................................71
DQ7: Data# Polling .............................................................................................71
Figure 7. Data# Polling Algorithm........................................ 72
RY/BY#: Ready/Busy# ....................................................................................... 72
DQ6: Toggle Bit I ............................................................................................... 72
Figure 8. Toggle Bit Algorithm............................................. 74
DQ2: Toggle Bit II ..............................................................................................74
DQ5: Exceeded Timing Limits ........................................................................ 75
DQ3: Sector Erase Timer ................................................................................ 75
DQ1: Write-to-Buffer Abort ........................................................................... 75
Table 36. Write Operation Status ......................................... 76
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6
For S29GL064M (model R0) only ....................................................................7
For S29GL064M (model R0) only .................................................................. 10
For S29GL032M (model R0) only .................................................................. 12
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
S29GL064M (Models R1, R2, R8, R9) ............................................................ 14
S29GL064M (Models R3, R4) .......................................................................... 14
S29GL064M (Model R5) .....................................................................................15
S29GL064M (Model R6, R7) .............................................................................15
S29GL128M .............................................................................................................15
Ordering Information: S29GL032M . . . . . . . . . . . . 16
S29GL032M Standard Products ...................................................................... 16
Table 1. S29GL032M Ordering Options ................................. 17
Ordering Information: S29GL064M . . . . . . . . . . . 18
S29GL064M Standard Products ...................................................................... 18
Table 2. S29GL064M Ordering Options ................................. 19
Ordering Information: S29GL128M . . . . . . . . . . . .20
Table 3. S29GL128M Ordering Options ................................. 20
Ordering Information: S29GL256M . . . . . . . . . . . . 21
Table 4. S29GL256M Ordering Options ................................. 21
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .22
Table 5. Device Bus Operations ........................................... 22
Word/Byte Configuration ............................................................................... 22
Requirements for Reading Array Data ........................................................ 22
Page Mode Read ..................................................................................................23
Writing Commands/Command Sequences .................................................23
Write Buffer .....................................................................................................23
Accelerated Program Operation ...............................................................23
Autoselect Functions .....................................................................................23
Standby Mode ...................................................................................................... 24
Automatic Sleep Mode ..................................................................................... 24
RESET#: Hardware Reset Pin ........................................................................ 24
Output Disable Mode ....................................................................................... 24
Table 6. S29GL032M (Model R0) Sector Addresses ................ 25
Table 7. S29GL032M (Models R1, R2) Sector Addresses ......... 26
Table 8. S29GL032M (Model R3)
Top Boot Sector Addresses ................................................. 27
Table 9. S29GL032M (Model R4)
Bottom Boot Sector Addresses ............................................ 28
Table 11. S29GL064M (Models R1, R2, R8, R9)
Sector Addresses .............................................................. 30
Table 14. S29GL064M (Model R5, R6, R7) Sector Addresses ... 37
Table 16. S29GL256M Sector Address Table ......................... 41
Autoselect Mode .................................................................................................47
Table 17. Autoselect Codes, (High Voltage Method) ............... 47
Table 18. S29GL032M (Model R0) Sector Group Protection/
Unprotection Addresses ...................................................... 48
Table 19. S29GL032M (Models R1, R2) Sector Group Protection/
Unprotection Addresses ...................................................... 48
Table 20. S29GL032M (Model R3) Sector Group Protection/
Unprotection Address Table ................................................ 48
Table 21. S29GL032M (Model R4) Sector Group Protection/
Unprotection Address Table ................................................ 49
Table 22. S29GL064M (Model 00) Sector Group Protection/
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
3
D a t a S h e e t
Figure 23. Sector Group Protect and Unprotect Timing Diagram 92
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .77
Figure 9. Maximum Negative Overshoot Waveform................. 77
Figure 10. Maximum Positive Overshoot Waveform................. 77
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .77
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .78
CMOS Compatible ............................................................................................ 78
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 11. Test Setup ......................................................... 79
Table 37. Test Specifications ............................................... 79
Key to Switching Waveforms . . . . . . . . . . . . . . . .79
Figure 12. Input Waveforms and Measurement Levels............. 79
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .80
Read-Only Operations—S29GL256M Only ...............................................80
Read-Only Operations—S29GL128M only ................................................80
Read-Only Operations—S29GL064M Only ............................................... 81
Read-Only Operations—S29GL032M only ................................................ 82
Figure 13. Read Operation Timings....................................... 82
Figure 14. Page Read Timings.............................................. 83
Hardware Reset (RESET#) ...............................................................................83
Figure 15. Reset Timings..................................................... 84
Erase and Program Operations—S29GL256M Only ............................... 85
Erase and Program Operations—S29GL128M Only ............................... 86
Erase and Program Operations—S29GL064M Only .............................. 87
Erase and Program Operations—S29GL032M Only ..............................88
Figure 16. Program Operation Timings.................................. 89
Figure 17. Accelerated Program Timing Diagram .................... 89
Figure 18. Chip/Sector Erase Operation Timings..................... 90
Figure 19. Data# Polling Timings
Alternate CE# Controlled Erase and Program Operations—
S29GL256M .......................................................................................................... 93
Alternate CE# Controlled Erase and Program Operations—
S29GL128M ...........................................................................................................94
Alternate CE# Controlled Erase and Program Operations—
S29GL064M ..........................................................................................................95
Alternate CE# Controlled Erase and Program Operations—
S29GL032M ..........................................................................................................96
Figure 24. Alternate CE# Controlled Write (Erase/
Program) Operation Timings ............................................... 97
Erase and Programming Performance . . . . . . . . .98
TSOP Pin and BGA Package Capacitance . . . . . .98
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .99
TS040—40-Pin Standard Thin Small Outline Package (TSOP) ............99
TSR040—40-Pin Standard and Reverse Thin Small Outline Package
(TSOP) ................................................................................................................. 100
TS048—48-Pin Standard and Reverse Thin Small Outline Package
(TSOP) ...................................................................................................................101
TSR048—48-Pin Standard and Reverse Thin Small Outline Package
(TSOP) ..................................................................................................................102
TS056/TSR056—56-Pin Standard and Reverse Thin Small Outline Pack-
age (TSOP) ..........................................................................................................103
LAA064—64-Ball Fortified Ball Grid Array (FBGA) ..............................104
LAC064—64-Pin 18 x 12 mm Package .........................................................105
FBA048—48-Pin 6.15 x 8.15 mm Package ...................................................106
FBC048—48-Pin 8 x 9 mm Package ............................................................107
FBE063—63-Pin 12 x 11 mm Package ........................................................... 108
FPT-48P-M19 ...................................................................................................... 109
FPT-56P-M01 ....................................................................................................... 109
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 110
(During Embedded Algorithms)............................................ 90
Figure 20. Toggle Bit Timings (During Embedded Algorithms) .. 91
Figure 21. DQ2 vs. DQ6 ...................................................... 91
Temporary Sector Unprotect ......................................................................... 91
Figure 22. Temporary Sector Group Unprotect Timing Diagram 92
4
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Product Selector Guide
Part Number
S29GL256M
S29GL128M
S29GL064M
S29GL032M
Speed Option
10
11
110
110
30
90
10
100
100
30
90
90
90
25
25
10
100
100
30
11
110
110
30
90
90
90
25
25
10
100
100
30
11
110
110
30
Max. Access Time (ns)
100
100
30
90
90
25
25
Max. CE# Access Time (ns)
Max. Page Access Time (ns)
Max. OE# Access Time (ns)
30
30
30
30
30
30
30
Block Diagram
DQ15–DQ0 (A-1)
RY/BY#
VCC
VSS
Sector Switches
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
AMax**–A0
** A
: GL256M = A23, GL128M = A22, GL064M = A21 (GL064M-00 = A22), GL032M = A20 (GL032M-00 = A21)
Max
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
5
D a t a S h e e t
Connection Diagrams
A17
VSS
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
40-Pin Standard TSOP
5
6
7
A8
8
WE#
RESET#
ACC
RY/BY#
A18
A7
9
10
11
12
13
14
15
16
17
18
19
20
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
A6
A5
A4
A3
A2
A1
CE#
A0
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48-Pin Standard TSOP
A8
2
A19
9
A20
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
1,2
A21
2
2
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Notes:
1. Pin 13 is NC on S29GL032M.
2. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47 is V on S29GL064M (models R6, R7).
IO
6
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
For S29GL064M (model R0) only
NC
NC
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VIO
NC
A22
A16
A15
A14
A13
A12
A11
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin Standard TSOP
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
ACC
RY/BY#
A18
A7
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
NC
NC
A6
A5
A4
A3
A2
A1
NC
NC
1
2
A23
A22
1
2
3
4
5
6
7
8
9
56 NC
55 NC
54 A16
53 BYTE#
52 VSS
A15
A14
A13
A12
A11
A10
A9
56-Pin Standard TSOP
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A213 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
A1 26
32 CE#
31 A0
NC 27
30 NC
NC 28
29 VIO
Notes:
1. Pin 1 is NC on S29GL128M, 29GL064M, and S29GL032M.
2. Pin 2 is NC on S29GL064M, and S29GL032M.
3. Pin 15 is NC on S29GL032M.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
7
D a t a S h e e t
64-ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
NC
H8
4
A222
A233
VIO
VSS
NC
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
BYTE#5 DQ15/A-1
VSS
A13
A12
A14
A15
A16
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE# RESET# A211
A19
DQ5
DQ12
DQ4
VCC
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
B1
C1
D1
E1
F1
G1
NC
H1
4
NC
NC
NC
NC
NC
NC
VIO
Notes:
1. Ball C5 is NC on S29GL032M.
2. Ball B8 is NC on S29GL064M and S29GL032M.
3. Ball C8 is NC on S29GL128M, S29GL064M and S29GL032M.
4. Ball D8 and Ball F1 are NC on S29GL064M (models R3, R4) and S29GL032M (models R3, R4, R5, R6).
5. Ball F7 is NC on S29GL064M (model R5).
8
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
63-Ball Fine-Pitch BGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC*
NC*
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
BYTE#1 DQ15/A
-1
VSS
NC*
NC*
NC*
NC*
A13
A12
A14
A15
A16
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
VCC
WE# RESET#
A21
A19
DQ5
DQ12
DQ4
C4 D4
E4
F4
G4
H4
J4
K4
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A17
DQ0
DQ8
DQ9
DQ1
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
L2
M2
A2
VSS
CE#
OE#
NC*
NC*
NC*
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Note: Ball H7 is V on S29GL064M (model R5).
IO
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The
package and/or data integrity may be compromised if the package body is exposed to tempera-
tures above 150°C for prolonged periods of time.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
9
D a t a S h e e t
For S29GL064M (model R0) only
63-Ball Fine-Pitch BGA
Top View, Balls Facing Down
L8
M8
A8
B8
NC*
NC*
NC*
NC*
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
A7
B7
A14
A13
A15
A16
A17
NC
A20
V
SS
NC*
NC*
NC*
NC*
C6
A9
D6
A8
E6
F6
G6
H6
J6
K6
A11
A12
A19
A10
DQ6
DQ7
C5
D5
E5
F5
G5
H5
J5
K5
WE# RESET# A22
NC
DQ5
NC
V
DQ4
CC
C4
D4
E4
F4
G4
H4
J4
K4
RY/BY# ACC
NC
NC
DQ2
DQ3
V
A21
IO
C3
A7
D3
E3
A6
F3
A5
G3
H3
J3
K3
A18
DQ0
NC
NC
DQ1
A2
L2
M2
C2
A3
D2
A4
E2
A2
F2
A1
G2
A0
H2
J2
K2
NC*
CE#
OE#
V
NC*
NC*
SS
A1
B1
L1
M1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
NC*
NC*
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The
package and/or data integrity may be compromised if the package body is exposed to tempera-
tures above 150°C for prolonged periods of time.
10
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
48-ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
VCC
WE# RESET#
NC
A19
DQ5
DQ12
DQ4
A3 B3
C3
D3
E3
F3
G3
H3
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
VSS
CE#
OE#
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
11
D a t a S h e e t
For S29GL032M (model R0) only
48-Ball Fine-Pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A14
A13
A15
A16
A17
NC
A20
V
SS
A5
A9
B5
A8
C5
D5
E5
F5
G5
D6
H5
D7
A11
A12
A19
A10
A4
B4
C4
D4
E4
D5
F4
G4
H4
D4
WE# RESET#
NC
NC
NC
V
CC
A3
B3
C3
D3
E3
D2
F3
D3
G3
H3
RY/BY# ACC
NC
NC
V
A21
IO
A2
A7
B2
C2
A6
D2
A5
E2
D0
F2
G2
NC
H2
D1
A18
NC
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
V
SS
Special Package Handling Instructions
Special handling is required for Flash Memory products in moulded packages (TSOP and BGA).
The package and/or data integrity may be compromised if the package body is exposed to tem-
peratures above 150°C for prolonged periods of time.
12
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Pin Description
A23–A0
=
24 Address inputs
A22–A0
A21–A0
A20–A0
DQ7–DQ0
DQ14–DQ0
DQ15/A-1
=
=
=
=
=
=
23 Address inputs
22 Address inputs
21 Address inputs
8 Data inputs/outputs
15 Data inputs/outputs
DQ15 (Data input/output, word mode), A-1 (LSB
Address input, byte mode)
Chip Enable input
Output Enable input
Write Enable input
CE#
OE#
WE#
WP#/ACC
=
=
=
=
Hardware Write Protect input/Programming
Acceleration input
ACC
WP#
RESET#
RY/BY#
BYTE#
VCC
=
=
=
=
=
=
Acceleration input
Hardware Write Protect input
Hardware Reset Pin input
Ready/Busy output
Selects 8-bit or 16-bit mode
3.0 volt-only single power supply
(see Product Selector Guide for speed options and
voltage supply tolerances)
Device Ground
VSS
NC
VIO
=
=
=
Pin Not Connected Internally
Output Buffer Power
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
13
D a t a S h e e t
Logic Symbols
S29GL032M (Model R0)
S29GL032M (Models R1, R2)
22
21
A21–A0
A20–A0
8
16 or 8
DQ15–DQ0
DQ7–DQ0
CE#
OE#
WE#
CE#
OE#
WE#
(A-1)
ACC
WP#/ACC
RESET#
RESET#
BYTE#
V
RY/BY#
RY/BY#
IO
V
IO
S29GL032M (Models R3, R4)
S29GL064M (Model R0)
21
23
A20–A0
A22–A0
16 or 8
8
DQ15–DQ0
DQ7–DQ0
CE#
OE#
WE#
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
ACC
RESET#
V
IO
RY/BY#
RY/BY#
BYTE#
S29GL064M (Models R1, R2, R8, R9)
S29GL064M (Models R3, R4)
22
22
A21–A0
A21–A0
16 or 8
16 or 8
DQ15–DQ0
(A-1)
DQ15–DQ0
CE#
OE#
WE#
CE#
OE#
WE#
(A-1)
WP#/ACC
RESET#
BYTE#
WP#/ACC
RESET#
BYTE#
RY/BY#
RY/BY#
V
IO
14
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Logic Symbols
S29GL064M (Model R5)
S29GL064M (Model R6, R7)
22
22
A21–A0
A21–A0
16
16
DQ15–DQ0
DQ15–DQ0
CE#
CE#
OE#
WE#
OE#
WE#
WP#
ACC
ACC
RESET#
RESET#
V
RY/BY#
IO
V
IO
S29GL128M
S29GL256M
23
24
A22–A0
16 or 8
A23–A0
16 or 8
DQ15–DQ0
(A-1)
DQ15–DQ0
(A-1)
CE#
CE#
OE#
OE#
WE#
WE#
WP#/ACC
RESET#
WP#/ACC
RESET#
BYTE#
BYTE#
RY/BY#
RY/BY#
V
IO
V
IO
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
15
D a t a S h e e t
Ordering Information: S29GL032M
This product has been retired and is not recommended for designs. For new and current designs, S29GL032A supersedes S29GL032M, and is the
factory-recommended migration path. Please refer to the S29GL-A Datasheet for specifications and ordering information.
S29GL032M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL032M
10
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R0
R1
=
=
x8, VCC=3.0-3.6V, Uniform sector device
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#/ACC=VIL
R2
R3
R4
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address sectors
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
=
=
Industrial (–40
°
C to +85
°
C)
C)
C
Commercial (0
°
C to +70°
PACKAGE MATERIAL SET
A
F
B
C
=
=
=
=
Standard
Pb-Free
Standard
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL032M
32 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™
Process Technology, 3.0 Volt-only Read, Program, and Erase
16
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 1. S29GL032M Ordering Options
S29GL032M Valid Combinations
Package Description
(Notes)
Device
Number
Speed
Option
Package, Material,
Model
Packing
Type
& Temperature Range
TAC,TFC
BAC,BFC
TAC,TFC
FAC,FFC
TAC,TFC
BAC,BFC
FAC,FFC
TAI,TFI
Number
TS040 (2, 3, 5)
TSOP
R0
FBC048 (4)
Fine-Pitch BGA
TSOP
TS056 (2, 3, 5)
LAA064 (4)
R1,R2
90
Fortified BGA
TSOP
TS048 (2, 3, 5)
FBC048 (4)
R3,R4
Fine-Pitch BGA
Fortified BGA
TSOP
LAA064 (4)
0,2,3
(Note 1)
S29GL032M
TS040 (2, 3, 5)
FBC048 (4)
R0
BAI,BFI
Fine-Pitch BGA
TSOP
TAI,TFI
TS056 (2, 3, 5)
LAA064 (4)
R1,R2
FAI,FFI
Fortified BGA
TSOP
90, 10, 11
TAI,TFI
TS048 (2, 3, 5)
FBC048 (4)
BAI,BFI
Fine-Pitch BGA
Fortified BGA
TSOP
R3,R4
FAI,FFI
LAA064 (4)
TBI,TCI
FPT-48P-M19 (3, 6)
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
17
D a t a S h e e t
Ordering Information: S29GL064M
This product has been retired and is not recommended for designs. For new and current designs, S29GL064A supersedes S29GL064M, and is the
factory-recommended migration path. Please refer to the S29GL-A Datasheet for specifications and ordering information.
S29GL064M Standard Products
Standard products are available in several packages and operating ranges. The order number (Valid Combination)
is formed by a combination of the following:
S29GL064M
90
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
MODEL NUMBER
R0
R1
=
=
x8, VCC=3.0-3.6V, Uniform sector device
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
R2
R3
R4
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Top boot sector device, top two address
sectors protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC=VIL
R5
R6
=
=
x16, VCC=3.0-3.6V, Uniform sector device
x16, VCC=3.0-3.6V, Uniform sector device, highest address sector
protected when WP#=VIL
R7
R8
R9
=
=
=
x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL, FPT-56P-M01 package only
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL, FPT-56P-M01 package only
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE MATERIAL SET
A
F
B
C
D
=
=
=
=
=
Standard
Pb-Free
Standard
Pb-Free
Pb-Free
PACKAGE TYPE
T
B
F
=
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fine-pitch Ball-Grid Array Package
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL064M
64 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBitTM
Process Technology, 3.0 Volt-only Read, Program, and Erase
18
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 2. S29GL064M Ordering Options
S29GL064M Valid Combinations
Package Description
(Notes)
Device
Number
Speed
Option
Package, Material, &
Temperature Range
Model
Number
Packing
Type
R0,R3,R4,R6,R7
R1,R2
TS048 (2, 3, 5)
TAI, TFI
TS056 (2, 3, 5)
FPT-48P-M19 (3, 6)
FPT-56P-M01 (3, 6)
FBE063 (4, 6)
TSOP
TBI, TCI
TAI, TDI
BAI, BFI
FAI, FFI
R2,R7
0,2,3
(Note 1)
S29GL064M
90, 10, 11
R9
R0,R3,R4,R5
R1,R2,R3,R4,R5
Fine-Pitch BGA
Fortified BGA
LAA064 (4)
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
19
D a t a S h e e t
Ordering Information: S29GL128M
This product has been retired and is not recommended for designs. For new and current designs, S29GL128P supersedes S29GL128M, and is the
factory-recommended migration path. Please refer to the S29GL-P Datasheet for specifications and ordering information.
Standard products are available in several packages and operating ranges. The order number
(Valid Combination) is formed by a combination of the following:
S29GL128M
90
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
Model Number
R1
R2
R8
R9
=
=
=
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL, FPT-56P-M01 package only
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL, FPT-56P-M01 package only
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE MATERIAL SET
A
F
D
=
=
=
Standard
Pb-Free
Pb-Free
PACKAGE TYPE
T
F
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL128M
128 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™
Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 3. S29GL128M Ordering Options
S29GL128M Valid Combinations
Package Descriptions
(Notes)
Base Ordering
Part Number
Speed
Option
Package Type, Material,
& Temperature Range
Model
Number
Packing
Type
TAI, TFI
TAI, TDI
FAI, FFI
R1, R2
R9
TS056 (2, 3, 5)
TSOP
90, 10, 11
(Note 7)
S29GL128M
0, 2, 3 (Note 1)
FPT-56P-M01 (3, 6)
LAA064 (4)
R1, R2
Fortified-BGA
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. This package is recommended for new designs using TSOPs.
3. TSOP package marking omits packing type designator from the ordering part number.
4. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
5. 100% Matte Sn is used for Pb-free TSOP plating.
6. SnBi is used for Pb-free TSOP plating.
7. Contact your Spansion representative for availability of the 90ns speed option for LAA064.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
20
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Ordering Information: S29GL256M
This product has been retired and is not recommended for designs. For new and current designs, S29GL256P supersedes S29GL256M, and is the
factory-recommended migration path. Please refer to the S29GL-P Datasheet for specifications and ordering information.
Standard products are available in several packages and operating ranges. The order number
(Valid Combination) is formed by a combination of the following:
S29GL256M
11
T
A
I
R1
0
PACKING TYPE
0
2
3
=
=
=
Tray
7” Tape and Reel
13” Tape and Reel
Model Number
R1
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, highest address
sector protected when WP#/ACC=VIL
R2
=
x8/x16, VCC=3.0-3.6V, Uniform sector device, lowest address sector
protected when WP#/ACC=VIL
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE MATERIAL SET
A
F
=
=
Standard
Pb-Free
PACKAGE TYPE
T
F
=
=
Thin Small Outline Package (TSOP) Standard Pinout
Fortified Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29GL256M
256 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™
Process Technology, 3.0 Volt-only Read, Program, and Erase
Table 4. S29GL256M Ordering Options
S29GL256M Valid Combinations
Package Description
(Notes)
Device
Number
Speed
Option
Package, Material,
& Temperature Range
Model
Number
Packing
Type
TAI,TFI
FAI,FFI
TS056 (2, 3, 4)
LAC064 (3)
TSOP
10, 11
(Note 5)
0,2,3
(Note 1)
S29GL256M
R1,R2
Fortified BGA
Notes:
1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can be packed in Types 0, 2, or 3.
2. TSOP package marking omits the packing type designator from the ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from the ordering part number.
4. 100% Matte Sn is used for Pb-free TSOP plating.
5. Contact your Spansion representative for availability of the 100 ns speed option.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
21
D a t a S h e e t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated
through the internal command register. The command register itself does not occupy any addres-
sable memory location. The register is a latch used to store the commands, along with the
address and data information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the de-
vice. Table 5 lists the device bus operations, the inputs and control levels they require, and the
resulting output. The following subsections describe each of these operations in further detail.
Table 5. Device Bus Operations
DQ8–DQ15
OE
#
AC
C
Addresses
(Note 1)
DQ0–
DQ7
Operation
CE#
WE# RESET#
WP#
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
L
L
H
L
H
H
H
X
X
X
A
A
A
D
D
OUT
IN
IN
IN
OUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
H
H
(Note 3)
(Note 4) (Note 4)
(Note 4) (Note 4)
L
(Note 3) V
HH
V
±
V
±
CC
CC
Standby
X
X
X
H
X
High-Z
High-Z
High-Z
0.3 V
0.3 V
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
Sector Group Protect
(Note 2)
L
H
L
V
H
X
(Note 4)
(Note 4)
X
X
X
ID
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
Sector Group Unprotect
(Note 2)
L
H
X
L
V
V
H
H
X
X
X
ID
ID
Temporary Sector
Group Unprotect
X
X
A
(Note 4) (Note 4)
High-Z
IN
Legend: L = Logic Low = V , H = Logic High = V , V = 11.5–12.5 V,
IL
IH
ID
V
= 11.5 V – 12.5 V, X = Don’t Care, SA = Sector Address, A = Address In,
HH
IN
D
= Data In, D
= Data Out
IN
OUT
Notes:
1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15
in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming
equipment. See the “Sector Group Protection and Unprotection” section.
3. If WP# = V , the first or last sector remains protected (for uniform sector devices), and the two
IL
outer boot sectors are protected (for boot sector devices). If WP# = V , the first or last sector, or
IH
the two outer boot sectors are protected or unprotected as determined by the method described in
“Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the
factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
4.
D
or D
as required by command sequence, data polling, or sector protect algorithm (see
IN
OUT
Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active
and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–
DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and
the DQ15 pin is used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is
the power control and selects the device. OE# is the output control and gates array data to the
output pins. WE# should remain at VIH.
22
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register con-
tents are altered.
See Reading Array Data for more information. See AC Characteristics for timing specifications and
the timing diagram. See DC Characteristics for the active current specification on reading array
data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher
address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the
specific word within a page. This is an asynchronous operation; the microprocessor supplies the
specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as
long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC
.
When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE.
Fast page mode accesses are obtained by keeping the “read-page addresses” constant and
changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four. Word Program Command Sequence contains details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 6 and
Table 16 indicates the address space that each sector occupies.
See DC Characteristics for the active current specification for the write mode. AC Characteristics
contains timing specification tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard pro-
gramming algorithms. See Write Buffer Programming for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two
functions provided by the WP#/ACC or ACC pin, depending on model number. This function is pri-
marily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock
Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage
on the pin to reduce the time required for program operations. The system would use a two-cycle
program command sequence as required by the Unlock Bypass mode. Removing VHH from the
WP#/ACC or ACC pin, depending on model number, returns the device to normal operation. Note
that the WP#/ACC or ACC pin must not be at VHH for operations other than accelerated program-
ming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at
VIH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect
Mode and Autoselect Command Sequence for more information.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
23
D a t a S h e e t
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO
± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held
at VIH, but not within VIO ± 0.3 V, the device is in the standby mode, but the standby current is
greater. The device requires standard access time (tCE) for read access when the device is in ei-
ther of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
See DC Characteristics for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. See DC Characteristics for the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When
the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all output pins, and ignores all read/write commands for the du-
ration of the RESET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the
device draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the
standby current is greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
See AC Characteristics for RESET# parameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in
the high impedance state.
24
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 6. S29GL032M (Model R0) Sector Addresses
8-bit
Address
Range
8-bit
Address
Range
A21–A16
A21–A16
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
25
D a t a S h e e t
Table 7. S29GL032M (Models R1, R2) Sector Addresses
Sector
Size
(KB/
Sector
Size
(KB/
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A20-A15
A20-A15
Kwords)
Kwords)
SA0 0 0 0 0 0 0
SA1 0 0 0 0 0 1
SA2 0 0 0 0 1 0
SA3 0 0 0 0 1 1
SA4 0 0 0 1 0 0
SA5 0 0 0 1 0 1
SA6 0 0 0 1 1 0
SA7 0 0 0 1 1 1
SA8 0 0 1 0 0 0
SA9 0 0 1 0 0 1
SA10 0 0 1 0 1 0
SA11 0 0 1 0 1 1
SA12 0 0 1 1 0 0
SA13 0 0 1 1 0 1
SA14 0 0 1 1 1 0
SA15 0 0 1 1 1 1
SA16 0 1 0 0 0 0
SA17 0 1 0 0 0 1
SA18 0 1 0 0 1 0
SA19 0 1 0 0 1 1
SA20 0 1 0 1 0 0
SA21 0 1 0 1 0 1
SA22 0 1 0 1 1 0
SA23 0 1 0 1 1 1
SA24 0 1 1 0 0 0
SA25 0 1 1 0 0 1
SA26 0 1 1 0 1 0
SA27 0 1 1 0 1 1
SA28 0 1 1 1 0 0
SA29 0 1 1 1 0 1
SA30 0 1 1 1 1 0
SA31 0 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
SA32 1 0 0 0 0 0
SA33 1 0 0 0 0 1
SA34 1 0 0 0 1 0
SA35 1 0 0 0 1 1
SA36 1 0 0 1 0 0
SA37 1 0 0 1 0 1
SA38 1 0 0 1 1 0
SA39 1 0 0 1 1 1
SA40 1 0 1 0 0 0
SA41 1 0 1 0 0 1
SA42 1 0 1 0 1 0
SA43 1 0 1 0 1 1
SA44 1 0 1 1 0 0
SA45 1 0 1 1 0 1
SA46 1 0 1 1 1 0
SA47 1 0 1 1 1 1
SA48 1 1 0 0 0 0
SA49 1 1 0 0 0 1
SA50 1 1 0 0 1 0
SA51 1 1 0 0 1 1
SA52 1 1 0 1 0 0
SA53 1 1 0 1 0 1
SA54 1 1 0 1 1 0
SA55 1 1 0 1 1 1
SA56 1 1 1 0 0 0
SA57 1 1 1 0 0 1
SA58 1 1 1 0 1 0
SA59 1 1 1 0 1 1
SA60 1 1 1 1 0 0
SA61 1 1 1 1 0 1
SA62 1 1 1 1 1 0
SA63 1 1 1 1 1 1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
26
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 8. S29GL032M (Model R3)
Top Boot Sector Addresses
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A20–A12
A20–A12
SA0 000000xxx 64/32
SA1 000001xxx 64/32
SA2 000010xxx 64/32
SA3 000011xxx 64/32
SA4 000100xxx 64/32
SA5 000101xxx 64/32
SA6 000110xxx 64/32
SA7 000111xxx 64/32
SA8 001000xxx 64/32
SA9 001001xxx 64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA10 001010xxx 64/32 0A0000h–0AFFFFh
SA11 001011xxx 64/32 0B0000h–0BFFFFh
SA12 001100xxx 64/32 0C0000h–0CFFFFh
SA47 101111xxx 64/32
2F0000h–2FFFFFh 178000h–17FFFFh
SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA13 001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA14 001101xxx 64/32
SA15 001111xxx 64/32
SA16 010000xxx 64/32
SA17 010001xxx 64/32
SA18 010010xxx 64/32
SA19 010011xxx 64/32
SA20 010100xxx 64/32
SA21 010101xxx 64/32
SA22 010110xxx 64/32
SA23 010111xxx 64/32
SA24 011000xxx 64/32
SA25 011001xxx 64/32
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
SA26 011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA27 011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA63 111111000
SA64 111111001
SA65 111111010
SA66 111111011
SA67 111111100
SA68 111111101
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
3F0000h–3F1FFFh 1F8000h–1F8FFFh
3F2000h–3F3FFFh 1F9000h–1F9FFFh
3F4000h–3F5FFFh 1FA000h–1FAFFFh
3F6000h–3F7FFFh 1FB000h–1FBFFFh
3F8000h–3F9FFFh 1FC000h–1FCFFFh
3FA000h–3FBFFFh 1FD000h–1FDFFFh
3FC000h–3FDFFFh 1FE000h–1FEFFFh
3FE000h–3FFFFFh 1FF000h–1FFFFFh
SA28 011000xxx 64/32 1C0000h–1CFFFFh
E0000h–E7FFFh
SA29 011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA30 011110xxx 64/32
SA31 011111xxx 64/32
SA32 100000xxx 64/32
SA33 100001xxx 64/32
SA34 100010xxx 64/32
SA35 101011xxx 64/32
1E0000h–1EFFFFh
1F0000h–1FFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
200000h–20FFFFh F9000h–107FFFh
210000h–21FFFFh 108000h–10FFFFh SA69 111111110
220000h–22FFFFh 110000h–117FFFh SA70 111111111
230000h–23FFFFh 118000h–11FFFFh
* Sector sizes are given in Kbytes/Kwords.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
27
D a t a S h e e t
Table 9. S29GL032M (Model R4)
Bottom Boot Sector Addresses
Sector
Size*
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
A20–A12
A20–A12
SA0 000000000
SA1 000000001
SA2 000000010
SA3 000000011
SA4 000000100
SA5 000000101
SA6 000000110
SA7 000000111
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
F8000h–FFFFFh
F9000h–107FFFh
SA19 001100xxx 64/32 0C0000h–0CFFFFh
SA20 001101xxx 64/32 0D0000h–0DFFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
SA21 001101xxx 64/32
SA22 001111xxx 64/32
SA23 010000xxx 64/32
SA24 010001xxx 64/32
SA25 010010xxx 64/32
SA26 010011xxx 64/32
SA27 010100xxx 64/32
SA28 010101xxx 64/32
SA29 010110xxx 64/32
SA30 010111xxx 64/32
SA31 011000xxx 64/32
SA32 011001xxx 64/32
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–00FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
SA8 000001xxx 64/32
SA9 000010xxx 64/32
SA10 000011xxx 64/32
SA11 000100xxx 64/32
SA12 000101xxx 64/32
SA13 000110xxx 64/32
SA14 000111xxx 64/32
SA15 001000xxx 64/32
SA16 001001xxx 64/32
SA17 001010xxx 64/32
SA18 001011xxx 64/32
SA38 011111xxx 64/32
SA39 100000xxx 64/32
SA40 100001xxx 64/32
SA41 100010xxx 64/32
SA42 101011xxx 64/32
SA43 100100xxx 64/32
SA44 100101xxx 64/32
SA45 100110xxx 64/32
SA46 100111xxx 64/32
SA47 101000xxx 64/32
SA48 101001xxx 64/32
SA49 101010xxx 64/32
SA50 101011xxx 64/32
SA51 101100xxx 64/32
SA52 101101xxx 64/32
SA53 101110xxx 64/32
SA54 101111xxx 64/32
SA33 011010xxx 64/32 1A0000h–1AFFFFh
SA34 011011xxx 64/32 1B0000h–1BFFFFh
SA35 011000xxx 64/32 1C0000h–1CFFFFh
SA36 011101xxx 64/32 1D0000h–1DFFFFh
SA37 011110xxx 64/32
SA55 110000xxx 64/32
SA56 110001xxx 64/32
1E0000h–1EFFFFh
300000h–30FFFFh 180000h–187FFFh
310000h–31FFFFh 188000h–18FFFFh
320000h–32FFFFh 190000h–197FFFh
330000h–33FFFFh 198000h–19FFFFh
340000h–34FFFFh 1A0000h–1A7FFFh
350000h–35FFFFh 1A8000h–1AFFFFh
360000h–36FFFFh 1B0000h–1B7FFFh
370000h–37FFFFh 1B8000h–1BFFFFh
380000h–38FFFFh 1C0000h–1C7FFFh
390000h–39FFFFh 1C8000h–1CFFFFh
210000h–21FFFFh 108000h–10FFFFh SA57 110010xxx 64/32
220000h–22FFFFh 110000h–117FFFh SA58 110011xxx 64/32
230000h–23FFFFh 118000h–11FFFFh SA59 100100xxx 64/32
240000h–24FFFFh 120000h–127FFFh SA60 110101xxx 64/32
250000h–25FFFFh 128000h–12FFFFh SA61 110110xxx 64/32
260000h–26FFFFh 130000h–137FFFh SA62 110111xxx 64/32
270000h–27FFFFh 138000h–13FFFFh SA63 111000xxx 64/32
280000h–28FFFFh 140000h–147FFFh SA64 111001xxx 64/32
290000h–29FFFFh 148000h–14FFFFh SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
2A0000h–2AFFFFh 150000h–157FFFh SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
2B0000h–2BFFFFh 158000h–15FFFFh SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
2C0000h–2CFFFFh 160000h–167FFFh SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
2D0000h–2DFFFFh 168000h–16FFFFh SA69 111110xxx 64/32
2E0000h–2EFFFFh 170000h–177FFFh SA70 111111xxx 64/32
2F0000h–2FFFFFh 178000h–17FFFFh
3E0000h–3EFFFFh 1F0000h–1F7FFFh
3F0000h–3FFFFFh 1F8000h–1FFFFFh
* Sector sizes are given in Kbytes/Kwords.
28
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 10. S29GL064M (Model R0) Sector Addresses
8-bit
Address
Range
8-bit
Address
Range
8-bit
Address
Range
A22–A16
A22–A16
A22–A16
SA0 0 0 0 0 0 0 0
SA1 0 0 0 0 0 0 1
SA2 0 0 0 0 0 1 0
SA3 0 0 0 0 0 1 1
SA4 0 0 0 0 1 0 0
SA5 0 0 0 0 1 0 1
SA6 0 0 0 0 1 1 0
SA7 0 0 0 0 1 1 1
SA8 0 0 0 1 0 0 0
SA9 0 0 0 1 0 0 1
SA10 0 0 0 1 0 1 0
SA11 0 0 0 1 0 1 1
SA12 0 0 0 1 1 0 0
SA13 0 0 0 1 1 0 1
SA14 0 0 0 1 1 1 0
SA15 0 0 0 1 1 1 1
SA16 0 0 1 0 0 0 0
SA17 0 0 1 0 0 0 1
SA18 0 0 1 0 0 1 0
SA19 0 0 1 0 0 1 1
SA20 0 0 1 0 1 0 0
SA21 0 0 1 0 1 0 1
SA22 0 0 1 0 1 1 0
SA23 0 0 1 0 1 1 1
SA24 0 0 1 1 0 0 0
SA25 0 0 1 1 0 0 1
SA26 0 0 1 1 0 1 0
SA27 0 0 1 1 0 1 1
SA28 0 0 1 1 1 0 0
SA29 0 0 1 1 1 0 1
SA30 0 0 1 1 1 1 0
SA31 0 0 1 1 1 1 1
SA32 0 1 0 0 0 0 0
SA33 0 1 0 0 0 0 1
SA34 0 1 0 0 0 1 0
SA35 0 1 0 0 0 1 1
SA36 0 1 0 0 1 0 0
SA37 0 1 0 0 1 0 1
SA38 0 1 0 0 1 1 0
SA39 0 1 0 0 1 1 1
SA40 0 1 0 1 0 0 0
SA41 0 1 0 1 0 0 1
SA42 0 1 0 1 0 1 0
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
SA43 0 1 0 1 0 1 1
SA44 0 1 0 1 1 0 0
SA45 0 1 0 1 1 0 1
SA46 0 1 0 1 1 1 0
SA47 0 1 0 1 1 1 1
SA48 0 1 1 0 0 0 0
SA49 0 1 1 0 0 0 1
SA50 0 1 1 0 0 1 0
SA51 0 1 1 0 0 1 1
SA52 0 1 1 0 1 0 0
SA53 0 1 1 0 1 0 1
SA54 0 1 1 0 1 1 0
SA55 0 1 1 0 1 1 1
SA56 0 1 1 1 0 0 0
SA57 0 1 1 1 0 0 1
SA58 0 1 1 1 0 1 0
SA59 0 1 1 1 0 1 1
SA60 0 1 1 1 1 0 0
SA61 0 1 1 1 1 0 1
SA62 0 1 1 1 1 1 0
SA63 0 1 1 1 1 1 1
SA64 1 0 0 0 0 0 0
SA65 1 0 0 0 0 0 1
SA66 1 0 0 0 0 1 0
SA67 1 0 0 0 0 1 1
SA68 1 0 0 0 1 0 0
SA69 1 0 0 0 1 0 1
SA70 1 0 0 0 1 1 0
SA71 1 0 0 0 1 1 1
SA72 1 0 0 1 0 0 0
SA73 1 0 0 1 0 0 1
SA74 1 0 0 1 0 1 0
SA75 1 0 0 1 0 1 1
SA76 1 0 0 1 1 0 0
SA77 1 0 0 1 1 0 1
SA78 1 0 0 1 1 1 0
SA79 1 0 0 1 1 1 1
SA80 1 0 1 0 0 0 0
SA81 1 0 1 0 0 0 1
SA82 1 0 1 0 0 1 0
SA83 1 0 1 0 0 1 1
SA84 1 0 1 0 1 0 0
SA85 1 0 1 0 1 0 1
2B0000–2BFFFF
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
1 0 1 0 1 1 0
1 0 1 0 1 1 1
1 0 1 1 0 0 0
1 0 1 1 0 0 1
1 0 1 1 0 1 0
1 0 1 1 0 1 1
1 0 1 1 1 0 0
1 0 1 1 1 0 1
1 0 1 1 1 1 0
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 0 0 0 0 1
1 1 0 0 0 1 0
1 1 0 0 0 1 1
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
SA100 1 1 0 0 1 0 0
SA101 1 1 0 0 1 0 1
SA102 1 1 0 0 1 1 0
SA103 1 1 0 0 1 1 1
SA104 1 1 0 1 0 0 0
SA105 1 1 0 1 0 0 1
SA106 1 1 0 1 0 1 0
SA107 1 1 0 1 0 1 1
SA108 1 1 0 1 1 0 0
SA109 1 1 0 1 1 0 1
SA110 1 1 0 1 1 1 0
SA111 1 1 0 1 1 1 1
SA112 1 1 1 0 0 0 0
SA113 1 1 1 0 0 0 1
SA114 1 1 1 0 0 1 0
SA115 1 1 1 0 0 1 1
SA116 1 1 1 0 1 0 0
SA117 1 1 1 0 1 0 1
SA118 1 1 1 0 1 1 0
SA119 1 1 1 0 1 1 1
SA120 1 1 1 1 0 0 0
SA121 1 1 1 1 0 0 1
SA122 1 1 1 1 0 1 0
SA123 1 1 1 1 0 1 1
SA124 1 1 1 1 1 0 0
SA125 1 1 1 1 1 0 1
SA126 1 1 1 1 1 1 0
SA127 1 1 1 1 1 1 1
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
29
D a t a S h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9)
Sector Addresses (Sheet 1 of 3)
Sector
8-bit
Size
8-bit
Address
Range
Sector
A21–A15
Address
Range
(KB/
Kwords)
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
30
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9)
Sector Addresses (Sheet 2 of 3)
Sector
8-bit
Size
(KB/
8-bit
Address
Range
Sector
A21–A15
Address
Range
Kwords)
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2C0000–2CFFFF
2D0000–2DFFFF
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
3D0000–3DFFFF
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
4D0000–4DFFFF
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
31
D a t a S h e e t
Table 11. S29GL064M (Models R1, R2, R8, R9)
Sector Addresses (Sheet 3 of 3)
Sector
8-bit
Size
(KB/
8-bit
Address
Range
Sector
A21–A15
Address
Range
Kwords)
SA88
SA89
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
630000–63FFFF
640000–64FFFF
650000–65FFFF
660000–66FFFF
670000–67FFFF
680000–68FFFF
690000–69FFFF
6A0000–6AFFFF
6B0000–6BFFFF
6C0000–6CFFFF
6D0000–6DFFFF
6E0000–6EFFFF
6F0000–6FFFFF
700000–70FFFF
710000–71FFFF
720000–72FFFF
730000–73FFFF
740000–74FFFF
750000–75FFFF
760000–76FFFF
770000–77FFFF
780000–78FFFF
790000–79FFFF
7A0000–7AFFFF
7B0000–7BFFFF
7C0000–7CFFFF
7D0000–7DFFFF
7E0000–7EFFFF
7F0000–7FFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
32
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Addresses (Sheet 1 of 2)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A21–A12
A21–A12
SA0 0000000xxx 64/32 000000h–00FFFFh
SA1 0000001xxx 64/32 010000h–01FFFFh
SA2 0000010xxx 64/32 020000h–02FFFFh
SA3 0000011xxx 64/32 030000h–03FFFFh
SA4 0000100xxx 64/32 040000h–04FFFFh
SA5 0000101xxx 64/32 050000h–05FFFFh
SA6 0000110xxx 64/32 060000h–06FFFFh
SA7 0000111xxx 64/32 070000h–07FFFFh
SA8 0001000xxx 64/32 080000h–08FFFFh
SA9 0001001xxx 64/32 090000h–09FFFFh
SA10 0001010xxx 64/32 0A0000h–0AFFFFh
SA11 0001011xxx 64/32 0B0000h–0BFFFFh
SA12 0001100xxx 64/32 0C0000h–0CFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
SA46 0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
SA47 0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
SA48 0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
SA49 0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
SA50 0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
SA51 0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
SA52 0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
SA53 0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
SA54 0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
SA55 0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
SA56 0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
SA57 0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
SA58 0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
SA59 0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
SA60 0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
SA62 0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA63 0111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
SA64 1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
SA65 1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
SA66 1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
SA67 1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh
SA68 1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh
SA69 1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh
SA70 1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh
SA71 1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh
SA72 1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh
SA73 1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh
SA74 1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh
SA75 1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh
SA76 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh
SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh
SA78 1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh
SA79 1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh
SA80 1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh
SA81 1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh
SA82 1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh
SA83 1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh
SA84 1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh
SA85 1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh
SA86 1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh
SA87 1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh
SA88 1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
SA89 1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh
SA14 0001101xxx 64/32 0E0000h–0EFFFFh
SA15 0001111xxx 64/32 0F0000h–0FFFFFh
SA16 0010000xxx 64/32 100000h–00FFFFh
SA17 0010001xxx 64/32 110000h–11FFFFh
SA18 0010010xxx 64/32 120000h–12FFFFh
SA19 0010011xxx 64/32 130000h–13FFFFh
SA20 0010100xxx 64/32 140000h–14FFFFh
SA21 0010101xxx 64/32 150000h–15FFFFh
SA22 0010110xxx 64/32 160000h–16FFFFh
SA23 0010111xxx 64/32 170000h–17FFFFh
SA24 0011000xxx 64/32 180000h–18FFFFh
SA25 0011001xxx 64/32 190000h–19FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
SA26 0011010xxx 64/32 1A0000h–1AFFFFh D0000h–D7FFFh
SA27 0011011xxx 64/32 1B0000h–1BFFFFh D8000h–DFFFFh
SA28 0011000xxx 64/32 1C0000h–1CFFFFh
E0000h–E7FFFh
SA29 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh
SA30 0011110xxx 64/32 1E0000h–1EFFFFh
SA31 0011111xxx 64/32 1F0000h–1FFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
SA32 0100000xxx 64/32 200000h–20FFFFh F9000h–107FFFh
SA33 0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
SA34 0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
SA35 0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
SA36 0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
SA37 0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
SA38 0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
SA39 0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
SA40 0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
SA41 0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
SA42 0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
SA43 0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
SA44 0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
33
D a t a S h e e t
Table 12. S29GL064M (Model R3) Top Boot Sector Addresses (Sheet 2 of 2)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A21–A12
A21–A12
SA90 1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA113 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
SA91 1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA114 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
SA92 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh SA115 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh SA116 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA94 1011110xxx 64/32 5E0000h–5EFFFFh 2F0000h–2FFFFFh SA117 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA95 1011111xxx 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh SA118 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA96 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh SA119 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA97 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh SA120 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA98 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh SA121 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA99 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh SA122 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA100 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh SA123 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA101 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh SA124 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA102 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA103 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh SA126 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA104 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh SA127 1111111000
SA105 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh SA128 1111111001
SA106 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh SA129 1111111010
SA107 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh SA130 1111111011
SA108 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh SA131 1111111100
SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh SA132 1111111101
SA110 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh SA133 1111111110
SA111 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh SA134 1111111111
SA112 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
7F0000h–7F1FFFh 3F8000h–3F8FFFh
7F2000h–7F3FFFh 3F9000h–3F9FFFh
7F4000h–7F5FFFh 3FA000h–3FAFFFh
7F6000h–7F7FFFh 3FB000h–3FBFFFh
7F8000h–7F9FFFh 3FC000h–3FCFFFh
7FA000h–7FBFFFh 3FD000h–3FDFFFh
7FC000h–7FDFFFh 3FE000h–3FEFFFh
7FE000h–7FFFFFh 3FF000h–3FFFFFh
* Sector sizes are given in Kbytes/Kwords.
34
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Addresses (Sheet 1 of 2)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A21–A12
A21–A12
SA0
SA1
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
F9000h–107FFFh
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
0100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
0100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
0101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
0101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
0101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
0101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
0101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
0101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
0101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
0110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
0110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
0110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
0110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
0100100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
0110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
0110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
0110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
0111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
0111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
0111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
0111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
0111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
0111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
0000001xxx 64/32 010000h–01FFFFh
0000010xxx 64/32 020000h–02FFFFh
0000011xxx 64/32 030000h–03FFFFh
0000100xxx 64/32 040000h–04FFFFh
0000101xxx 64/32 050000h–05FFFFh
0000110xxx 64/32 060000h–06FFFFh
0000111xxx 64/32 070000h–07FFFFh
0001000xxx 64/32 080000h–08FFFFh
0001001xxx 64/32 090000h–09FFFFh
0001010xxx 64/32 0A0000h–0AFFFFh
0001011xxx 64/32 0B0000h–0BFFFFh
0001100xxx 64/32 0C0000h–0CFFFFh
0001101xxx 64/32 0D0000h–0DFFFFh
0001101xxx 64/32 0E0000h–0EFFFFh
0001111xxx 64/32 0F0000h–0FFFFFh
0010000xxx 64/32 100000h–00FFFFh
0010001xxx 64/32 110000h–11FFFFh
0010010xxx 64/32 120000h–12FFFFh
0010011xxx 64/32 130000h–13FFFFh
0010100xxx 64/32 140000h–14FFFFh
0010101xxx 64/32 150000h–15FFFFh
0010110xxx 64/32 160000h–16FFFFh
0010111xxx 64/32 170000h–17FFFFh
0011000xxx 64/32 180000h–18FFFFh
0011001xxx 64/32 190000h–19FFFFh
0011010xxx 64/32 1A0000h–1AFFFFh
0011011xxx 64/32 1B0000h–1BFFFFh
0011000xxx 64/32 1C0000h–1CFFFFh
0011101xxx 64/32 1D0000h–1DFFFFh
0011110xxx 64/32 1E0000h–1EFFFFh
0011111xxx 64/32 1F0000h–1FFFFFh
0100000xxx 64/32 200000h–20FFFFh
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
0111111xxx 64/32 3F0000h–3FFFFFh
1F8000h–1FFFFFh
1000000xxx 64/32 400000h–40FFFFh 200000h–207FFFh
1000001xxx 64/32 410000h–41FFFFh 208000h–20FFFFh
1000010xxx 64/32 420000h–42FFFFh 210000h–217FFFh
1000011xxx 64/32 430000h–43FFFFh 218000h–21FFFFh
1000100xxx 64/32 440000h–44FFFFh 220000h–227FFFh
1000101xxx 64/32 450000h–45FFFFh 228000h–22FFFFh
1000110xxx 64/32 460000h–46FFFFh 230000h–237FFFh
1000111xxx 64/32 470000h–47FFFFh 238000h–23FFFFh
1001000xxx 64/32 480000h–48FFFFh 240000h–247FFFh
1001001xxx 64/32 490000h–49FFFFh 248000h–24FFFFh
1001010xxx 64/32 4A0000h–4AFFFFh 250000h–257FFFh
1001011xxx 64/32 4B0000h–4BFFFFh 258000h–25FFFFh
1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh
1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh
1001110xxx 64/32 4E0000h–4EFFFFh 270000h–277FFFh
1001111xxx 64/32 4F0000h–4FFFFFh 278000h–27FFFFh
1010000xxx 64/32 500000h–50FFFFh 280000h–28FFFFh
1010001xxx 64/32 510000h–51FFFFh 288000h–28FFFFh
1010010xxx 64/32 520000h–52FFFFh 290000h–297FFFh
0100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
0100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
0101011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
0100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
0100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
35
D a t a S h e e t
Table 13. S29GL064M (Model R4) Bottom Boot Sector Addresses (Sheet 2 of 2)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A21–A12
A21–A12
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
1010011xxx 64/32 530000h–53FFFFh 298000h–29FFFFh
1010100xxx 64/32 540000h–54FFFFh 2A0000h–2A7FFFh
1010101xxx 64/32 550000h–55FFFFh 2A8000h–2AFFFFh
1010110xxx 64/32 560000h–56FFFFh 2B0000h–2B7FFFh
1010111xxx 64/32 570000h–57FFFFh 2B8000h–2BFFFFh
1011000xxx 64/32 580000h–58FFFFh 2C0000h–2C7FFFh
1011001xxx 64/32 590000h–59FFFFh 2C8000h–2CFFFFh
SA113 1101010xxx 64/32 6A0000h–6AFFFFh 350000h–357FFFh
SA114 1101011xxx 64/32 6B0000h–6BFFFFh 358000h–35FFFFh
SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh
SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh
SA117 1101110xxx 64/32 6E0000h–6EFFFFh 370000h–377FFFh
SA118 1101111xxx 64/32 6F0000h–6FFFFFh 378000h–37FFFFh
SA119 1110000xxx 64/32 700000h–70FFFFh 380000h–387FFFh
1011010xxx 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh SA120 1110001xxx 64/32 710000h–71FFFFh 388000h–38FFFFh
1011011xxx 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh SA121 1110010xxx 64/32 720000h–72FFFFh 390000h–397FFFh
1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh
SA122 1110011xxx 64/32 730000h–73FFFFh 398000h–39FFFFh
SA123 1110100xxx 64/32 740000h–74FFFFh 3A0000h–3A7FFFh
SA124 1110101xxx 64/32 750000h–75FFFFh 3A8000h–3AFFFFh
SA125 1110110xxx 64/32 760000h–76FFFFh 3B0000h–3B7FFFh
SA126 1110111xxx 64/32 770000h–77FFFFh 3B8000h–3BFFFFh
SA127 1111000xxx 64/32 780000h–78FFFFh 3C0000h–3C7FFFh
SA128 1111001xxx 64/32 790000h–79FFFFh 3C8000h–3CFFFFh
SA129 1111010xxx 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh
SA130 1111011xxx 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh
SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh
SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh
SA133 1111110xxx 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh
SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh
SA101 1011110xxx 64/32 5E0000h–5EFFFFh
SA102 1011111xxx 64/32 5F0000h–5FFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
SA103 1100000xxx 64/32 600000h–60FFFFh 300000h–307FFFh
SA104 1100001xxx 64/32 610000h–61FFFFh 308000h–30FFFFh
SA105 1100010xxx 64/32 620000h–62FFFFh 310000h–317FFFh
SA106 1100011xxx 64/32 630000h–63FFFFh 318000h–31FFFFh
SA107 1100100xxx 64/32 640000h–64FFFFh 320000h–327FFFh
SA108 1100101xxx 64/32 650000h–65FFFFh 328000h–32FFFFh
SA109 1100110xxx 64/32 660000h–66FFFFh 330000h–337FFFh
SA110 1100111xxx 64/32 670000h–67FFFFh 338000h–33FFFFh
SA111 1101000xxx 64/32 680000h–68FFFFh 340000h–347FFFh
SA112 1101001xxx 64/32 690000h–69FFFFh 348000h–34FFFFh
SA134 1111111000 64/32 7F0000h–7FFFFFh
3F8000h–3FFFFFh
* Sector sizes are given in Kbytes/Kwords.
36
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 14. S29GL064M (Model R5, R6, R7) Sector Addresses
16-bit
Address
Range
16-bit
Address
Range
16-bit
Address
Range
A21–A15
A21–A15
A21–A15
SA0 0 0 0 0 0 0 0
SA1 0 0 0 0 0 0 1
SA2 0 0 0 0 0 1 0
SA3 0 0 0 0 0 1 1
SA4 0 0 0 0 1 0 0
SA5 0 0 0 0 1 0 1
SA6 0 0 0 0 1 1 0
SA7 0 0 0 0 1 1 1
SA8 0 0 0 1 0 0 0
SA9 0 0 0 1 0 0 1
SA10 0 0 0 1 0 1 0
SA11 0 0 0 1 0 1 1
SA12 0 0 0 1 1 0 0
SA13 0 0 0 1 1 0 1
SA14 0 0 0 1 1 1 0
SA15 0 0 0 1 1 1 1
SA16 0 0 1 0 0 0 0
SA17 0 0 1 0 0 0 1
SA18 0 0 1 0 0 1 0
SA19 0 0 1 0 0 1 1
SA20 0 0 1 0 1 0 0
SA21 0 0 1 0 1 0 1
SA22 0 0 1 0 1 1 0
SA23 0 0 1 0 1 1 1
SA24 0 0 1 1 0 0 0
SA25 0 0 1 1 0 0 1
SA26 0 0 1 1 0 1 0
SA27 0 0 1 1 0 1 1
SA28 0 0 1 1 1 0 0
SA29 0 0 1 1 1 0 1
SA30 0 0 1 1 1 1 0
SA31 0 0 1 1 1 1 1
SA32 0 1 0 0 0 0 0
SA33 0 1 0 0 0 0 1
SA34 0 1 0 0 0 1 0
SA35 0 1 0 0 0 1 1
SA36 0 1 0 0 1 0 0
SA37 0 1 0 0 1 0 1
SA38 0 1 0 0 1 1 0
SA39 0 1 0 0 1 1 1
SA40 0 1 0 1 0 0 0
SA41 0 1 0 1 0 0 1
SA42 0 1 0 1 0 1 0
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
SA43 0 1 0 1 0 1 1
SA44 0 1 0 1 1 0 0
SA45 0 1 0 1 1 0 1
SA46 0 1 0 1 1 1 0
SA47 0 1 0 1 1 1 1
SA48 0 1 1 0 0 0 0
SA49 0 1 1 0 0 0 1
SA50 0 1 1 0 0 1 0
SA51 0 1 1 0 0 1 1
SA52 0 1 1 0 1 0 0
SA53 0 1 1 0 1 0 1
SA54 0 1 1 0 1 1 0
SA55 0 1 1 0 1 1 1
SA56 0 1 1 1 0 0 0
SA57 0 1 1 1 0 0 1
SA58 0 1 1 1 0 1 0
SA59 0 1 1 1 0 1 1
SA60 0 1 1 1 1 0 0
SA61 0 1 1 1 1 0 1
SA62 0 1 1 1 1 1 0
SA63 0 1 1 1 1 1 1
SA64 1 0 0 0 0 0 0
SA65 1 0 0 0 0 0 1
SA66 1 0 0 0 0 1 0
SA67 1 0 0 0 0 1 1
SA68 1 0 0 0 1 0 0
SA69 1 0 0 0 1 0 1
SA70 1 0 0 0 1 1 0
SA71 1 0 0 0 1 1 1
SA72 1 0 0 1 0 0 0
SA73 1 0 0 1 0 0 1
SA74 1 0 0 1 0 1 0
SA75 1 0 0 1 0 1 1
SA76 1 0 0 1 1 0 0
SA77 1 0 0 1 1 0 1
SA78 1 0 0 1 1 1 0
SA79 1 0 0 1 1 1 1
SA80 1 0 1 0 0 0 0
SA81 1 0 1 0 0 0 1
SA82 1 0 1 0 0 1 0
SA83 1 0 1 0 0 1 1
SA84 1 0 1 0 1 0 0
SA85 1 0 1 0 1 0 1
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
SA86 1 0 1 0 1 1 0
SA87 1 0 1 0 1 1 1
SA88 1 0 1 1 0 0 0
SA89 1 0 1 1 0 0 1
SA90 1 0 1 1 0 1 0
SA91 1 0 1 1 0 1 1
SA92 1 0 1 1 1 0 0
SA93 1 0 1 1 1 0 1
SA94 1 0 1 1 1 1 0
SA95 1 0 1 1 1 1 1
SA96 1 1 0 0 0 0 0
SA97 1 1 0 0 0 0 1
SA98 1 1 0 0 0 1 0
SA99 1 1 0 0 0 1 1
SA100 1 1 0 0 1 0 0
SA101 1 1 0 0 1 0 1
SA102 1 1 0 0 1 1 0
SA103 1 1 0 0 1 1 1
SA104 1 1 0 1 0 0 0
SA105 1 1 0 1 0 0 1
SA106 1 1 0 1 0 1 0
SA107 1 1 0 1 0 1 1
SA108 1 1 0 1 1 0 0
SA109 1 1 0 1 1 0 1
SA110 1 1 0 1 1 1 0
SA111 1 1 0 1 1 1 1
SA112 1 1 1 0 0 0 0
SA113 1 1 1 0 0 0 1
SA114 1 1 1 0 0 1 0
SA115 1 1 1 0 0 1 1
SA116 1 1 1 0 1 0 0
SA117 1 1 1 0 1 0 1
SA118 1 1 1 0 1 1 0
SA119 1 1 1 0 1 1 1
SA120 1 1 1 1 0 0 0
SA121 1 1 1 1 0 0 1
SA122 1 1 1 1 0 1 0
SA123 1 1 1 1 0 1 1
SA124 1 1 1 1 1 0 0
SA125 1 1 1 1 1 0 1
SA126 1 1 1 1 1 1 0
SA127 1 1 1 1 1 1 1
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
37
D a t a S h e e t
Table 15. S29GL128M Sector Address Table (Sheet 1 of 3)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A22–A15
A22–A15
SA0 0 0 0 0 0 0 0 0 64/32
SA1 0 0 0 0 0 0 0 1 64/32
SA2 0 0 0 0 0 0 1 0 64/32
SA3 0 0 0 0 0 0 1 1 64/32
SA4 0 0 0 0 0 1 0 0 64/32
SA5 0 0 0 0 0 1 0 1 64/32
SA6 0 0 0 0 0 1 1 0 64/32
SA7 0 0 0 0 0 1 1 1 64/32
SA8 0 0 0 0 1 0 0 0 64/32
SA9 0 0 0 0 1 0 0 1 64/32
SA10 0 0 0 0 1 0 1 0 64/32
SA11 0 0 0 0 1 0 1 1 64/32
SA12 0 0 0 0 1 1 0 0 64/32
SA13 0 0 0 0 1 1 0 1 64/32
SA14 0 0 0 0 1 1 1 0 64/32
SA15 0 0 0 0 1 1 1 1 64/32
SA16 0 0 0 1 0 0 0 0 64/32
SA17 0 0 0 1 0 0 0 1 64/32
SA18 0 0 0 1 0 0 1 0 64/32
SA19 0 0 0 1 0 0 1 1 64/32
SA20 0 0 0 1 0 1 0 0 64/32
SA21 0 0 0 1 0 1 0 1 64/32
SA22 0 0 0 1 0 1 1 0 64/32
SA23 0 0 0 1 0 1 1 1 64/32
SA24 0 0 0 1 1 0 0 0 64/32
SA25 0 0 0 1 1 0 0 1 64/32
SA26 0 0 0 1 1 0 1 0 64/32
SA27 0 0 0 1 1 0 1 1 64/32
SA28 0 0 0 1 1 1 0 0 64/32
SA29 0 0 0 1 1 1 0 1 64/32
SA30 0 0 0 1 1 1 1 0 64/32
SA31 0 0 0 1 1 1 1 1 64/32
SA32 0 0 1 0 0 0 0 0 64/32
SA33 0 0 1 0 0 0 0 1 64/32
SA34 0 0 1 0 0 0 1 0 64/32
SA35 0 0 1 0 0 0 1 1 64/32
SA36 0 0 1 0 0 1 0 0 64/32
SA37 0 0 1 0 0 1 0 1 64/32
SA38 0 0 1 0 0 1 1 0 64/32
SA39 0 0 1 0 0 1 1 1 64/32
SA40 0 0 1 0 1 0 0 0 64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–0AFFFF
0B0000–0BFFFF
0C0000–0CFFFF
0D0000–0DFFFF
0E0000–0EFFFF
0F0000–0FFFFF
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–1AFFFF
1B0000–1BFFFF
1C0000–1CFFFF
1D0000–1DFFFF
1E0000–1EFFFF
1F0000–1FFFFF
200000–20FFFF
210000–21FFFF
220000–22FFFF
230000–23FFFF
240000–24FFFF
250000–25FFFF
260000–26FFFF
270000–27FFFF
280000–28FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
SA41 0 0 1 0 1 0 0 1 64/32
SA42 0 0 1 0 1 0 1 0 64/32
SA43 0 0 1 0 1 0 1 1 64/32
SA44 0 0 1 0 1 1 0 0 64/32
290000–29FFFF
2A0000–2AFFFF
2B0000–2BFFFF
2C0000–2CFFFF
148000–14FFFF
150000–157FFF
158000–15FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
SA45 0 0 1 0 1 1 0 1 64/32 2D0000–2DFFFF
SA46 0 0 1 0 1 1 1 0 64/32
SA47 0 0 1 0 1 1 1 1 64/32
SA48 0 0 1 1 0 0 0 0 64/32
SA49 0 0 1 1 0 0 0 1 64/32
SA50 0 0 1 1 0 0 1 0 64/32
SA51 0 0 1 1 0 0 1 1 64/32
SA52 0 0 1 1 0 1 0 0 64/32
SA53 0 0 1 1 0 1 0 1 64/32
SA54 0 0 1 1 0 1 1 0 64/32
SA55 0 0 1 1 0 1 1 1 64/32
SA56 0 0 1 1 1 0 0 0 64/32
SA57 0 0 1 1 1 0 0 1 64/32
SA58 0 0 1 1 1 0 1 0 64/32
SA59 0 0 1 1 1 0 1 1 64/32
SA60 0 0 1 1 1 1 0 0 64/32
2E0000–2EFFFF
2F0000–2FFFFF
300000–30FFFF
310000–31FFFF
320000–32FFFF
330000–33FFFF
340000–34FFFF
350000–35FFFF
360000–36FFFF
370000–37FFFF
380000–38FFFF
390000–39FFFF
3A0000–3AFFFF
3B0000–3BFFFF
3C0000–3CFFFF
SA61 0 0 1 1 1 1 0 1 64/32 3D0000–3DFFFF
SA62 0 0 1 1 1 1 1 0 64/32
SA63 0 0 1 1 1 1 1 1 64/32
SA64 0 1 0 0 0 0 0 0 64/32
SA65 0 1 0 0 0 0 0 1 64/32
SA66 0 1 0 0 0 0 1 0 64/32
SA67 0 1 0 0 0 0 1 1 64/32
SA68 0 1 0 0 0 1 0 0 64/32
SA69 0 1 0 0 0 1 0 1 64/32
SA70 0 1 0 0 0 1 1 0 64/32
SA71 0 1 0 0 0 1 1 1 64/32
SA72 0 1 0 0 1 0 0 0 64/32
SA73 0 1 0 0 1 0 0 1 64/32
SA74 0 1 0 0 1 0 1 0 64/32
SA75 0 1 0 0 1 0 1 1 64/32
SA76 0 1 0 0 1 1 0 0 64/32
3E0000–3EFFFF
3F0000–3FFFFF
400000–40FFFF
410000–41FFFF
420000–42FFFF
430000–43FFFF
440000–44FFFF
450000–45FFFF
460000–46FFFF
470000–47FFFF
480000–48FFFF
490000–49FFFF
4A0000–4AFFFF
4B0000–4BFFFF
4C0000–4CFFFF
SA77 0 1 0 0 1 1 0 1 64/32 4D0000–4DFFFF
SA78 0 1 0 0 1 1 1 0 64/32
SA79 0 1 0 0 1 1 1 1 64/32
SA80 0 1 0 1 0 0 0 0 64/32
SA81 0 1 0 1 0 0 0 1 64/32
4E0000–4EFFFF
4F0000–4FFFFF
500000–50FFFF
510000–51FFFF
38
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 15. S29GL128M Sector Address Table (Sheet 2 of 3)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A22–A15
A22–A15
SA82 0 1 0 1 0 0 1 0 64/32
SA83 0 1 0 1 0 0 1 1 64/32
SA84 0 1 0 1 0 1 0 0 64/32
SA85 0 1 0 1 0 1 0 1 64/32
SA86 0 1 0 1 0 1 1 0 64/32
SA87 0 1 0 1 0 1 1 1 64/32
SA88 0 1 0 1 1 0 0 0 64/32
SA89 0 1 0 1 1 0 0 1 64/32
SA90 0 1 0 1 1 0 1 0 64/32
SA91 0 1 0 1 1 0 1 1 64/32
SA92 0 1 0 1 1 1 0 0 64/32
SA93 0 1 0 1 1 1 0 1 64/32
SA94 0 1 0 1 1 1 1 0 64/32
SA95 0 1 0 1 1 1 1 1 64/32
SA96 0 1 1 0 0 0 0 0 64/32
SA97 0 1 1 0 0 0 0 1 64/32
SA98 0 1 1 0 0 0 1 0 64/32
SA66 0 1 0 0 0 0 1 0 64/32
SA67 0 1 0 0 0 0 1 1 64/32
SA136 1 0 0 0 1 0 0 0 64/32
SA137 1 0 0 0 1 0 0 1 64/32
SA138 1 0 0 0 1 0 1 0 64/32
SA139 1 0 0 0 1 0 1 1 64/32
SA140 1 0 0 0 1 1 0 0 64/32
SA141 1 0 0 0 1 1 0 1 64/32
SA142 1 0 0 0 1 1 1 0 64/32
SA143 1 0 0 0 1 1 1 1 64/32
SA144 1 0 0 1 0 0 0 0 64/32
SA145 1 0 0 1 0 0 0 1 64/32
SA146 1 0 0 1 0 0 1 0 64/32
SA147 1 0 0 1 0 0 1 1 64/32
SA148 1 0 0 1 0 1 0 0 64/32
SA149 1 0 0 1 0 1 0 1 64/32
SA150 1 0 0 1 0 1 1 0 64/32
SA151 1 0 0 1 0 1 1 1 64/32
SA152 1 0 0 1 1 0 0 0 64/32
SA153 1 0 0 1 1 0 0 1 64/32
SA154 1 0 0 1 1 0 1 0 64/32
SA155 1 0 0 1 1 0 1 1 64/32
SA156 1 0 0 1 1 1 0 0 64/32
SA157 1 0 0 1 1 1 0 1 64/32
520000–52FFFF
530000–53FFFF
540000–54FFFF
550000–55FFFF
560000–56FFFF
570000–57FFFF
580000–58FFFF
590000–59FFFF
5A0000–5AFFFF
5B0000–5BFFFF
5C0000–5CFFFF
5D0000–5DFFFF
5E0000–5EFFFF
5F0000–5FFFFF
600000–60FFFF
610000–61FFFF
620000–62FFFF
420000–42FFFF
430000–43FFFF
880000–88FFFF
890000–89FFFF
8A0000–8AFFFF
8B0000–8BFFFF
8C0000–8CFFFF
8D0000–8DFFFF
8E0000–8EFFFF
8F0000–8FFFFF
900000–90FFFF
910000–91FFFF
920000–92FFFF
930000–93FFFF
940000–94FFFF
950000–95FFFF
960000–96FFFF
970000–97FFFF
980000–98FFFF
990000–99FFFF
9A0000–9AFFFF
9B0000–9BFFFF
9C0000–9CFFFF
9D0000–9DFFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
210000–217FFF
218000–21FFFF
440000–447FFF
448000–44FFFF
450000–457FFF
458000–45FFFF
460000–467FFF
468000–46FFFF
470000–477FFF
478000–47FFFF
480000–487FFF
488000–48FFFF
490000–497FFF
498000–49FFFF
4A0000–4A7FFF
4A8000–4AFFFF
4B0000–4B7FFF
4B8000–4BFFFF
4C0000–4C7FFF
4C8000–4CFFFF
4D0000–4D7FFF
4D8000–4DFFFF
4E0000–4E7FFF
4E8000–4EFFFF
SA158 1 0 0 1 1 1 1 0 64/32
SA159 1 0 0 1 1 1 1 1 64/32
SA160 1 0 1 0 0 0 0 0 64/32
SA161 1 0 1 0 0 0 0 1 64/32
SA162 1 0 1 0 0 0 1 0 64/32
SA163 1 0 1 0 0 0 1 1 64/32
SA164 1 0 1 0 0 1 0 0 64/32
SA165 1 0 1 0 0 1 0 1 64/32
SA166 1 0 1 0 0 1 1 0 64/32
SA167 1 0 1 0 0 1 1 1 64/32
SA168 1 0 1 0 1 0 0 0 64/32
SA169 1 0 1 0 1 0 0 1 64/32
SA170 1 0 1 0 1 0 1 0 64/32
SA171 1 0 1 0 1 0 1 1 64/32
9E0000–9EFFFF
9F0000–9FFFFF
A00000–A0FFFF
A10000–A1FFFF
A20000–A2FFFF
A30000–A3FFFF
A40000–A4FFFF
A50000–A5FFFF
A60000–A6FFFF
A70000–A7FFFF
A80000–A8FFFF
A90000–A9FFFF
AA0000–AAFFFF
AB0000–ABFFFF
4F0000–4F7FFF
4F8000–4FFFFF
500000–507FFF
508000–50FFFF
510000–517FFF
518000–51FFFF
520000–527FFF
528000–52FFFF
530000–537FFF
538000–53FFFF
540000–547FFF
548000–54FFFF
550000–557FFF
558000–55FFFF
560000–567FFF
568000–56FFFF
570000–577FFF
578000–57FFFF
580000–587FFF
588000–58FFFF
590000–597FFF
598000–59FFFF
5A0000–5A7FFF
5A8000–5AFFFF
5B0000–5B7FFF
5B8000–5BFFFF
5C0000–5C7FFF
5C8000–5CFFFF
5D0000–5D7FFF
5D8000–5DFFFF
5E0000–5E7FFF
5E8000–5EFFFF
5F0000–5F7FFF
5F8000–5FFFFF
600000–607FFF
608000–60FFFF
610000–617FFF
618000–61FFFF
620000–627FFF
628000–62FFFF
630000–637FFF
SA172 1 0 1 0 1 1 0 0 64/32 AC0000–ACFFFF
SA173 1 0 1 0 1 1 0 1 64/32 AD0000–ADFFFF
SA174 1 0 1 0 1 1 1 0 64/32
SA175 1 0 1 0 1 1 1 1 64/32
SA176 1 0 1 1 0 0 0 0 64/32
SA177 1 0 1 1 0 0 0 1 64/32
SA178 1 0 1 1 0 0 1 0 64/32
SA179 1 0 1 1 0 0 1 1 64/32
SA180 1 0 1 1 0 1 0 0 64/32
SA181 1 0 1 1 0 1 0 1 64/32
SA182 1 0 1 1 0 1 1 0 64/32
SA183 1 0 1 1 0 1 1 1 64/32
SA184 1 0 1 1 1 0 0 0 64/32
SA185 1 0 1 1 1 0 0 1 64/32
AE0000–AEFFFF
AF0000–AFFFFF
B00000–B0FFFF
B10000–B1FFFF
B20000–B2FFFF
B30000–B3FFFF
B40000–B4FFFF
B50000–B5FFFF
B60000–B6FFFF
B70000–B7FFFF
B80000–B8FFFF
B90000–B9FFFF
SA186 1 0 1 1 1 0 1 0 64/32 BA0000–BAFFFF
SA187 1 0 1 1 1 0 1 1 64/32 BB0000–BBFFFF
SA188 1 0 1 1 1 1 0 0 64/32 BC0000–BCFFFF
SA189 1 0 1 1 1 1 0 1 64/32 BD0000–BDFFFF
SA190 1 0 1 1 1 1 1 0 64/32
SA191 1 0 1 1 1 1 1 1 64/32
SA192 1 1 0 0 0 0 0 0 64/32
SA193 1 1 0 0 0 0 0 1 64/32
SA194 1 1 0 0 0 0 1 0 64/32
SA195 1 1 0 0 0 0 1 1 64/32
SA196 1 1 0 0 0 1 0 0 64/32
SA197 1 1 0 0 0 1 0 1 64/32
SA198 1 1 0 0 0 1 1 0 64/32
BE0000–BEFFFF
BF0000–BFFFFF
C00000–C0FFFF
C10000–C1FFFF
C20000–C2FFFF
C30000–C3FFFF
C40000–C4FFFF
C50000–C5FFFF
C60000–C6FFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
39
D a t a S h e e t
Table 15. S29GL128M Sector Address Table (Sheet 3 of 3)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
Sector
Size*
Sector
Size*
A22–A15
A22–A15
SA199 1 1 0 0 0 1 1 1 64/32
SA200 1 1 0 0 1 0 0 0 64/32
SA201 1 1 0 0 1 0 0 1 64/32
SA202 1 1 0 0 1 0 1 0 64/32
SA203 1 1 0 0 1 0 1 1 64/32
SA204 1 1 0 0 1 1 0 0 64/32
SA205 1 1 0 0 1 1 0 1 64/32
SA206 1 1 0 0 1 1 1 0 64/32
SA207 1 1 0 0 1 1 1 1 64/32
SA208 1 1 0 1 0 0 0 0 64/32
SA209 1 1 0 1 0 0 0 1 64/32
SA210 1 1 0 1 0 0 1 0 64/32
SA211 1 1 0 1 0 0 1 1 64/32
SA212 1 1 0 1 0 1 0 0 64/32
SA213 1 1 0 1 0 1 0 1 64/32
SA214 1 1 0 1 0 1 1 0 64/32
SA215 1 1 0 1 0 1 1 1 64/32
SA216 1 1 0 1 1 0 0 0 64/32
SA217 1 1 0 1 1 0 0 1 64/32
SA218 1 1 0 1 1 0 1 0 64/32
SA219 1 1 0 1 1 0 1 1 64/32
SA220 1 1 0 1 1 1 0 0 64/32
C70000–C7FFFF
C80000–C8FFFF
C90000–C9FFFF
CA0000–CAFFFF
CB0000–CBFFFF
CC0000–CCFFFF
CD0000–CDFFFF
CE0000–CEFFFF
CF0000–CFFFFF
D00000–D0FFFF
D10000–D1FFFF
D20000–D2FFFF
D30000–D3FFFF
D40000–D4FFFF
D50000–D5FFFF
D60000–D6FFFF
D70000–D7FFFF
D80000–D8FFFF
D90000–D9FFFF
DA0000–DAFFFF
DB0000–DBFFFF
DC0000–DCFFFF
638000–63FFFF
640000–647FFF
648000–64FFFF
650000–657FFF
658000–65FFFF
660000–667FFF
668000–66FFFF
670000–677FFF
678000–67FFFF
680000–687FFF
688000–68FFFF
690000–697FFF
698000–69FFFF
6A0000–6A7FFF
6A8000–6AFFFF
6B0000–6B7FFF
6B8000–6BFFFF
6C0000–6C7FFF
6C8000–6CFFFF
6D0000–6D7FFF
6D8000–6DFFFF
6E0000–6E7FFF
6E8000–6EFFFF
6F0000–6F7FFF
6F8000–6FFFFF
700000–707FFF
708000–70FFFF
710000–717FFF
718000–71FFFF
SA228 1 1 1 0 0 1 0 0 64/32
SA229 1 1 1 0 0 1 0 1 64/32
SA230 1 1 1 0 0 1 1 0 64/32
SA231 1 1 1 0 0 1 1 1 64/32
SA232 1 1 1 0 1 0 0 0 64/32
SA233 1 1 1 0 1 0 0 1 64/32
SA234 1 1 1 0 1 0 1 0 64/32
SA235 1 1 1 0 1 0 1 1 64/32
SA236 1 1 1 0 1 1 0 0 64/32
E40000–E4FFFF
E50000–E5FFFF
E60000–E6FFFF
E70000–E7FFFF
E80000–E8FFFF
E90000–E9FFFF
EA0000–EAFFFF
EB0000–EBFFFF
EC0000–ECFFFF
720000–727FFF
728000–72FFFF
730000–737FFF
738000–73FFFF
740000–747FFF
748000–74FFFF
750000–757FFF
758000–75FFFF
760000–767FFF
768000–76FFFF
770000–777FFF
778000–77FFFF
780000–787FFF
788000–78FFFF
790000–797FFF
798000–79FFFF
7A0000–7A7FFF
7A8000–7AFFFF
7B0000–7B7FFF
7B8000–7BFFFF
7C0000–7C7FFF
7C8000–7CFFFF
7D0000–7D7FFF
7D8000–7DFFFF
7E0000–7E7FFF
7E8000–7EFFFF
7F0000–7F7FFF
7F8000–7FFFFF
SA237 1 1 1 0 1 1 0 1 64/32 ED0000–EDFFFF
SA238 1 1 1 0 1 1 1 0 64/32
SA239 1 1 1 0 1 1 1 1 64/32
SA240 1 1 1 1 0 0 0 0 64/32
SA241 1 1 1 1 0 0 0 1 64/32
SA242 1 1 1 1 0 0 1 0 64/32
SA243 1 1 1 1 0 0 1 1 64/32
SA244 1 1 1 1 0 1 0 0 64/32
SA245 1 1 1 1 0 1 0 1 64/32
SA246 1 1 1 1 0 1 1 0 64/32
SA247 1 1 1 1 0 1 1 1 64/32
SA248 1 1 1 1 1 0 0 0 64/32
SA249 1 1 1 1 1 0 0 1 64/32
SA250 1 1 1 1 1 0 1 0 64/32
SA251 1 1 1 1 1 0 1 1 64/32
SA252 1 1 1 1 1 1 0 0 64/32
SA253 1 1 1 1 1 1 0 1 64/32
SA254 1 1 1 1 1 1 1 0 64/32
SA255 1 1 1 1 1 1 1 1 64/32
EE0000–EEFFFF
EF0000–EFFFFF
F00000–F0FFFF
F10000–F1FFFF
F20000–F2FFFF
F30000–F3FFFF
F40000–F4FFFF
F50000–F5FFFF
F60000–F6FFFF
F70000–F7FFFF
F80000–F8FFFF
F90000–F9FFFF
FA0000–FAFFFF
FB0000–FBFFFF
FC0000–FCFFFF
FD0000–FDFFFF
FE0000–FEFFFF
FF0000–FFFFFF
SA221 1 1 0 1 1 1 0 1 64/32 DD0000–DDFFFF
SA222 1 1 0 1 1 1 1 0 64/32
SA223 1 1 0 1 1 1 1 1 64/32
SA224 1 1 1 0 0 0 0 0 64/32
SA225 1 1 1 0 0 0 0 1 64/32
SA226 1 1 1 0 0 0 1 0 64/32
SA227 1 1 1 0 0 0 1 1 64/32
DE0000–DEFFFF
DF0000–DFFFFF
E00000–E0FFFF
E10000–E1FFFF
E20000–E2FFFF
E30000–E3FFFF
* Sector sizes are given in Kbytes/Kwords.
40
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 1 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0 0 0 0 0 0 0 0 0 0000000–000FFFF
0 0 0 0 0 0 0 0 1 0010000–001FFFF
0 0 0 0 0 0 0 1 0 0020000–002FFFF
0 0 0 0 0 0 0 1 1 0030000–003FFFF
0 0 0 0 0 0 1 0 0 0040000–004FFFF
0 0 0 0 0 0 1 0 1 0050000–005FFFF
0 0 0 0 0 0 1 1 0 0060000–006FFFF
0 0 0 0 0 0 1 1 1 0070000–007FFFF
0 0 0 0 0 1 0 0 0 0080000–008FFFF
0 0 0 0 0 1 0 0 1 0090000–009FFFF
000000–007FFF
008000–00FFFF
010000–017FFF
018000–01FFFF
020000–027FFF
028000–02FFFF
030000–037FFF
038000–03FFFF
040000–047FFF
048000–04FFFF
050000–057FFF
058000–05FFFF
060000–067FFF
068000–06FFFF
070000–077FFF
078000–07FFFF
080000–087FFF
088000–08FFFF
090000–097FFF
098000–09FFFF
0A0000–0A7FFF
0A8000–0AFFFF
0B0000–0B7FFF
0B8000–0BFFFF
0C0000–0C7FFF
0C8000–0CFFFF
0D0000–0D7FFF
0D8000–0DFFFF
0E0000–0E7FFF
0E8000–0EFFFF
0F0000–0F7FFF
0F8000–0FFFFF
100000–107FFF
108000–10FFFF
110000–117FFF
118000–11FFFF
120000–127FFF
128000–12FFFF
130000–137FFF
138000–13FFFF
140000–147FFF
148000–14FFFF
150000–157FFF
158000–15FFFF
SA44 0 0 0 1 0 1 1 0 0 02C0000–02CFFFF
SA45 0 0 0 1 0 1 1 0 1 02D0000–02DFFFF
SA46 0 0 0 1 0 1 1 1 0 02E0000–02EFFFF
SA47 0 0 0 1 0 1 1 1 1 02F0000–02FFFFF
SA48 0 0 0 1 1 0 0 0 0 0300000–030FFFF
SA49 0 0 0 1 1 0 0 0 1 0310000–031FFFF
SA50 0 0 0 1 1 0 0 1 0 0320000–032FFFF
SA51 0 0 0 1 1 0 0 1 1 0330000–033FFFF
SA52 0 0 0 1 1 0 1 0 0 0340000–034FFFF
SA53 0 0 0 1 1 0 1 0 1 0350000–035FFFF
SA54 0 0 0 1 1 0 1 1 0 0360000–036FFFF
SA55 0 0 0 1 1 0 1 1 1 0370000–037FFFF
SA56 0 0 0 1 1 1 0 0 0 0380000–038FFFF
SA57 0 0 0 1 1 1 0 0 1 0390000–039FFFF
SA58 0 0 0 1 1 1 0 1 0 03A0000–03AFFFF
SA59 0 0 0 1 1 1 0 1 1 03B0000–03BFFFF
SA60 0 0 0 1 1 1 1 0 0 03C0000–03CFFFF
SA61 0 0 0 1 1 1 1 0 1 03D0000–03DFFFF
SA62 0 0 0 1 1 1 1 1 0 03E0000–03EFFFF
SA63 0 0 0 1 1 1 1 1 1 03F0000–03FFFFF
SA64 0 0 1 0 0 0 0 0 0 0400000–040FFFF
SA65 0 0 1 0 0 0 0 0 1 0410000–041FFFF
SA66 0 0 1 0 0 0 0 1 0 0420000–042FFFF
SA67 0 0 1 0 0 0 0 1 1 0430000–043FFFF
SA68 0 0 1 0 0 0 1 0 0 0440000–044FFFF
SA69 0 0 1 0 0 0 1 0 1 0450000–045FFFF
SA70 0 0 1 0 0 0 1 1 0 0460000–046FFFF
SA71 0 0 1 0 0 0 1 1 1 0470000–047FFFF
SA72 0 0 1 0 0 1 0 0 0 0480000–048FFFF
SA73 0 0 1 0 0 1 0 0 1 0490000–049FFFF
SA74 0 0 1 0 0 1 0 1 0 04A0000–04AFFFF
SA75 0 0 1 0 0 1 0 1 1 04B0000–04BFFFF
SA76 0 0 1 0 0 1 1 0 0 04C0000–04CFFFF
SA77 0 0 1 0 0 1 1 0 1 04D0000–04DFFFF
SA78 0 0 1 0 0 1 1 1 0 04E0000–04EFFFF
SA79 0 0 1 0 0 1 1 1 1 04F0000–04FFFFF
SA80 0 0 1 0 1 0 0 0 0 0500000–050FFFF
SA81 0 0 1 0 1 0 0 0 1 0510000–051FFFF
SA82 0 0 1 0 1 0 0 1 0 0520000–052FFFF
SA83 0 0 1 0 1 0 0 1 1 0530000–053FFFF
SA84 0 0 1 0 1 0 1 0 0 0540000–054FFFF
SA85 0 0 1 0 1 0 1 0 1 0550000–055FFFF
SA86 0 0 1 0 1 0 1 1 0 0560000–056FFFF
SA87 0 0 1 0 1 0 1 1 1 0570000–057FFFF
160000–167FFF
168000–16FFFF
170000–177FFF
178000–17FFFF
180000–187FFF
188000–18FFFF
190000–197FFF
198000–19FFFF
1A0000–1A7FFF
1A8000–1AFFFF
1B0000–1B7FFF
1B8000–1BFFFF
1C0000–1C7FFF
1C8000–1CFFFF
1D0000–1D7FFF
1D8000–1DFFFF
1E0000–1E7FFF
1E8000–1EFFFF
1F0000–1F7FFF
1F8000–1FFFFF
200000–207FFF
208000–20FFFF
210000–217FFF
218000–21FFFF
220000–227FFF
228000–22FFFF
230000–237FFF
238000–23FFFF
240000–247FFF
248000–24FFFF
250000–257FFF
258000–25FFFF
260000–267FFF
268000–26FFFF
270000–277FFF
278000–27FFFF
280000–287FFF
288000–28FFFF
290000–297FFF
298000–29FFFF
2A0000–2A7FFF
2A8000–2AFFFF
2B0000–2B7FFF
2B8000–2BFFFF
SA10 0 0 0 0 0 1 0 1 0 00A0000–00AFFFF
SA11 0 0 0 0 0 1 0 1 1 00B0000–00BFFFF
SA12 0 0 0 0 0 1 1 0 0 00C0000–00CFFFF
SA13 0 0 0 0 0 1 1 0 1 00D0000–00DFFFF
SA14 0 0 0 0 0 1 1 1 0 00E0000–00EFFFF
SA15 0 0 0 0 0 1 1 1 1 00F0000–00FFFFF
SA16 0 0 0 0 1 0 0 0 0 0100000–010FFFF
SA17 0 0 0 0 1 0 0 0 1 0110000–011FFFF
SA18 0 0 0 0 1 0 0 1 0 0120000–012FFFF
SA19 0 0 0 0 1 0 0 1 1 0130000–013FFFF
SA20 0 0 0 0 1 0 1 0 0 0140000–014FFFF
SA21 0 0 0 0 1 0 1 0 1 0150000–015FFFF
SA22 0 0 0 0 1 0 1 1 0 0160000–016FFFF
SA23 0 0 0 0 1 0 1 1 1 0170000–017FFFF
SA24 0 0 0 0 1 1 0 0 0 0180000–018FFFF
SA25 0 0 0 0 1 1 0 0 1 0190000–019FFFF
SA26 0 0 0 0 1 1 0 1 0 01A0000–01AFFFF
SA27 0 0 0 0 1 1 0 1 1 01B0000–01BFFFF
SA28 0 0 0 0 1 1 1 0 0 01C0000–01CFFFF
SA29 0 0 0 0 1 1 1 0 1 01D0000–01DFFFF
SA30 0 0 0 0 1 1 1 1 0 01E0000–01EFFFF
SA31 0 0 0 0 1 1 1 1 1 01F0000–01FFFFF
SA32 0 0 0 1 0 0 0 0 0 0200000–020FFFF
SA33 0 0 0 1 0 0 0 0 1 0210000–021FFFF
SA34 0 0 0 1 0 0 0 1 0 0220000–022FFFF
SA35 0 0 0 1 0 0 0 1 1 0230000–023FFFF
SA36 0 0 0 1 0 0 1 0 0 0240000–024FFFF
SA37 0 0 0 1 0 0 1 0 1 0250000–025FFFF
SA38 0 0 0 1 0 0 1 1 0 0260000–026FFFF
SA39 0 0 0 1 0 0 1 1 1 0270000–027FFFF
SA40 0 0 0 1 0 1 0 0 0 0280000–028FFFF
SA41 0 0 0 1 0 1 0 0 1 0290000–029FFFF
SA42 0 0 0 1 0 1 0 1 0 02A0000–02AFFFF
SA43 0 0 0 1 0 1 0 1 1 02B0000–02BFFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
41
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 2 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA88 0 0 1 0 1 1 0 0 0 0580000–058FFFF
SA89 0 0 1 0 1 1 0 0 1 0590000–059FFFF
SA90 0 0 1 0 1 1 0 1 0 05A0000–05AFFFF
SA91 0 0 1 0 1 1 0 1 1 05B0000–05BFFFF
SA92 0 0 1 0 1 1 1 0 0 05C0000–05CFFFF
SA93 0 0 1 0 1 1 1 0 1 05D0000–05DFFFF
SA94 0 0 1 0 1 1 1 1 0 05E0000–05EFFFF
SA95 0 0 1 0 1 1 1 1 1 05F0000–05FFFFF
SA96 0 0 1 1 0 0 0 0 0 0600000–060FFFF
SA97 0 0 1 1 0 0 0 0 1 0610000–061FFFF
SA98 0 0 1 1 0 0 0 1 0 0620000–062FFFF
SA99 0 0 1 1 0 0 0 1 1 0630000–063FFFF
SA100 0 0 1 1 0 0 1 0 0 0640000–064FFFF
SA101 0 0 1 1 0 0 1 0 1 0650000–065FFFF
SA102 0 0 1 1 0 0 1 1 0 0660000–066FFFF
SA103 0 0 1 1 0 0 1 1 1 0670000–067FFFF
SA104 0 0 1 1 0 1 0 0 0 0680000–068FFFF
SA105 0 0 1 1 0 1 0 0 1 0690000–069FFFF
SA106 0 0 1 1 0 1 0 1 0 06A0000–06AFFFF
SA107 0 0 1 1 0 1 0 1 1 06B0000–06BFFFF
SA108 0 0 1 1 0 1 1 0 0 06C0000–06CFFFF
SA109 0 0 1 1 0 1 1 0 1 06D0000–06DFFFF
SA110 0 0 1 1 0 1 1 1 0 06E0000–06EFFFF
SA111 0 0 1 1 0 1 1 1 1 06F0000–06FFFFF
SA112 0 0 1 1 1 0 0 0 0 0700000–070FFFF
SA113 0 0 1 1 1 0 0 0 1 0710000–071FFFF
SA114 0 0 1 1 1 0 0 1 0 0720000–072FFFF
SA115 0 0 1 1 1 0 0 1 1 0730000–073FFFF
SA116 0 0 1 1 1 0 1 0 0 0740000–074FFFF
SA117 0 0 1 1 1 0 1 0 1 0750000–075FFFF
SA118 0 0 1 1 1 0 1 1 0 0760000–076FFFF
SA119 0 0 1 1 1 0 1 1 1 0770000–077FFFF
SA120 0 0 1 1 1 1 0 0 0 0780000–078FFFF
SA121 0 0 1 1 1 1 0 0 1 0790000–079FFFF
SA122 0 0 1 1 1 1 0 1 0 07A0000–07AFFFF
SA123 0 0 1 1 1 1 0 1 1 07B0000–07BFFFF
SA124 0 0 1 1 1 1 1 0 0 07C0000–07CFFFF
SA125 0 0 1 1 1 1 1 0 1 07D0000–07DFFFF
SA126 0 0 1 1 1 1 1 1 0 07E0000–07EFFFF
SA127 0 0 1 1 1 1 1 1 1 07F0000–07FFFFF
SA128 0 1 0 0 0 0 0 0 0 0800000–080FFFF
SA129 0 1 0 0 0 0 0 0 1 0810000–081FFFF
SA130 0 1 0 0 0 0 0 1 0 0820000–082FFFF
SA131 0 1 0 0 0 0 0 1 1 0830000–083FFFF
SA132 0 1 0 0 0 0 1 0 0 0840000–084FFFF
2C0000–2C7FFF
2C8000–2CFFFF
2D0000–2D7FFF
2D8000–2DFFFF
2E0000–2E7FFF
2E8000–2EFFFF
2F0000–2F7FFF
2F8000–2FFFFF
300000–307FFF
308000–30FFFF
310000–317FFF
318000–31FFFF
320000–327FFF
328000–32FFFF
330000–337FFF
338000–33FFFF
340000–347FFF
348000–34FFFF
350000–357FFF
358000–35FFFF
360000–367FFF
368000–36FFFF
370000–377FFF
378000–37FFFF
380000–387FFF
388000–38FFFF
390000–397FFF
398000–39FFFF
3A0000–3A7FFF
3A8000–3AFFFF
3B0000–3B7FFF
3B8000–3BFFFF
3C0000–3C7FFF
3C8000–3CFFFF
3D0000–3D7FFF
3D8000–3DFFFF
3E0000–3E7FFF
3E8000–3EFFFF
3F0000–3F7FFF
3F8000–3FFFFF
400000–407FFF
408000–40FFFF
410000–417FFF
418000–41FFFF
420000–427FFF
SA133 0 1 0 0 0 0 1 0 1 0850000–085FFFF
SA134 0 1 0 0 0 0 1 1 0 0860000–086FFFF
SA135 0 1 0 0 0 0 1 1 1 0870000–087FFFF
SA136 0 1 0 0 0 1 0 0 0 0880000–088FFFF
SA137 0 1 0 0 0 1 0 0 1 0890000–089FFFF
SA138 0 1 0 0 0 1 0 1 0 08A0000–08AFFFF
SA139 0 1 0 0 0 1 0 1 1 08B0000–08BFFFF
SA140 0 1 0 0 0 1 1 0 0 08C0000–08CFFFF
SA141 0 1 0 0 0 1 1 0 1 08D0000–08DFFFF
SA142 0 1 0 0 0 1 1 1 0 08E0000–08EFFFF
SA143 0 1 0 0 0 1 1 1 1 08F0000–08FFFFF
SA144 0 1 0 0 1 0 0 0 0 0900000–090FFFF
SA145 0 1 0 0 1 0 0 0 1 0910000–091FFFF
SA146 0 1 0 0 1 0 0 1 0 0920000–092FFFF
SA147 0 1 0 0 1 0 0 1 1 0930000–093FFFF
SA148 0 1 0 0 1 0 1 0 0 0940000–094FFFF
SA149 0 1 0 0 1 0 1 0 1 0950000–095FFFF
SA150 0 1 0 0 1 0 1 1 0 0960000–096FFFF
SA151 0 1 0 0 1 0 1 1 1 0970000–097FFFF
SA152 0 1 0 0 1 1 0 0 0 0980000–098FFFF
SA153 0 1 0 0 1 1 0 0 1 0990000–099FFFF
SA154 0 1 0 0 1 1 0 1 0 09A0000–09AFFFF
SA155 0 1 0 0 1 1 0 1 1 09B0000–09BFFFF
SA156 0 1 0 0 1 1 1 0 0 09C0000–09CFFFF
SA157 0 1 0 0 1 1 1 0 1 09D0000–09DFFFF
SA158 0 1 0 0 1 1 1 1 0 09E0000–09EFFFF
SA159 0 1 0 0 1 1 1 1 1 09F0000–09FFFFF
SA160 0 1 0 1 0 0 0 0 0 0A00000–0A0FFFF
SA161 0 1 0 1 0 0 0 0 1 0A10000–0A1FFFF
SA162 0 1 0 1 0 0 0 1 0 0A20000–0A2FFFF
SA163 0 1 0 1 0 0 0 1 1 0A30000–0A3FFFF
SA164 0 1 0 1 0 0 1 0 0 0A40000–0A4FFFF
SA165 0 1 0 1 0 0 1 0 1 0A50000–0A5FFFF
SA166 0 1 0 1 0 0 1 1 0 0A60000–0A6FFFF
SA167 0 1 0 1 0 0 1 1 1 0A70000–0A7FFFF
SA168 0 1 0 1 0 1 0 0 0 0A80000–0A8FFFF
SA169 0 1 0 1 0 1 0 0 1 0A90000–0A9FFFF
SA170 0 1 0 1 0 1 0 1 0 0AA0000–0AAFFFF
SA171 0 1 0 1 0 1 0 1 1 0AB0000–0ABFFFF
SA172 0 1 0 1 0 1 1 0 0 0AC0000–0ACFFFF
SA173 0 1 0 1 0 1 1 0 1 0AD0000–0ADFFFF
SA174 0 1 0 1 0 1 1 1 0 0AE0000–0AEFFFF
SA175 0 1 0 1 0 1 1 1 1 0AF0000–0AFFFFF
SA176 0 1 0 1 1 0 0 0 0 0B00000–0B0FFFF
SA177 0 1 0 1 1 0 0 0 1 0B10000–0B1FFFF
428000–42FFFF
430000–437FFF
438000–43FFFF
440000–447FFF
448000–44FFFF
450000–457FFF
458000–45FFFF
460000–467FFF
468000–46FFFF
470000–477FFF
478000–47FFFF
480000–487FFF
488000–48FFFF
490000–497FFF
498000–49FFFF
4A0000–4A7FFF
4A8000–4AFFFF
4B0000–4B7FFF
4B8000–4BFFFF
4C0000–4C7FFF
4C8000–4CFFFF
4D0000–4D7FFF
4D8000–4DFFFF
4E0000–4E7FFF
4E8000–4EFFFF
4F0000–4F7FFF
4F8000–4FFFFF
500000–507FFF
508000–50FFFF
510000–517FFF
518000–51FFFF
520000–527FFF
528000–52FFFF
530000–537FFF
538000–53FFFF
540000–547FFF
548000–54FFFF
550000–557FFF
558000–55FFFF
560000–567FFF
568000–56FFFF
570000–577FFF
578000–57FFFF
580000–587FFF
588000–58FFFF
42
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 3 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA178 0 1 0 1 1 0 0 1 0 0B20000–0B2FFFF
SA179 0 1 0 1 1 0 0 1 1 0B30000–0B3FFFF
SA180 0 1 0 1 1 0 1 0 0 0B40000–0B4FFFF
SA181 0 1 0 1 1 0 1 0 1 0B50000–0B5FFFF
SA182 0 1 0 1 1 0 1 1 0 0B60000–0B6FFFF
SA183 0 1 0 1 1 0 1 1 1 0B70000–0B7FFFF
SA184 0 1 0 1 1 1 0 0 0 0B80000–0B8FFFF
SA185 0 1 0 1 1 1 0 0 1 0B90000–0B9FFFF
SA186 0 1 0 1 1 1 0 1 0 0BA0000–0BAFFFF
SA187 0 1 0 1 1 1 0 1 1 0BB0000–0BBFFFF
SA188 0 1 0 1 1 1 1 0 0 0BC0000–0BCFFFF
SA189 0 1 0 1 1 1 1 0 1 0BD0000–0BDFFFF
SA190 0 1 0 1 1 1 1 1 0 0BE0000–0BEFFFF
SA191 0 1 0 1 1 1 1 1 1 0BF0000–0BFFFFF
SA192 0 1 1 0 0 0 0 0 0 0C00000–0C0FFFF
SA193 0 1 1 0 0 0 0 0 1 0C10000–0C1FFFF
SA194 0 1 1 0 0 0 0 1 0 0C20000–0C2FFFF
SA195 0 1 1 0 0 0 0 1 1 0C30000–0C3FFFF
SA196 0 1 1 0 0 0 1 0 0 0C40000–0C4FFFF
SA197 0 1 1 0 0 0 1 0 1 0C50000–0C5FFFF
SA198 0 1 1 0 0 0 1 1 0 0C60000–0C6FFFF
SA199 0 1 1 0 0 0 1 1 1 0C70000–0C7FFFF
SA200 0 1 1 0 0 1 0 0 0 0C80000–0C8FFFF
SA201 0 1 1 0 0 1 0 0 1 0C90000–0C9FFFF
SA202 0 1 1 0 0 1 0 1 0 0CA0000–0CAFFFF
SA203 0 1 1 0 0 1 0 1 1 0CB0000–0CBFFFF
SA204 0 1 1 0 0 1 1 0 0 0CC0000–0CCFFFF
SA205 0 1 1 0 0 1 1 0 1 0CD0000–0CDFFFF
SA206 0 1 1 0 0 1 1 1 0 0CE0000–0CEFFFF
SA207 0 1 1 0 0 1 1 1 1 0CF0000–0CFFFFF
SA208 0 1 1 0 1 0 0 0 0 0D00000–0D0FFFF
SA209 0 1 1 0 1 0 0 0 1 0D10000–0D1FFFF
SA210 0 1 1 0 1 0 0 1 0 0D20000–0D2FFFF
SA211 0 1 1 0 1 0 0 1 1 0D30000–0D3FFFF
SA212 0 1 1 0 1 0 1 0 0 0D40000–0D4FFFF
SA213 0 1 1 0 1 0 1 0 1 0D50000–0D5FFFF
SA214 0 1 1 0 1 0 1 1 0 0D60000–0D6FFFF
SA215 0 1 1 0 1 0 1 1 1 0D70000–0D7FFFF
SA216 0 1 1 0 1 1 0 0 0 0D80000–0D8FFFF
SA217 0 1 1 0 1 1 0 0 1 0D90000–0D9FFFF
SA218 0 1 1 0 1 1 0 1 0 0DA0000–0DAFFFF
SA219 0 1 1 0 1 1 0 1 1 0DB0000–0DBFFFF
SA220 0 1 1 0 1 1 1 0 0 0DC0000–0DCFFFF
SA221 0 1 1 0 1 1 1 0 1 0DD0000–0DDFFFF
SA222 0 1 1 0 1 1 1 1 0 0DE0000–0DEFFFF
590000–597FFF
598000–59FFFF
5A0000–5A7FFF
5A8000–5AFFFF
5B0000–5B7FFF
5B8000–5BFFFF
5C0000–5C7FFF
5C8000–5CFFFF
5D0000–5D7FFF
5D8000–5DFFFF
5E0000–5E7FFF
5E8000–5EFFFF
5F0000–5F7FFF
5F8000–5FFFFF
600000–607FFF
608000–60FFFF
610000–617FFF
618000–61FFFF
620000–627FFF
628000–62FFFF
630000–637FFF
638000–63FFFF
640000–647FFF
648000–64FFFF
650000–657FFF
658000–65FFFF
660000–667FFF
668000–66FFFF
670000–677FFF
678000–67FFFF
680000–687FFF
688000–68FFFF
690000–697FFF
698000–69FFFF
6A0000–6A7FFF
6A8000–6AFFFF
6B0000–6B7FFF
6B8000–6BFFFF
6C0000–6C7FFF
6C8000–6CFFFF
6D0000–6D7FFF
6D8000–6DFFFF
6E0000–6E7FFF
6E8000–6EFFFF
6F0000–6F7FFF
SA223 0 1 1 0 1 1 1 1 1 0DF0000–0DFFFFF
SA224 0 1 1 1 0 0 0 0 0 0E00000–0E0FFFF
SA225 0 1 1 1 0 0 0 0 1 0E10000–0E1FFFF
SA226 0 1 1 1 0 0 0 1 0 0E20000–0E2FFFF
SA227 0 1 1 1 0 0 0 1 1 0E30000–0E3FFFF
SA228 0 1 1 1 0 0 1 0 0 0E40000–0E4FFFF
SA229 0 1 1 1 0 0 1 0 1 0E50000–0E5FFFF
SA230 0 1 1 1 0 0 1 1 0 0E60000–0E6FFFF
SA231 0 1 1 1 0 0 1 1 1 0E70000–0E7FFFF
SA232 0 1 1 1 0 1 0 0 0 0E80000–0E8FFFF
SA233 0 1 1 1 0 1 0 0 1 0E90000–0E9FFFF
SA234 0 1 1 1 0 1 0 1 0 0EA0000–0EAFFFF
SA235 0 1 1 1 0 1 0 1 1 0EB0000–0EBFFFF
SA236 0 1 1 1 0 1 1 0 0 0EC0000–0ECFFFF
SA237 0 1 1 1 0 1 1 0 1 0ED0000–0EDFFFF
SA238 0 1 1 1 0 1 1 1 0 0EE0000–0EEFFFF
SA239 0 1 1 1 0 1 1 1 1 0EF0000–0EFFFFF
SA240 0 1 1 1 1 0 0 0 0 0F00000–0F0FFFF
SA241 0 1 1 1 1 0 0 0 1 0F10000–0F1FFFF
SA242 0 1 1 1 1 0 0 1 0 0F20000–0F2FFFF
SA243 0 1 1 1 1 0 0 1 1 0F30000–0F3FFFF
SA244 0 1 1 1 1 0 1 0 0 0F40000–0F4FFFF
SA245 0 1 1 1 1 0 1 0 1 0F50000–0F5FFFF
SA246 0 1 1 1 1 0 1 1 0 0F60000–0F6FFFF
SA247 0 1 1 1 1 0 1 1 1 0F70000–0F7FFFF
SA248 0 1 1 1 1 1 0 0 0 0F80000–0F8FFFF
SA249 0 1 1 1 1 1 0 0 1 0F90000–0F9FFFF
SA250 0 1 1 1 1 1 0 1 0 0FA0000–0FAFFFF
SA251 0 1 1 1 1 1 0 1 1 0FB0000–0FBFFFF
SA252 0 1 1 1 1 1 1 0 0 0FC0000–0FCFFFF
SA253 0 1 1 1 1 1 1 0 1 0FD0000–0FDFFFF
SA254 0 1 1 1 1 1 1 1 0 0FE0000–0FEFFFF
SA255 0 1 1 1 1 1 1 1 1 0FF0000–0FFFFFF
SA256 1 0 0 0 0 0 0 0 0 1000000–100FFFF
SA257 1 0 0 0 0 0 0 0 1 1010000–101FFFF
SA258 1 0 0 0 0 0 0 1 0 1020000–102FFFF
SA259 1 0 0 0 0 0 0 1 1 1030000–103FFFF
SA260 1 0 0 0 0 0 1 0 0 1040000–104FFFF
SA261 1 0 0 0 0 0 1 0 1 1050000–105FFFF
SA262 1 0 0 0 0 0 1 1 0 1060000–106FFFF
SA263 1 0 0 0 0 0 1 1 1 1070000–107FFFF
SA264 1 0 0 0 0 1 0 0 0 1080000–108FFFF
SA265 1 0 0 0 0 1 0 0 1 1090000–109FFFF
SA266 1 0 0 0 0 1 0 1 0 10A0000–10AFFFF
SA267 1 0 0 0 0 1 0 1 1 10B0000–10BFFFF
6F8000–6FFFFF
700000–707FFF
708000–70FFFF
710000–717FFF
718000–71FFFF
720000–727FFF
728000–72FFFF
730000–737FFF
738000–73FFFF
740000–747FFF
748000–74FFFF
750000–757FFF
758000–75FFFF
760000–767FFF
768000–76FFFF
770000–777FFF
778000–77FFFF
780000–787FFF
788000–78FFFF
790000–797FFF
798000–79FFFF
7A0000–7A7FFF
7A8000–7AFFFF
7B0000–7B7FFF
7B8000–7BFFFF
7C0000–7C7FFF
7C8000–7CFFFF
7D0000–7D7FFF
7D8000–7DFFFF
7E0000–7E7FFF
7E8000–7EFFFF
7F0000–7F7FFF
7F8000–7FFFFF
800000–807FFF
808000–80FFFF
810000–817FFF
818000–81FFFF
820000–827FFF
828000–82FFFF
830000–837FFF
838000–83FFFF
840000–847FFF
848000–84FFFF
850000–857FFF
858000–85FFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
43
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 4 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA268 1 0 0 0 0 1 1 0 0 10C0000–10CFFFF
SA269 1 0 0 0 0 1 1 0 1 10D0000–10DFFFF
SA270 1 0 0 0 0 1 1 1 0 10E0000–10EFFFF
SA271 1 0 0 0 0 1 1 1 1 10F0000–10FFFFF
SA272 1 0 0 0 1 0 0 0 0 1100000–110FFFF
SA273 1 0 0 0 1 0 0 0 1 1110000–111FFFF
SA274 1 0 0 0 1 0 0 1 0 1120000–112FFFF
SA275 1 0 0 0 1 0 0 1 1 1130000–113FFFF
SA276 1 0 0 0 1 0 1 0 0 1140000–114FFFF
SA277 1 0 0 0 1 0 1 0 1 1150000–115FFFF
SA278 1 0 0 0 1 0 1 1 0 1160000–116FFFF
SA279 1 0 0 0 1 0 1 1 1 1170000–117FFFF
SA280 1 0 0 0 1 1 0 0 0 1180000–118FFFF
SA281 1 0 0 0 1 1 0 0 1 1190000–119FFFF
SA282 1 0 0 0 1 1 0 1 0 11A0000–11AFFFF
SA283 1 0 0 0 1 1 0 1 1 11B0000–11BFFFF
SA284 1 0 0 0 1 1 1 0 0 11C0000–11CFFFF
SA285 1 0 0 0 1 1 1 0 1 11D0000–11DFFFF
SA286 1 0 0 0 1 1 1 1 0 11E0000–11EFFFF
SA287 1 0 0 0 1 1 1 1 1 11F0000–11FFFFF
SA288 1 0 0 1 0 0 0 0 0 1200000–120FFFF
SA289 1 0 0 1 0 0 0 0 1 1210000–121FFFF
SA290 1 0 0 1 0 0 0 1 0 1220000–122FFFF
SA291 1 0 0 1 0 0 0 1 1 1230000–123FFFF
SA292 1 0 0 1 0 0 1 0 0 1240000–124FFFF
SA293 1 0 0 1 0 0 1 0 1 1250000–125FFFF
SA294 1 0 0 1 0 0 1 1 0 1260000–126FFFF
SA295 1 0 0 1 0 0 1 1 1 1270000–127FFFF
SA296 1 0 0 1 0 1 0 0 0 1280000–128FFFF
SA297 1 0 0 1 0 1 0 0 1 1290000–129FFFF
SA298 1 0 0 1 0 1 0 1 0 12A0000–12AFFFF
SA299 1 0 0 1 0 1 0 1 1 12B0000–12BFFFF
SA300 1 0 0 1 0 1 1 0 0 12C0000–12CFFFF
SA301 1 0 0 1 0 1 1 0 1 12D0000–12DFFFF
SA302 1 0 0 1 0 1 1 1 0 12E0000–12EFFFF
SA303 1 0 0 1 0 1 1 1 1 12F0000–12FFFFF
SA304 1 0 0 1 1 0 0 0 0 1300000–130FFFF
SA305 1 0 0 1 1 0 0 0 1 1310000–131FFFF
SA306 1 0 0 1 1 0 0 1 0 1320000–132FFFF
SA307 1 0 0 1 1 0 0 1 1 1330000–133FFFF
SA308 1 0 0 1 1 0 1 0 0 1340000–134FFFF
SA309 1 0 0 1 1 0 1 0 1 1350000–135FFFF
SA310 1 0 0 1 1 0 1 1 0 1360000–136FFFF
SA311 1 0 0 1 1 0 1 1 1 1370000–137FFFF
SA312 1 0 0 1 1 1 0 0 0 1380000–138FFFF
860000–867FFF
868000–86FFFF
870000–877FFF
878000–87FFFF
880000–887FFF
888000–88FFFF
890000–897FFF
898000–89FFFF
8A0000–8A7FFF
8A8000–8AFFFF
8B0000–8B7FFF
8B8000–8BFFFF
8C0000–8C7FFF
8C8000–8CFFFF
8D0000–8D7FFF
8D8000–8DFFFF
8E0000–8E7FFF
8E8000–8EFFFF
8F0000–8F7FFF
8F8000–8FFFFF
900000–907FFF
908000–90FFFF
910000–917FFF
918000–91FFFF
920000–927FFF
928000–92FFFF
930000–937FFF
938000–93FFFF
940000–947FFF
948000–94FFFF
950000–957FFF
958000–95FFFF
960000–967FFF
968000–96FFFF
970000–977FFF
978000–97FFFF
980000–987FFF
988000–98FFFF
990000–997FFF
998000–99FFFF
9A0000–9A7FFF
9A8000–9AFFFF
9B0000–9B7FFF
9B8000–9BFFFF
9C0000–9C7FFF
SA313 1 0 0 1 1 1 0 0 1 1390000–139FFFF
SA314 1 0 0 1 1 1 0 1 0 13A0000–13AFFFF
SA315 1 0 0 1 1 1 0 1 1 13B0000–13BFFFF
SA316 1 0 0 1 1 1 1 0 0 13C0000–13CFFFF
SA317 1 0 0 1 1 1 1 0 1 13D0000–13DFFFF
SA318 1 0 0 1 1 1 1 1 0 13E0000–13EFFFF
SA319 1 0 0 1 1 1 1 1 1 13F0000–13FFFFF
SA320 1 0 1 0 0 0 0 0 0 1400000–140FFFF
SA321 1 0 1 0 0 0 0 0 1 1410000–141FFFF
SA322 1 0 1 0 0 0 0 1 0 1420000–142FFFF
SA323 1 0 1 0 0 0 0 1 1 1430000–143FFFF
SA324 1 0 1 0 0 0 1 0 0 1440000–144FFFF
SA325 1 0 1 0 0 0 1 0 1 1450000–145FFFF
SA326 1 0 1 0 0 0 1 1 0 1460000–146FFFF
SA327 1 0 1 0 0 0 1 1 1 1470000–147FFFF
SA328 1 0 1 0 0 1 0 0 0 1480000–148FFFF
SA329 1 0 1 0 0 1 0 0 1 1490000–149FFFF
SA330 1 0 1 0 0 1 0 1 0 14A0000–14AFFFF
SA331 1 0 1 0 0 1 0 1 1 14B0000–14BFFFF
SA332 1 0 1 0 0 1 1 0 0 14C0000–14CFFFF
SA333 1 0 1 0 0 1 1 0 1 14D0000–14DFFFF
SA334 1 0 1 0 0 1 1 1 0 14E0000–14EFFFF
SA335 1 0 1 0 0 1 1 1 1 14F0000–14FFFFF
SA336 1 0 1 0 1 0 0 0 0 1500000–150FFFF
SA337 1 0 1 0 1 0 0 0 1 1510000–151FFFF
SA338 1 0 1 0 1 0 0 1 0 1520000–152FFFF
SA339 1 0 1 0 1 0 0 1 1 1530000–153FFFF
SA340 1 0 1 0 1 0 1 0 0 1540000–154FFFF
SA341 1 0 1 0 1 0 1 0 1 1550000–155FFFF
SA342 1 0 1 0 1 0 1 1 0 1560000–156FFFF
SA343 1 0 1 0 1 0 1 1 1 1570000–157FFFF
SA344 1 0 1 0 1 1 0 0 0 1580000–158FFFF
SA345 1 0 1 0 1 1 0 0 1 1590000–159FFFF
SA346 1 0 1 0 1 1 0 1 0 15A0000–15AFFFF
SA347 1 0 1 0 1 1 0 1 1 15B0000–15BFFFF
SA348 1 0 1 0 1 1 1 0 0 15C0000–15CFFFF
SA349 1 0 1 0 1 1 1 0 1 15D0000–15DFFFF
SA350 1 0 1 0 1 1 1 1 0 15E0000–15EFFFF
SA351 1 0 1 0 1 1 1 1 1 15F0000–15FFFFF
SA352 1 0 1 1 0 0 0 0 0 1600000–160FFFF
SA353 1 0 1 1 0 0 0 0 1 1610000–161FFFF
SA354 1 0 1 1 0 0 0 1 0 1620000–162FFFF
SA355 1 0 1 1 0 0 0 1 1 1630000–163FFFF
SA356 1 0 1 1 0 0 1 0 0 1640000–164FFFF
SA357 1 0 1 1 0 0 1 0 1 1650000–165FFFF
9C8000–9CFFFF
9D0000–9D7FFF
9D8000–9DFFFF
9E0000–9E7FFF
9E8000–9EFFFF
9F0000–9F7FFF
9F8000–9FFFFF
A00000–A07FFF
A08000–A0FFFF
A10000–A17FFF
A18000–A1FFFF
A20000–A27FFF
A28000–A2FFFF
A30000–A37FFF
A38000–A3FFFF
A40000–A47FFF
A48000–A4FFFF
A50000–A57FFF
A58000–A5FFFF
A60000–A67FFF
A68000–A6FFFF
A70000–A77FFF
A78000–A7FFFF
A80000–A87FFF
A88000–A8FFFF
A90000–A97FFF
A98000–A9FFFF
AA0000–AA7FFF
AA8000–AAFFFF
AB0000–AB7FFF
AB8000–ABFFFF
AC0000–AC7FFF
AC8000–ACFFFF
AD0000–AD7FFF
AD8000–ADFFFF
AE0000–AE7FFF
AE8000–AEFFFF
AF0000–AF7FFF
AF8000–AFFFFF
B00000–B07FFF
B08000–B0FFFF
B10000–B17FFF
B18000–B1FFFF
B20000–B27FFF
B28000–B2FFFF
44
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 5 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA358 1 0 1 1 0 0 1 1 0 1660000–166FFFF
SA359 1 0 1 1 0 0 1 1 1 1670000–167FFFF
SA360 1 0 1 1 0 1 0 0 0 1680000–168FFFF
SA361 1 0 1 1 0 1 0 0 1 1690000–169FFFF
SA362 1 0 1 1 0 1 0 1 0 16A0000–16AFFFF
SA363 1 0 1 1 0 1 0 1 1 16B0000–16BFFFF
SA364 1 0 1 1 0 1 1 0 0 16C0000–16CFFFF
SA365 1 0 1 1 0 1 1 0 1 16D0000–16DFFFF
SA366 1 0 1 1 0 1 1 1 0 16E0000–16EFFFF
SA367 1 0 1 1 0 1 1 1 1 16F0000–16FFFFF
SA368 1 0 1 1 1 0 0 0 0 1700000–170FFFF
SA369 1 0 1 1 1 0 0 0 1 1710000–171FFFF
SA370 1 0 1 1 1 0 0 1 0 1720000–172FFFF
SA371 1 0 1 1 1 0 0 1 1 1730000–173FFFF
SA372 1 0 1 1 1 0 1 0 0 1740000–174FFFF
SA373 1 0 1 1 1 0 1 0 1 1750000–175FFFF
SA374 1 0 1 1 1 0 1 1 0 1760000–176FFFF
SA375 1 0 1 1 1 0 1 1 1 1770000–177FFFF
SA376 1 0 1 1 1 1 0 0 0 1780000–178FFFF
SA377 1 0 1 1 1 1 0 0 1 1790000–179FFFF
SA378 1 0 1 1 1 1 0 1 0 17A0000–17AFFFF
SA379 1 0 1 1 1 1 0 1 1 17B0000–17BFFFF
SA380 1 0 1 1 1 1 1 0 0 17C0000–17CFFFF
SA381 1 0 1 1 1 1 1 0 1 17D0000–17DFFFF
SA382 1 0 1 1 1 1 1 1 0 17E0000–17EFFFF
SA383 1 0 1 1 1 1 1 1 1 17F0000–17FFFFF
SA384 1 1 0 0 0 0 0 0 0 1800000–180FFFF
SA385 1 1 0 0 0 0 0 0 1 1810000–181FFFF
SA386 1 1 0 0 0 0 0 1 0 1820000–182FFFF
SA387 1 1 0 0 0 0 0 1 1 1830000–183FFFF
SA388 1 1 0 0 0 0 1 0 0 1840000–184FFFF
SA389 1 1 0 0 0 0 1 0 1 1850000–185FFFF
SA390 1 1 0 0 0 0 1 1 0 1860000–186FFFF
SA391 1 1 0 0 0 0 1 1 1 1870000–187FFFF
SA392 1 1 0 0 0 1 0 0 0 1880000–188FFFF
SA393 1 1 0 0 0 1 0 0 1 1890000–189FFFF
SA394 1 1 0 0 0 1 0 1 0 18A0000–18AFFFF
SA395 1 1 0 0 0 1 0 1 1 18B0000–18BFFFF
SA396 1 1 0 0 0 1 1 0 0 18C0000–18CFFFF
SA397 1 1 0 0 0 1 1 0 1 18D0000–18DFFFF
SA398 1 1 0 0 0 1 1 1 0 18E0000–18EFFFF
SA399 1 1 0 0 0 1 1 1 1 18F0000–18FFFFF
SA400 1 1 0 0 1 0 0 0 0 1900000–190FFFF
SA401 1 1 0 0 1 0 0 0 1 1910000–191FFFF
SA402 1 1 0 0 1 0 0 1 0 1920000–192FFFF
B30000–B37FFF
B38000–B3FFFF
B40000–B47FFF
B48000–B4FFFF
B50000–B57FFF
B58000–B5FFFF
B60000–B67FFF
B68000–B6FFFF
B70000–B77FFF
B78000–B7FFFF
B80000–B87FFF
B88000–B8FFFF
B90000–B97FFF
B98000–B9FFFF
BA0000–BA7FFF
BA8000–BAFFFF
BB0000–BB7FFF
BB8000–BBFFFF
BC0000–BC7FFF
BC8000–BCFFFF
BD0000–BD7FFF
BD8000–BDFFFF
BE0000–BE7FFF
BE8000–BEFFFF
BF0000–BF7FFF
BF8000–BFFFFF
C00000–C07FFF
C08000–C0FFFF
C10000–C17FFF
C18000–C1FFFF
C20000–C27FFF
C28000–C2FFFF
C30000–C37FFF
C38000–C3FFFF
C40000–C47FFF
C48000–C4FFFF
C50000–C57FFF
C58000–C5FFFF
C60000–C67FFF
C68000–C6FFFF
C70000–C77FFF
C78000–C7FFFF
C80000–C87FFF
C88000–C8FFFF
C90000–C97FFF
SA403 1 1 0 0 1 0 0 1 1 1930000–193FFFF
SA404 1 1 0 0 1 0 1 0 0 1940000–194FFFF
SA405 1 1 0 0 1 0 1 0 1 1950000–195FFFF
SA406 1 1 0 0 1 0 1 1 0 1960000–196FFFF
SA407 1 1 0 0 1 0 1 1 1 1970000–197FFFF
SA408 1 1 0 0 1 1 0 0 0 1980000–198FFFF
SA409 1 1 0 0 1 1 0 0 1 1990000–199FFFF
SA410 1 1 0 0 1 1 0 1 0 19A0000–19AFFFF
SA411 1 1 0 0 1 1 0 1 1 19B0000–19BFFFF
SA412 1 1 0 0 1 1 1 0 0 19C0000–19CFFFF
SA413 1 1 0 0 1 1 1 0 1 19D0000–19DFFFF
SA414 1 1 0 0 1 1 1 1 0 19E0000–19EFFFF
SA415 1 1 0 0 1 1 1 1 1 19F0000–19FFFFF
SA416 1 1 0 1 0 0 0 0 0 1A00000–1A0FFFF
SA417 1 1 0 1 0 0 0 0 1 1A10000–1A1FFFF
SA418 1 1 0 1 0 0 0 1 0 1A20000–1A2FFFF
SA419 1 1 0 1 0 0 0 1 1 1A30000–1A3FFFF
SA420 1 1 0 1 0 0 1 0 0 1A40000–1A4FFFF
SA421 1 1 0 1 0 0 1 0 1 1A50000–1A5FFFF
SA422 1 1 0 1 0 0 1 1 0 1A60000–1A6FFFF
SA423 1 1 0 1 0 0 1 1 1 1A70000–1A7FFFF
SA424 1 1 0 1 0 1 0 0 0 1A80000–1A8FFFF
SA425 1 1 0 1 0 1 0 0 1 1A90000–1A9FFFF
SA426 1 1 0 1 0 1 0 1 0 1AA0000–1AAFFFF
SA427 1 1 0 1 0 1 0 1 1 1AB0000–1ABFFFF
SA428 1 1 0 1 0 1 1 0 0 1AC0000–1ACFFFF
SA429 1 1 0 1 0 1 1 0 1 1AD0000–1ADFFFF
SA430 1 1 0 1 0 1 1 1 0 1AE0000–1AEFFFF
SA431 1 1 0 1 0 1 1 1 1 1AF0000–1AFFFFF
SA432 1 1 0 1 1 0 0 0 0 1B00000–1B0FFFF
SA433 1 1 0 1 1 0 0 0 1 1B10000–1B1FFFF
SA434 1 1 0 1 1 0 0 1 0 1B20000–1B2FFFF
SA435 1 1 0 1 1 0 0 1 1 1B30000–1B3FFFF
SA436 1 1 0 1 1 0 1 0 0 1B40000–1B4FFFF
SA437 1 1 0 1 1 0 1 0 1 1B50000–1B5FFFF
SA438 1 1 0 1 1 0 1 1 0 1B60000–1B6FFFF
SA439 1 1 0 1 1 0 1 1 1 1B70000–1B7FFFF
SA440 1 1 0 1 1 1 0 0 0 1B80000–1B8FFFF
SA441 1 1 0 1 1 1 0 0 1 1B90000–1B9FFFF
SA442 1 1 0 1 1 1 0 1 0 1BA0000–1BAFFFF
SA443 1 1 0 1 1 1 0 1 1 1BB0000–1BBFFFF
SA444 1 1 0 1 1 1 1 0 0 1BC0000–1BCFFFF
SA445 1 1 0 1 1 1 1 0 1 1BD0000–1BDFFFF
SA446 1 1 0 1 1 1 1 1 0 1BE0000–1BEFFFF
SA447 1 1 0 1 1 1 1 1 1 1BF0000–1BFFFFF
C98000–C9FFFF
CA0000–CA7FFF
CA8000–CAFFFF
CB0000–CB7FFF
CB8000–CBFFFF
CC0000–CC7FFF
CC8000–CCFFFF
CD0000–CD7FFF
CD8000–CDFFFF
CE0000–CE7FFF
CE8000–CEFFFF
CF0000–CF7FFF
CF8000–CFFFFF
D00000–D07FFF
D08000–D0FFFF
D10000–D17FFF
D18000–D1FFFF
D20000–D27FFF
D28000–D2FFFF
D30000–D37FFF
D38000–D3FFFF
D40000–D47FFF
D48000–D4FFFF
D50000–D57FFF
D58000–D5FFFF
D60000–D67FFF
D68000–D6FFFF
D70000–D77FFF
D78000–D7FFFF
D80000–D87FFF
D88000–D8FFFF
D90000–D97FFF
D98000–D9FFFF
DA0000–DA7FFF
DA8000–DAFFFF
DB0000–DB7FFF
DB8000–DBFFFF
DC0000–DC7FFF
DC8000–DCFFFF
DD0000–DD7FFF
DD8000–DDFFFF
DE0000–DE7FFF
DE8000–DEFFFF
DF0000–DF7FFF
DF8000–DFFFFF
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
45
D a t a S h e e t
Table 16. S29GL256M Sector Address Table (Sheet 6 of 6)
8-bit
Address
Range
16-bit
Address
Range
8-bit
Address
Range
16-bit
Address
Range
A23–A15
A23–A15
SA448 1 1 1 0 0 0 0 0 0 1C00000–1C0FFFF
SA449 1 1 1 0 0 0 0 0 1 1C10000–1C1FFFF
SA450 1 1 1 0 0 0 0 1 0 1C20000–1C2FFFF
SA451 1 1 1 0 0 0 0 1 1 1C30000–1C3FFFF
SA452 1 1 1 0 0 0 1 0 0 1C40000–1C4FFFF
SA453 1 1 1 0 0 0 1 0 1 1C50000–1C5FFFF
SA454 1 1 1 0 0 0 1 1 0 1C60000–1C6FFFF
SA455 1 1 1 0 0 0 1 1 1 1C70000–1C7FFFF
SA456 1 1 1 0 0 1 0 0 0 1C80000–1C8FFFF
SA457 1 1 1 0 0 1 0 0 1 1C90000–1C9FFFF
SA458 1 1 1 0 0 1 0 1 0 1CA0000–1CAFFFF
SA459 1 1 1 0 0 1 0 1 1 1CB0000–1CBFFFF
SA460 1 1 1 0 0 1 1 0 0 1CC0000–1CCFFFF
SA461 1 1 1 0 0 1 1 0 1 1CD0000–1CDFFFF
SA462 1 1 1 0 0 1 1 1 0 1CE0000–1CEFFFF
SA463 1 1 1 0 0 1 1 1 1 1CF0000–1CFFFFF
SA464 1 1 1 0 1 0 0 0 0 1D00000–1D0FFFF
SA465 1 1 1 0 1 0 0 0 1 1D10000–1D1FFFF
SA466 1 1 1 0 1 0 0 1 0 1D20000–1D2FFFF
SA467 1 1 1 0 1 0 0 1 1 1D30000–1D3FFFF
SA468 1 1 1 0 1 0 1 0 0 1D40000–1D4FFFF
SA469 1 1 1 0 1 0 1 0 1 1D50000–1D5FFFF
SA470 1 1 1 0 1 0 1 1 0 1D60000–1D6FFFF
SA471 1 1 1 0 1 0 1 1 1 1D70000–1D7FFFF
SA472 1 1 1 0 1 1 0 0 0 1D80000–1D8FFFF
SA473 1 1 1 0 1 1 0 0 1 1D90000–1D9FFFF
SA474 1 1 1 0 1 1 0 1 0 1DA0000–1DAFFFF
SA475 1 1 1 0 1 1 0 1 1 1DB0000–1DBFFFF
SA476 1 1 1 0 1 1 1 0 0 1DC0000–1DCFFFF
SA477 1 1 1 0 1 1 1 0 1 1DD0000–1DDFFFF
SA478 1 1 1 0 1 1 1 1 0 1DE0000–1DEFFFF
SA479 1 1 1 0 1 1 1 1 1 1DF0000–1DFFFFF
E00000–E07FFF
E08000–E0FFFF
E10000–E17FFF
E18000–E1FFFF
E20000–E27FFF
E28000–E2FFFF
E30000–E37FFF
E38000–E3FFFF
E40000–E47FFF
E48000–E4FFFF
E50000–E57FFF
E58000–E5FFFF
E60000–E67FFF
E68000–E6FFFF
E70000–E77FFF
E78000–E7FFFF
E80000–E87FFF
E88000–E8FFFF
E90000–E97FFF
E98000–E9FFFF
EA0000–EA7FFF
EA8000–EAFFFF
EB0000–EB7FFF
EB8000–EBFFFF
EC0000–EC7FFF
EC8000–ECFFFF
ED0000–ED7FFF
ED8000–EDFFFF
EE0000–EE7FFF
EE8000–EEFFFF
EF0000–EF7FFF
EF8000–EFFFFF
SA480 1 1 1 1 0 0 0 0 0 1E00000–1E0FFFF
SA481 1 1 1 1 0 0 0 0 1 1E10000–1E1FFFF
SA482 1 1 1 1 0 0 0 1 0 1E20000–1E2FFFF
SA483 1 1 1 1 0 0 0 1 1 1E30000–1E3FFFF
SA484 1 1 1 1 0 0 1 0 0 1E40000–1E4FFFF
SA485 1 1 1 1 0 0 1 0 1 1E50000–1E5FFFF
SA486 1 1 1 1 0 0 1 1 0 1E60000–1E6FFFF
SA487 1 1 1 1 0 0 1 1 1 1E70000–1E7FFFF
SA488 1 1 1 1 0 1 0 0 0 1E80000–1E8FFFF
SA489 1 1 1 1 0 1 0 0 1 1E90000–1E9FFFF
SA490 1 1 1 1 0 1 0 1 0 1EA0000–1EAFFFF
SA491 1 1 1 1 0 1 0 1 1 1EB0000–1EBFFFF
SA492 1 1 1 1 0 1 1 0 0 1EC0000–1ECFFFF
SA493 1 1 1 1 0 1 1 0 1 1ED0000–1EDFFFF
SA494 1 1 1 1 0 1 1 1 0 1EE0000–1EEFFFF
SA495 1 1 1 1 0 1 1 1 1 1EF0000–1EFFFFF
SA496 1 1 1 1 1 0 0 0 0 1F00000–1F0FFFF
SA497 1 1 1 1 1 0 0 0 1 1F10000–1F1FFFF
SA498 1 1 1 1 1 0 0 1 0 1F20000–1F2FFFF
SA499 1 1 1 1 1 0 0 1 1 1F30000–1F3FFFF
SA500 1 1 1 1 1 0 1 0 0 1F40000–1F4FFFF
SA501 1 1 1 1 1 0 1 0 1 1F50000–1F5FFFF
SA502 1 1 1 1 1 0 1 1 0 1F60000–1F6FFFF
SA503 1 1 1 1 1 0 1 1 1 1F70000–1F7FFFF
SA504 1 1 1 1 1 1 0 0 0 1F80000–1F8FFFF
SA505 1 1 1 1 1 1 0 0 1 1F90000–1F9FFFF
SA506 1 1 1 1 1 1 0 1 0 1FA0000–1FAFFFF
SA507 1 1 1 1 1 1 0 1 1 1FB0000–1FBFFFF
SA508 1 1 1 1 1 1 1 0 0 1FC0000–1FCFFFF
SA509 1 1 1 1 1 1 1 0 1 1FD0000–1FDFFFF
SA510 1 1 1 1 1 1 1 1 0 1FE0000–1FEFFFF
SA511 1 1 1 1 1 1 1 1 1 1FF0000–1FFFFFF
F00000–F07FFF
F08000–F0FFFF
F10000–F17FFF
F18000–F1FFFF
F20000–F27FFF
F28000–F2FFFF
F30000–F37FFF
F38000–F3FFFF
F40000–F47FFF
F48000–F4FFFF
F50000–F57FFF
F58000–F5FFFF
F60000–F67FFF
F68000–F6FFFF
F70000–F77FFF
F78000–F7FFFF
F80000–F87FFF
F88000–F8FFFF
F90000–F97FFF
F98000–F9FFFF
FA0000–FA7FFF
FA8000–FAFFFF
FB0000–FB7FFF
FB8000–FBFFFF
FC0000–FC7FFF
FC8000–FCFFFF
FD0000–FD7FFF
FD8000–FDFFFF
FE0000–FE7FFF
FE8000–FEFFFF
FF0000–FF7FFF
FF8000–FFFFFF
Note: All sectors are 64 Kbytes or 32 Kwords in size.
46
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector group protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for pro-
gramming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through
the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-
dress pins A6, A3, A2, A1, and A0 must be as shown in Table 17. In addition, when verifying sector
protection, the sector address must appear on the appropriate highest order address bits (see
Table 6 through Table 16). Table 17 shows the remaining address bits that are don’t care. When
all necessary bits are set as required, the programming equipment may then read the corre-
sponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via
the command register, as shown in Table 34 and Table 35. This method does not require VID. See
Autoselect Command Sequence for more information.
Table 17. Autoselect Codes, (High Voltage Method)
DQ7 to DQ0
A1
4
A
8
A
5
A
3
DQ8 to DQ15
A22 to
A15
A
6
A
1
A
0
Model Number
Description
CE# OE# WE#
to A9 to
to to
A1
0
A
7
A
4
A
2
BYTE#
BYTE#
= VIL
R1, R2,
R8, R9
R5, R6,
R7
R0
R3,R4
= VIH
Manufacturer ID:
V
D
01
h
I
L
L
L
L
H
H
X
X
X
X
L
L
X
L
L
L
00
X
01h
01h
01h
Spansion Products
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
12h
V
D
H
H
I
X
X
X
Cycle 3
H
H
H
22
X
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
12h
V
D
H
H
I
L
L
L
L
H
H
X
X
X
X
X
X
L
L
X
X
Cycle 3
Cycle 1
Cycle 2
H
L
H
L
H
H
L
22
22
22
X
X
X
00h
7Eh
0Ch
7E
h
7Eh
10h
7Eh
13h
13
h
H
H
V
D
I
00h (-R4,
bottom boot)
01h (-R3,
00
h
Cycle 3
H
H
H
22
X
01h
01h
top boot)
7E
h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
1Dh
7Eh
1Ah
7Eh
1Ah
1C
h
H
H
V
D
I
L
L
H
X
X
X
L
X
00h (-R4,
bottom boot)
01h (-R3,
00
h
Cycle 3
H
L
H
H
H
L
22
X
X
X
00h
top boot)
Sector Group
Protection
Verification
V
D
01h (protected),
00h (unprotected)
I
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects highest
address sector
V
D
98h (factory locked),
I
L
L
H
H
H
H
X
X
X
X
18h (not factory locked)
Secured Silicon
Sector Indicator
Bit (DQ7), WP#
protects lowest
address sector
V
D
88h (factory locked),
I
L
L
H
X
X
X
L
X
08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
47
D a t a S h e e t
Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any
sector group. In this device, a sector group consists of four adjacent sectors that are protected
or unprotected at the same time (see Table 4). The hardware sector group unprotection feature
re-enables both program and erase operations in previously protected sector groups. Sector
group protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented ei-
ther in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24
shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector
group unprotect, all unprotected sector groups must first be protected prior to the first sector
group unprotect write cycle.
The device is shipped with all sector groups unprotected. Spansion offers the option of program-
ming and protecting sector groups at its factory prior to shipping the device through Spansion
Programming Service. Contact a Spansion representative for details.
It is possible to determine whether a sector group is protected or unprotected. See Autoselect
Mode for details.
Table 18. S29GL032M (Model R0) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
A22–A18
00000
00001
00010
00011
Sector Group
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
A22–A18
00100
00101
00110
00111
Sector Group
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
A22–A18
01000
01001
01010
01011
Sector Group
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
A22–A18
01100
01101
01110
01111
SA4–SA7
SA8–SA11
SA12–SA15
Note: All sector groups are 256 Kwords in size.
Table 19. S29GL032M (Models R1, R2) Sector Group Protection/Unprotection Addresses
Sector Group
SA0
A20–A15
000000
000001
000010
000011
0001xx
0010xx
Sector Group
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
A20–A15
0011xx
0100xx
0101xx
0110xx
0111xx
1000xx
Sector Group
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
A20–A15
1001xx
1010xx
1011xx
1100xx
1101xx
Sector Group
SA56–SA59
SA60
A20–A15
1110xx
111100
111101
111110
111111
SA1
SA2
SA61
SA3
SA62
SA4–SA7
SA8–SA11
SA63
Table 20. S29GL032M (Model R3) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A20–A12
Sector
A20–A12
Sector
A20–A12
SA0-SA3
SA4-SA7
SA8-SA11
0000XXXXXh
0001XXXXXh
0010XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA36–SA39 1001XXXXXh
SA40–SA43 1010XXXXXh
SA44–SA47 1011XXXXXh
SA48–SA51 1100XXXXXh
SA52-SA55 1101XXXXXh
SA56-SA59 1110XXXXXh
111100XXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000h
111111001h
111111010h
111111011h
111111100h
111111101h
111111110h
111111111h
8
8
8
8
8
8
8
8
SA12-SA15 0011XXXXXh
SA16-SA19 0100XXXXXh
SA20-SA23 0101XXXXXh
SA24-SA27 0110XXXXXh
SA28-SA31 0111XXXXXh
SA32–SA35 1000XXXXXh
SA60-SA62 111101XXXh
111110XXXh
192 (3x64)
48
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 21. S29GL032M (Model R4) Sector Group Protection/Unprotection Address Table
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A20–A12
Sector
A20–A12
Sector
A20–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
000000000h
000000001h
000000010h
000000011h
000000100h
000000101h
000000110h
000000111h
8
8
8
8
8
8
8
8
000001XXXh
000010XXXh
000011XXXh
SA35-SA38 0111XXXXXh
SA39-SA42 1000XXXXXh
SA43-SA46 1001XXXXXh
SA47-SA50 1010XXXXXh
SA51-SA54 1011XXXXXh
SA55–SA58 1100XXXXXh
SA59–SA62 1101XXXXXh
SA63–SA66 1110XXXXXh
SA67–SA70 1111XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA8–SA10
192 (3x64)
SA11–SA14 0001XXXXXh
SA15–SA18 0010XXXXXh
SA19–SA22 0011XXXXXh
SA23–SA26 0100XXXXXh
SA27-SA30 0101XXXXXh
SA31-SA34 0110XXXXXh
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
l
Table 22. S29GL064M (Model 00) Sector Group Protection/Unprotection Address Table
Sector Group
A22–A18
00000
00001
00010
00011
00100
00101
00110
01000
Sector Group
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
A22–A18
01001
01010
01011
01100
01101
01110
01111
10000
Sector Group
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA88–SA91
SA92–SA95
SA96–SA99
A22–A18
10001
10010
10011
10100
10110
10111
11000
Sector Group
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
A22–A18
11001
11010
11011
11100
11101
11110
11111
SA0–SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA32–SA35
Note: All sector groups are 256 Kwords in size.
Table 23. S29GL064M (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses
Sector Group
SA0
A21–A15
0000000
0000001
0000010
0000011
00001xx
00010xx
00011xx
00100xx
00101xx
00110xx
Sector Group
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA28–SA31
A21–A15
00111xx
01000xx
01001xx
01010xx
01011xx
01100xx
01101xx
01110xx
01111xx
00111xx
Sector Group
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
A21–A15
10000xx
10001xx
10010xx
10011xx
10100xx
10101xx
10110xx
10111xx
11000xx
11001xx
Sector Group
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124
A21–A15
11010xx
11011xx
11100xx
11101xx
11110xx
1111100
1111101
1111110
1111111
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA125
SA126
SA127
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
49
D a t a S h e e t
Table 24. S29GL064M (Model R3) Sector Group Protection/Unprotection Address Table
Sector/ Sector
Block Size
Sector/ Sector
Block Size
Sector/ Sector
Block Size
Sector
A21–A12
Sector
A21–A12
Sector
A21–A12
(Kbytes)
(Kbytes)
(Kbytes)
SA0-SA3 00000XXXXX
SA4-SA7 00001XXXXX
SA8-SA11 00010XXXXX
SA12-SA15 00011XXXXX
SA16-SA19 00100XXXXX
SA20-SA23 00101XXXXX
SA24-SA27 00110XXXXX
SA28-SA31 00111XXXXX
SA32-SA35 01000XXXXX
SA36-SA39 01001XXXXX
SA40-SA43 01010XXXXX
SA44-SA47 01011XXXXX
SA48-SA51 01100XXXXX
SA52-SA55 01101XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA56-SA59
SA60-SA63
SA64-SA67
SA68-SA71
SA72-SA75
SA76-SA79
SA80-SA83
SA84-SA87
SA88-SA91
SA92-SA95
SA96-SA99
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA112-SA115 11100XXXXX
SA116-SA119 11101XXXXX
SA120-SA123 11110XXXXX
1111100XXX
256 (4x64)
256 (4x64)
256 (4x64)
SA124-SA126 1111101XXX
1111110XXX
192 (3x64)
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8
8
8
8
8
8
8
8
SA100-SA103 11001XXXXX
SA104-SA107 11010XXXXX
SA108-SA111 11011XXXXX
Table 25. S29GL064M (Model R4) Sector Group Protection/Unprotection Addresses
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector/Sector
Block Size
(Kbytes)
Sector
A21–A12
Sector
A21–A12
Sector
A21–A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001XXX
8
8
8
8
8
8
8
8
SA23–SA26 00100XXXXX
SA27-SA30 00101XXXXX
SA31-SA34 00110XXXXX
SA35-SA38 00111XXXXX
SA39-SA42 01000XXXXX
SA43-SA46 01001XXXXX
SA47-SA50 01010XXXXX
SA51-SA54 01011XXXXX
SA55–SA58 01100XXXXX
SA59–SA62 01101XXXXX
SA63–SA66 01110XXXXX
SA67–SA70 01111XXXXX
SA71–SA74 10000XXXXX
SA75–SA78 10001XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA79–SA82 10010XXXXX
SA83–SA86 10011XXXXX
SA87–SA90 10100XXXXX
SA91–SA94 10101XXXXX
SA95–SA98 10110XXXXX
SA99–SA102 10111XXXXX
SA103–SA106 11000XXXXX
SA107–SA110 11001XXXXX
SA111–SA114 11010XXXXX
SA115–SA118 11011XXXXX
SA119–SA122 11100XXXXX
SA123–SA126 11101XXXXX
SA127–SA130 11110XXXXX
SA131–SA134 11111XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
256 (4x64)
SA8–SA10 0000010XXX
0000011XXX
192 (3x64)
SA11–SA14 00001XXXXX
SA15–SA18 00010XXXXX
SA19–SA22 00011XXXXX
256 (4x64)
256 (4x64)
256 (4x64)
50
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 26. S29GL064M (Model R5) Sector Group Protection/Unprotection Addresses
Sector Group
SA0–SA3
A21–A17
00000
00001
00010
00011
00100
00101
00110
Sector Group
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
A21–A17
00111
01000
01001
01010
01011
01100
01101
Sector Group
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
A21–A17
01110
01111
10000
10001
10010
10011
Sector Group
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
A21–A17
10100
10101
10110
10111
11000
11001
Sector Group
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
A21–A17
11010
11011
11100
11101
11110
11111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
Note: All sector groups are 128 Kwords in size.
Table 27. S29GL064M (Models R6, R7) Sector Group Protection/Unprotection Address
Sector Group
SA0–SA3
A21–A17
00000
00001
00010
00011
00100
00101
00110
Sector Group
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
A21–A17
00111
01000
01001
01010
01011
01100
01101
Sector Group
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
A21–A17
01110
01111
10000
10001
10010
10011
Sector Group
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
A21–A17
10100
10101
10110
10111
11000
11001
Sector Group
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
A21–A17
11010
11011
11100
11101
11110
11111
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
Note: All sector groups are 128 Kwords in size.
Table 28. S29GL128M Sector Group Protection/Unprotection Addresses
Sector Group
SA0
A22–A15
00000000
00000001
00000010
00000011
000001xx
000010xx
000011xx
000100xx
000101xx
000110xx
000111xx
001000xx
001001xx
001010xx
001011xx
001100xx
001101xx
001110xx
001111xx
010000xx
010001xx
Sector Group
SA72–SA75
A22–A15
010010xx
010011xx
010100xx
010101xx
010110xx
010111xx
011000xx
011001xx
011010xx
011011xx
011100xx
011101xx
011110xx
011111xx
100000xx
100001xx
100010xx
100011xx
100100xx
100101xx
100110xx
Sector Group
SA156–SA159
SA160–SA163
SA164–SA167
SA168–SA171
SA172–SA175
SA176–SA179
SA180–SA183
SA184–SA187
SA188–SA191
SA192–SA195
SA196–SA199
SA200–SA203
SA204–SA207
SA208–SA211
SA212–SA215
SA216–SA219
SA220–SA223
SA224–SA227
SA228–SA231
SA232–SA235
SA236–SA239
A22–A15
100111xx
101000xx
101001xx
101010xx
101011xx
101100xx
101101xx
101110xx
101111xx
110000xx
110001xx
110010xx
110011xx
110100xx
110101xx
110110xx
110111xx
111000xx
111001xx
111010xx
111011xx
Sector Group
SA240–SA243
SA244–SA247
SA248–SA251
SA252
A22–A15
111100xx
111101xx
111110xx
11111100
11111101
11111110
11111111
SA1
SA76–SA79
SA2
SA80–SA83
SA3
SA84–SA87
SA4–SA7
SA88–SA91
SA253
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA92–SA95
SA254
SA96–SA99
SA255
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA124–SA127
SA128–SA131
SA132–SA135
SA136–SA139
SA140–SA143
SA144–SA147
SA148–SA151
SA152–SA155
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
51
D a t a S h e e t
Table 29. S29GL256M Sector Group Protection/Unprotection Addresses
Sector Group
SA0
A23–A15
000000000
000000001
000000010
000000011
0000001xx
0000010xx
0000011xx
0000100xx
0000101xx
0000110xx
0000111xx
0001000xx
0001001xx
0001010xx
0001011xx
0001100xx
0001101xx
0001110xx
0001111xx
0010000xx
0010001xx
0010010xx
0010011xx
0010100xx
0010101xx
0010110xx
0010111xx
0011000xx
0011001xx
0011010xx
0011011xx
0011100xx
0011101xx
0011110xx
Sector Group
SA124–SA127
SA128–SA131
SA132–SA135
SA136–SA139
SA140–SA143
SA144–SA147
SA148–SA151
SA152–SA155
SA156–SA159
SA160–SA163
SA164–SA167
SA168–SA171
SA172–SA175
SA176–SA179
SA180–SA183
SA184–SA187
SA188–SA191
SA192–SA195
SA196–SA199
SA200–SA203
SA204–SA207
SA208–SA211
SA212–SA215
SA216–SA219
SA220–SA223
SA224–SA227
SA228–SA231
SA232–SA235
SA236–SA239
SA240–SA243
SA244–SA247
SA248–SA251
SA252–SA255
SA256–SA259
A23–A15
0011111xx
0100000xx
0100001xx
0100010xx
0100011xx
0100100xx
0100101xx
0100110xx
0100111xx
0101000xx
0101001xx
0101010xx
0101011xx
0101100xx
0101101xx
0101110xx
0101111xx
0110000xx
0110001xx
0110010xx
0110011xx
0110100xx
0110101xx
0110110xx
0110111xx
0111000xx
0111001xx
0111010xx
0111011xx
0111100xx
0111101xx
0111110xx
0111111xx
1000000xx
Sector Group
SA260–SA263
SA264–SA267
SA268–SA271
SA276–SA279
SA276–SA279
SA280–SA283
SA284–SA287
SA288–SA291
SA292–SA295
SA296–SA299
SA300–SA303
SA304–SA307
SA308–SA311
SA312–SA315
SA316–SA319
SA320–SA323
SA324–SA327
SA328–SA331
SA332–SA335
SA336–SA339
SA340–SA343
SA344–SA347
SA348–SA351
SA352–SA355
SA356–SA359
SA360–SA363
SA364–SA367
SA368–SA371
SA372–SA375
SA376–SA379
SA380–SA383
SA384–SA387
SA388–SA391
A23–A15
Sector Group
SA392–SA395
SA396–SA399
SA400–SA403
SA404–SA407
SA408–SA411
SA412–SA415
SA416–SA419
SA420–SA423
SA424–SA427
SA428–SA431
SA432–SA435
SA436–SA439
SA440–SA443
SA444–SA447
SA448–SA451
SA452–SA455
SA456–SA459
SA460–SA463
SA464–SA467
SA468–SA471
SA472–SA475
SA476–SA479
SA480–SA483
SA484–SA487
SA488–SA491
SA492–SA495
SA496–SA499
SA500–SA503
SA504–SA507
SA508
A23–A15
1100010xx
1100011xx
1100100xx
1100101xx
1100110xx
1100111xx
1101000xx
1101001xx
1101010xx
1101011xx
1101100xx
1101101xx
1101110xx
1101111xx
1110000xx
1110001xx
1110010xx
1110011xx
1110100xx
1110101xx
1110110xx
1110111xx
1111000xx
1111001xx
1111010xx
1111011xx
1111100xx
1111101xx
1111110xx
111111100
111111101
111111110
111111111
1000001xx
1000010xx
1000011xx
1000101xx
1000101xx
1000110xx
1000111xx
1001000xx
1001001xx
1001010xx
1001011xx
1001100xx
1001101xx
1001110xx
1001111xx
1010000xx
1010001xx
1010010xx
1010011xx
1010100xx
1010101xx
1010110xx
1010111xx
1011000xx
1011001xx
1011010xx
1011011xx
1011100xx
1011101xx
1011110xx
1011111xx
1100000xx
1100001xx
SA1
SA2
SA3
SA4–SA7
SA8–SA11
SA12–SA15
SA16–SA19
SA20–SA23
SA24–SA27
SA28–SA31
SA32–SA35
SA36–SA39
SA40–SA43
SA44–SA47
SA48–SA51
SA52–SA55
SA56–SA59
SA60–SA63
SA64–SA67
SA68–SA71
SA72–SA75
SA76–SA79
SA80–SA83
SA84–SA87
SA88–SA91
SA92–SA95
SA96–SA99
SA100–SA103
SA104–SA107
SA108–SA111
SA112–SA115
SA116–SA119
SA120–SA123
SA509
SA510
SA511
52
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data
in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. Dur-
ing this mode, formerly protected sector groups can be programmed or erased by selecting the
sector group addresses. Once VID is removed from the RESET# pin, all the previously protected
sector groups are protected again. For this feature, Figure 1 shows the algorithm, and Figure 23
shows the timing diagrams.
START
RESET# = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Group Unprotect Completed
(Note 2)
Notes:
1. All protected sector groups unprotected (If WP# = V , the highest or lowest address sector
IL
remains protected for uniform sector devices, the top or bottom two address sectors remains
protected for boot sector devices).
2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
53
D a t a S h e e t
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
Temporary Sector
Group Unprotect
Mode
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Yes
Yes
Set up sector
group address
All sector
groups
No
protected?
Yes
Sector Group Protect:
Write 60h to sector
group address with
A6–A0 = 0xx0010
Set up first sector
group address
Sector Group
Unprotect:
Wait 150 µs
Write 60h to sector
group address with
A6–A0 = 1xx0010
Verify Sector Group
Protect: Write 40h
to sector group
address with
A6–A0 = 0xx0010
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
Verify Sector Group
Unprotect: Write
40h to sector group
address with
Read from
sector group address
with A6–A0
= 0xx0010
Increment
PLSCNT
A6–A0 = 1xx0010
No
No
PLSCNT
= 25?
Read from
sector group
address with
Data = 01h?
Yes
A6–A0 = 1xx0010
No
Yes
Set up
next sector group
address
Protect
another
sector group?
Yes
No
PLSCNT
= 1000?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
Last sector
group
verified?
No
Device failed
Write reset
command
Yes
Remove VID
from RESET#
Sector Group
Unprotect
Sector Group
Protect
Sector Group
Protect complete
Write reset
command
Algorithm
Algorithm
Sector Group
Unprotect complete
Figure 2. In-System Sector Group Protect/Sector Group Unprotect Algorithms
54
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes
in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the
Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the
factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the field.
The factory offers the device with the Secured Silicon Sector either customer lockable (standard
shipping option) or factory locked (contact a Spansion sales representative for ordering informa-
tion). The customer-lockable version is shipped with the Secured Silicon Sector unprotected,
allowing customers to program the sector after receiving the device. The customer-lockable ver-
sion also has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked
version is always protected when shipped from the factory, and has the Secured Silicon (Secured
Silicon) Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon Sector Indicator
Bit prevents customer-lockable devices from being used to replace devices that are factory
locked.
Note: The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
The Secured Silicon sector address space in this device is allocated as follows:
Secured Silicon Sector Address Range
Standard
Factory
Locked
ExpressFlash
Factory
Customer
Lockable
x16
x8
Locked
ESN or
determined by
customer
000000h – 000007h
000000h – 00000Fh
ESN
Determined by
customer
Determined by
customer
000008h – 00007Fh
000010h – 0000FFh
Unavailable
The system accesses the Secured Silicon Sector through a command sequence (see Write Protect
(WP#)). After the system writes the Enter Secured Silicon Sector command sequence, it may read
the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0).
This mode of operation continues until the system issues the Exit Secured Silicon Sector com-
mand sequence, or until power is removed from the device. On power-up, or following a hardware
reset, the device reverts to sending commands to sector SA0.
Customer Lockable: Secured Silicon Sector Not Programmed or Protected At the Factory
Unless otherwise specified, the device is shipped such that the customer may program and pro-
tect the 256-byte Secured Silicon sector.
The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or
unlock bypass methods, in addition to the standard programming command sequence (see Com-
mand Definitions).
Programming and protecting the Secured Silicon Sector must be used with caution since, once
protected, there is no procedure available for unprotecting the Secured Silicon Sector area and
none of the bits in the Secured Silicon Sector memory space can be modified in any way.
The Secured Silicon Sector area can be protected using one of the following procedures:
Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then fol-
low the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be
at either VIH or VID. This allows in-system protection of the Secured Silicon Sector without
raising any device pin to a high voltage. Note that this method is only applicable to the Se-
cured Silicon Sector.
Write the three-cycle Enter Secured Silicon Sector Region command sequence and then use
the alternate method of sector protection described in the “Sector Group Protection and Un-
protection” section.
Once the Secured Silicon Sector is programmed, locked, and verified, the system must write the
Exit Secured Silicon Sector Region command sequence to return to reading and writing within the
remainder of the array.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
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D a t a S h e e t
Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory
In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from
the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked
device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your sales
representative for details on ordering ESN Factory Locked devices.
Customers may opt to have their code programmed by the factory through the Spansion pro-
gramming service (Customer Factory Locked). The devices are then shipped from the factory with
the Secured Silicon Sector permanently locked. Contact your sales representative for details on
using the Spansion programming service.
Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector group
without using VID. Write Protect is one of two functions provided by the WP#/ACC input.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions
in the first or last sector group independently of whether those sector groups were protected or
unprotected. Note that if WP#/ACC is at VIL when the device is in the standby mode, the maxi-
mum input load current is increased (Table 29).
Note: If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously
set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that
WP# has an internal pullup; when unconnected, WP# is at VIH.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (Table 34 and Table 35 contain command definitions). In ad-
dition, the following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals during VCC
power-up and power-down transitions, or from system noise.
Low V
Write Inhibit
CC
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during
VCC power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is
greater than VLKO. The system must provide the proper signals to the control pins to prevent un-
intentional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is automatically reset to the read mode on
power-up.
56
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D a t a S h e e t
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software inter-
rogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-
dent, and forward- and backward-compatible for the specified flash device families. Flash vendors
can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array data. The system can read CFI informa-
tion at the addresses given in Table 30 through Table 33. To terminate reading CFI data, the
system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode.
The device enters the CFI query mode, and the system can read CFI data at the addresses given
in Table 30 through Table 33. The system must write the reset command to return the device to
reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Alterna-
tively, contact your sales representative for copies of these documents.
Table 30. CFI Query Identification String
Addresses(x16)
Addresses(x8)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h Query Unique ASCII string “QRY”
0059h
13h
14h
26h
28h
0002h
Primary OEM Command Set
0000h
15h
16h
2Ah
2Ch
0040h
Address for Primary Extended Table
0000h
17h
18h
2Eh
30h
0000h
Alternate OEM Command Set (00h = none exists)
0000h
19h
1Ah
32h
34h
0000h Address for Alternate OEM Extended Table
0000h (00h = none exists)
Table 31. System Interface String
Addresses (x16)
Addresses (x8)
Data
Description
V
Min. (write/erase)
CC
1Bh
36h
38h
0027h
D7–D4: volt, D3–D0: 100 millivolt
V
Max. (write/erase)
CC
1Ch
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
3Ah
3Ch
3Eh
0000h
0000h
V
V
Min. voltage (00h = no V pin present)
PP
PP
PP
Max. voltage (00h = no V pin present)
PP
0007h Reserved for future use
Typical timeout for Min. size buffer write 2N µs
20h
21h
22h
40h
42h
44h
0007h
(00h = not supported)
000Ah Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms
(00h = not supported)
0000h
23h
24h
25h
46h
48h
4Ah
0001h Reserved for future use
0005h Max. timeout for buffer write 2N times typical
0004h Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical
(00h = not supported)
26h
4Ch
0000h
Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the
Ordering Information tables to obtain the VCC range for particular part numbers. See the Erase and Programming
Performance table for typical timeout specifications.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
57
D a t a S h e e t
Table 32. Device Geometry Definition
Addresses
(x16)
Addresses
(x8)
Data
Description
0019h
0018h
0017h
0016h
Device Size = 2N byte
19 = 256 Mb, 18 = 128 Mb, 17 = 64 Mb, 16 = 32 Mb
27h
4Eh
Flash Device Interface description (refer to CFI publication 100)
0000h = x8-only bus devices
0001h = x16-only bus devices
28h
29h
50h
52h
000xh
0000h
0002h = x8/x16 bus devices
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
0001h
0002h
Number of Erase Block Regions within device
(01h = uniform device, 02h = boot device)
2Ch
58h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
003Fh, 0000h, 0000h, 0001h = 32 Mb (-R0, -R1, -R2, R5, R6)
007Fh, 0000h, 0020h, 0000h = 32 Mb (-R3, -R4), 64 Mb (-R3, -R4)
007Fh, 0000h, 0000h, 0001h = 64 Mb (-R0, -R1, -R2, -R5, -R6, -R7)
00FFh, 0000h, 0000h, 0001h = 128 Mb
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
00x0h
000xh
00FFh, 0001h, 0000h, 0001h = 256 Mb
31h
32h
33h
34h
60h
64h
66h
68h
00xxh
0000h
0000h
000xh
Erase Block Region 2 Information (refer to CFI publication 100)
003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)
007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2)
0000h, 0000h, 0000h, 0000h = all others
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
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S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Table 33. Primary Vendor-Specific Extended Query
Addresses
(x16)
Addresses
Data
Description
(x8)
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0010b = 0.23 μm MirrorBit
0009h = x8-only bus devices 0008h = all other devices
45h
8Ah
000xh
Erase Suspend
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
8Ch
8Eh
90h
92h
94h
96h
98h
9Ah
9Ch
0002h
0001h
0001h
0004h
0000h
0000h
0001h
00B5h
00C5h
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0004h = Standard Mode (Refer to Text)
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform Device without WP# protect,
02h = Bottom Boot Device, 03h = Top Boot Device,
04h = Uniform sectors bottom WP# protect,
05h = Uniform sectors top WP# protect
4Fh
50h
9Eh
A0h
00xxh
0001h
Program Suspend< 00h = Not Supported, 01h = Supported
February 7, 2007 S29GL-M_00_B8
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D a t a S h e e t
Command Definitions
Writing specific address and data commands or sequences into the command register initiates
device operations. Table 34 and Table 35 define the valid register command sequences. Writing
incorrect address and data values or writing them in the improper sequence may place the device
in an unknown state. A reset command is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. See AC Characteristics for
timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are
required to retrieve data. The device is ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the erase-suspend-read
mode, after which the system can read data from any non-erase-suspended sector. After com-
pleting a programming operation in the Erase Suspend mode, the system may once again read
array data with the same exception. See Erase Suspend/Erase Resume Commands for more
information.
The system must issue the reset command to return the device to the read (or erase-suspend-
read) mode if DQ5 goes high during an active program or erase operation, or if the device is in
the autoselect mode. See the next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the Device Bus Operations section for more in-
formation. The Read-Only Operations–AC Characteristics provides the read parameters, and
Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address
bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to the read mode. Once erasure begins, however,
the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command se-
quence before programming begins. This resets the device to the read mode. If the program
command sequence is written while the device is in the Erase Suspend mode, writing the reset
command returns the device to the erase-suspend-read mode. Once programming begins, how-
ever, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command se-
quence. Once in the autoselect mode, the reset command must be written to return to the read
mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the
reset command returns the device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).
Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write
the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.
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D a t a S h e e t
Autoselect Command Sequence
The autoselect command sequence allows the host system to read several identifier codes at spe-
cific addresses:
A7:A0
(x16)
A6:A-1
(x8)
Identifier Code
Manufacturer ID
Device ID, Cycle 1
00h
01h
00h
02h
Device ID, Cycle 2
0Eh
1Ch
Device ID, Cycle 3
0Fh
1Eh
Secured Silicon Sector Factory Protect
Sector Protect Verify
03h
06h
(SA)02h
(SA)04h
Note: 3.The device ID is read over three cycles. SA = Sector Address
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle that contains the autoselect command. The device then enters the autose-
lect mode. The system may read at any address any number of times without initiating another
autoselect command sequence:
The system must write the reset command to return to the read mode (or erase-suspend-read
mode if the device was previously in Erase Suspend).
Enter/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte
random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region
by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues
to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns
the device to normal operation. Table 34 and Table 35 show the address and data requirements
for both command sequences. Also, see Secured Silicon Sector Flash Memory Region for further
information. Note that the ACC function and unlock bypass modes are not available when the Se-
cured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-
ing two unlock write cycles, followed by the program set-up command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device automatically provides internally gen-
erated program pulses and verifies the programmed cell margin. Table 34 and Table 35 show the
address and data requirements for the word program command sequence, respectively.
When the Embedded Program algorithm is complete, the device then returns to the read mode
and addresses are no longer latched. The system can determine the status of the program oper-
ation by using DQ7 or DQ6. See Write Operation Status for information on these status bits. Any
commands written to the device during the Embedded Program Algorithm are ignored. Note that
the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program oper-
ation is in progress. Note that a hardware reset immediately terminates the program operation.
The program command sequence should be reinitiated once the device returns to the read mode,
to ensure data integrity.
Programming is allowed in any sequence of address locations and across sector boundaries. Pro-
gramming to the same word address multiple times without intervening erases (incremental bit
programming) requires a modified programming method. For such application requirements,
please contact your local Spansion representative. Word programming is supported for backward
compatibility with existing Flash driver software and for occasional writing of individual words. Use
of write buffer programming (see below) is strongly recommended for general programming use
when more than a few words are to be programmed. The effective word programming time using
write buffer programming is approximately four times shorter than the single word programming
time.
February 7, 2007 S29GL-M_00_B8
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D a t a S h e e t
Any bit in a word cannot be programmed from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was
successful. However, a succeeding read shows that the data is still “0.” Only erase operations can
convert a “0” to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using
the standard program command sequence. The unlock bypass command sequence is initiated by
first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass mode
command sequence is all that is required to program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the second cycle contains the program ad-
dress and data. Additional data is programmed in the same manner. This mode dispenses with
the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Table 34 and Table 35 show the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h. The second cycle
must contain the data 00h. The device then returns to the read mode.
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard pro-
gramming algorithms. The Write Buffer Programming command sequence is initiated by first
writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. The fourth cycle writes the
sector address and the number of word locations, minus one, to be programmed. For example, if
the system programs six unique address locations, then 05h should be written to the device. This
tells the device how many write buffer addresses are loaded with data and therefore when to ex-
pect the Program Buffer to Flash command. The number of locations to program cannot exceed
the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page
is selected by address bits AMAX–A4. All subsequent address/data pairs must fall within the se-
lected-write-buffer-page. The system then writes the remaining address/data pairs into the write
buffer. Write buffer locations may be loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write
buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer
pages.) This also means that Write Buffer Programming cannot be performed across multiple sec-
tors. If the system attempts to load programming data outside of the selected write-buffer page,
the operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter
is decremented for every data load operation. The host system must therefore account for loading
a write-buffer location more than once. The counter decrements for each data load operation, not
for each unique write-buffer-address location. Note also that if an address location is loaded more
than once into the buffer, the final data loaded for that address is programmed.
Once the specified number of write buffer locations are loaded, the system must then write the
Program Buffer to Flash command at the sector address. Any other address and data combination
aborts the Write Buffer Programming operation. The device then begins programming. Data poll-
ing should be used while monitoring the last address location loaded into the write buffer. DQ7,
DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer
Programming.
The write-buffer programming operation can be suspended using the standard program suspend/
resume commands. Upon successful completion of the Write Buffer Programming operation, the
device is ready to execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to Pro-
gram step.
62
S29GL-M MirrorBitTM Flash Family
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D a t a S h e e t
Write to an address in a sector different than the one specified during the Write-Buffer-Load
command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
Starting Address during the write buffer data loading stage of the operation.
Write data other than the Confirm Command after the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded),
DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to
reset the device for the next operation.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a pro-
gram operation is in progress. This flash device is capable of handling multiple write buffer
programming operations on the same write buffer address range without intervening erases. For
applications requiring incremental bit programming, a modified programming method is required;
please contact your local Spansion representative. Any bit in a write buffer address range
cannot be programmed from “0” back to a “1.” Attempting to do so can cause the device to
set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the operation was successful. How-
ever, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0”
to a “1.”
Accelerated Program
The device offers accelerated program operations through the WP#/ACC or ACC pin depending
on the particular product. When the system asserts VHH on the WP#/ACC or ACC pin. The device
uses the higher voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the
WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device
damage can result. WP# has an internal pullup; when unconnected, WP# is at VIH
.
Figure 3 illustrates the algorithm for the program operation. See Erase and Program Operations—
S29GL032M Only and AC Characteristics for parameters, and Figure 14 for timing diagrams.
February 7, 2007 S29GL-M_00_B8
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D a t a S h e e t
Write “Write to Buffer”
command and
Sector Address
Part of “Write to Buffer”
Command Sequence
Write number of addresses
to program minus 1(WC)
and Sector Address
Write first address/data
Yes
WC = 0 ?
No
Write to a different
sector address
Abort Write to
Buffer Operation?
Yes
Write to buffer ABORTED.
Must write “Write-to-buffer
Abort Reset” command
sequence to return
No
Write next address/data pair
(Note 1)
to read mode.
WC = WC - 1
Write program buffer to
flash sector address
Read DQ7 - DQ0 at
Last Loaded Address
Notes:
1. When Sector Address is specified, any address in
the selected sector is acceptable. However, when
loading Write-Buffer address locations with data, all
addresses must fall within the selected Write-Buffer
Page.
Yes
DQ7 = Data?
No
2. DQ7 may change simultaneously with DQ5.
Therefore, DQ7 should be verified.
3. If this flowchart location was reached because
DQ5= “1”, then the device FAILED. If this flowchart
location was reached because DQ1= “1”, then the
Write to Buffer operation was ABORTED. In either
case, the proper reset command must be written
before the device can begin another operation. If
DQ1=1, write the Write-Buffer-Programming-
Abort-Reset command. if DQ5=1, write the Reset
command.
No
No
DQ1 = 1?
DQ5 = 1?
Yes
Yes
Read DQ7 - DQ0 with
address = Last Loaded
Address
4. See Table 34 and Table 35 for command sequences
required for write buffer programming.
Yes
(Note 2)
DQ7 = Data?
No
FAIL or ABORT
PASS
(Note 3)
Figure 3. Write Buffer Programming Operation
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S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
Note: See Table 34 and Table 35 for program command sequence
Figure 4. Program Operation
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a
Write to Buffer programming operation so that data can be read from any non-suspended sector.
When the Program Suspend command is written during a programming process, the device halts
the program operation within 15 µs maximum (5 µs typical) and updates the status bits. Ad-
dresses are not required when writing the Program Suspend command.
After the programming operation is suspended, the system can read array data from any non-
suspended sector. The Program Suspend command can also be issued during a programming op-
eration while an erase is suspended. In this case, data can be read from any addresses not in
Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area
(One-time Program area), then user must use the proper command sequences to enter and exit
this region. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
The system can also write the autoselect command sequence when the device is in the Program
Suspend mode. The system can read as many autoselect codes as required. When the device
exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for an-
other valid operation. See Autoselect Command Sequence for more information.
After the Program Resume command is written, the device reverts to programming. The system
can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard program operation. See Write Operation Status for more information.
The system must write the Program Resume command (address bits are don’t care) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Resume
command are ignored. Another Program Suspend command can be written after the device re-
sumes programming.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
65
D a t a S h e e t
Program Operation
or Write-to-Buffer
Sequence in Progress
Write Program Suspend
Command Sequence
Write address/data
XXXh/B0h
Command is also valid for
Erase-suspended-program
operations
Wait 15 μs
Autoselect and SecSi Sector
read operations are also allowed
Read data as
required
Data cannot be read from erase- or
program-suspended sectors
Done
No
reading?
Yes
Write Program Resume
Command Sequence
Write address/data
XXXh/30h
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations. Table 34 and Table 35 show the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6, or DQ2. See Write Operation Status for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once the device returns to reading array data, to ensure data
integrity.
Figure 6 illustrates the algorithm for the erase operation. See Erase and Programming Perfor-
mance in AC Characteristics for parameters, and Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
Table 34 and Table 35 shows the address and data requirements for the sector erase command
sequence.
66
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
The device does not require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-
out period, additional sector addresses and sector erase commands can be written. Loading the
sector erase buffer can be done in any sequence, and the number of sectors can be from one
sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise
erasure may begin. Any sector erase address and command following the exceeded time-out can
or cannot be accepted. It is recommended that processor interrupts be disabled during this time
to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to the read mode. Note that the Secured Silicon Sector,
autoselect, and CFI functions are unavailable when an erase operation is in progress. The system
must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section
on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in
the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by
reading DQ7, DQ6, or DQ2 in the erasing sector. See Write Operation Status for information on
these status bits.
Once the sector erase operation starts, only the Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware reset immediately terminates the erase
operation. If that occurs, the sector erase command sequence should be reinitiated once the de-
vice returns to reading array data, to ensure data integrity.
Figure 6 illustrates the algorithm for the erase operation. See Erase and Programming Perfor-
mance in AC Characteristics for parameters, and Figure 18 for timing diagrams.
l
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 34 and Table 35 for program command sequence.
2. See DQ3: Sector Erase Timer for information on the sector erase timer.
Figure 6. Erase Operation
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
67
D a t a S h e e t
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the 50 µs time-out period during the sector
erase command sequence. The Erase Suspend command is ignored if written during the chip
erase operation or Embedded Program algorithm.
When the Erase Suspend command is written during the sector erase operation, the device re-
quires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase operation.
After the erase operation is suspended, the device enters the erase-suspend-read mode. The sys-
tem can read data from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sec-
tors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation
Status for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-sus-
pend-read mode. The system can determine the status of the program operation using the DQ7
or DQ6 status bits, just as in the standard word program operation. See Write Operation Status
for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence.
See Autoselect Mode and Autoselect Command Sequence for details.
To resume the sector erase operation, the system must write the Erase Resume command. Fur-
ther writes of the Resume command are ignored. Another Erase Suspend command can be
written after the chip resumes erasing.
Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system.
When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As
such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress are impeded
as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the
additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity
occurs only briefly. In such cases, erase performance is not significantly impacted.
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S29GL-M MirrorBitTM Flash Family
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D a t a S h e e t
Command Definitions
Table 34. Command Definitions( x16 Mode, BYTE# = V
)
IH
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Addr
Second
Third
Addr
Fourth
Fifth
Sixth
Data
RD
F0
Addr
Data
Data
Addr
Data
Addr
Data
Addr
Data
Read (6)
Reset (7)
1
1
4
RA
XXX
555
Manufacturer ID
Device ID (9)
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
(Note
18)
(Note
18)
4
4
4
555
555
555
AA
AA
AA
X0E
X0F
Secured Silicon Sector Factory
Protect (10)
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify
(12)
(SA)X02
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Program
3
4
4
3
1
3
3
2
2
6
6
1
1
1
555
555
555
555
SA
AA
AA
AA
AA
29
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
Write to Buffer (11)
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash
Write to Buffer Abort Reset (13)
Unlock Bypass
555
555
XXX
XXX
555
555
XXX
XXX
55
2AA
2AA
PA
55
55
PD
00
55
55
555
555
F0
20
Unlock Bypass Program (14)
Unlock Bypass Reset (15)
Chip Erase
XXX
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Program/Erase Suspend (16)
Program/Erase Resume (16)
CFI Query (18)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence for more
information.
8. Device ID must be read in three cycles.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
18. Refer to Table 17, AutoSelect Codes for individual Device IDs
per device density and model number.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
69
D a t a S h e e t
Table 35. Command Definitions (x8 Mode, BYTE# = V )
IL
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Data
Fifth
Data
Sixth
Addr Data
Addr Data Addr Data Addr Data
Addr
Addr
Read (6)
Reset (7)
1
1
4
4
RA
RD
F0
XXX
AAA
AAA
Manufacturer ID
AA
AA
555
555
55
55
AAA
AAA
90
90
X00
X02
01
7E
Device ID (9)
X1C (Note 17) X1E (Note 17)
Secured Silicon Sector Factory
Protect (10)
4
AAA
AA
555
55
AAA
90
X06
(Note 10)
00/01
Sector Group Protect Verify (12)
Enter Secured Silicon Sector Region
Exit Secured Silicon Sector Region
Write to Buffer (11)
4
3
4
3
1
3
6
6
1
1
1
AAA
AAA
AAA
AAA
SA
AA
AA
AA
AA
29
AA
AA
AA
B0
30
98
555
555
555
555
55
55
55
55
AAA
AAA
AAA
SA
90 (SA)X04
88
90
25
XXX
SA
00
BC
PA
PD
WBL
PD
Program Buffer to Flash
Write to Buffer Abort Reset (13)
Chip Erase
AAA
AAA
AAA
XXX
XXX
AA
555
555
555
55
55
55
AAA
AAA
AAA
F0
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Program/Erase Suspend (14)
Program/Erase Resume (15)
CFI Query (16)
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
BC = Byte Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or AAA as shown in table, address bits above A11 are don’t
care.
10. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
11. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
12. Total number of cycles in command sequence is determined by
number of bytes written to write buffer. Maximum number of
cycles in command sequence is 37, including “Program Buffer to
Flash” command.
13. Command sequence resets device for next command after
aborted write-to-buffer operation.
14. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
15. Erase Resume command is valid only during Erase Suspend
mode.
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
mode.
7. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
8. Fourth cycle of autoselect command sequence is a read cycle.
Data bits DQ15–DQ8 are don’t care. See Autoselect Command
Sequence section or more information.
9. Device ID must be read in three cycles.
16. Command is valid when device is ready to read array data or
when device is in autoselect mode.
17. Refer to Table 17, AutoSelect Codes for individual Device IDs
per device density and model number.
70
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2,
DQ3, DQ5, DQ6, and DQ7. Table 36 and the following subsections describe the function of these
bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is
complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to
determine whether an Embedded Program or Erase operation is in progress or is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling
is valid after the rising edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.
When the Embedded Program algorithm is complete, the device outputs the datum programmed
to DQ7. The system must provide the program address to read valid status information on DQ7.
If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-
mately 1 µs, then the device returns to the read mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embed-
ded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling
produces a “1” on DQ7. The system must provide an address within any of the sectors selected
for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that are protected. However, if the system reads
DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asyn-
chronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device can
change from providing status information to valid data on DQ7. Depending on when the system
samples the DQ7 output, it can read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be
still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.
Table 36 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algo-
rithm. Figure 17 shows the Data# Polling timing diagram.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
71
D a t a S h e e t
START
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ15–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any
sector address within the sector being erased. During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 can change simultaneously with DQ5.
Figure 7. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algo-
rithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE#
pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can
be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes program-
ming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode,
the standby mode, or in the erase-suspend-read mode. Table 36 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at
any address, and is valid after the rising edge of the final WE# pulse in the command sequence
(prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles.
When the operation is complete, DQ6 stops toggling.
72
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or
is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm
is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-
gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-
suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the
program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-
ded Program algorithm is complete.
Table 36 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm.
Figure 20 shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2
and DQ6 in graphical form. Also, see DQ2: Toggle Bit II.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
73
D a t a S h e e t
START
Read DQ7–DQ0
Read DQ7–DQ0
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Program/Erase
Operation Complete
Complete, Write
Reset Command
Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for more information.
Figure 8. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively
erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-
suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command
sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for era-
sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot
distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, in-
dicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode
information. Refer to Table 36 to compare outputs for DQ2 and DQ6.
74
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II”
explains the algorithm, also see RY/BY#: Ready/Busy#. Figure 20 shows the toggle bit timing di-
agram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 did not go high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase
cycle was not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5
produces a “1.”
In all these cases, the system must write the reset command to return the device to the reading
the array (or to erase-suspend-read if the device was previously in the erase-suspend-program
mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure started. (The sector erase timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire time-out also applies after each additional
sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.”
If the time between additional sector erase commands from the system can be assumed to be
less than 50 µs, the system need not monitor DQ3(see Sector Erase Command Sequence).
After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure that the device accepted the command sequence, and then
reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm started; all further commands (except
Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts
additional sector erase commands. To ensure the command was accepted, the system software
should check the status of DQ3 prior to and following each subsequent sector erase command. If
DQ3 is high on the second status check, the last command might not have been accepted.
Table 36 shows the status of DQ3 relative to the other status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 pro-
duces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return
the device to reading array data. See Write Buffer for more details.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
75
D a t a S h e e t
Table 36. Write Operation Status
DQ7
(Note 2
)
DQ5
(Note 1)
DQ2
(Note 2)
Status
DQ6
DQ3
DQ1 RY/BY#
Standar Embedded Program Algorithm
d
DQ7#
0
Toggle
Toggle
0
0
N/A No toggle
0
0
0
1
Embedded Erase Algorithm
1
Toggle
N/A
Mode
Program-Suspended Sector
Invalid (not allowed)
Data
Program Program-
Suspend Suspend
Mode Read
Non-Program
Suspended Sector
1
1
1
Erase-Suspended Sector
1
No toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Suspend
Erase
Non-Erase Suspended
Sector
Data
Read
Suspend
Mode
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
0
Write- Busy (Note 3)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
to-
Abort (Note 4)
Buffer
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation
exceeded the maximum timing limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate
subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address
location.
4. DQ1 switches to ‘1’ when the device aborts the write-to-buffer operation
76
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Absolute Maximum Ratings
Storage Temperature, Plastic Packages
Ambient Temperature with Power Applied
–65°C to +150°C
–65°C to +125°C
–0.5 V to +4.0 V
–0.5 V to +12.5 V
V
(Note 1)
CC
Voltage with Respect to Ground
A9, OE#, ACC and RESET# (Note 2)
All other pins (Note 1)
–0.5 V to V +0.5 V
CC
Output Short Circuit Current (Note 3)
200 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may overshoot V to –2.0 V for periods of up to
SS
20 ns. See Figure 9, Maximum Negative Overshoot Waveform. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage
CC
transitions, input or I/O pins may overshoot to V + 2.0 V for periods up to 20 ns. See Figure 10.
CC
2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may
overshoot V to –2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V
SS
which may overshoot to +14.0V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
2.0 V
20 ns
20 ns
Figure 10. Maximum Positive Overshoot Waveform
Operating Ranges
Ambient Temperature (T )
A
Industrial (I) Devices
–40°C to +85°C
V
V
V
for full voltage range
+2.7 V to +3.6 V
+3.0 V to +3.6 V
CC
CC
IO
Supply Voltages
for regulated voltage range
V
CC
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
77
D a t a S h e e t
DC Characteristics
CMOS Compatible
Parameter
Symbol
Parameter Description
(Notes)
Uni
t
Test Conditions
Min
Typ
Max
V
V
= V to V
,
CC
IN
CC
SS
I
Input Load Current (1)
±1.0
µA
LI
= V
CC max
CC max
CC max
I
A9, ACC Input Load Current
Reset Leakage Current
V
V
= V
= V
; A9 = 12.5 V
35
35
µA
µA
LIT
CC
I
; RESET# = 12.5 V
LR
CC
V
V
= V to V
SS
CC max
,
CC
OUT
CC
I
Output Leakage Current
±1.0
µA
LO
= V
1 MHz
5
20
25
35
50
60
20
40
60
5 MHz (4)
5 MHz (5)
10 MHz (4)
10 MHz (5)
10 MHz
18
25
35
40
5
I
I
V
Initial Read Current (2, 3)
CE# = V OE# = V
mA
CC1
CC2
CC
IL,
IH
V
Intra-Page Read Current (2, 3)
CE# = V OE# = V
mA
CC
IL,
IH
IH
40 MHz
10
50
I
I
I
I
V
V
V
Active Write Current (3, 4)
Standby Current (3)
Reset Current (3)
CE# = V OE# = V
mA
µA
µA
µA
CC3
CC4
CC5
CC6
CC
CC
CC
IL,
CE#, RESET# = V ± 0.3 V,
CC
1
1
1
5
5
WP# = V
IH
RESET# = V ± 0.3 V, WP# = V
SS
IH
V
= V ± 0.3 V;
CC
IH
Automatic Sleep Mode (3, 7)
5
-0.1< V ≤ 0.3 V, WP# = V
IL
IH
V
Input Low Voltage (1, 8)
–0.5
0.8
V
V
V
IL
V
Input High Voltage 1, 8)
0.7 V
V
+ 0.5
IH
CC
CC
V
Voltage for ACC Program Acceleration
V
V
= 2.7 –3.6 V
= 2.7 –3.6 V
11.5
11.5
12.0
12.0
12.5
12.5
0.45
HH
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
V
ID
CC
V
Output Low Voltage (8)
I
I
I
= 4.0 mA, V = V
CC min
V
V
V
V
OL
OL
OH
OH
CC
V
V
= –2.0 mA, V = V
0.85 V
CC
OH1
OH2
CC
CC min
CC min
Output High Voltage
= –100 µA, V = V
V
–0.4
CC
CC
V
Low V Lock-Out Voltage (9)
2.3
2.5
LKO
CC
Notes:
1. On the WP#/ACC pin only, the maximum input load current when WP# = V is ±5.0 µA.
IL
2. The I current listed is typically less than 3.5 mA/MHz, with OE# at V
.
CC
IH
3. Maximum I specifications are tested with V = V max.
CC
CC
CC
4. S29GL032M, S29GL064M
5. S29GL128M, S29GL256M
6.
I
active while Embedded Erase or Embedded Program is in progress.
CC
7. Automatic sleep mode enables the low power mode when addresses remain stable for t
ns.
+ 30
ACC
8.
V
voltage requirements.
CC
9. Not 100% tested.
78
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Test Conditions
3.3 V
2.7 kΩ
Device
Under
Test
C
6.2 k
Ω
L
Note: Diodes are IN3064 or equivalent
Figure 11. Te st S e t up
Table 37. Test Specifications
Test Condition
All Speeds
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
5
pF
Input Rise and Fall Times
Input Pulse Levels
ns
V
0.0 or V
CC
Input timing measurement reference levels
(See Note)
0.5 V
0.5 V
V
V
CC
CC
Output timing measurement reference levels
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care,
Any Change Permitted
Changing, State Unknown
Center Line is High
Impedance State (High Z)
Does Not Apply
V
CC
0.5 V
Input
0.5 V
Measurement Level
Output
CC
CC
0.0 V
Figure 12. Input Waveforms and Measurement Levels
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
79
D a t a S h e e t
AC Characteristics
Read-Only Operations—S29GL256M Only
Parameter
Description
JEDEC Std.
Speed Options
Test Setup
Unit
10
100
100
100
30
11
100
100
100
30
t
t
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
Max
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
RC
t
t
Address to Output Delay
CE#, OE# = V
ACC
IL
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ELQV
CE
t
PACC
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
GLQV
EHQZ
GHQZ
OE
t
t
t
16
16
DF
DF
t
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (Note 1)
OEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 37 for test specifications.
Read-Only Operations—S29GL128M only
Parameter
Description
JEDEC Std.
Speed Options
Test Setup
Unit
90
90
90
90
25
25
10
100
100
100
30
t
t
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
Max
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
RC
t
t
Address to Output Delay
CE#, OE# = V
ACC
IL
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ELQV
CE
t
PACC
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
GLQV
EHQZ
GHQZ
OE
t
t
t
16
16
DF
DF
t
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (Note 1)
OEH
Toggle and
Data# Polling
10
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 37 for test specifications.
80
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Read-Only Operations—S29GL064M Only
Parameter
Description
JEDEC Std.
Speed Options
Test Setup
Unit
90
Min 90
Max 90
Max 90
Max 25
Max 25
Max
10
100
100
100
30
11
110
110
110
30
t
t
Read Cycle Time (Note 1)
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
RC
t
t
Address to Output Delay
CE#, OE# = V
ACC
IL
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ELQV
CE
t
PACC
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (See Note)
Output Enable to Output High Z (See Note)
30
30
GLQV
EHQZ
GHQZ
OE
t
t
t
16
DF
DF
t
Max
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (See Note)
OEH
Toggle and
10
Data# Polling
Note: Not 100% tested.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
81
D a t a S h e e t
AC Characteristics
Read-Only Operations—S29GL032M only
Parameter
Description
JEDEC Std.
Speed Options
Test Setup
Unit
90
Min 90
Max 90
Max 90
Max 25
Max 25
Max
10
100
100
100
30
11
110
110
110
30
t
t
Read Cycle Time (Note 1)
ns
ns
ns
ns
ns
ns
ns
AVAV
AVQV
RC
t
t
Address to Output Delay
CE#, OE# = V
ACC
IL
t
t
Chip Enable to Output Delay
Page Access Time
OE# = V
IL
ELQV
CE
t
PACC
t
t
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
30
30
GLQV
EHQZ
GHQZ
OE
t
t
t
16
DF
DF
t
Max
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
t
t
Min
Min
Min
0
0
ns
ns
ns
AXQX
OH
Read
t
Output Enable Hold Time (Note 1)
OEH
Toggle and
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 37 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operation Timings
82
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
AC Characteristics
Same Page
A23-A2
A1-A0*
Ad
Aa
Ab
Ac
tPACC
tPACC
tPACC
tACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Note: Figure shows device in word mode. Addresses are A1–A-1 for byte mode.
Figure 14. Page Read Timings
Hardware Reset (RESET#)
Parameter
JEDEC Std.
All Speed
Options
Description
Unit
RESET# Pin Low (During Embedded Algorithms) to Read Mode
(See Note)
t
t
Max
20
µs
ns
Ready
Ready
RESET# Pin Low (NOT During Embedded Algorithms) to Read
Mode (See Note)
Max
500
t
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
RP
t
Reset High Time Before Read (See Note)
RESET# Input Low to Standby Mode (See Note)
RY/BY# Output High to CE#, OE# pin Low
RH
t
RPD
t
RB
Note: Not 100% tested.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
83
D a t a S h e e t
AC Characteristics
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRH
tRP
Figure 15. Reset Timings
84
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
AC Characteristics
Erase and Program Operations—S29GL256M Only
Parameter
Speed Options
Description
Unit
JEDEC
Std.
10
11
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVWL
WC
t
t
Address Setup Time
0
15
45
0
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
ASO
t
t
WLAX
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling Min
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Max
Max
45
0
DVWH
DS
DH
t
Data Hold Time
WHDX
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
t
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
µs
ns
µs
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
100
110
BUSY
t
Program Valid before Status Polling
4
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information.
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command is written). If the
suspend command was issued after t
, status data is available immediately after programming
POLL
resumes. See Figure 16.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
85
D a t a S h e e t
AC Characteristics
Erase and Program Operations—S29GL128M Only
Parameter
Speed Options
Uni
t
Description
JEDEC
Std.
90
10
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
90
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVWL
WC
t
t
Address Setup Time
0
15
45
0
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
ASO
t
t
WLAX
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling Min
AHT
t
t
t
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Min
Max
Max
45
0
DVWH
DS
DH
t
Data Hold Time
WHDX
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
20
20
0
CEPH
OEPH
t
t
t
t
GHWL
GHWL
t
t
0
ELWL
WHEH
WLWH
CS
CH
WP
t
CE# Hold Time
0
t
t
Write Pulse Width
35
30
240
60
54
0.5
250
50
t
t
Write Pulse Width High
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
µs
ns
µs
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
VHH
HH
CC
t
VCS
t
WE# High to RY/BY# Low
90
100
BUSY
t
Program Valid before Status Polling
4
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
, status data is available immediately
POLL
after programming resumes. See Figure 16.
86
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
AC Characteristics
Erase and Program Operations—S29GL064M Only
Parameter
Speed Options
Description
Unit
JEDEC
Std.
90
Min 90
Min
10
100
0
11
t
t
Write Cycle Time (Note 1)
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVWL
WC
t
t
Address Setup Time
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
Min
15
45
0
ASO
t
t
Min
WLAX
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
Min
AHT
t
t
t
Min
35
0
DVWH
WHDX
DS
DH
t
Data Hold Time
Min
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
Min
20
20
0
CEPH
OEPH
t
Min
t
t
t
Min
GHWL
GHWL
t
t
Min
0
ELWL
WHEH
WLWH
CS
CH
WP
t
CE# Hold Time
Min
0
t
t
Write Pulse Width
Min
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
Min
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
Typ
t
t
t
t
Typ
µs
WHWH1
WHWH2
WHWH1
WHWH2
Typ
Typ
sec
ns
µs
ns
µs
t
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
Min
VHH
HH
CC
t
V
Min
VCS
t
WE# High to RY/BY# Low
Max 90
Max
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
, status data is available immediately
POLL
after programming resumes. See Figure 16.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
87
D a t a S h e e t
AC Characteristics
Erase and Program Operations—S29GL032M Only
Parameter
Description
Speed Options
Unit
JEDEC
Std.
90
10
100
0
11
110
t
t
Write Cycle Time (Note 1)
Min 90
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVWL
WC
t
t
Address Setup Time
AS
t
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
Min
15
45
0
ASO
t
t
Min
WLAX
AH
t
Address Hold Time From CE# or OE# high during toggle bit polling Min
AHT
t
t
t
Data Setup Time
Min
Min
35
0
DVWH
DS
DH
t
Data Hold Time
WHDX
t
CE# High during toggle bit polling
OE# High during toggle bit polling
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
Min
20
20
0
CEPH
OEPH
t
Min
t
t
t
Min
GHWL
GHWL
t
t
Min
0
ELWL
WHEH
WLWH
CS
CH
WP
t
CE# Hold Time
Min
0
t
t
Write Pulse Width
Min
35
30
240
60
54
0.5
250
50
100
4
t
t
Write Pulse Width High
Min
WHDL
WPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
Typ
t
t
t
t
Typ
µs
WHWH1
WHWH2
WHWH1
WHWH2
Typ
Typ
sec
ns
µs
ns
µs
t
V
V
Rise and Fall Time (Note 1)
Setup Time (Note 1)
Min
VHH
HH
CC
t
Min
VCS
t
WE# High to RY/BY# Low
Max 90
Max
110
BUSY
t
Program Valid before Status Polling
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. If a program suspend command is issued within t , the device requires t before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
, status data is available immediately
POLL
after programming resumes. See Figure 16.
88
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
AC Characteristics
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tPOLL
tWP
WE#
Data
tWPH
tCS
tWHWH1
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
2. Illustration shows device in word mode.
is the true data at the program address.
OUT
Figure 16. Program Operation Timings
V
HH
V
or V
IL IH
V
or V
IL IH
ACC
t
t
VHH
VHH
Figure 17. Accelerated Program Timing Diagram
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
89
D a t a S h e e t
AC Characteristics
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write
Operation Status).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
tRC
Addresses
VA
tACC
tCE
VA
VA
tPOLL
CE#
tCH
tOE
OE#
WE#
tDF
tOH
tOEH
High Z
DQ7
Valid Data
Complement
Complement
True
High Z
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Figure 19. Data# Polling Timings
(During Embedded Algorithms)
90
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
AC Characteristics
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6 / DQ2
RY/BY#
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
WE#
Erase
Erase Suspend
Read
Suspend
Program
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to
toggle DQ2 and DQ6.
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
Description
Rise and Fall Time (See Note)
ID
All Speed Options
JEDEC
Std
Unit
ns
t
V
Min
Min
500
4
VIDR
t
RESET# Setup Time for Temporary Sector Unprotect
µs
RSP
Note: Not 100% tested.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
91
D a t a S h e e t
AC Characteristics
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 22. Temporary Sector Group Unprotect Timing Diagram
V
V
ID
IH
RESET#
SA, A6,
A3, A2,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect or Unprotect
Verify
40h
Data
60h
60h
Sector Group Protect: 150 µs,
Sector Group Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.
Figure 23. Sector Group Protect and Unprotect Timing Diagram
92
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Alternate CE# Controlled Erase and Program Operations—S29GL256M
Parameter
Speed Options
Description
Unit
JEDEC
Std.
10
11
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
Min
100
110
ns
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
0
45
45
0
AVWL
AS
AH
DS
DH
t
t
ELAX
DVEH
EHDX
t
t
t
t
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resume (that is, the program resume command has been written).
If the suspend command was issued after t
, status data is available immediately after
POLL
programming resumes. See Figure 24.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
93
D a t a S h e e t
Alternate CE# Controlled Erase and Program Operations—S29GL128M
Parameter
Speed Options
Description
Unit
JEDEC Std.
10
11
t
t
Write Cycle Time (Note 1)
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
100
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
Address Setup Time
0
45
45
0
AVWL
AS
AH
DS
DH
t
t
Address Hold Time
ELAX
DVEH
EHDX
t
t
t
Data Setup Time
t
Data Hold Time
t
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
WLEL
GHEL
t
0
WS
WH
t
t
WE# Hold Time
0
EHWH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
sec
ns
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
, status data is available immediately
POLL
after programming resumes. See Figure 24.
94
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Alternate CE# Controlled Erase and Program Operations—S29GL064M
Parameter
Speed Options
Description
Unit
JEDEC Std.
90
10
100
0
11
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
AVWL
AS
AH
DS
DH
t
t
45
35
0
ELAX
DVEH
EHDX
t
t
t
t
Data Hold Time
t
t
t
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
0
GHEL
WLEL
GHEL
t
0
WS
WH
t
t
WE# Hold Time
0
EHWH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 5)
t
t
t
t
µs
WHWH1
WHWH2
WHWH1
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
after programming resumes. See Figure 24.
, status data is available immediately
POLL
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
95
D a t a S h e e t
Alternate CE# Controlled Erase and Program Operations—S29GL032M
Parameter
Speed Options
Description
Unit
JEDEC Std.
90
10
100
0
11
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
90
110
ns
ns
ns
ns
ns
AVAV
WC
t
t
AVWL
AS
AH
DS
DH
t
t
45
35
0
ELAX
DVEH
EHDX
t
t
t
t
Data Hold Time
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
Typ
Typ
Min
Max
0
0
ns
ns
ns
ns
WLEL
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
35
25
240
60
54
0.5
50
4
ELEH
EHEL
CP
t
t
CE# Pulse Width High
CPH
Write Buffer Program Operation (Notes 2, 3)
Single Word Program Operation (Note 2)
Accelerated Single Word Program Operation (Note 2)
Sector Erase Operation (Note 2)
RESET# High Time Before Write
Program Valid before Status Polling (Note 4)
t
t
t
t
µs
WHWH1
WHWH1
WHWH2
sec
ns
WHWH2
t
RH
t
µs
POLL
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance for more information
3. For 1–16 words/1–32 bytes programmed.
4. If a program suspend command is issued within t
, the device requires t
before reading
POLL
POLL
status data, once programming resumes (that is, the program resume command has been
written). If the suspend command was issued after t
, status data is available immediately
POLL
after programming resumes. See Figure 24.
96
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
PBA for program
SA for program buffer to flash
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tPOLL
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
Data
tRH
PBD for program 29 for program buffer to flash
55 for erase
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
is the data written to the device.
OUT
4. Illustration shows device in word mode.
Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
97
D a t a S h e e t
Erase and Programming Performance
Parameter
(Notes)
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
0.5
32
3.5
64
sec
Excludes 00h
programming
prior to
erasure
(Note 6)
S29GL032M
S29GL064M
S29GL128M
S29GL256M
64
128
256
512
Chip Erase Time
sec
128
256
240
Total Write Buffer Program Time (3, 5)
µs
µs
Total Accelerated Effective Write Buffer Program Time
(4, 5)
200
Excludes
system level
overhead
S29GL032M
31.5
63
S29GL064M
Chip Program Time
(Note 7)
sec
S29GL128M
126
252
S29GL256M
Notes:
1. Typical program and erase times assume the following conditions: 25°C, V = 3.0V, 10,000
CC
cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C; Worst case V , 100,000 cycles.
CC
3. Effective programming time (typ) is 15 μs (per word), 7.5 μs (per byte).
4. Effective accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).
5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-
byte write buffer operation.
6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h
before erasure.
7. System-level overhead is the time required to execute the command sequence(s) for the program
command. See Table 34 and Table 35 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
For package types TA, TF, BA, BF, FA, FF (refer to Ordering Information Pages):
Parameter
Symbol
Parameter
Description
Test
Setup
Typ
Max
Unit
TSOP
BGA
6
7.5
5.0
12
pF
pF
pF
pF
pF
pF
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
V
= 0
IN
IN
4.2
8.5
5.4
7.5
3.9
TSOP
BGA
C
V
= 0
= 0
OUT
OUT
6.5
9
TSOP
BGA
C
V
IN
IN2
4.7
For package types TB, TC, BB, BC, (refer to Ordering Information Pages):
Parameter
Symbol
Parameter
Description
Test
Setup
Typ
Max
Unit
TSOP
BGA
8
8
10
10
12
12
10
10
25
20
pF
pF
pF
pF
pF
pF
pF
pF
C
Input Capacitance
Output Capacitance
V
= 0
IN
IN
TSOP
BGA
8.5
8.5
8
C
V
= 0
= 0
= 0
OUT
OUT
TSOP
BGA
C
C
Control Pin Capacitance
V
IN2
IN3
IN
IN
8
TSOP
BGA
20
15
RESET# and WP#/ACC Pin Capacitance
V
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
98
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
TS040—40-Pin Standard Thin Small Outline Package (TSOP)
Dwg rev AA; 10/99
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
99
D a t a S h e e t
Physical Dimensions
TSR040—40-Pin Standard and Reverse Thin Small Outline Package (TSOP)
REVERSE PIN OUT (TOP VIEW)
A2
3
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TSR 040
MO-142 (B) EC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
NOT APPLICABLE.
A
A1
A2
b1
b
c1
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
9.90 10.00 10.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
40
3324 \ 16-038.10a
100
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
TS048—48-Pin Standard and Reverse Thin Small Outline Package (TSOP)
STANDARD PIN OUT (TOP VIEW)
A2
2
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TS 048
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
MO-142 (B) EC
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
NOT APPLICABLE.
A
A1
A2
b1
b
c1
c
D
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3325 \ 16-038.10a
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
101
D a t a S h e e t
Physical Dimensions
TSR048—48-Pin Standard and Reverse Thin Small Outline Package (TSOP)
REVERSE PIN OUT (TOP VIEW)
A2
3
0.10 C
1
N
SEE DETAIL B
-A-
-B-
5
E
e
9
N
2
N
2
+1
5
A1
D1
4
C
D
SEATING
PLANE
B
A
0.08MM (0.0031")
M
C
A-B
6
S
B
b
7
SEE DETAIL A
WITH PLATING
c1
(c)
7
b1
BASE METAL
R
SECTION B-B
e/2
c
GAGE LINE
0.25MM (0.0098") BSC
0˚
-X-
X = A OR B
PARALLEL TO
SEATING PLANE
L
DETAIL A
DETAIL B
NOTES:
Package
TSR 048
MO-142 (B) EC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
Jedec
1
2
3
4
MIN
NOM MAX
1.20
Symbol
NOT APPLICABLE.
A
A1
A2
b1
b
c1
c
D
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.15
0.05
0.95
0.17
0.17
0.10
0.10
1.00
0.20
1.05
0.23
0.27
0.16
0.21
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
0.22
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15MM (.0059") PER SIDE.
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
D1
E
e
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
0.50 BASIC
L
0
R
N
0.50
0˚
0.60
3˚
0.70
5˚
8
9
LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
0.20
48
3326 \ 16-038.10a
102
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
TS056/TSR056—56-Pin Standard and Reverse Thin Small Outline Package (TSOP)
NOTES:
PACKAGE
TS/TSR 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
4
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5
6
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
---
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
D
19.90
18.30
20.00
18.40
20.20
18.50
D1
E
e
13.90
14.00
14.10
7
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
0.50 BASIC
L
0.50
0˚
0.60
3˚
0.70
5˚
8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
O
R
N
0.08
---
0.20
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
56
3160\38.10A
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
103
D a t a S h e e t
Physical Dimensions
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
104
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
LAC064—64-Pin 18 x 12 mm Package
D1
D
A
0.20 C
2X
eD
H
G
F
E
D
C
B
A
8
7
6
5
4
3
2
1
7
SE
eE
E
E1
A1 CORNER ID.
(INK OR LASER)
A1
CORNER
1.00 0.5
B
6
SD
0.20
2X
C
NXφb
φ 0.25 M C A
7
TOP VIEW
B
A1
φ 0.10 M
C
CORNER
BOTTOM VIEW
0.25
C
A
A2
A1
SEATING PLANE
C
0.15 C
SIDE VIEW
NOTES:
PACKAGE
JEDEC
LAC 064
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
18.00 mm x 12.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
NOM
---
MAX
NOTE
PROFILE HEIGHT
STANDOFF
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
---
1.40
---
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.40
0.60
---
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
A2
---
---
BODY THICKNESS
BODY SIZE
D
18.00 BSC.
12.00 BSC.
7.00 BSC.
7.00 BSC.
8
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
BODY SIZE
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
E1
MATRIX FOOTPRINT
MATRIX FOOTPRINT
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
MD
ME
N
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
8
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
64
φb
0.50
0.60
0.70
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
eD
eE
1.00 BSC.
1.00 BSC.
0.50 BSC.
NONE
BALL PITCH - D DIRECTION
BALL PITCH - E DIRECTION
SOLDER BALL PLACEMENT
8. NOT USED.
SD / SE
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
DEPOPULATED SOLDER BALLS
3243 \ 16-038.12d
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
105
D a t a S h e e t
Physical Dimensions
FBA048—48-Pin 6.15 x 8.15 mm Package
Dwg rev AF; 10/99
106
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
FBC048—48-Pin 8 x 9 mm Package
Dwg rev AF; 10/99
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
107
D a t a S h e e t
Physical Dimensions
FBE063—63-Pin 12 x 11 mm Package
Dwg rev AF; 10/99
108
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Physical Dimensions
FPT-48P-M19
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60 0.15
(.024 .006)
24
25
*
20.00 0.20
(.787 .008)
12.00 0.20
(.472 .008)
*18.40 0.20
(.724 .008)
1.10 –+00..0150
.043 –+..000024
(Mounting
height)
0.10 0.05
(.004 .002)
(Stand off height)
0.50(.020)
"A"
0.10(.004)
0.17 –+00..0083
0.22 0.05
(.009 .002)
M
0.10(.004)
.007 –+..000031
FPT-56P-M01
0.10 0.05
(.004 .002)
(Stand off)
LEAD No.
1
56
INDEX
0.22 0.05
(.009 .002)
M
0.10(.004)
1 14.00 0.10
*
(.551 .004)
0.50(.020)
28
29
Details of "A" part
1.10 –+00..0150
20.00 0.20(.787 .008)
2 18.40 0.10(.724 .004)
.043 +–..000024
(Mounting height)
0˚~8˚
*
0.17 0.03
.007 .001
0.60 0.15
(.024 .006)
0.25(.010)
"A"
0.08(.003)
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
109
D a t a S h e e t
Revision Summary
Revision A (January 29, 2004)
Initial Release.
Revision A1 (February 23, 2004)
Connection Diagrams
Removed 80-ball Fine-pitch BGA pinout.
Ordering Information
Added additional packing type.
Removed frame description from package material set.
Updated valid combinations to reflect the addition of new package type.
Added marking descriptions to all valid combination tables.
Word Program Command Sequence and Unlock Bypass
Command Sequence
Added these sections.
Figure 3, Write Buffer Programming Operation, Figure 4,
Program Operation
Updated figure.
Table 34, “Command Definitions( x16 Mode, BYTE# = V ),” on
IH
page 69
Updated table.
Added note 19.
Table 35, “Command Definitions (x8 Mode, BYTE# = V ),” on
IL
page 70
Updated table.
Added note 17.
Figure 7, Data# Polling Algorithm
Updated figure.
Erase and Program Operations and Alternate CE# Controlled
Erase and Program Operations
Updated TWHWHI description
Added Note 4.
Program Operation Timings, Chip/Sector Erase Operation
Timings, Toggle Bit Timings (During Embedded Algorithms),
Alternate CE# Controlled Write (Erase/
Program) Operation Timings figures
Updated figures.
Physical Dimensions
Removed BGA-63P-M02 and BGA-80P-M01. Added the TS040 package
110
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Revision A2 (February 25, 2004)
Connection Diagrams
Removed the 40-pin reverse TSOP diagram.
Updated the 48-pin standard TSOP diagram.
Removed the 48-pin reverse TSOP diagram.
Removed the 56-pin reverse TSOP diagram.
Ordering Information
Removed all references to package type R.
Autoselect Codes, (High Voltage Method)
Updated the R3, R4 column replacing -04 and -03 designators with -R4 and -R3 respectively.
Word Program Command Sequence
Included statements documenting word programming support for backward compatibility with
existing Flash drivers.
Physical Dimensions
Removed the BGA-80P-M02 diagram.
Revision A3 (February 26, 2004)
Distinctive Characteristics
Corrected typo in the Flexible Sector Architecture section.
Revision A4 (March 24, 2004)
CMOS Compatible
Removed VCC from Max for VOL
.
Erase and Program Operations-S29GL256M only
Corrected unit typos.
Erase and Program Operations-S29GL128M only
Corrected the minimum Data Setup Time.
Alternate CE# Controlled Erase and Program Operations-S29GL128M
Corrected the minimum CE# Pulse width.
TSOP Pin and BGA Package Capacitance: Pkg types TB, TC, BB, BC
Added CIN3.
Connection Diagrams
40-pin standard TSOP: Corrected pin 30 to be VIO
.
48-pin standard TSOP: Added superscripts to designators for pin 9, 13, 14, 15 and 47. Changed
pin 13 to A21. Added two notes below illustration.
56-pin standard TSOP: Added superscripts to designators for pin 1, 2 and 12. Changed pin 56 to
NC. Added three notes below illustration.
64-ball Fortified BGA: Corrected ball D8 to be VIO. Added superscripts to designators for ball D8,
F7, and F1. Added two notes below illustration.
63-ball Fine-pitch BGA: Added superscript to designator for Ball H7. Added one note below illus-
tration. Added connection diagrams for S29GL064M (model R0) and S29GL032M (model R0).
Pin Description
Added VIO description.
Logic Symbols
Added VIO on all models except R3 and R4.
Figure 3 Write Buffer Programming Operation
Corrected the DQ locations and added callouts to notes one through three.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
111
D a t a S h e e t
DC Characteristics
Corrected test conditions for ICC6
.
Revision A5 (April 30, 2004)
Ordering Information - S29GL032M
Added R5 and R6 model numbers to the breakout table.
Updated the Valid Combinations for BGA packages table to reflect model numbers R5 and R6.
Ordering Information - S29GL064M
Revised R8 and R9 model numbers on the breakout table.
Updated the Valid Combinations for TSOP packages table.
Ordering Information - S29GL0128M
Added R8 and R9 model numbers to the breakout table.
Revised the Package Material Set options on the breakout table.
Updated the Valid Combinations for TSOP packages table.
Ordering Information - S29GL256M
Revised the Package Material Set options on the breakout table.
Connection Diagrams (56-Pin TSOP)
Added a callout to Note 3 for pin 15.
Device Geometry Definition table
Revised the data and description information for addresses: 28h/50h and
29h/52h.
Primary Vendor Specific Extended Query table
Revised the data and description information for addresses: 45h/8Ah (x16/x8)
Revised the data information for addresses: 4Ch/98h (x16/x8)
Erase and Programming Performance table
Revised notes 1 and 2 below the table.
Revision B0 (May 24, 2004)
Global
Converted to full datasheet status.
Figure 17, Autoselect Codes, (High Voltage Method)
Corrected typos in description.
Added values for R5, R6, R7 description for cycle 1-3.
Added R8 and R9 to Model Number.
Revision B1 (August 2, 2004)
Ordering Information-S29GL032M
Added the following temperature range: “C = Commercial (0°C to +70°C)'.
Commercial temperature range options added for 90ns speeds.
Global Change
S29GL032M, S29GL064M, S29GL128M, S29GL236M ordering options pages:
Updated note 3 with the following “...TSOPs can be packed in Types 0 and 3; BGAs can be packed
in Types 0, 2, or 3.
Revision B2 (September 8, 2004)
Connection Diagram - 64-ball Fortified BGA
Modified note 4.
112
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
D a t a S h e e t
Logic Symbol-S29GL032M (Models R3, R4)
Added models R5 and R6 to the logic symbol.
Logic Symbol-S29GL064M (Models R1, R2)
Added models R8 & R9 to the logic symbol.
S29GL032M Valid Combinations
Corrected ordering part numbers for LAA064 packages.
Physical Dimensions
Renamed the BGA-48P-M20 package as the FBG048 package.
Ordering Information
Added footnotes to indicate TSOP Pb-free leadframe plating.
Revision B3 (October 9, 2004)
General
Updated all references to Figures, Tables, and Headings to reflect page number (active link)
Updated tables 20, 21, and 22
Updated tables 24, 25, and 26
S29GL064M Valid combination
Corrected ordering part numbers for TS056 packages
S29GL032M Sector Protection/Uprotection Address Tables
Corrected table titles
S29GL064M Sector Protection/Uprotection Address Tables
Corrected table titles
Primary Vendor-Specific Extended Query
Corrected CFI data at address 48h/90h to be 0001h
DC Characteristics
Updated note 2
Figure 15, Reset Timing
Added tRH
Revision B4 (January 10, 2005)
Secured Sector Flash Memory Region
Updated Secured Silicon Sector address table with addresses in x8-mode
DC Characteristics, CMOS Compatible
Corrected WP#/ACC input load current footnote
Document
Updated cross-references and format.
Valid Combination Tables
Added notes to the 128 Mb and 256 Mb combination tables.
Revision B5 (December 13, 2005)
Added Supersession text.
Corrected typos on connection diagrams and in CFI table.
February 7, 2007 S29GL-M_00_B8
S29GL-M MirrorBitTM Flash Family
113
D a t a S h e e t
Revision B6 (October 10, 2006)
Global
Deleted FBG048 package from S29GL032M device. Added “retired product” status text to cover
page, and first page and Ordering Information sections of data sheet.
Revision B7 (January 22, 2007)
AC Characteristics
Erase/Program Operations table, all devices: Changed tBUSY to a maximum specification.
Revision B8 (February 7, 2007)
Global
Updated retired product status text.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion Inc. Spansion Inc. reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion Inc. assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright © 2004–2007 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof, are trade-
marks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trademarks of their re-
spective companies.
114
S29GL-M MirrorBitTM Flash Family
S29GL-M_00_B8 February 7, 2007
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