S29GL032M11BAIR52_技术文档

D a t a S h e e t

General Description

The S29GL256/128/064/032M family of devices are 3.0 V single power Flash memory manufac-

tured using 0.23 µm MirrorBit technology. The S29GL256M is a 256†Mbit, organized as

16,777,216 words or 33,554,432 bytes. The S29GL128M is a 128 Mbit, organized as 8,388,608

words or 16,777,216 bytes. The S29GL064M is a 64 Mbit, organized as 4,194,304 words or

8,388,608 bytes. The S29GL032M is a 32 Mbit, organized as 2,097,152 words or 4,194,304

bytes. Depending on the model number, the devices have an 8-bit wide data bus only, 16-bit wide

data bus only, or a 16-bit wide data bus that can also function as an 8-bit wide data bus by using

the BYTE# input. The devices can be programmed either in the host system or in standard EPROM

programmers.

Access times as fast as 90 ns (S29GL128M, S29GL064M, S29GL032M) or 100 ns (S29GL256M)

are available. Note that each access time has a specific operating voltage range (V ) as specified

CC

in Product Selector Guide and Ordering Information. Package offerings include 40-pin TSOP, 48-

pin TSOP, 56-pin TSOP, 48-ball fine-pitch BGA, 63-ball fine-pitch BGA and 64-ball Fortified BGA,

depending on model number. Each device has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

Each device requires only a single 3.0 volt power supply for both read and write functions. In

addition to a V

input, a high-voltage accelerated program (ACC) feature provides shorter

CC

programming times through increased current on the WP#/ACC input. This feature is intended to

facilitate factory throughput during system production, but may also be used in the field if desired.

The device is entirely command set compatible with the JEDEC single-power-supply Flash

standard. Commands are written to the device using standard microprocessor write timing.

Write cycles also internally latch addresses and data needed for the programming and erase

operations.

The sector erase architecture allows memory sectors to be erased and reprogrammed without

affecting the data contents of other sectors. The device is fully erased when shipped from the

factory.

Device programming and erasure are initiated through command sequences. Once a program or

erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle)

status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the opera-

tion is complete. To facilitate programming, an Unlock Bypass mode reduces command

sequence overhead by requiring only two write cycles to program data instead of four.

Hardware data protection measures include a low V detector that automatically inhibits write

CC

operations during power transitions. The hardware sector protection feature disables both pro-

gram and erase operations in any combination of sectors of memory. This can be achieved in-

system or via programming equipment.

The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation

in a given sector to read or program any other sector and then complete the erase operation. The

Program Suspend/Program Resume feature enables the host system to pause a program op-

eration in a given sector to read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the device, after

which it is then ready for a new operation. The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the device, enabling the host system to read boot-

up firmware from the Flash memory device.

The device reduces power consumption in the standby mode when it detects specific voltage

levels on CE# and RESET#, or when addresses are stable for a specified period of time.

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S29GL-M MirrorBit^TMFlash Family

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The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the

WP#/ACC pin or WP# pin, depending on model number. The protected sector is still protected

even during accelerated programming.

The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected, no further changes within the sector can

occur.

Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience

to produce the highest levels of quality, reliability and cost effectiveness. The device electrically

erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed

using hot electron injection.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Table of Contents

Table 24. S29GL064M (Models R1, R2, R8, R9) Sector Group

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6

S29GL256M, S29GL128M, S29GL064M, and S29GL032M .........................6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .8

For S29GL064M (model R0) only. ..................................................................13

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

S29GL064M (Models R1, R2, R8, R9) .............................................................17

S29GL064M (Models R3, R4) ...........................................................................17

S29GL064M (Model R5) .................................................................................... 18

S29GL064M (Model R6, R7) ............................................................................ 18

S29GL128M ............................................................................................................ 18

Protection/Unprotection Addresses .......................................45

Table 25. S29GL064M (Model R3) Sector Group Protection/

Unprotection Address Table .................................................45

Table 27. S29GL064M (Model R5) Sector Group Protection/

Unprotection Addresses ......................................................46

Table 28. S29GL064M (Models R6, R7) Sector Group Protection/

Unprotection Address .........................................................46

Table 29. S29GL128M Sector Group Protection/Unprotection

Addresses .........................................................................46

Table 30. S29GL256M Sector Group Protection/Unprotection

Addresses .........................................................................47

Temporary Sector Group Unprotect ..........................................................48

Figure 1. Temporary Sector Group Unprotect Operation.......... 48

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

....................................................................................... 49

Secured Silicon Sector Flash Memory Region ...........................................50

Ordering Information-S29GL032M . . . . . . . . . . . . 19

S29GL032M Standard Products ...................................................................... 19

Table 1. S29GL032M Ordering Options ................................. 20

Ordering Information-S29GL064M . . . . . . . . . . . . 21

S29GL064M Standard Products ...................................................................... 21

Table 2. S29GL064M Ordering Options ................................. 22

Ordering Information-S29GL128M . . . . . . . . . . . .23

Table 3. S29GL128M Ordering Options ................................. 24

Ordering Information-S29GL256M . . . . . . . . . . . .25

Table 4. S29GL256M Ordering Options ................................. 25

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .26

Table 5. Device Bus Operations ........................................... 26

Word/Byte Configuration ............................................................................... 26

Requirements for Reading Array Data ........................................................ 26

Page Mode Read ..................................................................................................27

Writing Commands/Command Sequences .................................................27

Write Buffer .....................................................................................................27

Accelerated Program Operation ...............................................................27

Autoselect Functions .................................................................................... 28

Standby Mode ...................................................................................................... 28

Automatic Sleep Mode ..................................................................................... 28

RESET#: Hardware Reset Pin ........................................................................ 28

Output Disable Mode ....................................................................................... 29

Table 6. S29GL032M (Model R0) Sector Addresses ................ 29

Table 7. S29GL032M (Models R1, R2) Sector Addresses ......... 29

Table 8. S29GL032M (Models R3, R5) Top Boot Sector Addresses

....................................................................................... 30

Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Addresses

30

Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Addresses

....................................................................................... 32

Table 14. S29GL064M (Model R5) Sector Addresses ............... 35

Table 17. S29GL256M Sector Address Table ......................... 39

Autoselect Mode .................................................................................................43

Table 18. Autoselect Codes, (High Voltage Method) ............... 43

Table 19. S29GL032M (Model R0) Sector Group Protection/

Unprotection Addresses ...................................................... 44

Table 20. S29GL032M (Models R1, R2) Sector Group Protection/

Unprotection Addresses ...................................................... 44

Table 21. S29GL032M (Models R3, R5) Sector Group Protection/

Unprotection Address Table ................................................ 44

Table 22. S29GL032M (Models R4, R6) Sector Group Protection/

Unprotection Address Table ................................................ 45

Table 23. S29GL064M (Model 00) Sector Group Protection/

Unprotection Address Table ................................................ 45

Write Protect (WP#) ........................................................................................ 51

Hardware Data Protection .............................................................................. 51

Low VCC Write Inhibit ................................................................................ 51

Write Pulse “Glitch” Protection ................................................................ 51

Logical Inhibit .................................................................................................... 51

Power-Up Write Inhibit ................................................................................ 51

Common Flash Memory Interface (CFI) . . . . . . . 52

Table 31. CFI Query Identification String ...............................52

Table 32. System Interface String ........................................52

Table 33. Device Geometry Definition ...................................53

Table 34. Primary Vendor-Specific Extended Query ................53

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 54

Reading Array Data ........................................................................................... 54

Reset Command ................................................................................................. 54

Autoselect Command Sequence ................................................................... 55

Enter/Exit Secured Silicon Sector Command Sequence ......................... 55

Word Program Command Sequence ...................................................... 55

Unlock Bypass Command Sequence ........................................................ 56

Write Buffer Programming ......................................................................... 56

Accelerated Program .................................................................................... 57

Figure 3. Write Buffer Programming Operation....................... 58

Figure 4. Program Operation ............................................... 59

Program Suspend/Program Resume Command Sequence .................... 59

Figure 5. Program Suspend/Program Resume........................ 60

Chip Erase Command Sequence ...................................................................60

Sector Erase Command Sequence .................................................................61

Figure 6. Erase Operation ................................................... 62

Erase Suspend/Erase Resume Commands ..................................................62

Command Definitions .......................................................................................64

Table 35. Command Definitions( x16 Mode, BYTE# = V_IH) ......64

Table 36. Command Definitions (x8 Mode, BYTE# = V_IL) .........65

Write Operation Status ...................................................................................66

DQ7: Data# Polling ...........................................................................................66

Figure 7. Data# Polling Algorithm ........................................ 67

RY/BY#: Ready/Busy# ....................................................................................... 67

DQ6: Toggle Bit I ............................................................................................... 67

Figure 8. Toggle Bit Algorithm ............................................. 69

DQ2: Toggle Bit II ..............................................................................................69

DQ5: Exceeded Timing Limits ........................................................................70

DQ3: Sector Erase Timer ................................................................................70

DQ1: Write-to-Buffer Abort ............................................................................ 71

Table 37. Write Operation Status .........................................71

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 72

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S29GL-M MirrorBit^TMFlash Family

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Figure 9. Maximum Negative Overshoot Waveform................. 72

Figure 10. Maximum Positive Overshoot Waveform................. 72

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 23. Sector Group Protect and Unprotect Timing Diagram 86

Alternate CE# Controlled Erase and Program Operations-S29GL064M

...................................................................................................................................88

Alternate CE# Controlled Erase and Program Operations-S29GL032M

...................................................................................................................................88

Figure 24. Alternate CE# Controlled Write (Erase/

CMOS Compatible .............................................................................................73

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 11. Test Setup ......................................................... 74

Table 38. Test Specifications ............................................... 74

Program) Operation Timings................................................ 89

Erase and Programming Performance . . . . . . . . 90

TSOP Pin and BGA Package Capacitance . . . . . .91

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 92

TS040—40-Pin Standard Thin Small Outline Package ............................92

TSR040—40-Pin Standard/Reverse Thin Small Outline Package

(TSOP) ................................................................................................................... 93

TS048—48-Pin Standard/Reverse Thin Small Outline Package

(TSOP) ...................................................................................................................94

TSR048—48-Pin Standard/Reverse Thin Small Outline Package

(TSOP) ................................................................................................................... 95

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package

(TSOP) ...................................................................................................................96

LAA064—64-Ball Fortified Ball Grid Array (FBGA) ............................... 97

LAC064—64-Pin 18 x 12 mm Package ..........................................................98

FBA048—48-Pin 6.15 x 8.15 mm Package ....................................................99

FBC048—48-Pin 8 x 9 mm Package .......................................................... 100

FBE063—63-Pin 12 x 11 mm Package .............................................................101

FPT-48P-M19 .......................................................................................................102

FPT-56P-M01 .......................................................................................................102

FBG048—48-Pin 8 x 6 mm Package ...........................................................103

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 104

Key to Switching Waveforms . . . . . . . . . . . . . . . .74

Figure 12. Input Waveforms and Measurement Levels............. 74

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .75

Read-Only Operations-S29GL256M Only ...................................................75

Read-Only Operations-S29GL128M only .....................................................75

Read-Only Operations-S29GL064M Only ..................................................75

Read-Only Operations-S29GL032M only ....................................................76

Figure 13. Read Operation Timings....................................... 76

Figure 14. Page Read Timings.............................................. 77

Hardware Reset (RESET#) ...............................................................................77

Figure 15. Reset Timings..................................................... 78

Erase and Program Operations-S29GL256M Only ...................................79

Erase and Program Operations-S29GL128M Only ..................................80

Erase and Program Operations-S29GL064M Only .................................. 81

Erase and Program Operations-S29GL032M Only .................................. 82

Figure 16. Program Operation Timings.................................. 83

Figure 17. Accelerated Program Timing Diagram .................... 83

Figure 18. Chip/Sector Erase Operation Timings..................... 84

Figure 19. Data# Polling Timings (During Embedded Algorithms)

....................................................................................... 84

Figure 20. Toggle Bit Timings (During Embedded Algorithms) .. 85

Figure 21. DQ2 vs. DQ6...................................................... 85

Temporary Sector Unprotect ........................................................................ 85

Figure 22. Temporary Sector Group Unprotect Timing Diagram 86

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Product Selector Guide

S29GL256M, S29GL128M, S29GL064M, and S29GL032M

Part Number

Speed Option

S29GL256M

S29GL128M

S29GL064M

S29GL032M

10

100

30

11

110

30

90

25

10

100

30

90

10

11

90

10

11

Max. Access Time (ns)

90

25

100 110

90

25

100 110

Max. CE# Access Time (ns)

Max. Page Access Time (ns)

Max. OE# Access Time (ns)

30

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S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

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Block Diagram

DQ15–DQ0 (A-1)

RY/BY#

V_CC

V_SS

Sector Switches

Erase Voltage

Generator

Input/Output

Buffers

RESET#

WE#

WP#/ACC

BYTE#

State

Control

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A_Max**–A0

** A_MaxGL256M = A23

A

_MaxGL128M = A22

A_MaxGL064M = A21 (A_MaxGL064M-00 = A22)

_MaxGL032M = A20 (A_MaxGL032M-00 = A21)

A

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Connection Diagrams

A17

V_SS

A16

A15

A14

A13

A12

A11

A9

1

2

3

4

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

40-Pin Standard TSOP

5

6

7

A8

8

WE#

RESET#

ACC

RY/BY#

A18

A7

9

10

11

12

13

14

15

16

17

18

19

20

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

A6

A5

A4

A3

A2

A1

CE#

A0

A15

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

2

BYTE#

A14

A13

A12

A11

A10

A9

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

48-Pin Standard TSOP

A8

2

A19

9

A20

WE#

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

RESET#

1,2

A21

2

WP#/ACC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

Notes:

1. Pin 13 is NC on S29GL032M.

2. Pin 9 is A21, Pin 13 is ACC, Pin 14 is WP#, Pin 15 is A19, and Pin 47

is V_IOon S29GL064M (models R6, R7).

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S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Connection Diagrams

For S29GL064M (model R0) only

NC

A17

V_SS

A20

A19

A10

DQ7

DQ6

DQ5

DQ4

V_CC

V_IO

NC

A22

A16

A15

A14

A13

A12

A11

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

48-Pin Standard TSOP

9

A8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

ACC

RY/BY#

A18

A7

A21

DQ3

DQ2

DQ1

DQ0

OE#

V_SS

CE#

A0

NC

A6

A5

A4

A3

A2

A1

NC

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Connection Diagrams

1

A23

A22

1

2

3

4

5

6

7

8

9

56 NC

2

55 NC

A15

A14

A13

A12

A11

A10

A9

54 A16

53 BYTE#

52 V_SS

56-Pin Standard TSOP

51 DQ15/A-1

50 DQ7

49 DQ14

48 DQ6

47 DQ13

46 DQ5

45 DQ12

44 DQ4

43 V_CC

A8 10

A19 11

A20 12

WE# 13

RESET# 14

A21³15

WP#/ACC 16

RY/BY# 17

A18 18

A17 19

A7 20

42 DQ11

41 DQ3

40 DQ10

39 DQ2

38 DQ9

37 DQ1

36 DQ8

35 DQ0

34 OE#

33 V_SS

A6 21

A5 22

A4 23

A3 24

A2 25

32 CE#

31 A0

A1 26

NC 27

30 NC

NC 28

29 V_IO

Notes:

1. Pin 1 is NC on S29GL128M, 29GL064M, and

S29GL032M.

2. Pin 2 is NC on S29GL064M, and S29GL032M.

3. Pin 15 is NC on S29GL032M.

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S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Connection Diagrams

64-ball Fortified BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

NC

H8

4

A22²

A23³

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

BYTE#⁵DQ15/A-1

V_SS

A13

A12

A14

A15

A16

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET# A21¹

A19

DQ5

DQ12

DQ4

V_CC

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

B1

C1

D1

E1

F1

G1

NC

H1

4

NC

V_IO

Notes:

1. Ball C5 is NC on S29GL032M.

2. Ball B8 is NC on S29GL064M and S29GL032M.

3. Ball C8 is NC on S29GL128M, S29GL064M and S29GL032M.

4. Ball D8 and Ball F1 are NC on S29GL064M (models R3, R4) and

S29GL032M (models R3, R4, R5, R6).

5. Ball F7 is NC on S29GL064M (model R5).

Special Package Handling Instructions

Special handling is required for Flash Memory products in moulded packages (TSOP and BGA).

The package and/or data integrity may be compromised if the package body is exposed to tem-

peratures above 150°C for prolonged periods of time.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Connection Diagrams

63-Ball Fine-Pitch BGA

Top View, Balls Facing Down

L8

M8

A8

B8

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

BYTE#¹DQ15/A

-1

V_SS

NC*

A13

A12

A14

A15

A16

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

Note: Ball H7 is V_IOon S29GL064M (model R5).

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA).

The package and/or data integrity may be compromised if the package body is exposed to tem-

peratures above 150°C for prolonged periods of time.

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S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Connection Diagrams

For S29GL064M (model R0) only.

63-Ball Fine-Pitch BGA

Top View, Balls Facing Down

L8

M8

A8

B8

NC*

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

A7

B7

A14

A13

A15

A16

A17

NC

A20

V

SS

NC*

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A11

A12

A19

A10

DQ6

DQ7

C5

D5

E5

F5

G5

H5

J5

K5

WE# RESET# A22

NC

DQ5

NC

V

DQ4

CC

C4

D4

E4

F4

G4

H4

J4

K4

RY/BY# ACC

NC

DQ2

DQ3

V

A21

IO

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A18

DQ0

NC

DQ1

A2

L2

M2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

NC*

CE#

OE#

V

NC*

SS

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA).

The package and/or data integrity may be compromised if the package body is exposed to tem-

peratures above 150°C for prolonged periods of time.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

13

D a t a S h e e t

Connection Diagrams

48-ball Fine-pitch BGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

A3 B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V_SS

CE#

OE#

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA).

The package and/or data integrity may be compromised if the package body is exposed to tem-

peratures above 150°C for prolonged periods of time.

14

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Connection Diagrams

For S29GL032M (model R0) only.

48-Ball Fine-Pitch BGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A14

A13

A15

A16

A17

NC

A20

V

SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

D6

H5

D7

A11

A12

A19

A10

A4

B4

C4

D4

E4

D5

F4

G4

H4

D4

WE# RESET#

NC

V

CC

A3

B3

C3

D3

E3

D2

F3

D3

G3

H3

RY/BY# ACC

NC

V

A21

IO

A2

A7

B2

C2

A6

D2

A5

E2

D0

F2

G2

NC

H2

D1

A18

NC

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V

SS

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages (TSOP and BGA).

The package and/or data integrity may be compromised if the package body is exposed to tem-

peratures above 150°C for prolonged periods of time.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

15

D a t a S h e e t

Pin Description

A23–A0

A22–A0

A21–A0

A20–A0

DQ7–DQ0

DQ14–DQ0

DQ15/A-1

=

24 Address inputs

23 Address inputs

22 Address inputs

21 Address inputs

8 Data inputs/outputs

15 Data inputs/outputs

DQ15 (Data input/output, word mode), A-1 (LSB

Address input, byte mode)

Chip Enable input

Output Enable input

Write Enable input

CE#

OE#

WE#

WP#/ACC

=

Hardware Write Protect input/Programming

Acceleration input

ACC

WP#

RESET#

RY/BY#

BYTE#

=

Acceleration input

Hardware Write Protect input

Hardware Reset Pin input

Ready/Busy output

Selects 8-bit or 16-bit mode

3.0 volt-only single power supply

(see Product Selector Guide for speed options and

voltage supply tolerances)

Device Ground

V

CC

V

=

SS

NC

Pin Not Connected Internally

Output Buffer Power

V

IO

16

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Logic Symbols

S29GL032M (Model R0)

S29GL032M (Models R1, R2)

22

21

A21–A0

A20–A0

8

16 or 8

DQ15–DQ0

DQ7–DQ0

CE#

OE#

WE#

CE#

OE#

WE#

(A-1)

ACC

WP#/ACC

RESET#

BYTE#

V

RY/BY#

IO

V

IO

S29GL032M (Models R3, R4, R5, R6)

S29GL064M (Model R0)

21

23

A20–A0

A22–A0

16 or 8

8

DQ15–DQ0

(A-1)

DQ7–DQ0

CE#

OE#

WE#

CE#

OE#

WE#

WP#/ACC

RESET#

ACC

RESET#

V

IO

RY/BY#

BYTE#

S29GL064M (Models R1, R2, R8, R9)

S29GL064M (Models R3, R4)

22

A21–A0

16 or 8

DQ15–DQ0

(A-1)

DQ15–DQ0

CE#

OE#

WE#

CE#

OE#

WE#

(A-1)

WP#/ACC

RESET#

BYTE#

WP#/ACC

RESET#

BYTE#

RY/BY#

V

IO

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

17

D a t a S h e e t

Logic Symbols

S29GL064M (Model R5)

S29GL064M (Model R6, R7)

22

A21–A0

16

DQ15–DQ0

CE#

OE#

WE#

OE#

WE#

WP#

ACC

RESET#

V

RY/BY#

IO

V

IO

S29GL128M

S29GL256M

23

24

A22–A0

16 or 8

A23–A0

16 or 8

DQ15–DQ0

(A-1)

DQ15–DQ0

(A-1)

CE#

OE#

WE#

WP#/ACC

RESET#

WP#/ACC

RESET#

BYTE#

RY/BY#

V

IO

V

IO

18

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Ordering Information-S29GL032M

For new designs, S29GL032A supersedes S29GL032M, and is the factory-recommended migration path. Please refer to the S29GL-A Datasheet for specifications and ordering information.

S29GL032M Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid Combination)

is formed by a combination of the following:

S29GL032M

10

T

A

I

R1

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER

R0

R1

=

x8, V_CC=3.0-3.6V, Uniform sector device

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address sector

protected when WP#/ACC=V_IL

R2

R3

R4

R5

R6

=

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Top boot sector device, top two address sectors

protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Bottom boot sector device, bottom two

address sectors protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Top boot sector device, top two address sectors

protected when WP#/ACC=V_IL,FBG048 package only

x8/x16, V_CC=3.0-3.6V, Bottom boot sector device, bottom two

address sectors protected when WP#/ACC=V_ILFBG048 package only

TEMPERATURE RANGE

I

=

Industrial (–40

°

C to +85

°

C)

C

Commercial (0°C to +70°

PACKAGE MATERIAL SET

A

F

B

C

=

Standard

Pb-Free

Standard

Pb-Free

PACKAGE TYPE

T

B

F

=

Thin Small Outline Package (TSOP) Standard Pinout

Fine-pitch Ball-Grid Array Package

Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL032M

32 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™

Process Technology, 3.0 Volt-only Read, Program, and Erase

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

19

D a t a S h e e t

Table 1. S29GL032M Ordering Options

S29GL032M Valid Combinations

Package Description

(Notes)

Device

Number

Speed

Option

Package, Material,

Model

Packing

Type

& Temperature Range

TAC,TFC

BAC,BFC

TAC,TFC

FAC,FFC

TAC,TFC

BAC,BFC

FAC,FFC

TAI,TFI

Number

TS040 (2, 3, 5)

TSOP

R0

FBC048 (4)

Fine-Pitch BGA

TSOP

TS056 (2, 3, 5)

LAA064 (4)

R1,R2

90

Fortified BGA

TSOP

TS048 (2, 3, 5)

FBC048 (4)

R3,R4

Fine-Pitch BGA

Fortified BGA

TSOP

LAA064 (4)

TS040 (2, 3, 5)

FBC048 (4)

0,2,3

(Note 1)

S29GL032M

R0

BAI,BFI

Fine-Pitch BGA

TSOP

TAI,TFI

TS056 (2, 3, 5)

LAA064 (4)

R1,R2

FAI,FFI

Fortified BGA

TSOP

90, 10, 11

TAI,TFI

TS048 (2, 3, 5)

FBC048 (4)

BAI,BFI

Fine-Pitch BGA

Fortified BGA

TSOP

R3,R4

R5,R6

FAI,FFI

LAA064 (4)

TBI,TCI

FPT-48P-M19 (3, 6)

FBG048 (4)

BAI,BFI

Fine-Pitch BGA

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can

be packed in Types 0, 2, or 3.

2. This package is recommended for new designs using TSOPs.

3. TSOP package marking omits packing type designator from the ordering part number.

4. BGA package marking omits leading “S29” and packing type designator from the ordering part

number.

5. 100% Matte Sn is used for Pb-free TSOP plating.

6. SnBi is used for Pb-free TSOP plating.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

20

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Ordering Information-S29GL064M

For new designs, S29GL064A supersedes S29GL064M, and is the factory-recommended migration path. Please refer to the S29GL-A Datasheet for specifications and ordering information.

S29GL064M Standard Products

Standard products are available in several packages and operating ranges. The order number (Valid Combination)

is formed by a combination of the following:

S29GL064M

90

T

A

I

R1

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

MODEL NUMBER

R0

R1

=

x8, V_CC=3.0-3.6V, Uniform sector device

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address

sector protected when WP#/ACC=V_IL

R2

R3

R4

=

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Top boot sector device, top two address

sectors protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Bottom boot sector device, bottom two

address sectors protected when WP#/ACC=V_IL

R5

R6

=

x16, V_CC=3.0-3.6V, Uniform sector device

x16, V_CC=3.0-3.6V, Uniform sector device, highest address sector

protected when WP#=V_IL

R7

R8

R9

=

x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#=V_IL

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address

sector protected when WP#/ACC=V_IL, FPT-56P-M01 package only

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL, FPT-56P-M01 package only

TEMPERATURE RANGE

I

= Industrial (–40°C to +85°C)

PACKAGE MATERIAL SET

A

F

B

C

D

=

Standard

Pb-Free

Standard

Pb-Free

PACKAGE TYPE

T

B

F

=

Thin Small Outline Package (TSOP) Standard Pinout

Fine-pitch Ball-Grid Array Package

Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL064M

64 Megabit Page-Mode Flash Memory Manufactured using 0.23 um MirrorBit^TM

Process Technology, 3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

21

D a t a S h e e t

Table 2. S29GL064M Ordering Options

S29GL064M Valid Combinations

Package Description

(Notes)

Device

Number

Speed

Option

Package, Material, &

Temperature Range

Model

Number

Packing

Type

R0,R3,R4,R6,R7

R1,R2

TS048 (2, 3, 5)

TAI, TFI

TS056 (2, 3, 5)

FPT-48P-M19 (3, 6)

FPT-56P-M01 (3, 6)

FBE063 (4, 6)

TSOP

TBI, TCI

TAI, TDI

BAI, BFI

FAI, FFI

R2,R7

0,2,3

(Note 1)

S29GL064M

90, 10, 11

R9

R0,R3,R4,R5

R1,R2,R3,R4,R5

Fine-Pitch BGA

Fortified BGA

LAA064 (4)

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can

be packed in Types 0, 2, or 3.

2. This package is recommended for new designs using TSOPs.

3. TSOP package marking omits packing type designator from the ordering part number.

4. BGA package marking omits leading “S29” and packing type designator from the ordering part

number.

5. 100% Matte Sn is used for Pb-free TSOP plating.

6. SnBi is used for Pb-free TSOP plating.

22

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Ordering Information-S29GL128M

For new designs, S29GL128N supersedes S29GL128M, and is the factory-recommended migration path. Please refer to the S29GL-N Datasheet for specifications and ordering information.

Standard products are available in several packages and operating ranges. The order number

(Valid Combination) is formed by a combination of the following:

S29GL128M

90

T

A

I

R1

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

Model Number

R1

R2

R8

R9

=

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address

sector protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address

sector protected when WP#/ACC=V_IL, FPT-56P-M01 package only

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL, FPT-56P-M01 package only

TEMPERATURE RANGE

I

= Industrial (–40°C to +85°C)

PACKAGE MATERIAL SET

A

F

D

=

Standard

Pb-Free

PACKAGE TYPE

T

F

=

Thin Small Outline Package (TSOP) Standard Pinout

Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL128M

128 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™

Process Technology, 3.0 Volt-only Read, Program, and Erase

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

23

D a t a S h e e t

Table 3. S29GL128M Ordering Options

S29GL128M Valid Combinations

Package Descriptions

(Notes)

Base Ordering

Part Number

Speed

Option

Package Type, Material,

Model

Packing

Type

& Temperature Range

TAI, TFI

Number

R1, R2

R9

TS056 (2, 3, 5)

TSOP

90, 10, 11

(Note 7)

S29GL128M

TAI, TDI

0, 2, 3 (Note 1)

FPT-56P-M01 (3, 6)

LAA064 (4)

FAI, FFI

R1, R2

Fortified-BGA

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can

be packed in Types 0, 2, or 3.

2. This package is recommended for new designs using TSOPs.

3. TSOP package marking omits packing type designator from the ordering part number.

4. BGA package marking omits leading “S29” and packing type designator from the ordering part

number.

5. 100% Matte Sn is used for Pb-free TSOP plating.

6. SnBi is used for Pb-free TSOP plating.

7. Contact your Spansion representative for availability of the 90ns speed option for LAA064.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

24

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Ordering Information-S29GL256M

For new designs, S29GL256N supersedes S29GL256M, and is the factory-recommended migration path. Please refer to the S29GL-N Datasheet for specifications and ordering information.

Standard products are available in several packages and operating ranges. The order number

(Valid Combination) is formed by a combination of the following:

S29GL256M

11

T

A

I

R1

0

PACKING TYPE

0

2

3

=

Tray

7” Tape and Reel

13” Tape and Reel

Model Number

R1

=

x8/x16, V_CC=3.0-3.6V, Uniform sector device, highest address

sector protected when WP#/ACC=V_IL

R2

=

x8/x16, V_CC=3.0-3.6V, Uniform sector device, lowest address sector

protected when WP#/ACC=V_IL

TEMPERATURE RANGE

I

= Industrial (–40°C to +85°C)

PACKAGE MATERIAL SET

A

F

=

Standard

Pb-Free

PACKAGE TYPE

T

F

=

Thin Small Outline Package (TSOP) Standard Pinout

Fortified Ball-Grid Array Package

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

S29GL256M

256 Megabit Page-Mode Flash Memory Manufactured using 0.23 µm MirrorBit™

Process Technology, 3.0 Volt-only Read, Program, and Erase

Table 4. S29GL256M Ordering Options

S29GL256M Valid Combinations

Package Description

(Notes)

Device

Number

Speed

Option

Package, Material,

& Temperature Range

Model

Number

Packing

Type

TAI,TFI

FAI,FFI

TS056 (2, 3, 4)

LAC064 (3)

TSOP

10, 11

(Note 5)

0,2,3

(Note 1)

S29GL256M

R1,R2

Fortified BGA

Notes:

1. Type 0 is standard. Specify others as required: TSOPs can be packed in Types 0 and 3; BGAs can

be packed in Types 0, 2, or 3.

2. TSOP package marking omits the packing type designator from the ordering part number.

3. BGA package marking omits leading “S29” and packing type designator from the ordering part

number.

4. 100% Matte Sn is used for Pb-free TSOP plating.

5. Contact your Spansion representative for availability of the 100 ns speed option.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult

your local sales office to confirm availability of specific valid combinations and to check on newly

released combinations.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

25

D a t a S h e e t

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated

through the internal command register. The command register itself does not occupy any addres-

sable memory location. The register is a latch used to store the commands, along with the

address and data information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the function of the de-

vice. Table 5 lists the device bus operations, the inputs and control levels they require, and the

resulting output. The following subsections describe each of these operations in further detail.

Table 5. Device Bus Operations

DQ8–DQ15

Addresses

(Note 1)

DQ0–

DQ7

Operation

CE# OE# WE# RESET#

WP#

ACC

BYTE#

= V_IH

D_OUT

BYTE#

= V_IL

DQ8–DQ14

Read

L

H

L

H

X

A_IN

D_OUT

Write (Program/Erase)

Accelerated Program

(Note 3)

(Note 3) V_HH

(Note 4) (Note 4) = High-Z,

DQ15 = A-1

L

H

(Note 4) (Note 4)

V_CC

±

V_CC±

0.3 V

Standby

X

H

X

High-Z

0.3 V

Output Disable

Reset

L

X

H

X

H

X

H

L

X

High-Z

SA, A6 =L,

A3=L, A2=L,

A1=H, A0=L

SA, A6=H,

A3=L, A2=L,

A1=H, A0=L

Sector Group Protect

(Note 2)

L

H

L

V_ID

H

X

(Note 4)

X

Sector Group Unprotect

(Note 2)

L

H

X

L

V_ID

H

X

Temporary Sector

Group Unprotect

X

A_IN

(Note 4) (Note 4)

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V,

V_HH= 11.5 V – 12.5 V, X = Don’t Care, SA = Sector Address, A_IN= Address In,

D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are Amax:A0 in word mode; Amax:A-1 in byte mode. Sector addresses are Amax:A15

in both modes.

2. The sector protect and sector unprotect functions may also be implemented via programming

equipment. See the “Sector Group Protection and Unprotection” section.

3. If WP# = V_IL, the first or last sector remains protected (for uniform sector devices), and the two

outer boot sectors are protected (for boot sector devices). If WP# = V_IH, the first or last sector, or

the two outer boot sectors are protected or unprotected as determined by the method described in

“Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the

factory (The Secured Silicon Sector may be factory protected depending on version ordered.)

4. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see

Figure 2).

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active

and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–

DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and

the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to V . CE# is

IL

the power control and selects the device. OE# is the output control and gates array data to the

output pins. WE# should remain at V

.

IH

26

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

The internal state machine is set for reading array data upon device power-up, or after a hardware

reset. This ensures that no spurious alteration of the memory content occurs during the power

transition. No command is necessary in this mode to obtain array data. Standard microprocessor

read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read access until the command register con-

tents are altered.

See Reading Array Data for more information. See AC Characteristics for timing specifications and

the timing diagram. See DC Characteristics for the active current specification on reading array

data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page mode Mask ROM

read operation. This mode provides faster read access speed for random locations within a page.

The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher

address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the

specific word within a page. This is an asynchronous operation; the microprocessor supplies the

specific word location.

The random or initial page access is equal to t

or t and subsequent page read accesses (as

CE

ACC

long as the locations specified by the microprocessor falls within that page) is equivalent to t

.

PACC

When CE# is deasserted and reasserted for a subsequent access, the access time is t

or t

CE

ACC

Fast page mode accesses are obtained by keeping the “read-page addresses” constant and

changing the “intra-read page” addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and

erasing sectors of memory), the system must drive WE# and CE# to V , and OE# to V

.

IH

IL

The device features an Unlock Bypass mode to facilitate faster programming. Once the device

enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of

four. Word Program Command Sequence contains details on programming data to the device

using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 6 and

Table 17 indicates the address space that each sector occupies.

See DC Characteristics for the active current specification for the write mode. AC Characteristics

contains timing specification tables and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one

programming operation. This results in faster effective programming time than the standard pro-

gramming algorithms. See Write Buffer Programming for more information.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This is one of two

functions provided by the WP#/ACC or ACC pin, depending on model number. This function is pri-

marily intended to allow faster manufacturing throughput at the factory.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

27

D a t a S h e e t

If the system asserts V on this pin, the device automatically enters the aforementioned Unlock

HH

Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage

on the pin to reduce the time required for program operations. The system would use a two-cycle

program command sequence as required by the Unlock Bypass mode. Removing V

from the

HH

WP#/ACC or ACC pin, depending on model number, returns the device to normal operation. Note

that the WP#/ACC or ACC pin must not be at V for operations other than accelerated program-

HH

ming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at

V

.

IH

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the autoselect mode.

The system can then read autoselect codes from the internal register (which is separate from the

memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect

Mode and Autoselect Command Sequence for more information.

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby

mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V

IO

± 0.3 V. (Note that this is a more restricted voltage range than V .) If CE# and RESET# are held

IH

at V , but not within V ± 0.3 V, the device is in the standby mode, but the standby current is

IH

IO

greater. The device requires standard access time (t ) for read access when the device is in ei-

CE

ther of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until

the operation is completed.

See DC Characteristics for the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically

enables this mode when addresses remain stable for t + 30 ns. The automatic sleep mode is

ACC

independent of the CE#, WE#, and OE# control signals. Standard address access timings provide

new data when addresses are changed. While in sleep mode, output data is latched and always

available to the system. See DC Characteristics for the automatic sleep mode current

specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When

the RESET# pin is driven low for at least a period of t , the device immediately terminates any

RP

operation in progress, tristates all output pins, and ignores all read/write commands for the du-

ration of the RESET# pulse. The device also resets the internal state machine to reading array

data. The operation that was interrupted should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at V ±0.3 V, the

SS

device draws CMOS standby current (I

standby current is greater.

). If RESET# is held at V but not within V ±0.3 V, the

IL SS

CC5

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset

the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.

See AC Characteristics for RESET# parameters and to Figure 15 for the timing diagram.

28

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Output Disable Mode

When the OE# input is at V , output from the device is disabled. The output pins are placed in

IH

the high impedance state.

Table 6. S29GL032M (Model R0) Sector Addresses

8-bit

Address

Range

8-bit

Address

Range

8-bit

Address

Range

8-bit

Address

Range

A21–A16

SA0 0 0 0 0 0 0 000000–00FFFF SA16 0 1 0 0 0 0 100000–10FFFF SA32 1 0 0 0 0 0 200000–20FFFF SA48 1 1 0 0 0 0 300000–30FFFF

SA1 0 0 0 0 0 1 010000–01FFFF SA17 0 1 0 0 0 1 110000–11FFFF SA33 1 0 0 0 0 1 210000–21FFFF SA49 1 1 0 0 0 1 310000–31FFFF

SA2 0 0 0 0 1 0 020000–02FFFF SA18 0 1 0 0 1 0 120000–12FFFF SA34 1 0 0 0 1 0 220000–22FFFF SA50 1 1 0 0 1 0 320000–32FFFF

SA3 0 0 0 0 1 1 030000–03FFFF SA19 0 1 0 0 1 1 130000–13FFFF SA35 1 0 0 0 1 1 230000–23FFFF SA51 1 1 0 0 1 1 330000–33FFFF

SA4 0 0 0 1 0 0 040000–04FFFF SA20 0 1 0 1 0 0 140000–14FFFF SA36 1 0 0 1 0 0 240000–24FFFF SA52 1 1 0 1 0 0 340000–34FFFF

SA5 0 0 0 1 0 1 050000–05FFFF SA21 0 1 0 1 0 1 150000–15FFFF SA37 1 0 0 1 0 1 250000–25FFFF SA53 1 1 0 1 0 1 350000–35FFFF

SA6 0 0 0 1 1 0 060000–06FFFF SA22 0 1 0 1 1 0 160000–16FFFF SA38 1 0 0 1 1 0 260000–26FFFF SA54 1 1 0 1 1 0 360000–36FFFF

SA7 0 0 0 1 1 1 070000–07FFFF SA23 0 1 0 1 1 1 170000–17FFFF SA39 1 0 0 1 1 1 270000–27FFFF SA55 1 1 0 1 1 1 370000–37FFFF

SA8 0 0 1 0 0 0 080000–08FFFF SA24 0 1 1 0 0 0 180000–18FFFF SA40 1 0 1 0 0 0 280000–28FFFF SA56 1 1 1 0 0 0 380000–38FFFF

SA9 0 0 1 0 0 1 090000–09FFFF SA25 0 1 1 0 0 1 190000–19FFFF SA41 1 0 1 0 0 1 290000–29FFFF SA57 1 1 1 0 0 1 390000–39FFFF

SA10 0 0 1 0 1 0 0A0000–0AFFFF SA26 0 1 1 0 1 0 1A0000–1AFFFF SA42 1 0 1 0 1 0 2A0000–2AFFFF SA58 1 1 1 0 1 0 3A0000–3AFFFF

SA11 0 0 1 0 1 1 0B0000–0BFFFF SA27 0 1 1 0 1 1 1B0000–1BFFFF SA43 1 0 1 0 1 1 2B0000–2BFFFF SA59 1 1 1 0 1 1 3B0000–3BFFFF

SA12 0 0 1 1 0 0 0C0000–0CFFFF SA28 0 1 1 1 0 0 1C0000–1CFFFF SA44 1 0 1 1 0 0 2C0000–2CFFFF SA60 1 1 1 1 0 0 3C0000–3CFFFF

SA13 0 0 1 1 0 1 0D0000–0DFFFF SA29 0 1 1 1 0 1 1D0000–1DFFFF SA45 1 0 1 1 0 1 2D0000–2DFFFF SA61 1 1 1 1 0 1 3D0000–3DFFFF

SA14 0 0 1 1 1 0 0E0000–0EFFFF SA30 0 1 1 1 1 0 1E0000–1EFFFF SA46 1 0 1 1 1 0 2E0000–2EFFFF SA62 1 1 1 1 1 0 3E0000–3EFFFF

SA15 0 0 1 1 1 1 0F0000–0FFFFF SA31 0 1 1 1 1 1 1F0000–1FFFFF SA47 1 0 1 1 1 1 2F0000–2FFFFF SA63 1 1 1 1 1 1 3F0000–3FFFFF

Table 7. S29GL032M (Models R1, R2) Sector Addresses

Sector

Size

Sector

Size

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A20-A15

(KB/

Kwords)

SA0 0 0 0 0 0 0

SA1 0 0 0 0 0 1

SA2 0 0 0 0 1 0

SA3 0 0 0 0 1 1

SA4 0 0 0 1 0 0

SA5 0 0 0 1 0 1

SA6 0 0 0 1 1 0

SA7 0 0 0 1 1 1

SA8 0 0 1 0 0 0

SA9 0 0 1 0 0 1

SA10 0 0 1 0 1 0

SA11 0 0 1 0 1 1

SA12 0 0 1 1 0 0

SA13 0 0 1 1 0 1

SA14 0 0 1 1 1 0

SA15 0 0 1 1 1 1

SA16 0 1 0 0 0 0

SA17 0 1 0 0 0 1

SA18 0 1 0 0 1 0

SA19 0 1 0 0 1 1

SA20 0 1 0 1 0 0

SA21 0 1 0 1 0 1

SA22 0 1 0 1 1 0

SA23 0 1 0 1 1 1

SA24 0 1 1 0 0 0

SA25 0 1 1 0 0 1

SA26 0 1 1 0 1 0

SA27 0 1 1 0 1 1

SA28 0 1 1 1 0 0

SA29 0 1 1 1 0 1

SA30 0 1 1 1 1 0

SA31 0 1 1 1 1 1

64/32

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

SA32 1 0 0 0 0 0

SA33 1 0 0 0 0 1

SA34 1 0 0 0 1 0

SA35 1 0 0 0 1 1

SA36 1 0 0 1 0 0

SA37 1 0 0 1 0 1

SA38 1 0 0 1 1 0

SA39 1 0 0 1 1 1

SA40 1 0 1 0 0 0

SA41 1 0 1 0 0 1

SA42 1 0 1 0 1 0

SA43 1 0 1 0 1 1

SA44 1 0 1 1 0 0

SA45 1 0 1 1 0 1

SA46 1 0 1 1 1 0

SA47 1 0 1 1 1 1

SA48 1 1 0 0 0 0

SA49 1 1 0 0 0 1

SA50 1 1 0 0 1 0

SA51 1 1 0 0 1 1

SA52 1 1 0 1 0 0

SA53 1 1 0 1 0 1

SA54 1 1 0 1 1 0

SA55 1 1 0 1 1 1

SA56 1 1 1 0 0 0

SA57 1 1 1 0 0 1

SA58 1 1 1 0 1 0

SA59 1 1 1 0 1 1

SA60 1 1 1 1 0 0

SA61 1 1 1 1 0 1

SA62 1 1 1 1 1 0

SA63 1 1 1 1 1 1

64/32

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

29

D a t a S h e e t

Table 8. S29GL032M (Models R3, R5) Top Boot Sector Addresses

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A20–A12

(KB/

Kwords)

SA0 000000xxx

SA1 000001xxx

SA2 000010xxx

SA3 000011xxx

SA4 000100xxx

SA5 000101xxx

SA6 000110xxx

SA7 000111xxx

SA8 001000xxx

SA9 001001xxx

SA10 001010xxx

SA11 001011xxx

SA12 001100xxx

SA13 001101xxx

SA14 001101xxx

SA15 001111xxx

SA16 010000xxx

SA17 010001xxx

SA18 010010xxx

SA19 010011xxx

SA20 010100xxx

SA21 010101xxx

SA22 010110xxx

SA23 010111xxx

SA24 011000xxx

SA25 011001xxx

SA26 011010xxx

SA27 011011xxx

SA28 011000xxx

SA29 011101xxx

SA30 011110xxx

SA31 011111xxx

SA32 100000xxx

SA33 100001xxx

SA34 100010xxx

SA35 101011xxx

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

SA36 100100xxx

SA37 100101xxx

SA38 100110xxx

SA39 100111xxx

SA40 101000xxx

SA41 101001xxx

SA42 101010xxx

SA43 101011xxx

SA44 101100xxx

SA45 101101xxx

SA46 101110xxx

SA47 101111xxx

SA48 110000xxx

SA49 110001xxx

SA50 110010xxx

SA51 110011xxx

SA52 100100xxx

SA53 110101xxx

SA54 110110xxx

SA55 110111xxx

SA56 111000xxx

SA57 111001xxx

SA58 111010xxx

SA59 111011xxx

SA60 111100xxx

SA61 111101xxx

SA62 111110xxx

SA63 111111000

SA64 111111001

SA65 111111010

SA66 111111011

SA67 111111100

64/32

8/4

240000h–24FFFFh 120000h–127FFFh

250000h–25FFFFh 128000h–12FFFFh

260000h–26FFFFh 130000h–137FFFh

270000h–27FFFFh 138000h–13FFFFh

280000h–28FFFFh 140000h–147FFFh

290000h–29FFFFh 148000h–14FFFFh

2A0000h–2AFFFFh 150000h–157FFFh

2B0000h–2BFFFFh 158000h–15FFFFh

2C0000h–2CFFFFh 160000h–167FFFh

2D0000h–2DFFFFh 168000h–16FFFFh

2E0000h–2EFFFFh 170000h–177FFFh

2F0000h–2FFFFFh 178000h–17FFFFh

300000h–30FFFFh 180000h–187FFFh

310000h–31FFFFh 188000h–18FFFFh

320000h–32FFFFh 190000h–197FFFh

330000h–33FFFFh 198000h–19FFFFh

340000h–34FFFFh 1A0000h–1A7FFFh

350000h–35FFFFh 1A8000h–1AFFFFh

360000h–36FFFFh 1B0000h–1B7FFFh

370000h–37FFFFh 1B8000h–1BFFFFh

380000h–38FFFFh 1C0000h–1C7FFFh

390000h–39FFFFh 1C8000h–1CFFFFh

3A0000h–3AFFFFh 1D0000h–1D7FFFh

3B0000h–3BFFFFh 1D8000h–1DFFFFh

3C0000h–3CFFFFh 1E0000h–1E7FFFh

3D0000h–3DFFFFh 1E8000h–1EFFFFh

3E0000h–3EFFFFh 1F0000h–1F7FFFh

3F0000h–3F1FFFh 1F8000h–1F8FFFh

3F2000h–3F3FFFh 1F9000h–1F9FFFh

3F4000h–3F5FFFh 1FA000h–1FAFFFh

3F6000h–3F7FFFh 1FB000h–1FBFFFh

3F8000h–3F9FFFh 1FC000h–1FCFFFh

3FA000h–3FBFFFh 1FD000h–1FDFFFh

3FC000h–3FDFFFh 1FE000h–1FEFFFh

3FE000h–3FFFFFh 1FF000h–1FFFFFh

1A0000h–1AFFFFh D0000h–D7FFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh F9000h–107FFFh SA68 111111101

210000h–21FFFFh 108000h–10FFFFh SA69 111111110

220000h–22FFFFh 110000h–117FFFh SA70 111111111

230000h–23FFFFh 118000h–11FFFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

8/4

Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Addresses (Sheet 1 of 2)

Sector

Size

Sector

Size

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A20–A12

(KB/

Kwords)

SA0 000000000

SA1 000000001

SA2 000000010

SA3 000000011

SA4 000000100

SA5 000000101

SA6 000000110

SA7 000000111

SA8 000001xxx

SA9 000010xxx

SA10 000011xxx

SA11 000100xxx

SA12 000101xxx

SA13 000110xxx

SA14 000111xxx

SA15 001000xxx

SA16 001001xxx

SA17 001010xxx

SA18 001011xxx

8/4

64/32

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–007FFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00E000h–00FFFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

SA19 001100xxx 64/32

SA20 001101xxx 64/32

SA21 001101xxx 64/32

SA22 001111xxx 64/32

SA23 010000xxx 64/32

SA24 010001xxx 64/32

SA25 010010xxx 64/32

SA26 010011xxx 64/32

SA27 010100xxx 64/32

SA28 010101xxx 64/32

SA29 010110xxx 64/32

SA30 010111xxx 64/32

SA31 011000xxx 64/32

SA32 011001xxx 64/32

SA33 011010xxx 64/32

SA34 011011xxx 64/32

SA35 011000xxx 64/32

SA36 011101xxx 64/32

SA37 011110xxx 64/32

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

30

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 9. S29GL032M (Models R4, R6) Bottom Boot Sector Addresses (Sheet 2 of 2)

Sector

Size

Sector

Size

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A20–A12

(KB/

Kwords)

SA38 011111xxx

SA39 100000xxx

SA40 100001xxx

SA41 100010xxx

SA42 101011xxx

SA43 100100xxx

SA44 100101xxx

SA45 100110xxx

SA46 100111xxx

SA47 101000xxx

SA48 101001xxx

SA49 101010xxx

SA50 101011xxx

SA51 101100xxx

SA52 101101xxx

SA53 101110xxx

SA54 101111xxx

64/32

1F0000h–1FFFFFh

200000h–20FFFFh

F8000h–FFFFFh

F9000h–107FFFh SA56 110001xxx 64/32

SA55 110000xxx 64/32

300000h–30FFFFh 180000h–187FFFh

310000h–31FFFFh 188000h–18FFFFh

320000h–32FFFFh 190000h–197FFFh

330000h–33FFFFh 198000h–19FFFFh

340000h–34FFFFh 1A0000h–1A7FFFh

350000h–35FFFFh 1A8000h–1AFFFFh

360000h–36FFFFh 1B0000h–1B7FFFh

370000h–37FFFFh 1B8000h–1BFFFFh

380000h–38FFFFh 1C0000h–1C7FFFh

390000h–39FFFFh 1C8000h–1CFFFFh

3A0000h–3AFFFFh 1D0000h–1D7FFFh

3B0000h–3BFFFFh 1D8000h–1DFFFFh

3C0000h–3CFFFFh 1E0000h–1E7FFFh

3D0000h–3DFFFFh 1E8000h–1EFFFFh

3E0000h–3EFFFFh 1F0000h–1F7FFFh

3F0000h–3FFFFFh 1F8000h–1FFFFFh

210000h–21FFFFh 108000h–10FFFFh SA57 110010xxx 64/32

220000h–22FFFFh 110000h–117FFFh SA58 110011xxx 64/32

230000h–23FFFFh 118000h–11FFFFh SA59 100100xxx 64/32

240000h–24FFFFh 120000h–127FFFh SA60 110101xxx 64/32

250000h–25FFFFh 128000h–12FFFFh SA61 110110xxx 64/32

260000h–26FFFFh 130000h–137FFFh SA62 110111xxx 64/32

270000h–27FFFFh 138000h–13FFFFh SA63 111000xxx 64/32

280000h–28FFFFh 140000h–147FFFh SA64 111001xxx 64/32

290000h–29FFFFh 148000h–14FFFFh SA65 111010xxx 64/32

2A0000h–2AFFFFh 150000h–157FFFh SA66 111011xxx 64/32

2B0000h–2BFFFFh 158000h–15FFFFh SA67 111100xxx 64/32

2C0000h–2CFFFFh 160000h–167FFFh SA68 111101xxx 64/32

2D0000h–2DFFFFh 168000h–16FFFFh SA69 111110xxx 64/32

2E0000h–2EFFFFh 170000h–177FFFh SA70 111111xxx 64/32

2F0000h–2FFFFFh 178000h–17FFFFh

Table 10. S29GL064M (Model R0) Sector Addresses

8-bit

Address

Range

8-bit

Address

Range

8-bit

Address

Range

8-bit

Address

Range

A22–A16

SA0 0 0 0 0 0 0 0 000000–00FFFF SA32 0 1 0 0 0 0 0 200000–20FFFF SA64 1 0 0 0 0 0 0 400000–40FFFF SA96 1 1 0 0 0 0 0 600000–60FFFF

SA1 0 0 0 0 0 0 1 010000–01FFFF SA33 0 1 0 0 0 0 1 210000–21FFFF SA65 1 0 0 0 0 0 1 410000–41FFFF SA97 1 1 0 0 0 0 1 610000–61FFFF

SA2 0 0 0 0 0 1 0 020000–02FFFF SA34 0 1 0 0 0 1 0 220000–22FFFF SA66 1 0 0 0 0 1 0 420000–42FFFF SA98 1 1 0 0 0 1 0 620000–62FFFF

SA3 0 0 0 0 0 1 1 030000–03FFFF SA35 0 1 0 0 0 1 1 230000–23FFFF SA67 1 0 0 0 0 1 1 430000–43FFFF SA99 1 1 0 0 0 1 1 630000–63FFFF

SA4 0 0 0 0 1 0 0 040000–04FFFF SA36 0 1 0 0 1 0 0 240000–24FFFF SA68 1 0 0 0 1 0 0 440000–44FFFF SA100 1 1 0 0 1 0 0 640000–64FFFF

SA5 0 0 0 0 1 0 1 050000–05FFFF SA37 0 1 0 0 1 0 1 250000–25FFFF SA69 1 0 0 0 1 0 1 450000–45FFFF SA101 1 1 0 0 1 0 1 650000–65FFFF

SA6 0 0 0 0 1 1 0 060000–06FFFF SA38 0 1 0 0 1 1 0 260000–26FFFF SA70 1 0 0 0 1 1 0 460000–46FFFF SA102 1 1 0 0 1 1 0 660000–66FFFF

SA7 0 0 0 0 1 1 1 070000–07FFFF SA39 0 1 0 0 1 1 1 270000–27FFFF SA71 1 0 0 0 1 1 1 470000–47FFFF SA103 1 1 0 0 1 1 1 670000–67FFFF

SA8 0 0 0 1 0 0 0 080000–08FFFF SA40 0 1 0 1 0 0 0 280000–28FFFF SA72 1 0 0 1 0 0 0 480000–48FFFF SA104 1 1 0 1 0 0 0 680000–68FFFF

SA9 0 0 0 1 0 0 1 090000–09FFFF SA41 0 1 0 1 0 0 1 290000–29FFFF SA73 1 0 0 1 0 0 1 490000–49FFFF SA105 1 1 0 1 0 0 1 690000–69FFFF

SA10 0 0 0 1 0 1 0 0A0000–0AFFFF SA42 0 1 0 1 0 1 0 2A0000–2AFFFF SA74 1 0 0 1 0 1 0 4A0000–4AFFFF SA106 1 1 0 1 0 1 0 6A0000–6AFFFF

SA11 0 0 0 1 0 1 1 0B0000–0BFFFF SA43 0 1 0 1 0 1 1 2B0000–2BFFFF SA75 1 0 0 1 0 1 1 4B0000–4BFFFF SA107 1 1 0 1 0 1 1 6B0000–6BFFFF

SA12 0 0 0 1 1 0 0 0C0000–0CFFFF SA44 0 1 0 1 1 0 0 2C0000–2CFFFF SA76 1 0 0 1 1 0 0 4C0000–4CFFFF SA108 1 1 0 1 1 0 0 6C0000–6CFFFF

SA13 0 0 0 1 1 0 1 0D0000–0DFFFF SA45 0 1 0 1 1 0 1 2D0000–2DFFFF SA77 1 0 0 1 1 0 1 4D0000–4DFFFF SA109 1 1 0 1 1 0 1 6D0000–6DFFFF

SA14 0 0 0 1 1 1 0 0E0000–0EFFFF SA46 0 1 0 1 1 1 0 2E0000–2EFFFF SA78 1 0 0 1 1 1 0 4E0000–4EFFFF SA110 1 1 0 1 1 1 0 6E0000–6EFFFF

SA15 0 0 0 1 1 1 1 0F0000–0FFFFF SA47 0 1 0 1 1 1 1 2F0000–2FFFFF SA79 1 0 0 1 1 1 1 4F0000–4FFFFF SA111 1 1 0 1 1 1 1 6F0000–6FFFFF

SA16 0 0 1 0 0 0 0 100000–10FFFF SA48 0 1 1 0 0 0 0 300000–30FFFF SA80 1 0 1 0 0 0 0 500000–50FFFF SA112 1 1 1 0 0 0 0 700000–70FFFF

SA17 0 0 1 0 0 0 1 110000–11FFFF SA49 0 1 1 0 0 0 1 310000–31FFFF SA81 1 0 1 0 0 0 1 510000–51FFFF SA113 1 1 1 0 0 0 1 710000–71FFFF

SA18 0 0 1 0 0 1 0 120000–12FFFF SA50 0 1 1 0 0 1 0 320000–32FFFF SA82 1 0 1 0 0 1 0 520000–52FFFF SA114 1 1 1 0 0 1 0 720000–72FFFF

SA19 0 0 1 0 0 1 1 130000–13FFFF SA51 0 1 1 0 0 1 1 330000–33FFFF SA83 1 0 1 0 0 1 1 530000–53FFFF SA115 1 1 1 0 0 1 1 730000–73FFFF

SA20 0 0 1 0 1 0 0 140000–14FFFF SA52 0 1 1 0 1 0 0 340000–34FFFF SA84 1 0 1 0 1 0 0 540000–54FFFF SA116 1 1 1 0 1 0 0 740000–74FFFF

SA21 0 0 1 0 1 0 1 150000–15FFFF SA53 0 1 1 0 1 0 1 350000–35FFFF SA85 1 0 1 0 1 0 1 550000–55FFFF SA117 1 1 1 0 1 0 1 750000–75FFFF

SA22 0 0 1 0 1 1 0 160000–16FFFF SA54 0 1 1 0 1 1 0 360000–36FFFF SA86 1 0 1 0 1 1 0 560000–56FFFF SA118 1 1 1 0 1 1 0 760000–76FFFF

SA23 0 0 1 0 1 1 1 170000–17FFFF SA55 0 1 1 0 1 1 1 370000–37FFFF SA87 1 0 1 0 1 1 1 570000–57FFFF SA119 1 1 1 0 1 1 1 770000–77FFFF

SA24 0 0 1 1 0 0 0 180000–18FFFF SA56 0 1 1 1 0 0 0 380000–38FFFF SA88 1 0 1 1 0 0 0 580000–58FFFF SA120 1 1 1 1 0 0 0 780000–78FFFF

SA25 0 0 1 1 0 0 1 190000–19FFFF SA57 0 1 1 1 0 0 1 390000–39FFFF SA89 1 0 1 1 0 0 1 590000–59FFFF SA121 1 1 1 1 0 0 1 790000–79FFFF

SA26 0 0 1 1 0 1 0 1A0000–1AFFFF SA58 0 1 1 1 0 1 0 3A0000–3AFFFF SA90 1 0 1 1 0 1 0 5A0000–5AFFFF SA122 1 1 1 1 0 1 0 7A0000–7AFFFF

SA27 0 0 1 1 0 1 1 1B0000–1BFFFF SA59 0 1 1 1 0 1 1 3B0000–3BFFFF SA91 1 0 1 1 0 1 1 5B0000–5BFFFF SA123 1 1 1 1 0 1 1 7B0000–7BFFFF

SA28 0 0 1 1 1 0 0 1C0000–1CFFFF SA60 0 1 1 1 1 0 0 3C0000–3CFFFF SA92 1 0 1 1 1 0 0 5C0000–5CFFFF SA124 1 1 1 1 1 0 0 7C0000–7CFFFF

SA29 0 0 1 1 1 0 1 1D0000–1DFFFF SA61 0 1 1 1 1 0 1 3D0000–3DFFFF SA93 1 0 1 1 1 0 1 5D0000–5DFFFF SA125 1 1 1 1 1 0 1 7D0000–7DFFFF

SA30 0 0 1 1 1 1 0 1E0000–1EFFFF SA62 0 1 1 1 1 1 0 3E0000–3EFFFF SA94 1 0 1 1 1 1 0 5E0000–5EFFFF SA126 1 1 1 1 1 1 0 7E0000–7EFFFF

SA31 0 0 1 1 1 1 1 1F0000–1FFFFF SA63 0 1 1 1 1 1 1 3F0000–3FFFFF SA95 1 0 1 1 1 1 1 5F0000–5FFFFF SA127 1 1 1 1 1 1 1 7F0000–7FFFFF

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

31

D a t a S h e e t

Table 11. S29GL064M (Models R1, R2, R8, R9) Sector Addresses

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A21–A15

(KB/

Kwords)

SA0 0 0 0 0 0 0 0

SA1 0 0 0 0 0 0 1

SA2 0 0 0 0 0 1 0

SA3 0 0 0 0 0 1 1

SA4 0 0 0 0 1 0 0

SA5 0 0 0 0 1 0 1

SA6 0 0 0 0 1 1 0

SA7 0 0 0 0 1 1 1

SA8 0 0 0 1 0 0 0

SA9 0 0 0 1 0 0 1

SA10 0 0 0 1 0 1 0

SA11 0 0 0 1 0 1 1

SA12 0 0 0 1 1 0 0

SA13 0 0 0 1 1 0 1

SA14 0 0 0 1 1 1 0

SA15 0 0 0 1 1 1 1

SA16 0 0 1 0 0 0 0

SA17 0 0 1 0 0 0 1

SA18 0 0 1 0 0 1 0

SA19 0 0 1 0 0 1 1

SA20 0 0 1 0 1 0 0

SA21 0 0 1 0 1 0 1

SA22 0 0 1 0 1 1 0

SA23 0 0 1 0 1 1 1

SA24 0 0 1 1 0 0 0

SA25 0 0 1 1 0 0 1

SA26 0 0 1 1 0 1 0

SA27 0 0 1 1 0 1 1

SA28 0 0 1 1 1 0 0

SA29 0 0 1 1 1 0 1

SA30 0 0 1 1 1 1 0

SA31 0 0 1 1 1 1 1

SA32 0 1 0 0 0 0 0

SA33 0 1 0 0 0 0 1

SA34 0 1 0 0 0 1 0

SA35 0 1 0 0 0 1 1

SA36 0 1 0 0 1 0 0

SA37 0 1 0 0 1 0 1

SA38 0 1 0 0 1 1 0

SA39 0 1 0 0 1 1 1

SA40 0 1 0 1 0 0 0

SA41 0 1 0 1 0 0 1

SA42 0 1 0 1 0 1 0

SA43 0 1 0 1 0 1 1

SA44 0 1 0 1 1 0 0

SA45 0 1 0 1 1 0 1

SA46 0 1 0 1 1 1 0

SA47 0 1 0 1 1 1 1

SA48 0 1 1 0 0 0 0

SA49 0 1 1 0 0 0 1

SA50 0 1 1 0 0 1 0

SA51 0 1 1 0 0 1 1

SA52 0 1 1 0 1 0 0

SA53 0 1 1 0 1 0 1

SA54 0 1 1 0 1 1 0

SA55 0 1 1 0 1 1 1

SA56 0 1 1 1 0 0 0

SA57 0 1 1 1 0 0 1

SA58 0 1 1 1 0 1 0

SA59 0 1 1 1 0 1 1

SA60 0 1 1 1 1 0 0

SA61 0 1 1 1 1 0 1

SA62 0 1 1 1 1 1 0

SA63 0 1 1 1 1 1 1

64/32

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

200000–20FFFF

210000–21FFFF

220000–22FFFF

230000–23FFFF

240000–24FFFF

250000–25FFFF

260000–26FFFF

270000–27FFFF

280000–28FFFF

290000–29FFFF

2A0000–2AFFFF

2B0000–2BFFFF

2C0000–2CFFFF

2D0000–2DFFFF

2E0000–2EFFFF

2F0000–2FFFFF

300000–30FFFF

310000–31FFFF

320000–32FFFF

330000–33FFFF

340000–34FFFF

350000–35FFFF

360000–36FFFF

370000–37FFFF

380000–38FFFF

390000–39FFFF

3A0000–3AFFFF

3B0000–3BFFFF

3C0000–3CFFFF

3D0000–3DFFFF

3E0000–3EFFFF

3F0000–3FFFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

SA64 1 0 0 0 0 0 0

SA65 1 0 0 0 0 0 1

SA66 1 0 0 0 0 1 0

SA67 1 0 0 0 0 1 1

SA68 1 0 0 0 1 0 0

SA69 1 0 0 0 1 0 1

SA70 1 0 0 0 1 1 0

SA71 1 0 0 0 1 1 1

SA72 1 0 0 1 0 0 0

SA73 1 0 0 1 0 0 1

SA74 1 0 0 1 0 1 0

SA75 1 0 0 1 0 1 1

SA76 1 0 0 1 1 0 0

SA77 1 0 0 1 1 0 1

SA78 1 0 0 1 1 1 0

SA79 1 0 0 1 1 1 1

SA80 1 0 1 0 0 0 0

SA81 1 0 1 0 0 0 1

SA82 1 0 1 0 0 1 0

SA83 1 0 1 0 0 1 1

SA84 1 0 1 0 1 0 0

SA85 1 0 1 0 1 0 1

SA86 1 0 1 0 1 1 0

SA87 1 0 1 0 1 1 1

SA88 1 0 1 1 0 0 0

SA89 1 0 1 1 0 0 1

SA90 1 0 1 1 0 1 0

SA91 1 0 1 1 0 1 1

SA92 1 0 1 1 1 0 0

SA93 1 0 1 1 1 0 1

SA94 1 0 1 1 1 1 0

SA95 1 0 1 1 1 1 1

SA96 1 1 0 0 0 0 0

SA97 1 1 0 0 0 0 1

SA98 1 1 0 0 0 1 0

SA99 1 1 0 0 0 1 1

SA100 1 1 0 0 1 0 0

SA101 1 1 0 0 1 0 1

SA102 1 1 0 0 1 1 0

SA103 1 1 0 0 1 1 1

SA104 1 1 0 1 0 0 0

SA105 1 1 0 1 0 0 1

SA106 1 1 0 1 0 1 0

SA107 1 1 0 1 0 1 1

SA108 1 1 0 1 1 0 0

SA109 1 1 0 1 1 0 1

SA110 1 1 0 1 1 1 0

SA111 1 1 0 1 1 1 1

SA112 1 1 1 0 0 0 0

SA113 1 1 1 0 0 0 1

SA114 1 1 1 0 0 1 0

SA115 1 1 1 0 0 1 1

SA116 1 1 1 0 1 0 0

SA117 1 1 1 0 1 0 1

SA118 1 1 1 0 1 1 0

SA119 1 1 1 0 1 1 1

SA120 1 1 1 1 0 0 0

SA121 1 1 1 1 0 0 1

64/32

400000–40FFFF

410000–41FFFF

420000–42FFFF

430000–43FFFF

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF

4B0000–4BFFFF

4C0000–4CFFFF

4D0000–4DFFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF

550000–55FFFF

560000–56FFFF

570000–57FFFF

580000–58FFFF

590000–59FFFF

5A0000–5AFFFF

5B0000–5BFFFF

5C0000–5CFFFF

5D0000–5DFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF

6B0000–6BFFFF

6C0000–6CFFFF

6D0000–6DFFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF

750000–75FFFF

760000–76FFFF

770000–77FFFF

780000–78FFFF

790000–79FFFF

7A0000–7AFFFF

7B0000–7BFFFF

7C0000–7CFFFF

7D0000–7DFFFF

7E0000–7EFFFF

7F0000–7FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

1D0000–1D7FFF SA122 1 1 1 1 0 1 0

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

SA123 1 1 1 1 0 1 1

SA124 1 1 1 1 1 0 0

SA125 1 1 1 1 1 0 1

SA126 1 1 1 1 1 1 0

SA127 1 1 1 1 1 1 1

32

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 12. S29GL064M (Model R3) Top Boot Sector Addresses

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A21–A12

(KB/

Kwords)

SA0 0000000xxx 64/32

SA1 0000001xxx 64/32

SA2 0000010xxx 64/32

SA3 0000011xxx 64/32

SA4 0000100xxx 64/32

SA5 0000101xxx 64/32

SA6 0000110xxx 64/32

SA7 0000111xxx 64/32

SA8 0001000xxx 64/32

SA9 0001001xxx 64/32

SA10 0001010xxx 64/32

SA11 0001011xxx 64/32

SA12 0001100xxx 64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

SA68 1000100xxx 64/32

SA69 1000101xxx 64/32

SA70 1000110xxx 64/32

SA71 1000111xxx 64/32

SA72 1001000xxx 64/32

SA73 1001001xxx 64/32

SA74 1001010xxx 64/32

SA75 1001011xxx 64/32

SA76 1001100xxx 64/32

440000h–44FFFFh 220000h–227FFFh

450000h–45FFFFh 228000h–22FFFFh

460000h–46FFFFh 230000h–237FFFh

470000h–47FFFFh 238000h–23FFFFh

480000h–48FFFFh 240000h–247FFFh

490000h–49FFFFh 248000h–24FFFFh

4A0000h–4AFFFFh 250000h–257FFFh

4B0000h–4BFFFFh 258000h–25FFFFh

4C0000h–4CFFFFh 260000h–267FFFh

SA77 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh

SA78 1001110xxx 64/32

SA79 1001111xxx 64/32

SA80 1010000xxx 64/32

SA81 1010001xxx 64/32

SA82 1010010xxx 64/32

SA83 1010011xxx 64/32

SA84 1010100xxx 64/32

SA85 1010101xxx 64/32

SA86 1010110xxx 64/32

SA87 1010111xxx 64/32

SA88 1011000xxx 64/32

SA89 1011001xxx 64/32

SA90 1011010xxx 64/32

SA91 1011011xxx 64/32

SA92 1011100xxx 64/32

4E0000h–4EFFFFh 270000h–277FFFh

4F0000h–4FFFFFh 278000h–27FFFFh

500000h–50FFFFh 280000h–28FFFFh

510000h–51FFFFh 288000h–28FFFFh

520000h–52FFFFh 290000h–297FFFh

530000h–53FFFFh 298000h–29FFFFh

540000h–54FFFFh 2A0000h–2A7FFFh

550000h–55FFFFh 2A8000h–2AFFFFh

560000h–56FFFFh 2B0000h–2B7FFFh

570000h–57FFFFh 2B8000h–2BFFFFh

580000h–58FFFFh 2C0000h–2C7FFFh

590000h–59FFFFh 2C8000h–2CFFFFh

5A0000h–5AFFFFh 2D0000h–2D7FFFh

5B0000h–5BFFFFh 2D8000h–2DFFFFh

5C0000h–5CFFFFh 2E0000h–2E7FFFh

SA13 0001101xxx 64/32 0D0000h–0DFFFFh 68000h–6FFFFh

SA14 0001101xxx 64/32

SA15 0001111xxx 64/32

SA16 0010000xxx 64/32

SA17 0010001xxx 64/32

SA18 0010010xxx 64/32

SA19 0010011xxx 64/32

SA20 0010100xxx 64/32

SA21 0010101xxx 64/32

SA22 0010110xxx 64/32

SA23 0010111xxx 64/32

SA24 0011000xxx 64/32

SA25 0011001xxx 64/32

SA26 0011010xxx 64/32

SA27 0011011xxx 64/32

SA28 0011000xxx 64/32

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

SA93 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh

1A0000h–1AFFFFh D0000h–D7FFFh

1B0000h–1BFFFFh D8000h–DFFFFh

1C0000h–1CFFFFh

SA94 1011110xxx 64/32

SA95 1011111xxx 64/32

SA96 1100000xxx 64/32

SA97 1100001xxx 64/32

SA98 1100010xxx 64/32

SA99 1100011xxx 64/32

5E0000h–5EFFFFh 2F0000h–2FFFFFh

5F0000h–5FFFFFh 2F8000h–2FFFFFh

600000h–60FFFFh 300000h–307FFFh

610000h–61FFFFh 308000h–30FFFFh

620000h–62FFFFh 310000h–317FFFh

630000h–63FFFFh 318000h–31FFFFh

640000h–64FFFFh 320000h–327FFFh

650000h–65FFFFh 328000h–32FFFFh

660000h–66FFFFh 330000h–337FFFh

670000h–67FFFFh 338000h–33FFFFh

680000h–68FFFFh 340000h–347FFFh

690000h–69FFFFh 348000h–34FFFFh

6A0000h–6AFFFFh 350000h–357FFFh

6B0000h–6BFFFFh 358000h–35FFFFh

6C0000h–6CFFFFh 360000h–367FFFh

E0000h–E7FFFh

SA29 0011101xxx 64/32 1D0000h–1DFFFFh E8000h–EFFFFh

SA30 0011110xxx 64/32

SA31 0011111xxx 64/32

SA32 0100000xxx 64/32

SA33 0100001xxx 64/32

SA34 0100010xxx 64/32

SA35 0101011xxx 64/32

SA36 0100100xxx 64/32

SA37 0100101xxx 64/32

SA38 0100110xxx 64/32

SA39 0100111xxx 64/32

SA40 0101000xxx 64/32

SA41 0101001xxx 64/32

SA42 0101010xxx 64/32

SA43 0101011xxx 64/32

SA44 0101100xxx 64/32

1E0000h–1EFFFFh

1F0000h–1FFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

200000h–20FFFFh F9000h–107FFFh SA100 1100100xxx 64/32

210000h–21FFFFh 108000h–10FFFFh SA101 1100101xxx 64/32

220000h–22FFFFh 110000h–117FFFh SA102 1100110xxx 64/32

230000h–23FFFFh 118000h–11FFFFh SA103 1100111xxx 64/32

240000h–24FFFFh 120000h–127FFFh SA104 1101000xxx 64/32

250000h–25FFFFh 128000h–12FFFFh SA105 1101001xxx 64/32

260000h–26FFFFh 130000h–137FFFh SA106 1101010xxx 64/32

270000h–27FFFFh 138000h–13FFFFh SA107 1101011xxx 64/32

280000h–28FFFFh 140000h–147FFFh SA108 1101100xxx 64/32

290000h–29FFFFh 148000h–14FFFFh SA109 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh

2A0000h–2AFFFFh 150000h–157FFFh SA110 1101110xxx 64/32

2B0000h–2BFFFFh 158000h–15FFFFh SA111 1101111xxx 64/32

2C0000h–2CFFFFh 160000h–167FFFh SA112 1110000xxx 64/32

6E0000h–6EFFFFh 370000h–377FFFh

6F0000h–6FFFFFh 378000h–37FFFFh

700000h–70FFFFh 380000h–387FFFh

710000h–71FFFFh 388000h–38FFFFh

720000h–72FFFFh 390000h–397FFFh

730000h–73FFFFh 398000h–39FFFFh

740000h–74FFFFh 3A0000h–3A7FFFh

750000h–75FFFFh 3A8000h–3AFFFFh

760000h–76FFFFh 3B0000h–3B7FFFh

770000h–77FFFFh 3B8000h–3BFFFFh

780000h–78FFFFh 3C0000h–3C7FFFh

790000h–79FFFFh 3C8000h–3CFFFFh

7A0000h–7AFFFFh 3D0000h–3D7FFFh

7B0000h–7BFFFFh 3D8000h–3DFFFFh

7C0000h–7CFFFFh 3E0000h–3E7FFFh

SA45 0101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh SA113 1110001xxx 64/32

SA46 0101110xxx 64/32

SA47 0101111xxx 64/32

SA48 0110000xxx 64/32

SA49 0110001xxx 64/32

SA50 0110010xxx 64/32

SA51 0110011xxx 64/32

SA52 0100100xxx 64/32

SA53 0110101xxx 64/32

SA54 0110110xxx 64/32

SA55 0110111xxx 64/32

SA56 0111000xxx 64/32

SA57 0111001xxx 64/32

SA58 0111010xxx 64/32

SA59 0111011xxx 64/32

SA60 0111100xxx 64/32

2E0000h–2EFFFFh 170000h–177FFFh SA114 1110010xxx 64/32

2F0000h–2FFFFFh 178000h–17FFFFh SA115 1110011xxx 64/32

300000h–30FFFFh 180000h–187FFFh SA116 1110100xxx 64/32

310000h–31FFFFh 188000h–18FFFFh SA117 1110101xxx 64/32

320000h–32FFFFh 190000h–197FFFh SA118 1110110xxx 64/32

330000h–33FFFFh 198000h–19FFFFh SA119 1110111xxx 64/32

340000h–34FFFFh 1A0000h–1A7FFFh SA120 1111000xxx 64/32

350000h–35FFFFh 1A8000h–1AFFFFh SA121 1111001xxx 64/32

360000h–36FFFFh 1B0000h–1B7FFFh SA122 1111010xxx 64/32

370000h–37FFFFh 1B8000h–1BFFFFh SA123 1111011xxx 64/32

380000h–38FFFFh 1C0000h–1C7FFFh SA124 1111100xxx 64/32

390000h–39FFFFh 1C8000h–1CFFFFh SA125 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

3A0000h–3AFFFFh 1D0000h–1D7FFFh SA126 1111110xxx 64/32

3B0000h–3BFFFFh 1D8000h–1DFFFFh SA127 1111111000

3C0000h–3CFFFFh 1E0000h–1E7FFFh SA128 1111111001

7E0000h–7EFFFFh 3F0000h–3F7FFFh

7F0000h–7F1FFFh 3F8000h–3F8FFFh

7F2000h–7F3FFFh 3F9000h–3F9FFFh

7F4000h–7F5FFFh 3FA000h–3FAFFFh

7F6000h–7F7FFFh 3FB000h–3FBFFFh

7F8000h–7F9FFFh 3FC000h–3FCFFFh

7FA000h–7FBFFFh 3FD000h–3FDFFFh

7FC000h–7FDFFFh 3FE000h–3FEFFFh

7FE000h–7FFFFFh 3FF000h–3FFFFFh

8/4

SA61 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh SA129 1111111010

SA62 0111110xxx 64/32

SA63 0111111xxx 64/32

SA64 1000000xxx 64/32

SA65 1000001xxx 64/32

SA66 1000010xxx 64/32

SA67 1000011xxx 64/32

3E0000h–3EFFFFh 1F0000h–1F7FFFh SA130 1111111011

3F0000h–3FFFFFh 1F8000h–1FFFFFh SA131 1111111100

400000h–40FFFFh 200000h–207FFFh SA132 1111111101

410000h–41FFFFh 208000h–20FFFFh SA133 1111111110

420000h–42FFFFh 210000h–217FFFh SA134 1111111111

430000h–43FFFFh 218000h–21FFFFh

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

33

D a t a S h e e t

Table 13. S29GL064M (Model R4) Bottom Boot Sector Addresses

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A21–A12

(KB/

Kwords)

SA0 0000000000

SA1 0000000001

SA2 0000000010

SA3 0000000011

SA4 0000000100

SA5 0000000101

SA6 0000000110

SA7 0000000111

8/4

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–007FFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

SA68 0111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

SA69 0111110xxx 64/32

SA70 0111111xxx 64/32

SA71 1000000xxx 64/32

SA72 1000001xxx 64/32

SA73 1000010xxx 64/32

SA74 1000011xxx 64/32

SA75 1000100xxx 64/32

SA76 1000101xxx 64/32

SA77 1000110xxx 64/32

SA78 1000111xxx 64/32

SA79 1001000xxx 64/32

SA80 1001001xxx 64/32

SA81 1001010xxx 64/32

SA82 1001011xxx 64/32

3E0000h–3EFFFFh 1F0000h–1F7FFFh

3F0000h–3FFFFFh 1F8000h–1FFFFFh

400000h–40FFFFh 200000h–207FFFh

410000h–41FFFFh 208000h–20FFFFh

420000h–42FFFFh 210000h–217FFFh

430000h–43FFFFh 218000h–21FFFFh

440000h–44FFFFh 220000h–227FFFh

450000h–45FFFFh 228000h–22FFFFh

460000h–46FFFFh 230000h–237FFFh

470000h–47FFFFh 238000h–23FFFFh

480000h–48FFFFh 240000h–247FFFh

490000h–49FFFFh 248000h–24FFFFh

4A0000h–4AFFFFh 250000h–257FFFh

4B0000h–4BFFFFh 258000h–25FFFFh

00E000h–00FFFFFh 07000h–07FFFh

SA8 0000001xxx 64/32

SA9 0000010xxx 64/32

SA10 0000011xxx 64/32

SA11 0000100xxx 64/32

SA12 0000101xxx 64/32

SA13 0000110xxx 64/32

SA14 0000111xxx 64/32

SA15 0001000xxx 64/32

SA16 0001001xxx 64/32

SA17 0001010xxx 64/32

SA18 0001011xxx 64/32

SA19 0001100xxx 64/32

SA20 0001101xxx 64/32

SA21 0001101xxx 64/32

SA22 0001111xxx 64/32

SA23 0010000xxx 64/32

SA24 0010001xxx 64/32

SA25 0010010xxx 64/32

SA26 0010011xxx 64/32

SA27 0010100xxx 64/32

SA28 0010101xxx 64/32

SA29 0010110xxx 64/32

SA30 0010111xxx 64/32

SA31 0011000xxx 64/32

SA32 0011001xxx 64/32

SA33 0011010xxx 64/32

SA34 0011011xxx 64/32

SA35 0011000xxx 64/32

SA36 0011101xxx 64/32

SA37 0011110xxx 64/32

SA38 0011111xxx 64/32

SA39 0100000xxx 64/32

SA40 0100001xxx 64/32

SA41 0100010xxx 64/32

SA42 0101011xxx 64/32

SA43 0100100xxx 64/32

SA44 0100101xxx 64/32

SA45 0100110xxx 64/32

SA46 0100111xxx 64/32

SA47 0101000xxx 64/32

SA48 0101001xxx 64/32

SA49 0101010xxx 64/32

SA50 0101011xxx 64/32

SA51 0101100xxx 64/32

SA52 0101101xxx 64/32

SA53 0101110xxx 64/32

SA54 0101111xxx 64/32

SA55 0110000xxx 64/32

SA56 0110001xxx 64/32

SA57 0110010xxx 64/32

SA58 0110011xxx 64/32

SA59 0100100xxx 64/32

SA60 0110101xxx 64/32

SA61 0110110xxx 64/32

SA62 0110111xxx 64/32

SA63 0111000xxx 64/32

SA64 0111001xxx 64/32

SA65 0111010xxx 64/32

SA66 0111011xxx 64/32

SA67 0111100xxx 64/32

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–00FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

80000h–87FFFh

88000h–8FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

SA83 1001100xxx 64/32 4C0000h–4CFFFFh 260000h–267FFFh

SA84 1001101xxx 64/32 4D0000h–4DFFFFh 268000h–26FFFFh

SA85 1001110xxx 64/32

SA86 1001111xxx 64/32

SA87 1010000xxx 64/32

SA88 1010001xxx 64/32

SA89 1010010xxx 64/32

SA90 1010011xxx 64/32

SA91 1010100xxx 64/32

SA92 1010101xxx 64/32

SA93 1010110xxx 64/32

SA94 1010111xxx 64/32

SA95 1011000xxx 64/32

SA96 1011001xxx 64/32

SA97 1011010xxx 64/32

SA98 1011011xxx 64/32

4E0000h–4EFFFFh 270000h–277FFFh

4F0000h–4FFFFFh 278000h–27FFFFh

500000h–50FFFFh 280000h–28FFFFh

510000h–51FFFFh 288000h–28FFFFh

520000h–52FFFFh 290000h–297FFFh

530000h–53FFFFh 298000h–29FFFFh

540000h–54FFFFh 2A0000h–2A7FFFh

550000h–55FFFFh 2A8000h–2AFFFFh

560000h–56FFFFh 2B0000h–2B7FFFh

570000h–57FFFFh 2B8000h–2BFFFFh

580000h–58FFFFh 2C0000h–2C7FFFh

590000h–59FFFFh 2C8000h–2CFFFFh

5A0000h–5AFFFFh 2D0000h–2D7FFFh

5B0000h–5BFFFFh 2D8000h–2DFFFFh

SA99 1011100xxx 64/32 5C0000h–5CFFFFh 2E0000h–2E7FFFh

SA100 1011101xxx 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh

1A0000h–1AFFFFh D0000h–D7FFFh SA101 1011110xxx 64/32

5E0000h–5EFFFFh 2F0000h–2FFFFFh

5F0000h–5FFFFFh 2F8000h–2FFFFFh

600000h–60FFFFh 300000h–307FFFh

610000h–61FFFFh 308000h–30FFFFh

620000h–62FFFFh 310000h–317FFFh

630000h–63FFFFh 318000h–31FFFFh

640000h–64FFFFh 320000h–327FFFh

650000h–65FFFFh 328000h–32FFFFh

660000h–66FFFFh 330000h–337FFFh

670000h–67FFFFh 338000h–33FFFFh

680000h–68FFFFh 340000h–347FFFh

690000h–69FFFFh 348000h–34FFFFh

6A0000h–6AFFFFh 350000h–357FFFh

6B0000h–6BFFFFh 358000h–35FFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh F9000h–107FFFh SA107 1100100xxx 64/32

210000h–21FFFFh 108000h–10FFFFh SA108 1100101xxx 64/32

220000h–22FFFFh 110000h–117FFFh SA109 1100110xxx 64/32

230000h–23FFFFh 118000h–11FFFFh SA110 1100111xxx 64/32

240000h–24FFFFh 120000h–127FFFh SA111 1101000xxx 64/32

250000h–25FFFFh 128000h–12FFFFh SA112 1101001xxx 64/32

260000h–26FFFFh 130000h–137FFFh SA113 1101010xxx 64/32

270000h–27FFFFh 138000h–13FFFFh SA114 1101011xxx 64/32

D8000h–DFFFFh SA102 1011111xxx 64/32

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

SA103 1100000xxx 64/32

SA104 1100001xxx 64/32

SA105 1100010xxx 64/32

SA106 1100011xxx 64/32

280000h–28FFFFh 140000h–147FFFh SA115 1101100xxx 64/32 6C0000h–6CFFFFh 360000h–367FFFh

290000h–29FFFFh 148000h–14FFFFh SA116 1101101xxx 64/32 6D0000h–6DFFFFh 368000h–36FFFFh

2A0000h–2AFFFFh 150000h–157FFFh SA117 1101110xxx 64/32

2B0000h–2BFFFFh 158000h–15FFFFh SA118 1101111xxx 64/32

2C0000h–2CFFFFh 160000h–167FFFh SA119 1110000xxx 64/32

2D0000h–2DFFFFh 168000h–16FFFFh SA120 1110001xxx 64/32

2E0000h–2EFFFFh 170000h–177FFFh SA121 1110010xxx 64/32

2F0000h–2FFFFFh 178000h–17FFFFh SA122 1110011xxx 64/32

300000h–30FFFFh 180000h–187FFFh SA123 1110100xxx 64/32

310000h–31FFFFh 188000h–18FFFFh SA124 1110101xxx 64/32

320000h–32FFFFh 190000h–197FFFh SA125 1110110xxx 64/32

330000h–33FFFFh 198000h–19FFFFh SA126 1110111xxx 64/32

340000h–34FFFFh 1A0000h–1A7FFFh SA127 1111000xxx 64/32

350000h–35FFFFh 1A8000h–1AFFFFh SA128 1111001xxx 64/32

360000h–36FFFFh 1B0000h–1B7FFFh SA129 1111010xxx 64/32

370000h–37FFFFh 1B8000h–1BFFFFh SA130 1111011xxx 64/32

6E0000h–6EFFFFh 370000h–377FFFh

6F0000h–6FFFFFh 378000h–37FFFFh

700000h–70FFFFh 380000h–387FFFh

710000h–71FFFFh 388000h–38FFFFh

720000h–72FFFFh 390000h–397FFFh

730000h–73FFFFh 398000h–39FFFFh

740000h–74FFFFh 3A0000h–3A7FFFh

750000h–75FFFFh 3A8000h–3AFFFFh

760000h–76FFFFh 3B0000h–3B7FFFh

770000h–77FFFFh 3B8000h–3BFFFFh

780000h–78FFFFh 3C0000h–3C7FFFh

790000h–79FFFFh 3C8000h–3CFFFFh

7A0000h–7AFFFFh 3D0000h–3D7FFFh

7B0000h–7BFFFFh 3D8000h–3DFFFFh

380000h–38FFFFh 1C0000h–1C7FFFh SA131 1111100xxx 64/32 7C0000h–7CFFFFh 3E0000h–3E7FFFh

390000h–39FFFFh 1C8000h–1CFFFFh SA132 1111101xxx 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

3A0000h–3AFFFFh 1D0000h–1D7FFFh SA133 1111110xxx 64/32

3B0000h–3BFFFFh 1D8000h–1DFFFFh SA134 1111111000 64/32

3C0000h–3CFFFFh 1E0000h–1E7FFFh

7E0000h–7EFFFFh 3F0000h–3F7FFFh

7F0000h–7FFFFFh 3F8000h–3FFFFFh

34

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 14. S29GL064M (Model R5) Sector Addresses

16-bit

Address

Range

16-bit

Address

Range

16-bit

Address

Range

A21–A15

SA0 0 0 0 0 0 0 0

SA1 0 0 0 0 0 0 1

SA2 0 0 0 0 0 1 0

SA3 0 0 0 0 0 1 1

SA4 0 0 0 0 1 0 0

SA5 0 0 0 0 1 0 1

SA6 0 0 0 0 1 1 0

SA7 0 0 0 0 1 1 1

SA8 0 0 0 1 0 0 0

SA9 0 0 0 1 0 0 1

SA10 0 0 0 1 0 1 0

SA11 0 0 0 1 0 1 1

SA12 0 0 0 1 1 0 0

SA13 0 0 0 1 1 0 1

SA14 0 0 0 1 1 1 0

SA15 0 0 0 1 1 1 1

SA16 0 0 1 0 0 0 0

SA17 0 0 1 0 0 0 1

SA18 0 0 1 0 0 1 0

SA19 0 0 1 0 0 1 1

SA20 0 0 1 0 1 0 0

SA21 0 0 1 0 1 0 1

SA22 0 0 1 0 1 1 0

SA23 0 0 1 0 1 1 1

SA24 0 0 1 1 0 0 0

SA25 0 0 1 1 0 0 1

SA26 0 0 1 1 0 1 0

SA27 0 0 1 1 0 1 1

SA28 0 0 1 1 1 0 0

SA29 0 0 1 1 1 0 1

SA30 0 0 1 1 1 1 0

SA31 0 0 1 1 1 1 1

SA32 0 1 0 0 0 0 0

SA33 0 1 0 0 0 0 1

SA34 0 1 0 0 0 1 0

SA35 0 1 0 0 0 1 1

SA36 0 1 0 0 1 0 0

SA37 0 1 0 0 1 0 1

SA38 0 1 0 0 1 1 0

SA39 0 1 0 0 1 1 1

SA40 0 1 0 1 0 0 0

SA41 0 1 0 1 0 0 1

SA42 0 1 0 1 0 1 0

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

SA43 0 1 0 1 0 1 1

SA44 0 1 0 1 1 0 0

SA45 0 1 0 1 1 0 1

SA46 0 1 0 1 1 1 0

SA47 0 1 0 1 1 1 1

SA48 0 1 1 0 0 0 0

SA49 0 1 1 0 0 0 1

SA50 0 1 1 0 0 1 0

SA51 0 1 1 0 0 1 1

SA52 0 1 1 0 1 0 0

SA53 0 1 1 0 1 0 1

SA54 0 1 1 0 1 1 0

SA55 0 1 1 0 1 1 1

SA56 0 1 1 1 0 0 0

SA57 0 1 1 1 0 0 1

SA58 0 1 1 1 0 1 0

SA59 0 1 1 1 0 1 1

SA60 0 1 1 1 1 0 0

SA61 0 1 1 1 1 0 1

SA62 0 1 1 1 1 1 0

SA63 0 1 1 1 1 1 1

SA64 1 0 0 0 0 0 0

SA65 1 0 0 0 0 0 1

SA66 1 0 0 0 0 1 0

SA67 1 0 0 0 0 1 1

SA68 1 0 0 0 1 0 0

SA69 1 0 0 0 1 0 1

SA70 1 0 0 0 1 1 0

SA71 1 0 0 0 1 1 1

SA72 1 0 0 1 0 0 0

SA73 1 0 0 1 0 0 1

SA74 1 0 0 1 0 1 0

SA75 1 0 0 1 0 1 1

SA76 1 0 0 1 1 0 0

SA77 1 0 0 1 1 0 1

SA78 1 0 0 1 1 1 0

SA79 1 0 0 1 1 1 1

SA80 1 0 1 0 0 0 0

SA81 1 0 1 0 0 0 1

SA82 1 0 1 0 0 1 0

SA83 1 0 1 0 0 1 1

SA84 1 0 1 0 1 0 0

SA85 1 0 1 0 1 0 1

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

SA86 1 0 1 0 1 1 0

SA87 1 0 1 0 1 1 1

SA88 1 0 1 1 0 0 0

SA89 1 0 1 1 0 0 1

SA90 1 0 1 1 0 1 0

SA91 1 0 1 1 0 1 1

SA92 1 0 1 1 1 0 0

SA93 1 0 1 1 1 0 1

SA94 1 0 1 1 1 1 0

SA95 1 0 1 1 1 1 1

SA96 1 1 0 0 0 0 0

SA97 1 1 0 0 0 0 1

SA98 1 1 0 0 0 1 0

SA99 1 1 0 0 0 1 1

SA100 1 1 0 0 1 0 0

SA101 1 1 0 0 1 0 1

SA102 1 1 0 0 1 1 0

SA103 1 1 0 0 1 1 1

SA104 1 1 0 1 0 0 0

SA105 1 1 0 1 0 0 1

SA106 1 1 0 1 0 1 0

SA107 1 1 0 1 0 1 1

SA108 1 1 0 1 1 0 0

SA109 1 1 0 1 1 0 1

SA110 1 1 0 1 1 1 0

SA111 1 1 0 1 1 1 1

SA112 1 1 1 0 0 0 0

SA113 1 1 1 0 0 0 1

SA114 1 1 1 0 0 1 0

SA115 1 1 1 0 0 1 1

SA116 1 1 1 0 1 0 0

SA117 1 1 1 0 1 0 1

SA118 1 1 1 0 1 1 0

SA119 1 1 1 0 1 1 1

SA120 1 1 1 1 0 0 0

SA121 1 1 1 1 0 0 1

SA122 1 1 1 1 0 1 0

SA123 1 1 1 1 0 1 1

SA124 1 1 1 1 1 0 0

SA125 1 1 1 1 1 0 1

SA126 1 1 1 1 1 1 0

SA127 1 1 1 1 1 1 1

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

35

D a t a S h e e t

Table 15. S29GL064M (Model R6, R7) Sector Addresses

16-bit

Address

Range

16-bit

Address

Range

16-bit

Address

Range

A21–A15

SA0 0 0 0 0 0 0 0

SA1 0 0 0 0 0 0 1

SA2 0 0 0 0 0 1 0

SA3 0 0 0 0 0 1 1

SA4 0 0 0 0 1 0 0

SA5 0 0 0 0 1 0 1

SA6 0 0 0 0 1 1 0

SA7 0 0 0 0 1 1 1

SA8 0 0 0 1 0 0 0

SA9 0 0 0 1 0 0 1

SA10 0 0 0 1 0 1 0

SA11 0 0 0 1 0 1 1

SA12 0 0 0 1 1 0 0

SA13 0 0 0 1 1 0 1

SA14 0 0 0 1 1 1 0

SA15 0 0 0 1 1 1 1

SA16 0 0 1 0 0 0 0

SA17 0 0 1 0 0 0 1

SA18 0 0 1 0 0 1 0

SA19 0 0 1 0 0 1 1

SA20 0 0 1 0 1 0 0

SA21 0 0 1 0 1 0 1

SA22 0 0 1 0 1 1 0

SA23 0 0 1 0 1 1 1

SA24 0 0 1 1 0 0 0

SA25 0 0 1 1 0 0 1

SA26 0 0 1 1 0 1 0

SA27 0 0 1 1 0 1 1

SA28 0 0 1 1 1 0 0

SA29 0 0 1 1 1 0 1

SA30 0 0 1 1 1 1 0

SA31 0 0 1 1 1 1 1

SA32 0 1 0 0 0 0 0

SA33 0 1 0 0 0 0 1

SA34 0 1 0 0 0 1 0

SA35 0 1 0 0 0 1 1

SA36 0 1 0 0 1 0 0

SA37 0 1 0 0 1 0 1

SA38 0 1 0 0 1 1 0

SA39 0 1 0 0 1 1 1

SA40 0 1 0 1 0 0 0

SA41 0 1 0 1 0 0 1

SA42 0 1 0 1 0 1 0

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

SA43 0 1 0 1 0 1 1

SA44 0 1 0 1 1 0 0

SA45 0 1 0 1 1 0 1

SA46 0 1 0 1 1 1 0

SA47 0 1 0 1 1 1 1

SA48 0 1 1 0 0 0 0

SA49 0 1 1 0 0 0 1

SA50 0 1 1 0 0 1 0

SA51 0 1 1 0 0 1 1

SA52 0 1 1 0 1 0 0

SA53 0 1 1 0 1 0 1

SA54 0 1 1 0 1 1 0

SA55 0 1 1 0 1 1 1

SA56 0 1 1 1 0 0 0

SA57 0 1 1 1 0 0 1

SA58 0 1 1 1 0 1 0

SA59 0 1 1 1 0 1 1

SA60 0 1 1 1 1 0 0

SA61 0 1 1 1 1 0 1

SA62 0 1 1 1 1 1 0

SA63 0 1 1 1 1 1 1

SA64 1 0 0 0 0 0 0

SA65 1 0 0 0 0 0 1

SA66 1 0 0 0 0 1 0

SA67 1 0 0 0 0 1 1

SA68 1 0 0 0 1 0 0

SA69 1 0 0 0 1 0 1

SA70 1 0 0 0 1 1 0

SA71 1 0 0 0 1 1 1

SA72 1 0 0 1 0 0 0

SA73 1 0 0 1 0 0 1

SA74 1 0 0 1 0 1 0

SA75 1 0 0 1 0 1 1

SA76 1 0 0 1 1 0 0

SA77 1 0 0 1 1 0 1

SA78 1 0 0 1 1 1 0

SA79 1 0 0 1 1 1 1

SA80 1 0 1 0 0 0 0

SA81 1 0 1 0 0 0 1

SA82 1 0 1 0 0 1 0

SA83 1 0 1 0 0 1 1

SA84 1 0 1 0 1 0 0

SA85 1 0 1 0 1 0 1

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

SA86 1 0 1 0 1 1 0

SA87 1 0 1 0 1 1 1

SA88 1 0 1 1 0 0 0

SA89 1 0 1 1 0 0 1

SA90 1 0 1 1 0 1 0

SA91 1 0 1 1 0 1 1

SA92 1 0 1 1 1 0 0

SA93 1 0 1 1 1 0 1

SA94 1 0 1 1 1 1 0

SA95 1 0 1 1 1 1 1

SA96 1 1 0 0 0 0 0

SA97 1 1 0 0 0 0 1

SA98 1 1 0 0 0 1 0

SA99 1 1 0 0 0 1 1

SA100 1 1 0 0 1 0 0

SA101 1 1 0 0 1 0 1

SA102 1 1 0 0 1 1 0

SA103 1 1 0 0 1 1 1

SA104 1 1 0 1 0 0 0

SA105 1 1 0 1 0 0 1

SA106 1 1 0 1 0 1 0

SA107 1 1 0 1 0 1 1

SA108 1 1 0 1 1 0 0

SA109 1 1 0 1 1 0 1

SA110 1 1 0 1 1 1 0

SA111 1 1 0 1 1 1 1

SA112 1 1 1 0 0 0 0

SA113 1 1 1 0 0 0 1

SA114 1 1 1 0 0 1 0

SA115 1 1 1 0 0 1 1

SA116 1 1 1 0 1 0 0

SA117 1 1 1 0 1 0 1

SA118 1 1 1 0 1 1 0

SA119 1 1 1 0 1 1 1

SA120 1 1 1 1 0 0 0

SA121 1 1 1 1 0 0 1

SA122 1 1 1 1 0 1 0

SA123 1 1 1 1 0 1 1

SA124 1 1 1 1 1 0 0

SA125 1 1 1 1 1 0 1

SA126 1 1 1 1 1 1 0

SA127 1 1 1 1 1 1 1

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

36

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 16. S29GL128M Sector Address Table (Sheet 1 of 2)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A22–A15

(KB/

Kwords)

SA0 0 0 0 0 0 0 0 0 64/32

SA1 0 0 0 0 0 0 0 1 64/32

SA2 0 0 0 0 0 0 1 0 64/32

SA3 0 0 0 0 0 0 1 1 64/32

SA4 0 0 0 0 0 1 0 0 64/32

SA5 0 0 0 0 0 1 0 1 64/32

SA6 0 0 0 0 0 1 1 0 64/32

SA7 0 0 0 0 0 1 1 1 64/32

SA8 0 0 0 0 1 0 0 0 64/32

SA9 0 0 0 0 1 0 0 1 64/32

SA10 0 0 0 0 1 0 1 0 64/32

SA11 0 0 0 0 1 0 1 1 64/32

SA12 0 0 0 0 1 1 0 0 64/32

SA13 0 0 0 0 1 1 0 1 64/32

SA14 0 0 0 0 1 1 1 0 64/32

SA15 0 0 0 0 1 1 1 1 64/32

SA16 0 0 0 1 0 0 0 0 64/32

SA17 0 0 0 1 0 0 0 1 64/32

SA18 0 0 0 1 0 0 1 0 64/32

SA19 0 0 0 1 0 0 1 1 64/32

SA20 0 0 0 1 0 1 0 0 64/32

SA21 0 0 0 1 0 1 0 1 64/32

SA22 0 0 0 1 0 1 1 0 64/32

SA23 0 0 0 1 0 1 1 1 64/32

SA24 0 0 0 1 1 0 0 0 64/32

SA25 0 0 0 1 1 0 0 1 64/32

SA26 0 0 0 1 1 0 1 0 64/32

SA27 0 0 0 1 1 0 1 1 64/32

SA28 0 0 0 1 1 1 0 0 64/32

SA29 0 0 0 1 1 1 0 1 64/32

SA30 0 0 0 1 1 1 1 0 64/32

SA31 0 0 0 1 1 1 1 1 64/32

SA32 0 0 1 0 0 0 0 0 64/32

SA33 0 0 1 0 0 0 0 1 64/32

SA34 0 0 1 0 0 0 1 0 64/32

SA35 0 0 1 0 0 0 1 1 64/32

SA36 0 0 1 0 0 1 0 0 64/32

SA37 0 0 1 0 0 1 0 1 64/32

SA38 0 0 1 0 0 1 1 0 64/32

SA39 0 0 1 0 0 1 1 1 64/32

SA40 0 0 1 0 1 0 0 0 64/32

SA41 0 0 1 0 1 0 0 1 64/32

SA42 0 0 1 0 1 0 1 0 64/32

SA43 0 0 1 0 1 0 1 1 64/32

SA44 0 0 1 0 1 1 0 0 64/32

SA45 0 0 1 0 1 1 0 1 64/32

SA46 0 0 1 0 1 1 1 0 64/32

SA47 0 0 1 0 1 1 1 1 64/32

SA48 0 0 1 1 0 0 0 0 64/32

SA49 0 0 1 1 0 0 0 1 64/32

SA50 0 0 1 1 0 0 1 0 64/32

SA51 0 0 1 1 0 0 1 1 64/32

SA52 0 0 1 1 0 1 0 0 64/32

SA53 0 0 1 1 0 1 0 1 64/32

SA54 0 0 1 1 0 1 1 0 64/32

SA55 0 0 1 1 0 1 1 1 64/32

SA56 0 0 1 1 1 0 0 0 64/32

SA57 0 0 1 1 1 0 0 1 64/32

SA58 0 0 1 1 1 0 1 0 64/32

SA59 0 0 1 1 1 0 1 1 64/32

SA60 0 0 1 1 1 1 0 0 64/32

SA61 0 0 1 1 1 1 0 1 64/32

SA62 0 0 1 1 1 1 1 0 64/32

SA63 0 0 1 1 1 1 1 1 64/32

SA64 0 1 0 0 0 0 0 0 64/32

SA65 0 1 0 0 0 0 0 1 64/32

SA66 0 1 0 0 0 0 1 0 64/32

SA67 0 1 0 0 0 0 1 1 64/32

000000–00FFFF 000000–007FFF

010000–01FFFF 008000–00FFFF

020000–02FFFF 010000–017FFF

030000–03FFFF 018000–01FFFF

040000–04FFFF 020000–027FFF

050000–05FFFF 028000–02FFFF

060000–06FFFF 030000–037FFF

070000–07FFFF 038000–03FFFF

080000–08FFFF 040000–047FFF

090000–09FFFF 048000–04FFFF

0A0000–0AFFFF 050000–057FFF

0B0000–0BFFFF 058000–05FFFF

0C0000–0CFFFF 060000–067FFF

0D0000–0DFFFF 068000–06FFFF

0E0000–0EFFFF 070000–077FFF

0F0000–0FFFFF 078000–07FFFF

100000–10FFFF 080000–087FFF

110000–11FFFF 088000–08FFFF

120000–12FFFF 090000–097FFF

130000–13FFFF 098000–09FFFF

140000–14FFFF 0A0000–0A7FFF

150000–15FFFF 0A8000–0AFFFF

160000–16FFFF 0B0000–0B7FFF

170000–17FFFF 0B8000–0BFFFF

180000–18FFFF 0C0000–0C7FFF

190000–19FFFF 0C8000–0CFFFF

SA68 0 1 0 0 0 1 0 0 64/32

SA69 0 1 0 0 0 1 0 1 64/32

SA70 0 1 0 0 0 1 1 0 64/32

SA71 0 1 0 0 0 1 1 1 64/32

SA72 0 1 0 0 1 0 0 0 64/32

SA73 0 1 0 0 1 0 0 1 64/32

SA74 0 1 0 0 1 0 1 0 64/32

SA75 0 1 0 0 1 0 1 1 64/32

SA76 0 1 0 0 1 1 0 0 64/32

SA77 0 1 0 0 1 1 0 1 64/32

SA78 0 1 0 0 1 1 1 0 64/32

SA79 0 1 0 0 1 1 1 1 64/32

SA80 0 1 0 1 0 0 0 0 64/32

SA81 0 1 0 1 0 0 0 1 64/32

SA82 0 1 0 1 0 0 1 0 64/32

SA83 0 1 0 1 0 0 1 1 64/32

SA84 0 1 0 1 0 1 0 0 64/32

SA85 0 1 0 1 0 1 0 1 64/32

SA86 0 1 0 1 0 1 1 0 64/32

SA87 0 1 0 1 0 1 1 1 64/32

SA88 0 1 0 1 1 0 0 0 64/32

SA89 0 1 0 1 1 0 0 1 64/32

SA90 0 1 0 1 1 0 1 0 64/32

SA91 0 1 0 1 1 0 1 1 64/32

SA92 0 1 0 1 1 1 0 0 64/32

SA93 0 1 0 1 1 1 0 1 64/32

440000–44FFFF

450000–45FFFF

460000–46FFFF

470000–47FFFF

480000–48FFFF

490000–49FFFF

4A0000–4AFFFF 250000–257FFF

4B0000–4BFFFF 258000–25FFFF

4C0000–4CFFFF 260000–267FFF

4D0000–4DFFFF 268000–26FFFF

4E0000–4EFFFF

4F0000–4FFFFF

500000–50FFFF

510000–51FFFF

520000–52FFFF

530000–53FFFF

540000–54FFFF 2A0000–2A7FFF

550000–55FFFF 2A8000–2AFFFF

560000–56FFFF 2B0000–2B7FFF

570000–57FFFF 2B8000–2BFFFF

580000–58FFFF 2C0000–2C7FFF

590000–59FFFF 2C8000–2CFFFF

5A0000–5AFFFF 2D0000–2D7FFF

5B0000–5BFFFF 2D8000–2DFFFF

5C0000–5CFFFF 2E0000–2E7FFF

5D0000–5DFFFF 2E8000–2EFFFF

5E0000–5EFFFF

5F0000–5FFFFF

600000–60FFFF

610000–61FFFF

620000–62FFFF

630000–63FFFF

640000–64FFFF

650000–65FFFF

660000–66FFFF

670000–67FFFF

680000–68FFFF

690000–69FFFF

6A0000–6AFFFF 350000–357FFF

6B0000–6BFFFF 358000–35FFFF

6C0000–6CFFFF 360000–367FFF

6D0000–6DFFFF 368000–36FFFF

6E0000–6EFFFF

6F0000–6FFFFF

700000–70FFFF

710000–71FFFF

720000–72FFFF

730000–73FFFF

740000–74FFFF 3A0000–3A7FFF

750000–75FFFF 3A8000–3AFFFF

760000–76FFFF 3B0000–3B7FFF

770000–77FFFF 3B8000–3BFFFF

780000–78FFFF 3C0000–3C7FFF

790000–79FFFF 3C8000–3CFFFF

7A0000–7AFFFF 3D0000–3D7FFF

7B0000–7BFFFF 3D8000–3DFFFF

7C0000–7CFFFF 3E0000–3E7FFF

7D0000–7DFFFF 3E8000–3EFFFF

7E0000–7EFFFF

7F0000–7FFFFF

800000–80FFFF

810000–81FFFF

820000–82FFFF

830000–83FFFF

840000–84FFFF

850000–85FFFF

860000–86FFFF

870000–87FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

1A0000–1AFFFF 0D0000–0D7FFF SA94 0 1 0 1 1 1 1 0 64/32

2F0000–2F7FFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

1B0000–1BFFFF 0D8000–0DFFFF

1C0000–1CFFFF 0E0000–0E7FFF

1D0000–1DFFFF 0E8000–0EFFFF

1E0000–1EFFFF 0F0000–0F7FFF

SA95 0 1 0 1 1 1 1 1 64/32

SA96 0 1 1 0 0 0 0 0 64/32

SA97 0 1 1 0 0 0 0 1 64/32

SA98 0 1 1 0 0 0 1 0 64/32

SA99 0 1 1 0 0 0 1 1 64/32

1F0000–1FFFFF

0F8000–0FFFFF

200000–20FFFF 100000–107FFF SA100 0 1 1 0 0 1 0 0 64/32

210000–21FFFF 108000–10FFFF SA101 0 1 1 0 0 1 0 1 64/32

220000–22FFFF 110000–117FFF SA102 0 1 1 0 0 1 1 0 64/32

230000–23FFFF 118000–11FFFF SA103 0 1 1 0 0 1 1 1 64/32

240000–24FFFF 120000–127FFF SA104 0 1 1 0 1 0 0 0 64/32

250000–25FFFF 128000–12FFFF SA105 0 1 1 0 1 0 0 1 64/32

260000–26FFFF 130000–137FFF SA106 0 1 1 0 1 0 1 0 64/32

270000–27FFFF 138000–13FFFF SA107 0 1 1 0 1 0 1 1 64/32

280000–28FFFF 140000–147FFF SA108 0 1 1 0 1 1 0 0 64/32

290000–29FFFF 148000–14FFFF SA109 0 1 1 0 1 1 0 1 64/32

2A0000–2AFFFF 150000–157FFF SA110 0 1 1 0 1 1 1 0 64/32

2B0000–2BFFFF 158000–15FFFF SA111 0 1 1 0 1 1 1 1 64/32

2C0000–2CFFFF 160000–167FFF SA112 0 1 1 1 0 0 0 0 64/32

2D0000–2DFFFF 168000–16FFFF SA113 0 1 1 1 0 0 0 1 64/32

2E0000–2EFFFF 170000–177FFF SA114 0 1 1 1 0 0 1 0 64/32

2F0000–2FFFFF 178000–17FFFF SA115 0 1 1 1 0 0 1 1 64/32

300000–30FFFF 180000–187FFF SA116 0 1 1 1 0 1 0 0 64/32

310000–31FFFF 188000–18FFFF SA117 0 1 1 1 0 1 0 1 64/32

320000–32FFFF 190000–197FFF SA118 0 1 1 1 0 1 1 0 64/32

330000–33FFFF 198000–19FFFF SA119 0 1 1 1 0 1 1 1 64/32

340000–34FFFF 1A0000–1A7FFF SA120 0 1 1 1 1 0 0 0 64/32

350000–35FFFF 1A8000–1AFFFF SA121 0 1 1 1 1 0 0 1 64/32

360000–36FFFF 1B0000–1B7FFF SA122 0 1 1 1 1 0 1 0 64/32

370000–37FFFF 1B8000–1BFFFF SA123 0 1 1 1 1 0 1 1 64/32

380000–38FFFF 1C0000–1C7FFF SA124 0 1 1 1 1 1 0 0 64/32

390000–39FFFF 1C8000–1CFFFF SA125 0 1 1 1 1 1 0 1 64/32

3A0000–3AFFFF 1D0000–1D7FFF SA126 0 1 1 1 1 1 1 0 64/32

3B0000–3BFFFF 1D8000–1DFFFF SA127 0 1 1 1 1 1 1 1 64/32

3C0000–3CFFFF 1E0000–1E7FFF SA128 1 0 0 0 0 0 0 0 64/32

3D0000–3DFFFF 1E8000–1EFFFF SA129 1 0 0 0 0 0 0 1 64/32

3E0000–3EFFFF 1F0000–1F7FFF SA130 1 0 0 0 0 0 1 0 64/32

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3F0000–3F7FFF

3F8000–3FFFFF

400000–407FFF

408000–40FFFF

410000–417FFF

418000–41FFFF

420000–427FFF

428000–42FFFF

430000–437FFF

438000–43FFFF

3F0000–3FFFFF

1F8000–1FFFFF SA131 1 0 0 0 0 0 1 1 64/32

400000–40FFFF 200000–207FFF SA132 1 0 0 0 0 1 0 0 64/32

410000–41FFFF 208000–20FFFF SA133 1 0 0 0 0 1 0 1 64/32

420000–42FFFF 210000–217FFF SA134 1 0 0 0 0 1 1 0 64/32

430000–43FFFF 218000–21FFFF SA135 1 0 0 0 0 1 1 1 64/32

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

37

D a t a S h e e t

Table 16. S29GL128M Sector Address Table (Sheet 2 of 2)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A22–A15

(KB/

Kwords)

SA136 1 0 0 0 1 0 0 0 64/32

SA137 1 0 0 0 1 0 0 1 64/32

SA138 1 0 0 0 1 0 1 0 64/32

SA139 1 0 0 0 1 0 1 1 64/32

SA140 1 0 0 0 1 1 0 0 64/32

SA141 1 0 0 0 1 1 0 1 64/32

SA142 1 0 0 0 1 1 1 0 64/32

SA143 1 0 0 0 1 1 1 1 64/32

SA144 1 0 0 1 0 0 0 0 64/32

SA145 1 0 0 1 0 0 0 1 64/32

SA146 1 0 0 1 0 0 1 0 64/32

SA147 1 0 0 1 0 0 1 1 64/32

SA148 1 0 0 1 0 1 0 0 64/32

SA149 1 0 0 1 0 1 0 1 64/32

SA150 1 0 0 1 0 1 1 0 64/32

SA151 1 0 0 1 0 1 1 1 64/32

SA152 1 0 0 1 1 0 0 0 64/32

SA153 1 0 0 1 1 0 0 1 64/32

SA154 1 0 0 1 1 0 1 0 64/32

SA155 1 0 0 1 1 0 1 1 64/32

SA156 1 0 0 1 1 1 0 0 64/32

SA157 1 0 0 1 1 1 0 1 64/32

SA158 1 0 0 1 1 1 1 0 64/32

SA159 1 0 0 1 1 1 1 1 64/32

SA160 1 0 1 0 0 0 0 0 64/32

SA161 1 0 1 0 0 0 0 1 64/32

SA162 1 0 1 0 0 0 1 0 64/32

SA163 1 0 1 0 0 0 1 1 64/32

SA164 1 0 1 0 0 1 0 0 64/32

SA165 1 0 1 0 0 1 0 1 64/32

SA166 1 0 1 0 0 1 1 0 64/32

SA167 1 0 1 0 0 1 1 1 64/32

SA168 1 0 1 0 1 0 0 0 64/32

SA169 1 0 1 0 1 0 0 1 64/32

SA170 1 0 1 0 1 0 1 0 64/32

SA171 1 0 1 0 1 0 1 1 64/32

SA172 1 0 1 0 1 1 0 0 64/32

SA173 1 0 1 0 1 1 0 1 64/32

SA174 1 0 1 0 1 1 1 0 64/32

SA175 1 0 1 0 1 1 1 1 64/32

SA176 1 0 1 1 0 0 0 0 64/32

SA177 1 0 1 1 0 0 0 1 64/32

SA178 1 0 1 1 0 0 1 0 64/32

SA179 1 0 1 1 0 0 1 1 64/32

SA180 1 0 1 1 0 1 0 0 64/32

SA181 1 0 1 1 0 1 0 1 64/32

SA182 1 0 1 1 0 1 1 0 64/32

SA183 1 0 1 1 0 1 1 1 64/32

SA184 1 0 1 1 1 0 0 0 64/32

SA185 1 0 1 1 1 0 0 1 64/32

SA186 1 0 1 1 1 0 1 0 64/32

SA187 1 0 1 1 1 0 1 1 64/32

SA188 1 0 1 1 1 1 0 0 64/32

SA189 1 0 1 1 1 1 0 1 64/32

SA190 1 0 1 1 1 1 1 0 64/32

SA191 1 0 1 1 1 1 1 1 64/32

SA192 1 1 0 0 0 0 0 0 64/32

SA193 1 1 0 0 0 0 0 1 64/32

SA194 1 1 0 0 0 0 1 0 64/32

SA195 1 1 0 0 0 0 1 1 64/32

880000–88FFFF 440000–447FFF SA196 1 1 0 0 0 1 0 0 64/32

890000–89FFFF 448000–44FFFF SA197 1 1 0 0 0 1 0 1 64/32

8A0000–8AFFFF 450000–457FFF SA198 1 1 0 0 0 1 1 0 64/32

8B0000–8BFFFF 458000–45FFFF SA199 1 1 0 0 0 1 1 1 64/32

8C0000–8CFFFF 460000–467FFF SA200 1 1 0 0 1 0 0 0 64/32

8D0000–8DFFFF 468000–46FFFF SA201 1 1 0 0 1 0 0 1 64/32

8E0000–8EFFFF 470000–477FFF SA202 1 1 0 0 1 0 1 0 64/32

8F0000–8FFFFF 478000–47FFFF SA203 1 1 0 0 1 0 1 1 64/32

900000–90FFFF 480000–487FFF SA204 1 1 0 0 1 1 0 0 64/32

910000–91FFFF 488000–48FFFF SA205 1 1 0 0 1 1 0 1 64/32

920000–92FFFF 490000–497FFF SA206 1 1 0 0 1 1 1 0 64/32

930000–93FFFF 498000–49FFFF SA207 1 1 0 0 1 1 1 1 64/32

940000–94FFFF 4A0000–4A7FFF SA208 1 1 0 1 0 0 0 0 64/32

950000–95FFFF 4A8000–4AFFFF SA209 1 1 0 1 0 0 0 1 64/32

960000–96FFFF 4B0000–4B7FFF SA210 1 1 0 1 0 0 1 0 64/32

970000–97FFFF 4B8000–4BFFFF SA211 1 1 0 1 0 0 1 1 64/32

980000–98FFFF 4C0000–4C7FFF SA212 1 1 0 1 0 1 0 0 64/32

990000–99FFFF 4C8000–4CFFFF SA213 1 1 0 1 0 1 0 1 64/32

9A0000–9AFFFF 4D0000–4D7FFF SA214 1 1 0 1 0 1 1 0 64/32

9B0000–9BFFFF 4D8000–4DFFFF SA215 1 1 0 1 0 1 1 1 64/32

9C0000–9CFFFF 4E0000–4E7FFF SA216 1 1 0 1 1 0 0 0 64/32

9D0000–9DFFFF 4E8000–4EFFFF SA217 1 1 0 1 1 0 0 1 64/32

9E0000–9EFFFF 4F0000–4F7FFF SA218 1 1 0 1 1 0 1 0 64/32

C40000–C4FFFF 620000–627FFF

C50000–C5FFFF 628000–62FFFF

C60000–C6FFFF 630000–637FFF

C70000–C7FFFF 638000–63FFFF

C80000–C8FFFF 640000–647FFF

C90000–C9FFFF 648000–64FFFF

CA0000–CAFFFF 650000–657FFF

CB0000–CBFFFF 658000–65FFFF

CC0000–CCFFFF 660000–667FFF

CD0000–CDFFFF 668000–66FFFF

CE0000–CEFFFF 670000–677FFF

CF0000–CFFFFF

678000–67FFFF

D00000–D0FFFF 680000–687FFF

D10000–D1FFFF 688000–68FFFF

D20000–D2FFFF 690000–697FFF

D30000–D3FFFF 698000–69FFFF

D40000–D4FFFF 6A0000–6A7FFF

D50000–D5FFFF 6A8000–6AFFFF

D60000–D6FFFF 6B0000–6B7FFF

D70000–D7FFFF 6B8000–6BFFFF

D80000–D8FFFF 6C0000–6C7FFF

D90000–D9FFFF 6C8000–6CFFFF

DA0000–DAFFFF 6D0000–6D7FFF

DB0000–DBFFFF 6D8000–6DFFFF

DC0000–DCFFFF 6E0000–6E7FFF

DD0000–DDFFFF 6E8000–6EFFFF

DE0000–DEFFFF 6F0000–6F7FFF

9F0000–9FFFFF

4F8000–4FFFFF SA219 1 1 0 1 1 0 1 1 64/32

A00000–A0FFFF 500000–507FFF SA220 1 1 0 1 1 1 0 0 64/32

A10000–A1FFFF 508000–50FFFF SA221 1 1 0 1 1 1 0 1 64/32

A20000–A2FFFF 510000–517FFF SA222 1 1 0 1 1 1 1 0 64/32

A30000–A3FFFF 518000–51FFFF SA223 1 1 0 1 1 1 1 1 64/32

A40000–A4FFFF 520000–527FFF SA224 1 1 1 0 0 0 0 0 64/32

A50000–A5FFFF 528000–52FFFF SA225 1 1 1 0 0 0 0 1 64/32

A60000–A6FFFF 530000–537FFF SA226 1 1 1 0 0 0 1 0 64/32

A70000–A7FFFF 538000–53FFFF SA227 1 1 1 0 0 0 1 1 64/32

A80000–A8FFFF 540000–547FFF SA228 1 1 1 0 0 1 0 0 64/32

A90000–A9FFFF 548000–54FFFF SA229 1 1 1 0 0 1 0 1 64/32

AA0000–AAFFFF 550000–557FFF SA230 1 1 1 0 0 1 1 0 64/32

AB0000–ABFFFF 558000–55FFFF SA231 1 1 1 0 0 1 1 1 64/32

AC0000–ACFFFF 560000–567FFF SA232 1 1 1 0 1 0 0 0 64/32

AD0000–ADFFFF 568000–56FFFF SA233 1 1 1 0 1 0 0 1 64/32

AE0000–AEFFFF 570000–577FFF SA234 1 1 1 0 1 0 1 0 64/32

AF0000–AFFFFF 578000–57FFFF SA235 1 1 1 0 1 0 1 1 64/32

B00000–B0FFFF 580000–587FFF SA236 1 1 1 0 1 1 0 0 64/32

B10000–B1FFFF 588000–58FFFF SA237 1 1 1 0 1 1 0 1 64/32

B20000–B2FFFF 590000–597FFF SA238 1 1 1 0 1 1 1 0 64/32

B30000–B3FFFF 598000–59FFFF SA239 1 1 1 0 1 1 1 1 64/32

B40000–B4FFFF 5A0000–5A7FFF SA240 1 1 1 1 0 0 0 0 64/32

B50000–B5FFFF 5A8000–5AFFFF SA241 1 1 1 1 0 0 0 1 64/32

B60000–B6FFFF 5B0000–5B7FFF SA242 1 1 1 1 0 0 1 0 64/32

B70000–B7FFFF 5B8000–5BFFFF SA243 1 1 1 1 0 0 1 1 64/32

B80000–B8FFFF 5C0000–5C7FFF SA244 1 1 1 1 0 1 0 0 64/32

B90000–B9FFFF 5C8000–5CFFFF SA245 1 1 1 1 0 1 0 1 64/32

BA0000–BAFFFF 5D0000–5D7FFF SA246 1 1 1 1 0 1 1 0 64/32

BB0000–BBFFFF 5D8000–5DFFFF SA247 1 1 1 1 0 1 1 1 64/32

BC0000–BCFFFF 5E0000–5E7FFF SA248 1 1 1 1 1 0 0 0 64/32

BD0000–BDFFFF 5E8000–5EFFFF SA249 1 1 1 1 1 0 0 1 64/32

BE0000–BEFFFF 5F0000–5F7FFF SA250 1 1 1 1 1 0 1 0 64/32

BF0000–BFFFFF 5F8000–5FFFFF SA251 1 1 1 1 1 0 1 1 64/32

C00000–C0FFFF 600000–607FFF SA252 1 1 1 1 1 1 0 0 64/32

C10000–C1FFFF 608000–60FFFF SA253 1 1 1 1 1 1 0 1 64/32

C20000–C2FFFF 610000–617FFF SA254 1 1 1 1 1 1 1 0 64/32

C30000–C3FFFF 618000–61FFFF SA255 1 1 1 1 1 1 1 1 64/32

DF0000–DFFFFF

E00000–E0FFFF

E10000–E1FFFF

E20000–E2FFFF

E30000–E3FFFF

E40000–E4FFFF

E50000–E5FFFF

E60000–E6FFFF

E70000–E7FFFF

E80000–E8FFFF

E90000–E9FFFF

6F8000–6FFFFF

700000–707FFF

708000–70FFFF

710000–717FFF

718000–71FFFF

720000–727FFF

728000–72FFFF

730000–737FFF

738000–73FFFF

740000–747FFF

748000–74FFFF

EA0000–EAFFFF 750000–757FFF

EB0000–EBFFFF 758000–75FFFF

EC0000–ECFFFF 760000–767FFF

ED0000–EDFFFF 768000–76FFFF

EE0000–EEFFFF

EF0000–EFFFFF

F00000–F0FFFF

F10000–F1FFFF

F20000–F2FFFF

F30000–F3FFFF

F40000–F4FFFF

F50000–F5FFFF

F60000–F6FFFF

F70000–F7FFFF

F80000–F8FFFF

F90000–F9FFFF

770000–777FFF

778000–77FFFF

780000–787FFF

788000–78FFFF

790000–797FFF

798000–79FFFF

7A0000–7A7FFF

7A8000–7AFFFF

7B0000–7B7FFF

7B8000–7BFFFF

7C0000–7C7FFF

7C8000–7CFFFF

FA0000–FAFFFF 7D0000–7D7FFF

FB0000–FBFFFF 7D8000–7DFFFF

FC0000–FCFFFF

7E0000–7E7FFF

FD0000–FDFFFF 7E8000–7EFFFF

FE0000–FEFFFF

FF0000–FFFFFF

7F0000–7F7FFF

7F8000–7FFFFF

38

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 17. S29GL256M Sector Address Table (Sheet 1 of 4)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A23–A15

(KB/

Kwords)

SA0 0 0 0 0 0 0 0 0 0 64/32 0000000–000FFFF 000000–007FFF SA68 0 0 1 0 0 0 1 0 0 64/32 0440000–044FFFF 220000–227FFF

SA1 0 0 0 0 0 0 0 0 1 64/32 0010000–001FFFF 008000–00FFFF SA69 0 0 1 0 0 0 1 0 1 64/32 0450000–045FFFF 228000–22FFFF

SA2 0 0 0 0 0 0 0 1 0 64/32 0020000–002FFFF 010000–017FFF SA70 0 0 1 0 0 0 1 1 0 64/32 0460000–046FFFF 230000–237FFF

SA3 0 0 0 0 0 0 0 1 1 64/32 0030000–003FFFF 018000–01FFFF SA71 0 0 1 0 0 0 1 1 1 64/32 0470000–047FFFF 238000–23FFFF

SA4 0 0 0 0 0 0 1 0 0 64/32 0040000–004FFFF 020000–027FFF SA72 0 0 1 0 0 1 0 0 0 64/32 0480000–048FFFF 240000–247FFF

SA5 0 0 0 0 0 0 1 0 1 64/32 0050000–005FFFF 028000–02FFFF SA73 0 0 1 0 0 1 0 0 1 64/32 0490000–049FFFF 248000–24FFFF

SA6 0 0 0 0 0 0 1 1 0 64/32 0060000–006FFFF 030000–037FFF SA74 0 0 1 0 0 1 0 1 0 64/32 04A0000–04AFFFF 250000–257FFF

SA7 0 0 0 0 0 0 1 1 1 64/32 0070000–007FFFF 038000–03FFFF SA75 0 0 1 0 0 1 0 1 1 64/32 04B0000–04BFFFF 258000–25FFFF

SA8 0 0 0 0 0 1 0 0 0 64/32 0080000–008FFFF 040000–047FFF SA76 0 0 1 0 0 1 1 0 0 64/32 04C0000–04CFFFF 260000–267FFF

SA9 0 0 0 0 0 1 0 0 1 64/32 0090000–009FFFF 048000–04FFFF SA77 0 0 1 0 0 1 1 0 1 64/32 04D0000–04DFFFF 268000–26FFFF

SA10 0 0 0 0 0 1 0 1 0 64/32 00A0000–00AFFFF 050000–057FFF SA78 0 0 1 0 0 1 1 1 0 64/32 04E0000–04EFFFF 270000–277FFF

SA11 0 0 0 0 0 1 0 1 1 64/32 00B0000–00BFFFF 058000–05FFFF SA79 0 0 1 0 0 1 1 1 1 64/32

04F0000–04FFFFF 278000–27FFFF

SA12 0 0 0 0 0 1 1 0 0 64/32 00C0000–00CFFFF 060000–067FFF SA80 0 0 1 0 1 0 0 0 0 64/32 0500000–050FFFF 280000–287FFF

SA13 0 0 0 0 0 1 1 0 1 64/32 00D0000–00DFFFF 068000–06FFFF SA81 0 0 1 0 1 0 0 0 1 64/32 0510000–051FFFF 288000–28FFFF

SA14 0 0 0 0 0 1 1 1 0 64/32 00E0000–00EFFFF 070000–077FFF SA82 0 0 1 0 1 0 0 1 0 64/32 0520000–052FFFF 290000–297FFF

SA15 0 0 0 0 0 1 1 1 1 64/32 00F0000–00FFFFF 078000–07FFFF SA83 0 0 1 0 1 0 0 1 1 64/32 0530000–053FFFF 298000–29FFFF

SA16 0 0 0 0 1 0 0 0 0 64/32 0100000–010FFFF 080000–087FFF SA84 0 0 1 0 1 0 1 0 0 64/32 0540000–054FFFF 2A0000–2A7FFF

SA17 0 0 0 0 1 0 0 0 1 64/32 0110000–011FFFF 088000–08FFFF SA85 0 0 1 0 1 0 1 0 1 64/32 0550000–055FFFF 2A8000–2AFFFF

SA18 0 0 0 0 1 0 0 1 0 64/32 0120000–012FFFF 090000–097FFF SA86 0 0 1 0 1 0 1 1 0 64/32 0560000–056FFFF 2B0000–2B7FFF

SA19 0 0 0 0 1 0 0 1 1 64/32 0130000–013FFFF 098000–09FFFF SA87 0 0 1 0 1 0 1 1 1 64/32 0570000–057FFFF 2B8000–2BFFFF

SA20 0 0 0 0 1 0 1 0 0 64/32 0140000–014FFFF 0A0000–0A7FFF SA88 0 0 1 0 1 1 0 0 0 64/32 0580000–058FFFF 2C0000–2C7FFF

SA21 0 0 0 0 1 0 1 0 1 64/32 0150000–015FFFF 0A8000–0AFFFF SA89 0 0 1 0 1 1 0 0 1 64/32 0590000–059FFFF 2C8000–2CFFFF

SA22 0 0 0 0 1 0 1 1 0 64/32 0160000–016FFFF 0B0000–0B7FFF SA90 0 0 1 0 1 1 0 1 0 64/32 05A0000–05AFFFF 2D0000–2D7FFF

SA23 0 0 0 0 1 0 1 1 1 64/32 0170000–017FFFF 0B8000–0BFFFF SA91 0 0 1 0 1 1 0 1 1 64/32 05B0000–05BFFFF 2D8000–2DFFFF

SA24 0 0 0 0 1 1 0 0 0 64/32 0180000–018FFFF 0C0000–0C7FFF SA92 0 0 1 0 1 1 1 0 0 64/32 05C0000–05CFFFF 2E0000–2E7FFF

SA25 0 0 0 0 1 1 0 0 1 64/32 0190000–019FFFF 0C8000–0CFFFF SA93 0 0 1 0 1 1 1 0 1 64/32 05D0000–05DFFFF 2E8000–2EFFFF

SA26 0 0 0 0 1 1 0 1 0 64/32 01A0000–01AFFFF 0D0000–0D7FFF SA94 0 0 1 0 1 1 1 1 0 64/32 05E0000–05EFFFF 2F0000–2F7FFF

SA27 0 0 0 0 1 1 0 1 1 64/32 01B0000–01BFFFF 0D8000–0DFFFF SA95 0 0 1 0 1 1 1 1 1 64/32

05F0000–05FFFFF 2F8000–2FFFFF

SA28 0 0 0 0 1 1 1 0 0 64/32 01C0000–01CFFFF 0E0000–0E7FFF SA96 0 0 1 1 0 0 0 0 0 64/32 0600000–060FFFF 300000–307FFF

SA29 0 0 0 0 1 1 1 0 1 64/32 01D0000–01DFFFF 0E8000–0EFFFF SA97 0 0 1 1 0 0 0 0 1 64/32 0610000–061FFFF 308000–30FFFF

SA30 0 0 0 0 1 1 1 1 0 64/32 01E0000–01EFFFF 0F0000–0F7FFF SA98 0 0 1 1 0 0 0 1 0 64/32 0620000–062FFFF 310000–317FFF

SA31 0 0 0 0 1 1 1 1 1 64/32 01F0000–01FFFFF 0F8000–0FFFFF SA99 0 0 1 1 0 0 0 1 1 64/32 0630000–063FFFF 318000–31FFFF

SA32 0 0 0 1 0 0 0 0 0 64/32 0200000–020FFFF 100000–107FFF SA100 0 0 1 1 0 0 1 0 0 64/32 0640000–064FFFF 320000–327FFF

SA33 0 0 0 1 0 0 0 0 1 64/32 0210000–021FFFF 108000–10FFFF SA101 0 0 1 1 0 0 1 0 1 64/32 0650000–065FFFF 328000–32FFFF

SA34 0 0 0 1 0 0 0 1 0 64/32 0220000–022FFFF 110000–117FFF SA102 0 0 1 1 0 0 1 1 0 64/32 0660000–066FFFF 330000–337FFF

SA35 0 0 0 1 0 0 0 1 1 64/32 0230000–023FFFF 118000–11FFFF SA103 0 0 1 1 0 0 1 1 1 64/32 0670000–067FFFF 338000–33FFFF

SA36 0 0 0 1 0 0 1 0 0 64/32 0240000–024FFFF 120000–127FFF SA104 0 0 1 1 0 1 0 0 0 64/32 0680000–068FFFF 340000–347FFF

SA37 0 0 0 1 0 0 1 0 1 64/32 0250000–025FFFF 128000–12FFFF SA105 0 0 1 1 0 1 0 0 1 64/32 0690000–069FFFF 348000–34FFFF

SA38 0 0 0 1 0 0 1 1 0 64/32 0260000–026FFFF 130000–137FFF SA106 0 0 1 1 0 1 0 1 0 64/32 06A0000–06AFFFF 350000–357FFF

SA39 0 0 0 1 0 0 1 1 1 64/32 0270000–027FFFF 138000–13FFFF SA107 0 0 1 1 0 1 0 1 1 64/32 06B0000–06BFFFF 358000–35FFFF

SA40 0 0 0 1 0 1 0 0 0 64/32 0280000–028FFFF 140000–147FFF SA108 0 0 1 1 0 1 1 0 0 64/32 06C0000–06CFFFF 360000–367FFF

SA41 0 0 0 1 0 1 0 0 1 64/32 0290000–029FFFF 148000–14FFFF SA109 0 0 1 1 0 1 1 0 1 64/32 06D0000–06DFFFF 368000–36FFFF

SA42 0 0 0 1 0 1 0 1 0 64/32 02A0000–02AFFFF 150000–157FFF SA110 0 0 1 1 0 1 1 1 0 64/32 06E0000–06EFFFF 370000–377FFF

SA43 0 0 0 1 0 1 0 1 1 64/32 02B0000–02BFFFF 158000–15FFFF SA111 0 0 1 1 0 1 1 1 1 64/32

06F0000–06FFFFF 378000–37FFFF

SA44 0 0 0 1 0 1 1 0 0 64/32 02C0000–02CFFFF 160000–167FFF SA112 0 0 1 1 1 0 0 0 0 64/32 0700000–070FFFF 380000–387FFF

SA45 0 0 0 1 0 1 1 0 1 64/32 02D0000–02DFFFF 168000–16FFFF SA113 0 0 1 1 1 0 0 0 1 64/32 0710000–071FFFF 388000–38FFFF

SA46 0 0 0 1 0 1 1 1 0 64/32 02E0000–02EFFFF 170000–177FFF SA114 0 0 1 1 1 0 0 1 0 64/32 0720000–072FFFF 390000–397FFF

SA47 0 0 0 1 0 1 1 1 1 64/32 02F0000–02FFFFF 178000–17FFFF SA115 0 0 1 1 1 0 0 1 1 64/32 0730000–073FFFF 398000–39FFFF

SA48 0 0 0 1 1 0 0 0 0 64/32 0300000–030FFFF 180000–187FFF SA116 0 0 1 1 1 0 1 0 0 64/32 0740000–074FFFF 3A0000–3A7FFF

SA49 0 0 0 1 1 0 0 0 1 64/32 0310000–031FFFF 188000–18FFFF SA117 0 0 1 1 1 0 1 0 1 64/32 0750000–075FFFF 3A8000–3AFFFF

SA50 0 0 0 1 1 0 0 1 0 64/32 0320000–032FFFF 190000–197FFF SA118 0 0 1 1 1 0 1 1 0 64/32 0760000–076FFFF 3B0000–3B7FFF

SA51 0 0 0 1 1 0 0 1 1 64/32 0330000–033FFFF 198000–19FFFF SA119 0 0 1 1 1 0 1 1 1 64/32 0770000–077FFFF 3B8000–3BFFFF

SA52 0 0 0 1 1 0 1 0 0 64/32 0340000–034FFFF 1A0000–1A7FFF SA120 0 0 1 1 1 1 0 0 0 64/32 0780000–078FFFF 3C0000–3C7FFF

SA53 0 0 0 1 1 0 1 0 1 64/32 0350000–035FFFF 1A8000–1AFFFF SA121 0 0 1 1 1 1 0 0 1 64/32 0790000–079FFFF 3C8000–3CFFFF

SA54 0 0 0 1 1 0 1 1 0 64/32 0360000–036FFFF 1B0000–1B7FFF SA122 0 0 1 1 1 1 0 1 0 64/32 07A0000–07AFFFF 3D0000–3D7FFF

SA55 0 0 0 1 1 0 1 1 1 64/32 0370000–037FFFF 1B8000–1BFFFF SA123 0 0 1 1 1 1 0 1 1 64/32 07B0000–07BFFFF 3D8000–3DFFFF

SA56 0 0 0 1 1 1 0 0 0 64/32 0380000–038FFFF 1C0000–1C7FFF SA124 0 0 1 1 1 1 1 0 0 64/32 07C0000–07CFFFF 3E0000–3E7FFF

SA57 0 0 0 1 1 1 0 0 1 64/32 0390000–039FFFF 1C8000–1CFFFF SA125 0 0 1 1 1 1 1 0 1 64/32 07D0000–07DFFFF 3E8000–3EFFFF

SA58 0 0 0 1 1 1 0 1 0 64/32 03A0000–03AFFFF 1D0000–1D7FFF SA126 0 0 1 1 1 1 1 1 0 64/32 07E0000–07EFFFF 3F0000–3F7FFF

SA59 0 0 0 1 1 1 0 1 1 64/32 03B0000–03BFFFF 1D8000–1DFFFF SA127 0 0 1 1 1 1 1 1 1 64/32

07F0000–07FFFFF 3F8000–3FFFFF

SA60 0 0 0 1 1 1 1 0 0 64/32 03C0000–03CFFFF 1E0000–1E7FFF SA128 0 1 0 0 0 0 0 0 0 64/32 0800000–080FFFF 400000–407FFF

SA61 0 0 0 1 1 1 1 0 1 64/32 03D0000–03DFFFF 1E8000–1EFFFF SA129 0 1 0 0 0 0 0 0 1 64/32 0810000–081FFFF 408000–40FFFF

SA62 0 0 0 1 1 1 1 1 0 64/32 03E0000–03EFFFF 1F0000–1F7FFF SA130 0 1 0 0 0 0 0 1 0 64/32 0820000–082FFFF 410000–417FFF

SA63 0 0 0 1 1 1 1 1 1 64/32 03F0000–03FFFFF 1F8000–1FFFFF SA131 0 1 0 0 0 0 0 1 1 64/32 0830000–083FFFF 418000–41FFFF

SA64 0 0 1 0 0 0 0 0 0 64/32 0400000–040FFFF 200000–207FFF SA132 0 1 0 0 0 0 1 0 0 64/32 0840000–084FFFF 420000–427FFF

SA65 0 0 1 0 0 0 0 0 1 64/32 0410000–041FFFF 208000–20FFFF SA133 0 1 0 0 0 0 1 0 1 64/32 0850000–085FFFF 428000–42FFFF

SA66 0 0 1 0 0 0 0 1 0 64/32 0420000–042FFFF 210000–217FFF SA134 0 1 0 0 0 0 1 1 0 64/32 0860000–086FFFF 430000–437FFF

SA67 0 0 1 0 0 0 0 1 1 64/32 0430000–043FFFF 218000–21FFFF SA135 0 1 0 0 0 0 1 1 1 64/32 0870000–087FFFF 438000–43FFFF

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

39

D a t a S h e e t

Table 17. S29GL256M Sector Address Table (Sheet 2 of 4)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A23–A15

(KB/

Kwords)

SA136 0 1 0 0 0 1 0 0 0 64/32 0880000–088FFFF 440000–447FFF SA204 0 1 1 0 0 1 1 0 0 64/32 0CC0000–0CCFFFF 660000–667FFF

SA137 0 1 0 0 0 1 0 0 1 64/32 0890000–089FFFF 448000–44FFFF SA205 0 1 1 0 0 1 1 0 1 64/32 0CD0000–0CDFFFF 668000–66FFFF

SA138 0 1 0 0 0 1 0 1 0 64/32 08A0000–08AFFFF 450000–457FFF SA206 0 1 1 0 0 1 1 1 0 64/32 0CE0000–0CEFFFF 670000–677FFF

SA139 0 1 0 0 0 1 0 1 1 64/32 08B0000–08BFFFF 458000–45FFFF SA207 0 1 1 0 0 1 1 1 1 64/32 0CF0000–0CFFFFF 678000–67FFFF

SA140 0 1 0 0 0 1 1 0 0 64/32 08C0000–08CFFFF 460000–467FFF SA208 0 1 1 0 1 0 0 0 0 64/32 0D00000–0D0FFFF 680000–687FFF

SA141 0 1 0 0 0 1 1 0 1 64/32 08D0000–08DFFFF 468000–46FFFF SA209 0 1 1 0 1 0 0 0 1 64/32 0D10000–0D1FFFF 688000–68FFFF

SA142 0 1 0 0 0 1 1 1 0 64/32 08E0000–08EFFFF 470000–477FFF SA210 0 1 1 0 1 0 0 1 0 64/32 0D20000–0D2FFFF 690000–697FFF

SA143 0 1 0 0 0 1 1 1 1 64/32 08F0000–08FFFFF 478000–47FFFF SA211 0 1 1 0 1 0 0 1 1 64/32 0D30000–0D3FFFF 698000–69FFFF

SA144 0 1 0 0 1 0 0 0 0 64/32 0900000–090FFFF 480000–487FFF SA212 0 1 1 0 1 0 1 0 0 64/32 0D40000–0D4FFFF 6A0000–6A7FFF

SA145 0 1 0 0 1 0 0 0 1 64/32 0910000–091FFFF 488000–48FFFF SA213 0 1 1 0 1 0 1 0 1 64/32 0D50000–0D5FFFF 6A8000–6AFFFF

SA146 0 1 0 0 1 0 0 1 0 64/32 0920000–092FFFF 490000–497FFF SA214 0 1 1 0 1 0 1 1 0 64/32 0D60000–0D6FFFF 6B0000–6B7FFF

SA147 0 1 0 0 1 0 0 1 1 64/32 0930000–093FFFF 498000–49FFFF SA215 0 1 1 0 1 0 1 1 1 64/32 0D70000–0D7FFFF 6B8000–6BFFFF

SA148 0 1 0 0 1 0 1 0 0 64/32 0940000–094FFFF 4A0000–4A7FFF SA216 0 1 1 0 1 1 0 0 0 64/32 0D80000–0D8FFFF 6C0000–6C7FFF

SA149 0 1 0 0 1 0 1 0 1 64/32 0950000–095FFFF 4A8000–4AFFFF SA217 0 1 1 0 1 1 0 0 1 64/32 0D90000–0D9FFFF 6C8000–6CFFFF

SA150 0 1 0 0 1 0 1 1 0 64/32 0960000–096FFFF 4B0000–4B7FFF SA218 0 1 1 0 1 1 0 1 0 64/32 0DA0000–0DAFFFF 6D0000–6D7FFF

SA151 0 1 0 0 1 0 1 1 1 64/32 0970000–097FFFF 4B8000–4BFFFF SA219 0 1 1 0 1 1 0 1 1 64/32 0DB0000–0DBFFFF 6D8000–6DFFFF

SA152 0 1 0 0 1 1 0 0 0 64/32 0980000–098FFFF 4C0000–4C7FFF SA220 0 1 1 0 1 1 1 0 0 64/32 0DC0000–0DCFFFF 6E0000–6E7FFF

SA153 0 1 0 0 1 1 0 0 1 64/32 0990000–099FFFF 4C8000–4CFFFF SA221 0 1 1 0 1 1 1 0 1 64/32 0DD0000–0DDFFFF 6E8000–6EFFFF

SA154 0 1 0 0 1 1 0 1 0 64/32 09A0000–09AFFFF 4D0000–4D7FFF SA222 0 1 1 0 1 1 1 1 0 64/32 0DE0000–0DEFFFF 6F0000–6F7FFF

SA155 0 1 0 0 1 1 0 1 1 64/32 09B0000–09BFFFF 4D8000–4DFFFF SA223 0 1 1 0 1 1 1 1 1 64/32 0DF0000–0DFFFFF 6F8000–6FFFFF

SA156 0 1 0 0 1 1 1 0 0 64/32 09C0000–09CFFFF 4E0000–4E7FFF SA224 0 1 1 1 0 0 0 0 0 64/32 0E00000–0E0FFFF 700000–707FFF

SA157 0 1 0 0 1 1 1 0 1 64/32 09D0000–09DFFFF 4E8000–4EFFFF SA225 0 1 1 1 0 0 0 0 1 64/32 0E10000–0E1FFFF 708000–70FFFF

SA158 0 1 0 0 1 1 1 1 0 64/32 09E0000–09EFFFF 4F0000–4F7FFF SA226 0 1 1 1 0 0 0 1 0 64/32 0E20000–0E2FFFF 710000–717FFF

SA159 0 1 0 0 1 1 1 1 1 64/32 09F0000–09FFFFF 4F8000–4FFFFF SA227 0 1 1 1 0 0 0 1 1 64/32 0E30000–0E3FFFF 718000–71FFFF

SA160 0 1 0 1 0 0 0 0 0 64/32 0A00000–0A0FFFF 500000–507FFF SA228 0 1 1 1 0 0 1 0 0 64/32 0E40000–0E4FFFF 720000–727FFF

SA161 0 1 0 1 0 0 0 0 1 64/32 0A10000–0A1FFFF 508000–50FFFF SA229 0 1 1 1 0 0 1 0 1 64/32 0E50000–0E5FFFF 728000–72FFFF

SA162 0 1 0 1 0 0 0 1 0 64/32 0A20000–0A2FFFF 510000–517FFF SA230 0 1 1 1 0 0 1 1 0 64/32 0E60000–0E6FFFF 730000–737FFF

SA163 0 1 0 1 0 0 0 1 1 64/32 0A30000–0A3FFFF 518000–51FFFF SA231 0 1 1 1 0 0 1 1 1 64/32 0E70000–0E7FFFF 738000–73FFFF

SA164 0 1 0 1 0 0 1 0 0 64/32 0A40000–0A4FFFF 520000–527FFF SA232 0 1 1 1 0 1 0 0 0 64/32 0E80000–0E8FFFF 740000–747FFF

SA165 0 1 0 1 0 0 1 0 1 64/32 0A50000–0A5FFFF 528000–52FFFF SA233 0 1 1 1 0 1 0 0 1 64/32 0E90000–0E9FFFF 748000–74FFFF

SA166 0 1 0 1 0 0 1 1 0 64/32 0A60000–0A6FFFF 530000–537FFF SA234 0 1 1 1 0 1 0 1 0 64/32 0EA0000–0EAFFFF 750000–757FFF

SA167 0 1 0 1 0 0 1 1 1 64/32 0A70000–0A7FFFF 538000–53FFFF SA235 0 1 1 1 0 1 0 1 1 64/32 0EB0000–0EBFFFF 758000–75FFFF

SA168 0 1 0 1 0 1 0 0 0 64/32 0A80000–0A8FFFF 540000–547FFF SA236 0 1 1 1 0 1 1 0 0 64/32 0EC0000–0ECFFFF 760000–767FFF

SA169 0 1 0 1 0 1 0 0 1 64/32 0A90000–0A9FFFF 548000–54FFFF SA237 0 1 1 1 0 1 1 0 1 64/32 0ED0000–0EDFFFF 768000–76FFFF

SA170 0 1 0 1 0 1 0 1 0 64/32 0AA0000–0AAFFFF 550000–557FFF SA238 0 1 1 1 0 1 1 1 0 64/32 0EE0000–0EEFFFF 770000–777FFF

SA171 0 1 0 1 0 1 0 1 1 64/32 0AB0000–0ABFFFF 558000–55FFFF SA239 0 1 1 1 0 1 1 1 1 64/32

SA172 0 1 0 1 0 1 1 0 0 64/32 0AC0000–0ACFFFF 560000–567FFF SA240 0 1 1 1 1 0 0 0 0 64/32

SA173 0 1 0 1 0 1 1 0 1 64/32 0AD0000–0ADFFFF 568000–56FFFF SA241 0 1 1 1 1 0 0 0 1 64/32

SA174 0 1 0 1 0 1 1 1 0 64/32 0AE0000–0AEFFFF 570000–577FFF SA242 0 1 1 1 1 0 0 1 0 64/32

SA175 0 1 0 1 0 1 1 1 1 64/32 0AF0000–0AFFFFF 578000–57FFFF SA243 0 1 1 1 1 0 0 1 1 64/32

SA176 0 1 0 1 1 0 0 0 0 64/32 0B00000–0B0FFFF 580000–587FFF SA244 0 1 1 1 1 0 1 0 0 64/32

SA177 0 1 0 1 1 0 0 0 1 64/32 0B10000–0B1FFFF 588000–58FFFF SA245 0 1 1 1 1 0 1 0 1 64/32

SA178 0 1 0 1 1 0 0 1 0 64/32 0B20000–0B2FFFF 590000–597FFF SA246 0 1 1 1 1 0 1 1 0 64/32

SA179 0 1 0 1 1 0 0 1 1 64/32 0B30000–0B3FFFF 598000–59FFFF SA247 0 1 1 1 1 0 1 1 1 64/32

SA180 0 1 0 1 1 0 1 0 0 64/32 0B40000–0B4FFFF 5A0000–5A7FFF SA248 0 1 1 1 1 1 0 0 0 64/32

SA181 0 1 0 1 1 0 1 0 1 64/32 0B50000–0B5FFFF 5A8000–5AFFFF SA249 0 1 1 1 1 1 0 0 1 64/32

SA182 0 1 0 1 1 0 1 1 0 64/32 0B60000–0B6FFFF 5B0000–5B7FFF SA250 0 1 1 1 1 1 0 1 0 64/32

0EF0000–0EFFFFF 778000–77FFFF

0F00000–0F0FFFF 780000–787FFF

0F10000–0F1FFFF 788000–78FFFF

0F20000–0F2FFFF 790000–797FFF

0F30000–0F3FFFF 798000–79FFFF

0F40000–0F4FFFF 7A0000–7A7FFF

0F50000–0F5FFFF 7A8000–7AFFFF

0F60000–0F6FFFF 7B0000–7B7FFF

0F70000–0F7FFFF 7B8000–7BFFFF

0F80000–0F8FFFF 7C0000–7C7FFF

0F90000–0F9FFFF 7C8000–7CFFFF

0FA0000–0FAFFFF 7D0000–7D7FFF

SA183 0 1 0 1 1 0 1 1 1 64/32 0B70000–0B7FFFF 5B8000–5BFFFF SA251 0 1 1 1 1 1 0 1 1 64/32 0FB0000–0FBFFFF 7D8000–7DFFFF

SA184 0 1 0 1 1 1 0 0 0 64/32 0B80000–0B8FFFF 5C0000–5C7FFF SA252 0 1 1 1 1 1 1 0 0 64/32 0FC0000–0FCFFFF 7E0000–7E7FFF

SA185 0 1 0 1 1 1 0 0 1 64/32 0B90000–0B9FFFF 5C8000–5CFFFF SA253 0 1 1 1 1 1 1 0 1 64/32 0FD0000–0FDFFFF 7E8000–7EFFFF

SA186 0 1 0 1 1 1 0 1 0 64/32 0BA0000–0BAFFFF 5D0000–5D7FFF SA254 0 1 1 1 1 1 1 1 0 64/32

SA187 0 1 0 1 1 1 0 1 1 64/32 0BB0000–0BBFFFF 5D8000–5DFFFF SA255 0 1 1 1 1 1 1 1 1 64/32

0FE0000–0FEFFFF 7F0000–7F7FFF

0FF0000–0FFFFFF 7F8000–7FFFFF

SA188 0 1 0 1 1 1 1 0 0 64/32 0BC0000–0BCFFFF 5E0000–5E7FFF SA256 1 0 0 0 0 0 0 0 0 64/32 1000000–100FFFF 800000–807FFF

SA189 0 1 0 1 1 1 1 0 1 64/32 0BD0000–0BDFFFF 5E8000–5EFFFF SA257 1 0 0 0 0 0 0 0 1 64/32 1010000–101FFFF 808000–80FFFF

SA190 0 1 0 1 1 1 1 1 0 64/32 0BE0000–0BEFFFF 5F0000–5F7FFF SA258 1 0 0 0 0 0 0 1 0 64/32 1020000–102FFFF 810000–817FFF

SA191 0 1 0 1 1 1 1 1 1 64/32 0BF0000–0BFFFFF 5F8000–5FFFFF SA259 1 0 0 0 0 0 0 1 1 64/32 1030000–103FFFF 818000–81FFFF

SA192 0 1 1 0 0 0 0 0 0 64/32 0C00000–0C0FFFF 600000–607FFF SA260 1 0 0 0 0 0 1 0 0 64/32 1040000–104FFFF 820000–827FFF

SA193 0 1 1 0 0 0 0 0 1 64/32 0C10000–0C1FFFF 608000–60FFFF SA261 1 0 0 0 0 0 1 0 1 64/32 1050000–105FFFF 828000–82FFFF

SA194 0 1 1 0 0 0 0 1 0 64/32 0C20000–0C2FFFF 610000–617FFF SA262 1 0 0 0 0 0 1 1 0 64/32 1060000–106FFFF 830000–837FFF

SA195 0 1 1 0 0 0 0 1 1 64/32 0C30000–0C3FFFF 618000–61FFFF SA263 1 0 0 0 0 0 1 1 1 64/32 1070000–107FFFF 838000–83FFFF

SA196 0 1 1 0 0 0 1 0 0 64/32 0C40000–0C4FFFF 620000–627FFF SA264 1 0 0 0 0 1 0 0 0 64/32 1080000–108FFFF 840000–847FFF

SA197 0 1 1 0 0 0 1 0 1 64/32 0C50000–0C5FFFF 628000–62FFFF SA265 1 0 0 0 0 1 0 0 1 64/32 1090000–109FFFF 848000–84FFFF

SA198 0 1 1 0 0 0 1 1 0 64/32 0C60000–0C6FFFF 630000–637FFF SA266 1 0 0 0 0 1 0 1 0 64/32 10A0000–10AFFFF 850000–857FFF

SA199 0 1 1 0 0 0 1 1 1 64/32 0C70000–0C7FFFF 638000–63FFFF SA267 1 0 0 0 0 1 0 1 1 64/32 10B0000–10BFFFF 858000–85FFFF

SA200 0 1 1 0 0 1 0 0 0 64/32 0C80000–0C8FFFF 640000–647FFF SA268 1 0 0 0 0 1 1 0 0 64/32 10C0000–10CFFFF 860000–867FFF

SA201 0 1 1 0 0 1 0 0 1 64/32 0C90000–0C9FFFF 648000–64FFFF SA269 1 0 0 0 0 1 1 0 1 64/32 10D0000–10DFFFF 868000–86FFFF

SA202 0 1 1 0 0 1 0 1 0 64/32 0CA0000–0CAFFFF 650000–657FFF SA270 1 0 0 0 0 1 1 1 0 64/32 10E0000–10EFFFF 870000–877FFF

SA203 0 1 1 0 0 1 0 1 1 64/32 0CB0000–0CBFFFF 658000–65FFFF SA271 1 0 0 0 0 1 1 1 1 64/32

10F0000–10FFFFF 878000–87FFFF

40

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 17. S29GL256M Sector Address Table (Sheet 3 of 4)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A23–A15

(KB/

Kwords)

SA272 1 0 0 0 1 0 0 0 0 64/32 1100000–110FFFF 880000–887FFF SA340 1 0 1 0 1 0 1 0 0 64/32 1540000–154FFFF AA0000–AA7FFF

SA273 1 0 0 0 1 0 0 0 1 64/32 1110000–111FFFF 888000–88FFFF SA341 1 0 1 0 1 0 1 0 1 64/32 1550000–155FFFF AA8000–AAFFFF

SA274 1 0 0 0 1 0 0 1 0 64/32 1120000–112FFFF 890000–897FFF SA342 1 0 1 0 1 0 1 1 0 64/32 1560000–156FFFF AB0000–AB7FFF

SA275 1 0 0 0 1 0 0 1 1 64/32 1130000–113FFFF 898000–89FFFF SA343 1 0 1 0 1 0 1 1 1 64/32 1570000–157FFFF AB8000–ABFFFF

SA276 1 0 0 0 1 0 1 0 0 64/32 1140000–114FFFF 8A0000–8A7FFF SA344 1 0 1 0 1 1 0 0 0 64/32 1580000–158FFFF AC0000–AC7FFF

SA277 1 0 0 0 1 0 1 0 1 64/32 1150000–115FFFF 8A8000–8AFFFF SA345 1 0 1 0 1 1 0 0 1 64/32 1590000–159FFFF AC8000–ACFFFF

SA278 1 0 0 0 1 0 1 1 0 64/32 1160000–116FFFF 8B0000–8B7FFF SA346 1 0 1 0 1 1 0 1 0 64/32 15A0000–15AFFFF AD0000–AD7FFF

SA279 1 0 0 0 1 0 1 1 1 64/32 1170000–117FFFF 8B8000–8BFFFF SA347 1 0 1 0 1 1 0 1 1 64/32 15B0000–15BFFFF AD8000–ADFFFF

SA280 1 0 0 0 1 1 0 0 0 64/32 1180000–118FFFF 8C0000–8C7FFF SA348 1 0 1 0 1 1 1 0 0 64/32 15C0000–15CFFFF AE0000–AE7FFF

SA281 1 0 0 0 1 1 0 0 1 64/32 1190000–119FFFF 8C8000–8CFFFF SA349 1 0 1 0 1 1 1 0 1 64/32 15D0000–15DFFFF AE8000–AEFFFF

SA282 1 0 0 0 1 1 0 1 0 64/32 11A0000–11AFFFF 8D0000–8D7FFF SA350 1 0 1 0 1 1 1 1 0 64/32 15E0000–15EFFFF AF0000–AF7FFF

SA283 1 0 0 0 1 1 0 1 1 64/32 11B0000–11BFFFF 8D8000–8DFFFF SA351 1 0 1 0 1 1 1 1 1 64/32

15F0000–15FFFFF AF8000–AFFFFF

SA284 1 0 0 0 1 1 1 0 0 64/32 11C0000–11CFFFF 8E0000–8E7FFF SA352 1 0 1 1 0 0 0 0 0 64/32 1600000–160FFFF B00000–B07FFF

SA285 1 0 0 0 1 1 1 0 1 64/32 11D0000–11DFFFF 8E8000–8EFFFF SA353 1 0 1 1 0 0 0 0 1 64/32 1610000–161FFFF B08000–B0FFFF

SA286 1 0 0 0 1 1 1 1 0 64/32 11E0000–11EFFFF 8F0000–8F7FFF SA354 1 0 1 1 0 0 0 1 0 64/32 1620000–162FFFF B10000–B17FFF

SA287 1 0 0 0 1 1 1 1 1 64/32 11F0000–11FFFFF 8F8000–8FFFFF SA355 1 0 1 1 0 0 0 1 1 64/32 1630000–163FFFF B18000–B1FFFF

SA288 1 0 0 1 0 0 0 0 0 64/32 1200000–120FFFF 900000–907FFF SA356 1 0 1 1 0 0 1 0 0 64/32 1640000–164FFFF B20000–B27FFF

SA289 1 0 0 1 0 0 0 0 1 64/32 1210000–121FFFF 908000–90FFFF SA357 1 0 1 1 0 0 1 0 1 64/32 1650000–165FFFF B28000–B2FFFF

SA290 1 0 0 1 0 0 0 1 0 64/32 1220000–122FFFF 910000–917FFF SA358 1 0 1 1 0 0 1 1 0 64/32 1660000–166FFFF B30000–B37FFF

SA291 1 0 0 1 0 0 0 1 1 64/32 1230000–123FFFF 918000–91FFFF SA359 1 0 1 1 0 0 1 1 1 64/32 1670000–167FFFF B38000–B3FFFF

SA292 1 0 0 1 0 0 1 0 0 64/32 1240000–124FFFF 920000–927FFF SA360 1 0 1 1 0 1 0 0 0 64/32 1680000–168FFFF B40000–B47FFF

SA293 1 0 0 1 0 0 1 0 1 64/32 1250000–125FFFF 928000–92FFFF SA361 1 0 1 1 0 1 0 0 1 64/32 1690000–169FFFF B48000–B4FFFF

SA294 1 0 0 1 0 0 1 1 0 64/32 1260000–126FFFF 930000–937FFF SA362 1 0 1 1 0 1 0 1 0 64/32 16A0000–16AFFFF B50000–B57FFF

SA295 1 0 0 1 0 0 1 1 1 64/32 1270000–127FFFF 938000–93FFFF SA363 1 0 1 1 0 1 0 1 1 64/32 16B0000–16BFFFF B58000–B5FFFF

SA296 1 0 0 1 0 1 0 0 0 64/32 1280000–128FFFF 940000–947FFF SA364 1 0 1 1 0 1 1 0 0 64/32 16C0000–16CFFFF B60000–B67FFF

SA297 1 0 0 1 0 1 0 0 1 64/32 1290000–129FFFF 948000–94FFFF SA365 1 0 1 1 0 1 1 0 1 64/32 16D0000–16DFFFF B68000–B6FFFF

SA298 1 0 0 1 0 1 0 1 0 64/32 12A0000–12AFFFF 950000–957FFF SA366 1 0 1 1 0 1 1 1 0 64/32 16E0000–16EFFFF B70000–B77FFF

SA299 1 0 0 1 0 1 0 1 1 64/32 12B0000–12BFFFF 958000–95FFFF SA367 1 0 1 1 0 1 1 1 1 64/32

16F0000–16FFFFF B78000–B7FFFF

SA300 1 0 0 1 0 1 1 0 0 64/32 12C0000–12CFFFF 960000–967FFF SA368 1 0 1 1 1 0 0 0 0 64/32 1700000–170FFFF B80000–B87FFF

SA301 1 0 0 1 0 1 1 0 1 64/32 12D0000–12DFFFF 968000–96FFFF SA369 1 0 1 1 1 0 0 0 1 64/32 1710000–171FFFF B88000–B8FFFF

SA302 1 0 0 1 0 1 1 1 0 64/32 12E0000–12EFFFF 970000–977FFF SA370 1 0 1 1 1 0 0 1 0 64/32 1720000–172FFFF B90000–B97FFF

SA303 1 0 0 1 0 1 1 1 1 64/32 12F0000–12FFFFF 978000–97FFFF SA371 1 0 1 1 1 0 0 1 1 64/32 1730000–173FFFF B98000–B9FFFF

SA304 1 0 0 1 1 0 0 0 0 64/32 1300000–130FFFF 980000–987FFF SA372 1 0 1 1 1 0 1 0 0 64/32 1740000–174FFFF BA0000–BA7FFF

SA305 1 0 0 1 1 0 0 0 1 64/32 1310000–131FFFF 988000–98FFFF SA373 1 0 1 1 1 0 1 0 1 64/32 1750000–175FFFF BA8000–BAFFFF

SA306 1 0 0 1 1 0 0 1 0 64/32 1320000–132FFFF 990000–997FFF SA374 1 0 1 1 1 0 1 1 0 64/32 1760000–176FFFF BB0000–BB7FFF

SA307 1 0 0 1 1 0 0 1 1 64/32 1330000–133FFFF 998000–99FFFF SA375 1 0 1 1 1 0 1 1 1 64/32 1770000–177FFFF BB8000–BBFFFF

SA308 1 0 0 1 1 0 1 0 0 64/32 1340000–134FFFF 9A0000–9A7FFF SA376 1 0 1 1 1 1 0 0 0 64/32 1780000–178FFFF BC0000–BC7FFF

SA309 1 0 0 1 1 0 1 0 1 64/32 1350000–135FFFF 9A8000–9AFFFF SA377 1 0 1 1 1 1 0 0 1 64/32 1790000–179FFFF BC8000–BCFFFF

SA310 1 0 0 1 1 0 1 1 0 64/32 1360000–136FFFF 9B0000–9B7FFF SA378 1 0 1 1 1 1 0 1 0 64/32 17A0000–17AFFFF BD0000–BD7FFF

SA311 1 0 0 1 1 0 1 1 1 64/32 1370000–137FFFF 9B8000–9BFFFF SA379 1 0 1 1 1 1 0 1 1 64/32 17B0000–17BFFFF BD8000–BDFFFF

SA312 1 0 0 1 1 1 0 0 0 64/32 1380000–138FFFF 9C0000–9C7FFF SA380 1 0 1 1 1 1 1 0 0 64/32 17C0000–17CFFFF BE0000–BE7FFF

SA313 1 0 0 1 1 1 0 0 1 64/32 1390000–139FFFF 9C8000–9CFFFF SA381 1 0 1 1 1 1 1 0 1 64/32 17D0000–17DFFFF BE8000–BEFFFF

SA314 1 0 0 1 1 1 0 1 0 64/32 13A0000–13AFFFF 9D0000–9D7FFF SA382 1 0 1 1 1 1 1 1 0 64/32 17E0000–17EFFFF BF0000–BF7FFF

SA315 1 0 0 1 1 1 0 1 1 64/32 13B0000–13BFFFF 9D8000–9DFFFF SA383 1 0 1 1 1 1 1 1 1 64/32

17F0000–17FFFFF BF8000–BFFFFF

SA316 1 0 0 1 1 1 1 0 0 64/32 13C0000–13CFFFF 9E0000–9E7FFF SA384 1 1 0 0 0 0 0 0 0 64/32 1800000–180FFFF C00000–C07FFF

SA317 1 0 0 1 1 1 1 0 1 64/32 13D0000–13DFFFF 9E8000–9EFFFF SA385 1 1 0 0 0 0 0 0 1 64/32 1810000–181FFFF C08000–C0FFFF

SA318 1 0 0 1 1 1 1 1 0 64/32 13E0000–13EFFFF 9F0000–9F7FFF SA386 1 1 0 0 0 0 0 1 0 64/32 1820000–182FFFF C10000–C17FFF

SA319 1 0 0 1 1 1 1 1 1 64/32 13F0000–13FFFFF 9F8000–9FFFFF SA387 1 1 0 0 0 0 0 1 1 64/32 1830000–183FFFF C18000–C1FFFF

SA320 1 0 1 0 0 0 0 0 0 64/32 1400000–140FFFF A00000–A07FFF SA388 1 1 0 0 0 0 1 0 0 64/32 1840000–184FFFF C20000–C27FFF

SA321 1 0 1 0 0 0 0 0 1 64/32 1410000–141FFFF A08000–A0FFFF SA389 1 1 0 0 0 0 1 0 1 64/32 1850000–185FFFF C28000–C2FFFF

SA322 1 0 1 0 0 0 0 1 0 64/32 1420000–142FFFF A10000–A17FFF SA390 1 1 0 0 0 0 1 1 0 64/32 1860000–186FFFF C30000–C37FFF

SA323 1 0 1 0 0 0 0 1 1 64/32 1430000–143FFFF A18000–A1FFFF SA391 1 1 0 0 0 0 1 1 1 64/32 1870000–187FFFF C38000–C3FFFF

SA324 1 0 1 0 0 0 1 0 0 64/32 1440000–144FFFF A20000–A27FFF SA392 1 1 0 0 0 1 0 0 0 64/32 1880000–188FFFF C40000–C47FFF

SA325 1 0 1 0 0 0 1 0 1 64/32 1450000–145FFFF A28000–A2FFFF SA393 1 1 0 0 0 1 0 0 1 64/32 1890000–189FFFF C48000–C4FFFF

SA326 1 0 1 0 0 0 1 1 0 64/32 1460000–146FFFF A30000–A37FFF SA394 1 1 0 0 0 1 0 1 0 64/32 18A0000–18AFFFF C50000–C57FFF

SA327 1 0 1 0 0 0 1 1 1 64/32 1470000–147FFFF A38000–A3FFFF SA395 1 1 0 0 0 1 0 1 1 64/32 18B0000–18BFFFF C58000–C5FFFF

SA328 1 0 1 0 0 1 0 0 0 64/32 1480000–148FFFF A40000–A47FFF SA396 1 1 0 0 0 1 1 0 0 64/32 18C0000–18CFFFF C60000–C67FFF

SA329 1 0 1 0 0 1 0 0 1 64/32 1490000–149FFFF A48000–A4FFFF SA397 1 1 0 0 0 1 1 0 1 64/32 18D0000–18DFFFF C68000–C6FFFF

SA330 1 0 1 0 0 1 0 1 0 64/32 14A0000–14AFFFF A50000–A57FFF SA398 1 1 0 0 0 1 1 1 0 64/32 18E0000–18EFFFF C70000–C77FFF

SA331 1 0 1 0 0 1 0 1 1 64/32 14B0000–14BFFFF A58000–A5FFFF SA399 1 1 0 0 0 1 1 1 1 64/32

18F0000–18FFFFF C78000–C7FFFF

SA332 1 0 1 0 0 1 1 0 0 64/32 14C0000–14CFFFF A60000–A67FFF SA400 1 1 0 0 1 0 0 0 0 64/32 1900000–190FFFF C80000–C87FFF

SA333 1 0 1 0 0 1 1 0 1 64/32 14D0000–14DFFFF A68000–A6FFFF SA401 1 1 0 0 1 0 0 0 1 64/32 1910000–191FFFF C88000–C8FFFF

SA334 1 0 1 0 0 1 1 1 0 64/32 14E0000–14EFFFF A70000–A77FFF SA402 1 1 0 0 1 0 0 1 0 64/32 1920000–192FFFF C90000–C97FFF

SA335 1 0 1 0 0 1 1 1 1 64/32 14F0000–14FFFFF A78000–A7FFFF SA403 1 1 0 0 1 0 0 1 1 64/32 1930000–193FFFF C98000–C9FFFF

SA336 1 0 1 0 1 0 0 0 0 64/32 1500000–150FFFF A80000–A87FFF SA404 1 1 0 0 1 0 1 0 0 64/32 1940000–194FFFF CA0000–CA7FFF

SA337 1 0 1 0 1 0 0 0 1 64/32 1510000–151FFFF A88000–A8FFFF SA405 1 1 0 0 1 0 1 0 1 64/32 1950000–195FFFF CA8000–CAFFFF

SA338 1 0 1 0 1 0 0 1 0 64/32 1520000–152FFFF A90000–A97FFF SA406 1 1 0 0 1 0 1 1 0 64/32 1960000–196FFFF CB0000–CB7FFF

SA339 1 0 1 0 1 0 0 1 1 64/32 1530000–153FFFF A98000–A9FFFF SA407 1 1 0 0 1 0 1 1 1 64/32 1970000–197FFFF CB8000–CBFFFF

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

41

D a t a S h e e t

Table 17. S29GL256M Sector Address Table (Sheet 4 of 4)

Sector

Size

Sector

Size

(KB/

8-bit

Address

Range

16-bit

Address

Range

8-bit

Address

Range

16-bit

Address

Range

A23–A15

(KB/

Kwords)

SA408 1 1 0 0 1 1 0 0 0 64/32 1980000–198FFFF CC0000–CC7FFF SA460 1 1 1 0 0 1 1 0 0 64/32 1CC0000–1CCFFFF E60000–E67FFF

SA409 1 1 0 0 1 1 0 0 1 64/32 1990000–199FFFF CC8000–CCFFFF SA461 1 1 1 0 0 1 1 0 1 64/32 1CD0000–1CDFFFF E68000–E6FFFF

SA410 1 1 0 0 1 1 0 1 0 64/32 19A0000–19AFFFF CD0000–CD7FFF SA462 1 1 1 0 0 1 1 1 0 64/32 1CE0000–1CEFFFF E70000–E77FFF

SA411 1 1 0 0 1 1 0 1 1 64/32 19B0000–19BFFFF CD8000–CDFFFF SA463 1 1 1 0 0 1 1 1 1 64/32 1CF0000–1CFFFFF E78000–E7FFFF

SA412 1 1 0 0 1 1 1 0 0 64/32 19C0000–19CFFFF CE0000–CE7FFF SA464 1 1 1 0 1 0 0 0 0 64/32 1D00000–1D0FFFF E80000–E87FFF

SA413 1 1 0 0 1 1 1 0 1 64/32 19D0000–19DFFFF CE8000–CEFFFF SA465 1 1 1 0 1 0 0 0 1 64/32 1D10000–1D1FFFF E88000–E8FFFF

SA414 1 1 0 0 1 1 1 1 0 64/32 19E0000–19EFFFF CF0000–CF7FFF SA466 1 1 1 0 1 0 0 1 0 64/32 1D20000–1D2FFFF E90000–E97FFF

SA415 1 1 0 0 1 1 1 1 1 64/32 19F0000–19FFFFF CF8000–CFFFFF SA467 1 1 1 0 1 0 0 1 1 64/32 1D30000–1D3FFFF E98000–E9FFFF

SA416 1 1 0 1 0 0 0 0 0 64/32 1A00000–1A0FFFF D00000–D07FFF SA468 1 1 1 0 1 0 1 0 0 64/32 1D40000–1D4FFFF EA0000–EA7FFF

SA417 1 1 0 1 0 0 0 0 1 64/32 1A10000–1A1FFFF D08000–D0FFFF SA469 1 1 1 0 1 0 1 0 1 64/32 1D50000–1D5FFFF EA8000–EAFFFF

SA418 1 1 0 1 0 0 0 1 0 64/32 1A20000–1A2FFFF D10000–D17FFF SA470 1 1 1 0 1 0 1 1 0 64/32 1D60000–1D6FFFF EB0000–EB7FFF

SA419 1 1 0 1 0 0 0 1 1 64/32 1A30000–1A3FFFF D18000–D1FFFF SA471 1 1 1 0 1 0 1 1 1 64/32 1D70000–1D7FFFF EB8000–EBFFFF

SA420 1 1 0 1 0 0 1 0 0 64/32 1A40000–1A4FFFF D20000–D27FFF SA472 1 1 1 0 1 1 0 0 0 64/32 1D80000–1D8FFFF EC0000–EC7FFF

SA421 1 1 0 1 0 0 1 0 1 64/32 1A50000–1A5FFFF D28000–D2FFFF SA473 1 1 1 0 1 1 0 0 1 64/32 1D90000–1D9FFFF EC8000–ECFFFF

SA422 1 1 0 1 0 0 1 1 0 64/32 1A60000–1A6FFFF D30000–D37FFF SA474 1 1 1 0 1 1 0 1 0 64/32 1DA0000–1DAFFFF ED0000–ED7FFF

SA423 1 1 0 1 0 0 1 1 1 64/32 1A70000–1A7FFFF D38000–D3FFFF SA475 1 1 1 0 1 1 0 1 1 64/32 1DB0000–1DBFFFF ED8000–EDFFFF

SA424 1 1 0 1 0 1 0 0 0 64/32 1A80000–1A8FFFF D40000–D47FFF SA476 1 1 1 0 1 1 1 0 0 64/32 1DC0000–1DCFFFF EE0000–EE7FFF

SA425 1 1 0 1 0 1 0 0 1 64/32 1A90000–1A9FFFF D48000–D4FFFF SA477 1 1 1 0 1 1 1 0 1 64/32 1DD0000–1DDFFFF EE8000–EEFFFF

SA426 1 1 0 1 0 1 0 1 0 64/32 1AA0000–1AAFFFF D50000–D57FFF SA478 1 1 1 0 1 1 1 1 0 64/32 1DE0000–1DEFFFF EF0000–EF7FFF

SA427 1 1 0 1 0 1 0 1 1 64/32 1AB0000–1ABFFFF D58000–D5FFFF SA479 1 1 1 0 1 1 1 1 1 64/32 1DF0000–1DFFFFF EF8000–EFFFFF

SA428 1 1 0 1 0 1 1 0 0 64/32 1AC0000–1ACFFFF D60000–D67FFF SA480 1 1 1 1 0 0 0 0 0 64/32 1E00000–1E0FFFF F00000–F07FFF

SA429 1 1 0 1 0 1 1 0 1 64/32 1AD0000–1ADFFFF D68000–D6FFFF SA481 1 1 1 1 0 0 0 0 1 64/32 1E10000–1E1FFFF F08000–F0FFFF

SA430 1 1 0 1 0 1 1 1 0 64/32 1AE0000–1AEFFFF D70000–D77FFF SA482 1 1 1 1 0 0 0 1 0 64/32 1E20000–1E2FFFF F10000–F17FFF

SA431 1 1 0 1 0 1 1 1 1 64/32 1AF0000–1AFFFFF D78000–D7FFFF SA483 1 1 1 1 0 0 0 1 1 64/32 1E30000–1E3FFFF F18000–F1FFFF

SA432 1 1 0 1 1 0 0 0 0 64/32 1B00000–1B0FFFF D80000–D87FFF SA484 1 1 1 1 0 0 1 0 0 64/32 1E40000–1E4FFFF F20000–F27FFF

SA433 1 1 0 1 1 0 0 0 1 64/32 1B10000–1B1FFFF D88000–D8FFFF SA485 1 1 1 1 0 0 1 0 1 64/32 1E50000–1E5FFFF F28000–F2FFFF

SA434 1 1 0 1 1 0 0 1 0 64/32 1B20000–1B2FFFF D90000–D97FFF SA486 1 1 1 1 0 0 1 1 0 64/32 1E60000–1E6FFFF F30000–F37FFF

SA435 1 1 0 1 1 0 0 1 1 64/32 1B30000–1B3FFFF D98000–D9FFFF SA487 1 1 1 1 0 0 1 1 1 64/32 1E70000–1E7FFFF F38000–F3FFFF

SA436 1 1 0 1 1 0 1 0 0 64/32 1B40000–1B4FFFF DA0000–DA7FFF SA488 1 1 1 1 0 1 0 0 0 64/32 1E80000–1E8FFFF F40000–F47FFF

SA437 1 1 0 1 1 0 1 0 1 64/32 1B50000–1B5FFFF DA8000–DAFFFF SA489 1 1 1 1 0 1 0 0 1 64/32 1E90000–1E9FFFF F48000–F4FFFF

SA438 1 1 0 1 1 0 1 1 0 64/32 1B60000–1B6FFFF DB0000–DB7FFF SA490 1 1 1 1 0 1 0 1 0 64/32 1EA0000–1EAFFFF F50000–F57FFF

SA439 1 1 0 1 1 0 1 1 1 64/32 1B70000–1B7FFFF DB8000–DBFFFF SA491 1 1 1 1 0 1 0 1 1 64/32 1EB0000–1EBFFFF F58000–F5FFFF

SA440 1 1 0 1 1 1 0 0 0 64/32 1B80000–1B8FFFF DC0000–DC7FFF SA492 1 1 1 1 0 1 1 0 0 64/32 1EC0000–1ECFFFF F60000–F67FFF

SA441 1 1 0 1 1 1 0 0 1 64/32 1B90000–1B9FFFF DC8000–DCFFFF SA493 1 1 1 1 0 1 1 0 1 64/32 1ED0000–1EDFFFF F68000–F6FFFF

SA442 1 1 0 1 1 1 0 1 0 64/32 1BA0000–1BAFFFF DD0000–DD7FFF SA494 1 1 1 1 0 1 1 1 0 64/32 1EE0000–1EEFFFF F70000–F77FFF

SA443 1 1 0 1 1 1 0 1 1 64/32 1BB0000–1BBFFFF DD8000–DDFFFF SA495 1 1 1 1 0 1 1 1 1 64/32

SA444 1 1 0 1 1 1 1 0 0 64/32 1BC0000–1BCFFFF DE0000–DE7FFF SA496 1 1 1 1 1 0 0 0 0 64/32

SA445 1 1 0 1 1 1 1 0 1 64/32 1BD0000–1BDFFFF DE8000–DEFFFF SA497 1 1 1 1 1 0 0 0 1 64/32

SA446 1 1 0 1 1 1 1 1 0 64/32 1BE0000–1BEFFFF DF0000–DF7FFF SA498 1 1 1 1 1 0 0 1 0 64/32

SA447 1 1 0 1 1 1 1 1 1 64/32 1BF0000–1BFFFFF DF8000–DFFFFF SA499 1 1 1 1 1 0 0 1 1 64/32

SA448 1 1 1 0 0 0 0 0 0 64/32 1C00000–1C0FFFF E00000–E07FFF SA500 1 1 1 1 1 0 1 0 0 64/32

SA449 1 1 1 0 0 0 0 0 1 64/32 1C10000–1C1FFFF E08000–E0FFFF SA501 1 1 1 1 1 0 1 0 1 64/32

SA450 1 1 1 0 0 0 0 1 0 64/32 1C20000–1C2FFFF E10000–E17FFF SA502 1 1 1 1 1 0 1 1 0 64/32

SA451 1 1 1 0 0 0 0 1 1 64/32 1C30000–1C3FFFF E18000–E1FFFF SA503 1 1 1 1 1 0 1 1 1 64/32

SA452 1 1 1 0 0 0 1 0 0 64/32 1C40000–1C4FFFF E20000–E27FFF SA504 1 1 1 1 1 1 0 0 0 64/32

SA453 1 1 1 0 0 0 1 0 1 64/32 1C50000–1C5FFFF E28000–E2FFFF SA505 1 1 1 1 1 1 0 0 1 64/32

SA454 1 1 1 0 0 0 1 1 0 64/32 1C60000–1C6FFFF E30000–E37FFF SA506 1 1 1 1 1 1 0 1 0 64/32

1EF0000–1EFFFFF F78000–F7FFFF

1F00000–1F0FFFF F80000–F87FFF

1F10000–1F1FFFF F88000–F8FFFF

1F20000–1F2FFFF F90000–F97FFF

1F30000–1F3FFFF F98000–F9FFFF

1F40000–1F4FFFF FA0000–FA7FFF

1F50000–1F5FFFF FA8000–FAFFFF

1F60000–1F6FFFF FB0000–FB7FFF

1F70000–1F7FFFF FB8000–FBFFFF

1F80000–1F8FFFF FC0000–FC7FFF

1F90000–1F9FFFF FC8000–FCFFFF

1FA0000–1FAFFFF FD0000–FD7FFF

SA455 1 1 1 0 0 0 1 1 1 64/32 1C70000–1C7FFFF E38000–E3FFFF SA507 1 1 1 1 1 1 0 1 1 64/32 1FB0000–1FBFFFF FD8000–FDFFFF

SA456 1 1 1 0 0 1 0 0 0 64/32 1C80000–1C8FFFF E40000–E47FFF SA508 1 1 1 1 1 1 1 0 0 64/32 1FC0000–1FCFFFF FE0000–FE7FFF

SA457 1 1 1 0 0 1 0 0 1 64/32 1C90000–1C9FFFF E48000–E4FFFF SA509 1 1 1 1 1 1 1 0 1 64/32 1FD0000–1FDFFFF FE8000–FEFFFF

SA458 1 1 1 0 0 1 0 1 0 64/32 1CA0000–1CAFFFF E50000–E57FFF SA510 1 1 1 1 1 1 1 1 0 64/32

SA459 1 1 1 0 0 1 0 1 1 64/32 1CB0000–1CBFFFF E58000–E5FFFF SA511 1 1 1 1 1 1 1 1 1 64/32

1FE0000–1FEFFFF FF0000–FF7FFF

1FF0000–1FFFFFF FF8000–FFFFFF

42

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector group protection

verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for pro-

gramming equipment to automatically match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can also be accessed in-system through

the command register.

When using programming equipment, the autoselect mode requires V on address pin A9. Ad-

ID

dress pins A6, A3, A2, A1, and A0 must be as shown in Table 18. In addition, when verifying sector

protection, the sector address must appear on the appropriate highest order address bits (see

Table 6 through Table 17). Table 18 shows the remaining address bits that are don’t care. When

all necessary bits are set as required, the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via

the command register, as shown in Table 35 and Table 36. This method does not require V . See

ID

Autoselect Command Sequence for more information.

Table 18. Autoselect Codes, (High Voltage Method)

DQ7 to DQ0

Model Number

DQ8 to DQ15

A14

A8

A5 A3

A22 to

A15

Description

CE# OE# WE#

to A9 to A6 to to A1 A0

BYTE#

= V_IL

R1, R2,

R8, R9

R5, R6,

R7

A10

A7

A4 A2

R0

R3,R4

= V_IH

Manufacturer ID:

L

H

X

V_ID

X

L

X

L

00

X

01h

Spansion Products

Cycle 1

Cycle 2

L

H

L

H

L

22

X

7Eh

12h

X

V_ID

X

Cycle 3

H

22

X

01h

Cycle 1

Cycle 2

L

H

L

H

L

22

X

7Eh

12h

L

H

X

V_ID

L

X

Cycle 3

H

22

X

00h

Cycle 1

Cycle 2

L

H

L

H

L

22

X

7Eh

13h 0Ch

7Eh

10h

00h (-R4,

bottom boot)

01h (-R3,

top boot)

7Eh

1Ah

00h (-R4,

bottom boot) bottom boot)

01h (-R3,

top boot)

7Eh

13h

X

V_ID

X

Cycle 3

H

22

X

00h

7Eh

01h

7Eh

01h

Cycle 1

Cycle 2

L

H

L

H

L

22

X

7Eh

1Ah

00h (-R6

1Ch 1Dh

L

H

X

V_ID

L

X

Cycle 3

H

L

H

L

22

X

00h 00h

01h

(-R5, top boot)

Sector Group

Protection

Verification

Secured Silicon

Sector Indicator Bit

(DQ7), WP#

protects highest

address sector

Secured Silicon

Sector Indicator Bit

(DQ7), WP#

protects lowest

address sector

01h (protected),

00h (unprotected)

L

H

SA

X

V_ID

X

L

X

98h (factory locked),

V_ID

L

H

X

18h (not factory locked)

88h (factory locked),

L

H

X

V_ID

X

L

X

08h (not factory locked)

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

43

D a t a S h e e t

Sector Group Protection and Unprotection

The hardware sector group protection feature disables both program and erase operations in any

sector group. In this device, a sector group consists of four adjacent sectors that are protected

or unprotected at the same time (see Table 4). The hardware sector group unprotection feature

re-enables both program and erase operations in previously protected sector groups. Sector

group protection/unprotection can be implemented via two methods.

Sector protection/unprotection requires V on the RESET# pin only, and can be implemented ei-

ID

ther in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24

shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector

group unprotect, all unprotected sector groups must first be protected prior to the first sector

group unprotect write cycle.

The device is shipped with all sector groups unprotected. Spansion offers the option of program-

ming and protecting sector groups at its factory prior to shipping the device through Spansion

Programming Service. Contact a Spansion representative for details.

It is possible to determine whether a sector group is protected or unprotected. See Autoselect

Mode for details.

Table 19. S29GL032M (Model R0) Sector Group Protection/Unprotection Addresses

Sector Group

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

A22–A18

00000

00001

00010

00011

Sector Group

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

A22–A18

00100

00101

00110

00111

Sector Group

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

A22–A18

01000

01001

01010

01011

Sector Group

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

A22–A18

01100

01101

01110

01111

Note: All sector groups are 256 Kwords in size.

Table 20. S29GL032M (Models R1, R2) Sector Group Protection/Unprotection Addresses

Sector Group

SA0

A20–A15

000000

000001

000010

000011

0001xx

0010xx

Sector Group

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

A20–A15

0011xx

0100xx

0101xx

0110xx

0111xx

1000xx

Sector Group

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

A20–A15

1001xx

1010xx

1011xx

1100xx

1101xx

Sector Group

SA56–SA59

SA60

A20–A15

1110xx

111100

111101

111110

111111

SA1

SA2

SA3

SA61

SA62

SA63

SA4–SA7

SA8–SA11

Table 21. S29GL032M (Models R3, R5) Sector Group Protection/Unprotection Address Table

Sector/Sector

Block Size

(Kbytes)

Sector/Sector

Block Size

(Kbytes)

Sector/Sector

Block Size

(Kbytes)

Sector

A20–A12

Sector

A20–A12

Sector

A20–A12

SA0-SA3

SA4-SA7

SA8-SA11

SA12-SA15 0011XXXXXh

SA16-SA19 0100XXXXXh

SA20-SA23 0101XXXXXh

SA24-SA27 0110XXXXXh

SA28-SA31 0111XXXXXh

SA32–SA35 1000XXXXXh

0000XXXXXh

0001XXXXXh

0010XXXXXh

256 (4x64)

SA36–SA39 1001XXXXXh

SA40–SA43 1010XXXXXh

SA44–SA47 1011XXXXXh

SA48–SA51 1100XXXXXh

SA52-SA55 1101XXXXXh

SA56-SA59 1110XXXXXh

111100XXXh

256 (4x64)

SA63 111111000h

SA64 111111001h

SA65 111111010h

SA66 111111011h

SA67 111111100h

SA68 111111101h

SA69 111111110h

SA70 111111111h

8

SA60-SA62 111101XXXh

111110XXXh

192 (3x64)

44

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 22. S29GL032M (Models R4, R6) Sector Group Protection/Unprotection Address Table

Sector/Sector

Block Size

(Kbytes)

Sector/Sector

Block Size

(Kbytes)

Sector

A20–A12

Sector

A20–A12

Sector

A20–A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

000000000h

000000001h

000000010h

000000011h

000000100h

000000101h

000000110h

000000111h

8

000001XXXh

000010XXXh

000011XXXh

SA35-SA38 0111XXXXXh

SA39-SA42 1000XXXXXh

SA43-SA46 1001XXXXXh

SA47-SA50 1010XXXXXh

SA51-SA54 1011XXXXXh

SA55–SA58 1100XXXXXh

SA59–SA62 1101XXXXXh

SA63–SA66 1110XXXXXh

SA67–SA70 1111XXXXXh

256 (4x64)

SA8–SA10

192 (3x64)

SA11–SA14 0001XXXXXh

SA15–SA18 0010XXXXXh

SA19–SA22 0011XXXXXh

SA23–SA26 0100XXXXXh

SA27-SA30 0101XXXXXh

SA31-SA34 0110XXXXXh

256 (4x64)

l

Table 23. S29GL064M (Model 00) Sector Group Protection/Unprotection Address Table

Sector Group

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA32–SA35

A22–A18

00000

00001

00010

00011

00100

00101

00110

01000

Sector Group

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

A22–A18

01001

01010

01011

01100

01101

01110

01111

10000

Sector Group

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA88–SA91

SA92–SA95

SA96–SA99

A22–A18

10001

10010

10011

10100

10110

10111

11000

Sector Group

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

A22–A18

11001

11010

11011

11100

11101

11110

11111

Note: All sector groups are 256 Kwords in size.

Table 24. S29GL064M (Models R1, R2, R8, R9) Sector Group Protection/Unprotection Addresses

Sector Group

SA0

A21–A15

0000000

0000001

0000010

0000011

00001xx

00010xx

00011xx

00100xx

00101xx

00110xx

Sector Group

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA28–SA31

A21–A15

00111xx

01000xx

01001xx

01010xx

01011xx

01100xx

01101xx

01110xx

01111xx

00111xx

Sector Group

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

A21–A15

10000xx

10001xx

10010xx

10011xx

10100xx

10101xx

10110xx

10111xx

11000xx

11001xx

Sector Group

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124

A21–A15

11010xx

11011xx

11100xx

11101xx

11110xx

1111100

1111101

1111110

1111111

SA1

SA2

SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA125

SA126

SA127

Table 25. S29GL064M (Model R3) Sector Group Protection/Unprotection Address Table

Sector/ Sector

Block Size

Sector/ Sector

Block Size

Sector/ Sector

Block Size

Sector

A21–A12

Sector

A21–A12

Sector

A21–A12

(Kbytes)

SA0-SA3

SA4-SA7

00000XXXXX

00001XXXXX

256 (4x64)

SA56-SA59 01110XXXXX

SA60-SA63 01111XXXXX

SA64-SA67 10000XXXXX

SA68-SA71 10001XXXXX

SA72-SA75 10010XXXXX

SA76-SA79 10011XXXXX

SA80-SA83 10100XXXXX

SA84-SA87 10101XXXXX

SA88-SA91 10110XXXXX

SA92-SA95 10111XXXXX

SA96-SA99 11000XXXXX

SA100-SA103 11001XXXXX

SA104-SA107 11010XXXXX

SA108-SA111 11011XXXXX

256 (4x64)

SA112-SA115 11100XXXXX

SA116-SA119 11101XXXXX

SA120-SA123 11110XXXXX

1111100XXX

SA124-SA126 1111101XXX

1111110XXX

256 (4x64)

SA8-SA11 00010XXXXX

SA12-SA15 00011XXXXX

SA16-SA19 00100XXXXX

SA20-SA23 00101XXXXX

SA24-SA27 00110XXXXX

SA28-SA31 00111XXXXX

SA32-SA35 01000XXXXX

SA36-SA39 01001XXXXX

SA40-SA43 01010XXXXX

SA44-SA47 01011XXXXX

SA48-SA51 01100XXXXX

SA52-SA55 01101XXXXX

192 (3x64)

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111110

1111111111

8

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

45

D a t a S h e e t

Table 26. S29GL064M (Model R4) Sector Group Protection/Unprotection Addresses

Sector/Sector

Block Size

(Kbytes)

Sector/Sector

Block Size

(Kbytes)

Sector/Sector

Block Size

(Kbytes)

Sector

A21–A12

Sector

A21–A12

Sector

A21–A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001XXX

8

SA23–SA26 00100XXXXX

SA27-SA30 00101XXXXX

SA31-SA34 00110XXXXX

SA35-SA38 00111XXXXX

SA39-SA42 01000XXXXX

SA43-SA46 01001XXXXX

SA47-SA50 01010XXXXX

SA51-SA54 01011XXXXX

SA55–SA58 01100XXXXX

SA59–SA62 01101XXXXX

SA63–SA66 01110XXXXX

SA67–SA70 01111XXXXX

SA71–SA74 10000XXXXX

SA75–SA78 10001XXXXX

256 (4x64)

SA79–SA82 10010XXXXX

SA83–SA86 10011XXXXX

SA87–SA90 10100XXXXX

SA91–SA94 10101XXXXX

SA95–SA98 10110XXXXX

SA99–SA102 10111XXXXX

SA103–SA106 11000XXXXX

SA107–SA110 11001XXXXX

SA111–SA114 11010XXXXX

SA115–SA118 11011XXXXX

SA119–SA122 11100XXXXX

SA123–SA126 11101XXXXX

SA127–SA130 11110XXXXX

SA131–SA134 11111XXXXX

256 (4x64)

SA8–SA10 0000010XXX

0000011XXX

SA11–SA14 00001XXXXX

SA15–SA18 00010XXXXX

SA19–SA22 00011XXXXX

192 (3x64)

256 (4x64)

Table 27. S29GL064M (Model R5) Sector Group Protection/Unprotection Addresses

Sector Group

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

A21–A17

00000

00001

00010

00011

00100

00101

00110

Sector Group

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

A21–A17

00111

01000

01001

01010

01011

01100

01101

Sector Group

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

A21–A17

01110

01111

10000

10001

10010

10011

Sector Group

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

A21–A17

10100

10101

10110

10111

11000

11001

Sector Group

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

A21–A17

11010

11011

11100

11101

11110

11111

Note: All sector groups are 128 Kwords in size.

Table 28. S29GL064M (Models R6, R7) Sector Group Protection/Unprotection Address

Sector Group

SA0–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

A21–A17

00000

00001

00010

00011

00100

00101

00110

Sector Group

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

A21–A17

00111

01000

01001

01010

01011

01100

01101

Sector Group

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

A21–A17

01110

01111

10000

10001

10010

10011

Sector Group

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

A21–A17

10100

10101

10110

10111

11000

11001

Sector Group

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

A21–A17

11010

11011

11100

11101

11110

11111

Note: All sector groups are 128 Kwords in size.

Table 29. S29GL128M Sector Group Protection/Unprotection Addresses

Sector Group

SA0

A22–A15

00000000

00000001

00000010

00000011

000001xx

000010xx

000011xx

000100xx

000101xx

000110xx

000111xx

001000xx

001001xx

001010xx

Sector Group

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

A22–A15

Sector Group

A22–A15

Sector Group

A22–A15

Sector Group

A22–A15

001011xx SA100–SA103 011001xx SA156–SA159 100111xx SA212–SA215 110101xx

001100xx SA104–SA107 011010xx SA160–SA163 101000xx SA216–SA219 110110xx

001101xx SA108–SA111 011011xx SA164–SA167 101001xx SA220–SA223 110111xx

001110xx SA112–SA115 011100xx SA168–SA171 101010xx SA224–SA227 111000xx

001111xx SA116–SA119 011101xx SA172–SA175 101011xx SA228–SA231 111001xx

010000xx SA120–SA123 011110xx SA176–SA179 101100xx SA232–SA235 111010xx

010001xx SA124–SA127 011111xx SA180–SA183 101101xx SA236–SA239 111011xx

010010xx SA128–SA131 100000xx SA184–SA187 101110xx SA240–SA243 111100xx

010011xx SA132–SA135 100001xx SA188–SA191 101111xx SA244–SA247 111101xx

010100xx SA136–SA139 100010xx SA192–SA195 110000xx SA248–SA251 111110xx

SA1

SA2

SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

010101xx SA140–SA143 100011xx SA196–SA199 110001xx

010110xx SA144–SA147 100100xx SA200–SA203 110010xx

010111xx SA148–SA151 100101xx SA204–SA207 110011xx

011000xx SA152–SA155 100110xx SA208–SA211 110100xx

SA252

SA253

SA254

SA255

11111100

11111101

11111110

11111111

46

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 30. S29GL256M Sector Group Protection/Unprotection Addresses

Sector Group

SA0

SA1

SA2

SA3

SA4–SA7

A23–A15

000000000

000000001

000000010

000000011

0000001xx

0000010xx

0000011xx

0000100xx

0000101xx

0000110xx

0000111xx

0001000xx

0001001xx

0001010xx

0001011xx

0001100xx

0001101xx

0001110xx

0001111xx

0010000xx

0010001xx

0010010xx

0010011xx

0010100xx

0010101xx

0010110xx

0010111xx

0011000xx

0011001xx

0011010xx

0011011xx

0011100xx

0011101xx

0011110xx

Sector Group

SA124–SA127

SA128–SA131

SA132–SA135

SA136–SA139

SA140–SA143

SA144–SA147

SA148–SA151

SA152–SA155

SA156–SA159

SA160–SA163

SA164–SA167

SA168–SA171

SA172–SA175

SA176–SA179

SA180–SA183

SA184–SA187

SA188–SA191

SA192–SA195

SA196–SA199

SA200–SA203

SA204–SA207

SA208–SA211

SA212–SA215

SA216–SA219

SA220–SA223

SA224–SA227

SA228–SA231

SA232–SA235

SA236–SA239

SA240–SA243

SA244–SA247

SA248–SA251

SA252–SA255

SA256–SA259

A23–A15

Sector Group

SA260–SA263

SA264–SA267

SA268–SA271

SA276–SA279

SA280–SA283

SA284–SA287

SA288–SA291

SA292–SA295

SA296–SA299

SA300–SA303

SA304–SA307

SA308–SA311

SA312–SA315

SA316–SA319

SA320–SA323

SA324–SA327

SA328–SA331

SA332–SA335

SA336–SA339

SA340–SA343

SA344–SA347

SA348–SA351

SA352–SA355

SA356–SA359

SA360–SA363

SA364–SA367

SA368–SA371

SA372–SA375

SA376–SA379

SA380–SA383

SA384–SA387

SA388–SA391

A23–A15

Sector Group

SA392–SA395

SA396–SA399

SA400–SA403

SA404–SA407

SA408–SA411

SA412–SA415

SA416–SA419

SA420–SA423

SA424–SA427

SA428–SA431

SA432–SA435

SA436–SA439

SA440–SA443

SA444–SA447

SA448–SA451

SA452–SA455

SA456–SA459

SA460–SA463

SA464–SA467

SA468–SA471

SA472–SA475

SA476–SA479

SA480–SA483

SA484–SA487

SA488–SA491

SA492–SA495

SA496–SA499

SA500–SA503

SA504–SA507

SA508

A23–A15

1100010xx

1100011xx

1100100xx

1100101xx

1100110xx

1100111xx

1101000xx

1101001xx

1101010xx

1101011xx

1101100xx

1101101xx

1101110xx

1101111xx

1110000xx

1110001xx

1110010xx

1110011xx

1110100xx

1110101xx

1110110xx

1110111xx

1111000xx

1111001xx

1111010xx

1111011xx

1111100xx

1111101xx

1111110xx

111111100

111111101

111111110

111111111

0011111xx

0100000xx

0100001xx

0100010xx

0100011xx

0100100xx

0100101xx

0100110xx

0100111xx

0101000xx

0101001xx

0101010xx

0101011xx

0101100xx

0101101xx

0101110xx

0101111xx

0110000xx

0110001xx

0110010xx

0110011xx

0110100xx

0110101xx

0110110xx

0110111xx

0111000xx

0111001xx

0111010xx

0111011xx

0111100xx

0111101xx

0111110xx

0111111xx

1000000xx

1000001xx

1000010xx

1000011xx

1000101xx

1000110xx

1000111xx

1001000xx

1001001xx

1001010xx

1001011xx

1001100xx

1001101xx

1001110xx

1001111xx

1010000xx

1010001xx

1010010xx

1010011xx

1010100xx

1010101xx

1010110xx

1010111xx

1011000xx

1011001xx

1011010xx

1011011xx

1011100xx

1011101xx

1011110xx

1011111xx

1100000xx

1100001xx

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

SA68–SA71

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA509

SA510

SA511

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

47

D a t a S h e e t

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previously protected sector groups to change data

in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to V . Dur-

ID

ing this mode, formerly protected sector groups can be programmed or erased by selecting the

sector group addresses. Once V is removed from the RESET# pin, all the previously protected

ID

sector groups are protected again. For this feature, Figure 1 shows the algorithm, and Figure 23

shows the timing diagrams.

START

RESET# = V

(Note 1)

ID

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Group Unprotect Completed

(Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V_IL, the highest or lowest address sector

remains protected for uniform sector devices, the top or bottom two address sectors remains

protected for boot sector devices).

2. All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group Unprotect Operation

48

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

START

PLSCNT = 1

RESET# = V_ID

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 μs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Yes

Sector Group Protect:

Write 60h to sector

group address with

A6–A0 = 0xx0010

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6–A0 = 1xx0010

Verify Sector Group

Protect: Write 40h

to sector group

address with

A6–A0 = 0xx0010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

Read from

sector group address

with A6–A0

= 0xx0010

Increment

PLSCNT

A6–A0 = 1xx0010

No

PLSCNT

= 25?

Read from

sector group

address with

Data = 01h?

Yes

A6–A0 = 1xx0010

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

49

D a t a S h e e t

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables permanent part

identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes

in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the

Secured Silicon Sector is locked when shipped from the factory. This bit is permanently set at the

factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the

security of the ESN once the product is shipped to the field.

The factory offers the device with the Secured Silicon Sector either customer lockable (standard

shipping option) or factory locked (contact a Spansion sales representative for ordering informa-

tion). The customer-lockable version is shipped with the Secured Silicon Sector unprotected,

allowing customers to program the sector after receiving the device. The customer-lockable ver-

sion also has the Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked

version is always protected when shipped from the factory, and has the Secured Silicon (Secured

Silicon) Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon Sector Indicator

Bit prevents customer-lockable devices from being used to replace devices that are factory

locked.

Note: The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.

The Secured Silicon sector address space in this device is allocated as follows:

Secured Silicon Sector Address Range

Standard

Factory

Locked

ExpressFlash

Factory

Customer

Lockable

x16

x8

Locked

ESN or

determined by

customer

Determined by

customer

000000h – 000007h

000008h – 00007Fh

000000h – 00000Fh

000010h – 0000FFh

ESN

Determined by

customer

Unavailable

The system accesses the Secured Silicon Sector through a command sequence (see Write Protect

(WP#)). After the system writes the Enter Secured Silicon Sector command sequence, it may read

the Secured Silicon Sector by using the addresses normally occupied by the first sector (SA0).

This mode of operation continues until the system issues the Exit Secured Silicon Sector com-

mand sequence, or until power is removed from the device. On power-up, or following a hardware

reset, the device reverts to sending commands to sector SA0.

Customer Lockable: Secured Silicon Sector Not Programmed or Protected At the Factory

Unless otherwise specified, the device is shipped such that the customer may program and pro-

tect the 256-byte Secured Silicon sector.

The system may program the Secured Silicon Sector using the write-buffer, accelerated and/or

unlock bypass methods, in addition to the standard programming command sequence (see Com-

mand Definitions).

Programming and protecting the Secured Silicon Sector must be used with caution since, once

protected, there is no procedure available for unprotecting the Secured Silicon Sector area and

none of the bits in the Secured Silicon Sector memory space can be modified in any way.

The Secured Silicon Sector area can be protected using one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then fol-

low the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be

at either V or V . This allows in-system protection of the Secured Silicon Sector without

IH

ID

raising any device pin to a high voltage. Note that this method is only applicable to the Se-

cured Silicon Sector.

Write the three-cycle Enter Secured Silicon Sector Region command sequence and then use

the alternate method of sector protection described in the “Sector Group Protection and Un-

protection” section.

50

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Once the Secured Silicon Sector is programmed, locked, and verified, the system must write the

Exit Secured Silicon Sector Region command sequence to return to reading and writing within the

remainder of the array.

Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device is shipped from

the factory. The Secured Silicon Sector cannot be modified in any way. An ESN Factory Locked

device has an 16-byte random ESN at addresses 000000h–000007h. Please contact your sales

representative for details on ordering ESN Factory Locked devices.

Customers may opt to have their code programmed by the factory through the Spansion pro-

gramming service (Customer Factory Locked). The devices are then shipped from the factory with

the Secured Silicon Sector permanently locked. Contact your sales representative for details on

using the Spansion programming service.

Write Protect (WP#)

The Write Protect function provides a hardware method of protecting the first or last sector group

without using V . Write Protect is one of two functions provided by the WP#/ACC input.

ID

If the system asserts V on the WP#/ACC pin, the device disables program and erase functions

IL

in the first or last sector group independently of whether those sector groups were protected or

unprotected. Note that if WP#/ACC is at V when the device is in the standby mode, the maxi-

IL

mum input load current is increased (Table 30).

Note: If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the first or last sector was previously

set to be protected or unprotected using the method described in “Sector Group Protection and Unprotection”. Note that

WP# has an internal pullup; when unconnected, WP# is at VIH.

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data

protection against inadvertent writes (Table 35 and Table 36 contain command definitions). In ad-

dition, the following hardware data protection measures prevent accidental erasure or

programming, which might otherwise be caused by spurious system level signals during V

power-up and power-down transitions, or from system noise.

CC

Low V

Write Inhibit

CC

When V is less than V

, the device does not accept any write cycles. This protects data during

LKO

CC

V

power-up and power-down. The command register and all internal program/erase circuits are

CC

disabled, and the device resets to the read mode. Subsequent writes are ignored until V

is

CC

greater than V

. The system must provide the proper signals to the control pins to prevent un-

LKO

intentional writes when V is greater than V

.

CC

LKO

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# = V . To initiate

IL

IH

a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = V and OE# = V during power up, the device does not accept commands on

IL

IH

the rising edge of WE#. The internal state machine is automatically reset to the read mode on

power-up.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

51

D a t a S h e e t

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system software inter-

rogation handshake, which allows specific vendor-specified software algorithms to be used for

entire families of devices. Software support can then be device-independent, JEDEC ID-indepen-

dent, and forward- and backward-compatible for the specified flash device families. Flash vendors

can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to

address 55h, any time the device is ready to read array data. The system can read CFI informa-

tion at the addresses given in Table 31 through Table 34. To terminate reading CFI data, the

system must write the reset command.

The system can also write the CFI query command when the device is in the autoselect mode.

The device enters the CFI query mode, and the system can read CFI data at the addresses given

in Table 31 through Table 34. The system must write the reset command to return the device to

reading array data.

For further information, please refer to the CFI Specification and CFI Publication 100. Alterna-

tively, contact your sales representative for copies of these documents.

Table 31. CFI Query Identification String

Addresses(x16)

Addresses(x8)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h Query Unique ASCII string “QRY”

0059h

13h

14h

26h

28h

0002h

Primary OEM Command Set

0000h

15h

16h

2Ah

2Ch

0040h

Address for Primary Extended Table

0000h

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

0000h

19h

1Ah

32h

34h

0000h Address for Alternate OEM Extended Table

0000h (00h = none exists)

Table 32. System Interface String

Addresses (x16)

Addresses (x8)

Data

Description

V_CCMin. (write/erase)

1Bh

36h

38h

0027h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h V_PPMin. voltage (00h = no V_PPpin present)

0000h V_PPMax. voltage (00h = no V_PPpin present)

0007h Reserved for future use

Typical timeout for Min. size buffer write 2^Nµs

20h

21h

22h

40h

42h

44h

0007h

(00h = not supported)

000Ah Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms

0000h

(00h = not supported)

23h

24h

25h

46h

48h

4Ah

0001h Reserved for future use

0005h Max. timeout for buffer write 2^Ntimes typical

0004h Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical

26h

4Ch

0000h

(00h = not supported)

Note: CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the

Ordering Information tables to obtain the VCC range for particular part numbers. See the Erase and Programming

Performance table for typical timeout specifications.

52

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Table 33. Device Geometry Definition

Addresses

(x16)

Addresses

Data

Description

(x8)

0019h

0018h

0017h

0016h

Device Size = 2^Nbyte

19 = 256 Mb, 18 = 128 Mb, 17 = 64 Mb, 16 = 32 Mb

27h

4Eh

Flash Device Interface description (refer to CFI publication 100)

0000h = x8-only bus devices

0001h = x16-only bus devices

28h

29h

50h

52h

000xh

0000h

0002h = x8/x16 bus devices

2Ah

2Bh

54h

56h

0005h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

0001h

0002h

Number of Erase Block Regions within device

(01h = uniform device, 02h = boot device)

2Ch

58h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

003Fh, 0000h, 0000h, 0001h = 32 Mb (-R0, -R1, -R2, R5, R6)

007Fh, 0000h, 0020h, 0000h = 32 Mb (-R3, -R4), 64 Mb (-R3, -R4)

007Fh, 0000h, 0000h, 0001h = 64 Mb (-R0, -R1, -R2, -R5, -R6, -R7)

00FFh, 0000h, 0000h, 0001h = 128 Mb

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

00xxh

000xh

00x0h

000xh

00FFh, 0001h, 0000h, 0001h = 256 Mb

31h

32h

33h

34h

60h

64h

66h

68h

00xxh

0000h

000xh

Erase Block Region 2 Information (refer to CFI publication 100)

003Eh, 0000h, 0000h, 0001h = 32 Mb (-R1, -R2)

007Eh, 0000h, 0000h, 0001h = 64 Mb (-R1, -R2)

0000h, 0000h, 0000h, 0000h = all others

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

6Ah

6Ch

6Eh

70h

72h

74h

76h

78h

0000h

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

Table 34. Primary Vendor-Specific Extended Query

Addresses

(x16)

Addresses

Data

Description

(x8)

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Process Technology (Bits 7-2) 0010b = 0.23 μm MirrorBit

0009h = x8-only bus devices 0008h = all other devices

45h

8Ah

000xh

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

8Ch

8Eh

90h

92h

94h

96h

98h

9Ah

9Ch

0002h

0001h

0004h

0000h

0001h

00B5h

00C5h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

0004h = Standard Mode (Refer to Text)

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

00h = Uniform Device without WP# protect,

02h = Bottom Boot Device, 03h = Top Boot Device,

04h = Uniform sectors bottom WP# protect,

05h = Uniform sectors top WP# protect

4Fh

50h

9Eh

A0h

00xxh

0001h

Program Suspend< 00h = Not Supported, 01h = Supported

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

53

D a t a S h e e t

Command Definitions

Writing specific address and data commands or sequences into the command register initiates

device operations. Table 35 and Table 36 define the valid register command sequences. Writing

incorrect address and data values or writing them in the improper sequence may place the device

in an unknown state. A reset command is then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is

latched on the rising edge of WE# or CE#, whichever happens first. See AC Characteristics for

timing diagrams.

Reading Array Data

The device is automatically set to reading array data after device power-up. No commands are

required to retrieve data. The device is ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the erase-suspend-read

mode, after which the system can read data from any non-erase-suspended sector. After com-

pleting a programming operation in the Erase Suspend mode, the system may once again read

array data with the same exception. See Erase Suspend/Erase Resume Commands for more

information.

The system must issue the reset command to return the device to the read (or erase-suspend-

read) mode if DQ5 goes high during an active program or erase operation, or if the device is in

the autoselect mode. See the next section, Reset Command, for more information.

See also Requirements for Reading Array Data in the Device Bus Operations section for more in-

formation. The Read-Only Operations–AC Characteristics provides the read parameters, and

Figure 13 shows the timing diagram.

Reset Command

Writing the reset command resets the device to the read or erase-suspend-read mode. Address

bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase command sequence

before erasing begins. This resets the device to the read mode. Once erasure begins, however,

the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in a program command se-

quence before programming begins. This resets the device to the read mode. If the program

command sequence is written while the device is in the Erase Suspend mode, writing the reset

command returns the device to the erase-suspend-read mode. Once programming begins, how-

ever, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect command se-

quence. Once in the autoselect mode, the reset command must be written to return to the read

mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the

reset command returns the device to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation, writing the reset command returns the

device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).

Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write

the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation.

54

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Autoselect Command Sequence

The autoselect command sequence allows the host system to read several identifier codes at spe-

cific addresses:

A7:A0

(x16)

A6:A-1

(x8)

Identifier Code

Manufacturer ID

Device ID, Cycle 1

00h

01h

00h

02h

Device ID, Cycle 2

0Eh

1Ch

Device ID, Cycle 3

0Fh

1Eh

Secured Silicon Sector Factory Protect

Sector Protect Verify

03h

(SA)02h

06h

(SA)04h

Note: 3.The device ID is read over three cycles. SA = Sector Address

The autoselect command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle that contains the autoselect command. The device then enters the autose-

lect mode. The system may read at any address any number of times without initiating another

autoselect command sequence:

The system must write the reset command to return to the read mode (or erase-suspend-read

mode if the device was previously in Erase Suspend).

Enter/Exit Secured Silicon Sector Command Sequence

The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte

random Electronic Serial Number (ESN). The system can access the Secured Silicon Sector region

by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues

to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured

Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns

the device to normal operation. Table 35 and Table 36 show the address and data requirements

for both command sequences. Also, see Secured Silicon Sector Flash Memory Region for further

information. Note that the ACC function and unlock bypass modes are not available when the Se-

cured Silicon Sector is enabled.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The program command sequence is initiated by writ-

ing two unlock write cycles, followed by the program set-up command. The program address and

data are written next, which in turn initiate the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device automatically provides internally gen-

erated program pulses and verifies the programmed cell margin. Table 35 and Table 36 show the

address and data requirements for the word program command sequence, respectively.

When the Embedded Program algorithm is complete, the device then returns to the read mode

and addresses are no longer latched. The system can determine the status of the program oper-

ation by using DQ7 or DQ6. See Write Operation Status for information on these status bits. Any

commands written to the device during the Embedded Program Algorithm are ignored. Note that

the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program oper-

ation is in progress. Note that a hardware reset immediately terminates the program operation.

The program command sequence should be reinitiated once the device returns to the read mode,

to ensure data integrity.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

55

D a t a S h e e t

Programming is allowed in any sequence of address locations and across sector boundaries. Pro-

gramming to the same word address multiple times without intervening erases (incremental bit

programming) requires a modified programming method. For such application requirements,

please contact your local Spansion representative. Word programming is supported for backward

compatibility with existing Flash driver software and for occasional writing of individual words. Use

of write buffer programming (see below) is strongly recommended for general programming use

when more than a few words are to be programmed. The effective word programming time using

write buffer programming is approximately four times shorter than the single word programming

time.

Any bit in a word cannot be programmed from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was

successful. However, a succeeding read shows that the data is still “0.” Only erase operations can

convert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program words to the device faster than using

the standard program command sequence. The unlock bypass command sequence is initiated by

first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass

command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass mode

command sequence is all that is required to program in this mode. The first cycle in this sequence

contains the unlock bypass program command, A0h; the second cycle contains the program ad-

dress and data. Additional data is programmed in the same manner. This mode dispenses with

the initial two unlock cycles required in the standard program command sequence, resulting in

faster total programming time. Table 35 and Table 36 show the requirements for the command

sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset com-

mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock

bypass reset command sequence. The first cycle must contain the data 90h. The second cycle

must contain the data 00h. The device then returns to the read mode.

Write Buffer Programming

Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one

programming operation. This results in faster effective programming time than the standard pro-

gramming algorithms. The Write Buffer Programming command sequence is initiated by first

writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which programming occurs. The fourth cycle writes the

sector address and the number of word locations, minus one, to be programmed. For example, if

the system programs six unique address locations, then 05h should be written to the device. This

tells the device how many write buffer addresses are loaded with data and therefore when to ex-

pect the Program Buffer to Flash command. The number of locations to program cannot exceed

the size of the write buffer or the operation aborts.

The fifth cycle writes the first address location and data to be programmed. The write-buffer-page

is selected by address bits A

–A . All subsequent address/data pairs must fall within the se-

4

MAX

lected-write-buffer-page. The system then writes the remaining address/data pairs into the write

buffer. Write buffer locations may be loaded in any order.

The write-buffer-page address must be the same for all address/data pairs loaded into the write

buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer

pages.) This also means that Write Buffer Programming cannot be performed across multiple sec-

tors. If the system attempts to load programming data outside of the selected write-buffer page,

the operation aborts.

56

S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter

is decremented for every data load operation. The host system must therefore account for loading

a write-buffer location more than once. The counter decrements for each data load operation, not

for each unique write-buffer-address location. Note also that if an address location is loaded more

than once into the buffer, the final data loaded for that address is programmed.

Once the specified number of write buffer locations are loaded, the system must then write the

Program Buffer to Flash command at the sector address. Any other address and data combination

aborts the Write Buffer Programming operation. The device then begins programming. Data poll-

ing should be used while monitoring the last address location loaded into the write buffer. DQ7,

DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer

Programming.

The write-buffer programming operation can be suspended using the standard program suspend/

resume commands. Upon successful completion of the Write Buffer Programming operation, the

device is ready to execute the next command.

The Write Buffer Programming Sequence can be aborted in the following ways:

Load a value that is greater than the page buffer size during the Number of Locations to Pro-

gram step.

Write to an address in a sector different than the one specified during the Write-Buffer-Load

command.

Write an Address/Data pair to a different write-buffer-page than the one selected by the

Starting Address during the write buffer data loading stage of the operation.

Write data other than the Confirm Command after the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded),

DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to

reset the device for the next operation.

Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a pro-

gram operation is in progress. This flash device is capable of handling multiple write buffer

programming operations on the same write buffer address range without intervening erases. For

applications requiring incremental bit programming, a modified programming method is required;

please contact your local Spansion representative. Any bit in a write buffer address range

cannot be programmed from “0” back to a “1.” Attempting to do so can cause the device to

set DQ5=1, of cause the DQ7 and DQ6 status bits to indicate the operation was successful. How-

ever, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0”

to a “1.”

Accelerated Program

The device offers accelerated program operations through the WP#/ACC or ACC pin depending

on the particular product. When the system asserts V

on the WP#/ACC or ACC pin. The device

HH

uses the higher voltage on the WP#/ACC or ACC pin to accelerate the operation. Note that the

WP#/ACC pin must not be at V for operations other than accelerated programming, or device

HH

damage can result. WP# has an internal pullup; when unconnected, WP# is at V

.

IH

Figure 3 illustrates the algorithm for the program operation. See Erase and Program Operations-

S29GL032M Only and AC Characteristics for parameters, and Figure 14 for timing diagrams.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

57

D a t a S h e e t

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Buffer Operation?

Yes

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

Write next address/data pair

(Note 1)

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Read DQ7 - DQ0 at

Last Loaded Address

Notes:

1. When Sector Address is specified, any address in

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

Yes

DQ7 = Data?

No

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached because

DQ5= “1”, then the device FAILED. If this flowchart

location was reached because DQ1= “1”, then the

Write to Buffer operation was ABORTED. In either

case, the proper reset command must be written

before the device can begin another operation. If

DQ1=1, write the Write-Buffer-Programming-

Abort-Reset command. if DQ5=1, write the Reset

command.

No

DQ1 = 1?

DQ5 = 1?

Yes

Read DQ7 - DQ0 with

address = Last Loaded

Address

4. See Table 35 and Table 36 for command sequences

required for write buffer programming.

Yes

(Note 2)

DQ7 = Data?

No

FAIL or ABORT

PASS

(Note 3)

Figure 3. Write Buffer Programming Operation

58

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Note: See Table 35 and Table 36 for program command sequence

Figure 4. Program Operation

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming operation or a

Write to Buffer programming operation so that data can be read from any non-suspended sector.

When the Program Suspend command is written during a programming process, the device halts

the program operation within 15 µs maximum (5 µs typical) and updates the status bits. Ad-

dresses are not required when writing the Program Suspend command.

After the programming operation is suspended, the system can read array data from any non-

suspended sector. The Program Suspend command can also be issued during a programming op-

eration while an erase is suspended. In this case, data can be read from any addresses not in

Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area

(One-time Program area), then user must use the proper command sequences to enter and exit

this region. Note that the Secured Silicon Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

The system can also write the autoselect command sequence when the device is in the Program

Suspend mode. The system can read as many autoselect codes as required. When the device

exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for an-

other valid operation. See Autoselect Command Sequence for more information.

After the Program Resume command is written, the device reverts to programming. The system

can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in

the standard program operation. See Write Operation Status for more information.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

59

D a t a S h e e t

The system must write the Program Resume command (address bits are don’t care) to exit the

Program Suspend mode and continue the programming operation. Further writes of the Resume

command are ignored. Another Program Suspend command can be written after the device re-

sumes programming.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0h

Command is also valid for

Erase-suspended-program

operations

Wait 15 μs

Autoselect and SecSi Sector

read operations are also allowed

Read data as

required

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Figure 5. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing

two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then

followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The

device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any controls or timings during these oper-

ations. Table 35 and Table 36 show the address and data requirements for the chip erase

command sequence.

When the Embedded Erase algorithm is complete, the device returns to the read mode and ad-

dresses are no longer latched. The system can determine the status of the erase operation by

using DQ7, DQ6, or DQ2. See Write Operation Status for information on these status bits.

Any commands written during the chip erase operation are ignored. However, note that a hard-

ware reset immediately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once the device returns to reading array data, to ensure data

integrity.

Figure 6 illustrates the algorithm for the erase operation. See Erase and Programming Perfor-

mance in AC Characteristics for parameters, and Figure 18 for timing diagrams.

60

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D a t a S h e e t

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-

ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,

and are then followed by the address of the sector to be erased, and the sector erase command.

Table 35 and Table 36 shows the address and data requirements for the sector erase command

sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-

out period, additional sector addresses and sector erase commands can be written. Loading the

sector erase buffer can be done in any sequence, and the number of sectors can be from one

sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise

erasure may begin. Any sector erase address and command following the exceeded time-out can

or cannot be accepted. It is recommended that processor interrupts be disabled during this time

to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase

command is written. Any command other than Sector Erase or Erase Suspend during the

time-out period resets the device to the read mode. Note that the Secured Silicon Sector,

autoselect, and CFI functions are unavailable when an erase operation is in progress. The system

must rewrite the command sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section

on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in

the command sequence.

When the Embedded Erase algorithm is complete, the device returns to reading array data and

addresses are no longer latched. The system can determine the status of the erase operation by

reading DQ7, DQ6, or DQ2 in the erasing sector. See Write Operation Status for information on

these status bits.

Once the sector erase operation starts, only the Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware reset immediately terminates the erase

operation. If that occurs, the sector erase command sequence should be reinitiated once the de-

vice returns to reading array data, to ensure data integrity.

Figure 6 illustrates the algorithm for the erase operation. See Erase and Programming Perfor-

mance in AC Characteristics for parameters, and Figure 18 for timing diagrams.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

61

D a t a S h e e t

l

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 35 and Table 36 for program command sequence.

2. See DQ3: Sector Erase Timer for information on the sector erase timer.

Figure 6. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and

then read data from, or program data to, any sector not selected for erasure. This command is

valid only during the sector erase operation, including the 50 µs time-out period during the sector

erase command sequence. The Erase Suspend command is ignored if written during the chip

erase operation or Embedded Program algorithm.

When the Erase Suspend command is written during the sector erase operation, the device re-

quires a typical of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the

Erase Suspend command is written during the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase operation.

After the erase operation is suspended, the device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sec-

tors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation

Status for information on these status bits.

After an erase-suspended program operation is complete, the device returns to the erase-sus-

pend-read mode. The system can determine the status of the program operation using the DQ7

or DQ6 status bits, just as in the standard word program operation. See Write Operation Status

for more information.

In the erase-suspend-read mode, the system can also issue the autoselect command sequence.

See Autoselect Mode and Autoselect Command Sequence for details.

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D a t a S h e e t

To resume the sector erase operation, the system must write the Erase Resume command. Fur-

ther writes of the Resume command are ignored. Another Erase Suspend command can be

written after the chip resumes erasing.

Note: During an erase operation, this flash device performs multiple internal operations which are invisible to the system.

When an erase operation is suspended, any of the internal operations that were not fully completed must be restarted. As

such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress are impeded

as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the

additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity

occurs only briefly. In such cases, erase performance is not significantly impacted.

December 13, 2005 S29GL-M_00_B5

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63

D a t a S h e e t

Command Definitions

Table 35. Command Definitions( x16 Mode, BYTE# = V

)

IH

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Addr

RA

XXX

555

Second

Third

Addr

Fourth

Fifth

Sixth

Data

RD

F0

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (6)

Reset (7)

1

4

Manufacturer ID

AA

2AA

55

555

90

X00

X01

0001

227E

(Note

18)

(Note

18)

Device ID (9)

4

555

AA

X0E

X0F

Secured Silicon Sector Factory

Protect (10)

2AA

55

555

90

X03

(Note 10)

00/01

Sector Group Protect Verify (12)

4

555

AA

(SA)X02

Enter Secured Silicon Sector Region

Exit Secured Silicon Sector Region

Program

3

4

3

1

3

2

6

1

555

SA

555

XXX

555

XXX

55

AA

29

AA

A0

90

AA

B0

30

98

2AA

55

555

SA

88

90

A0

25

XXX

PA

SA

00

PD

WC

Write to Buffer (11)

PA

PD

WBL

PD

Program Buffer to Flash

Write to Buffer Abort Reset (13)

Unlock Bypass

Unlock Bypass Program (14)

Unlock Bypass Reset (15)

Chip Erase

2AA

PA

XXX

2AA

55

PD

00

55

555

F0

20

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (16)

Program/Erase Resume (16)

CFI Query (18)

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

PD = Program Data for location PA. Data latches on rising edge of

WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within same write

buffer page as PA.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

10. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

2. All values are in hexadecimal.

11. Total number of cycles in command sequence is determined by

number of words written to write buffer. Maximum number of

cycles in command sequence is 21, including “Program Buffer to

Flash” command.

12. Command sequence resets device for next command after

aborted write-to-buffer operation.

13. Unlock Bypass command is required prior to Unlock Bypass

Program command.

14. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are

555 or 2AA as shown in table, address bits above A11 and data

bits above DQ7 are don’t care.

5. No unlock or command cycles required when device is in read

mode.

6. Reset command is required to return to read mode (or to erase-

suspend-read mode if previously in Erase Suspend) when device

is in autoselect mode, or if DQ5 goes high while device is

providing status information.

15. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

16. Erase Resume command is valid only during Erase Suspend

mode.

7. Fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD

and WC. See Autoselect Command Sequence for more

information.

8. Device ID must be read in three cycles.

17. Command is valid when device is ready to read array data or

when device is in autoselect mode.

18. Refer to Table 18, AutoSelect Codes for individual Device IDs

per device density and model number.

9. If WP# protects highest address sector, data is 98h for factory

locked and 18h for not factory locked. If WP# protects lowest

address sector, data is 88h for factory locked and 08h for not

factor locked.

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S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

Table 36. Command Definitions (x8 Mode, BYTE# = V )

IL

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Data

Fifth

Data

Sixth

Addr Data

Addr Data Addr Data Addr Data

Addr

Read (6)

Reset (7)

1

4

RA

RD

F0

AA

XXX

AAA

Manufacturer ID

Device ID (9)

555

55

AAA

90

X00

X02

01

7E

X1C (Note 17) X1E (Note 17)

Secured Silicon Sector Factory

Protect (10)

Sector Group Protect Verify (12)

Enter Secured Silicon Sector Region

Exit Secured Silicon Sector Region

Write to Buffer (11)

Program Buffer to Flash

Write to Buffer Abort Reset (13)

Chip Erase

4

AAA

AA

555

55

AAA

90

X06

(Note 10)

00/01

4

3

4

3

1

3

6

1

AAA

SA

AAA

XXX

AA

29

AA

B0

30

98

555

55

AAA

SA

90 (SA)X04

88

90

25

XXX

SA

00

BC

PA

PD

WBL

PD

555

55

AAA

F0

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Program/Erase Suspend (14)

Program/Erase Resume (15)

CFI Query (16)

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

PD = Program Data for location PA. Data latches on rising edge of

WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within same write

buffer page as PA.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are

555 or AAA as shown in table, address bits above A11 are don’t

care.

10. If WP# protects highest address sector, data is 98h for factory

locked and 18h for not factory locked. If WP# protects lowest

address sector, data is 88h for factory locked and 08h for not

factor locked.

11. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

12. Total number of cycles in command sequence is determined by

number of bytes written to write buffer. Maximum number of

cycles in command sequence is 37, including “Program Buffer to

Flash” command.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

14. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

15. Erase Resume command is valid only during Erase Suspend

mode.

5. Unless otherwise noted, address bits A21–A11 are don’t cares.

6. No unlock or command cycles required when device is in read

mode.

7. Reset command is required to return to read mode (or to erase-

suspend-read mode if previously in Erase Suspend) when device

is in autoselect mode, or if DQ5 goes high while device is

providing status information.

8. Fourth cycle of autoselect command sequence is a read cycle.

Data bits DQ15–DQ8 are don’t care. See Autoselect Command

Sequence section or more information.

9. Device ID must be read in three cycles.

16. Command is valid when device is ready to read array data or

when device is in autoselect mode.

17. Refer to Table 18, AutoSelect Codes for individual Device IDs

per device density and model number.

December 13, 2005 S29GL-M_00_B5

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65

D a t a S h e e t

Write Operation Status

The device provides several bits to determine the status of a program or erase operation: DQ2,

DQ3, DQ5, DQ6, and DQ7. Table 37 and the following subsections describe the function of these

bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is

complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to

determine whether an Embedded Program or Erase operation is in progress or is completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase

algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling

is valid after the rising edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend.

When the Embedded Program algorithm is complete, the device outputs the datum programmed

to DQ7. The system must provide the program address to read valid status information on DQ7.

If a program address falls within a protected sector, Data# Polling on DQ7 is active for approxi-

mately 1 µs, then the device returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embed-

ded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling

produces a “1” on DQ7. The system must provide an address within any of the sectors selected

for erasure to read valid status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to the read

mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that are protected. However, if the system reads

DQ7 at an address within a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asyn-

chronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device can

change from providing status information to valid data on DQ7. Depending on when the system

samples the DQ7 output, it can read the status or valid data. Even if the device has completed

the program or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may be

still invalid. Valid data on DQ0–DQ7 appears on successive read cycles.

Table 37 shows the outputs for Data# Polling on DQ7. Figure 7 shows the Data# Polling algo-

rithm. Figure 17 shows the Data# Polling timing diagram.

66

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

START

Read DQ15–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ15–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid address is any

sector address within the sector being erased. During chip erase, a valid address is any

non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 can change simultaneously with DQ5.

Figure 7. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algo-

rithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE#

pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can

be tied together in parallel with a pull-up resistor to V

.

CC

If the output is low (Busy), the device is actively erasing or programming. (This includes program-

ming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode,

the standby mode, or in the erase-suspend-read mode. Table 37 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or

complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at

any address, and is valid after the rising edge of the final WE# pulse in the command sequence

(prior to the program or erase operation), and during the sector erase time-out.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

67

D a t a S h e e t

During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-

dress cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles.

When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6

toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors

are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or

is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm

is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops tog-

gling. However, the system must also use DQ2 to determine which sectors are erasing or erase-

suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the

program command sequence is written, then returns to reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embed-

ded Program algorithm is complete.

Table 37 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm.

Figure 20 shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2

and DQ6 in graphical form. Also, see DQ2: Toggle Bit II.

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S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

START

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for more information.

Figure 8. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively

erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-

suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command

sequence.

DQ2 toggles when the system reads at addresses within those sectors that are selected for era-

sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot

distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, in-

dicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both status bits are required for sector and mode

information. Refer to Table 37 to compare outputs for DQ2 and DQ6.

December 13, 2005 S29GL-M_00_B5

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69

D a t a S h e e t

Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II”

explains the algorithm, also see RY/BY#: Ready/Busy#. Figure 20 shows the toggle bit timing di-

agram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.

Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least

twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and

store the value of the toggle bit after the first read. After the second read, the system would com-

pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system can read array data on DQ7–DQ0 on the

following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still tog-

gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If

it is, the system should then determine again whether the toggle bit is toggling, since the toggle

bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the

device has successfully completed the program or erase operation. If it is still toggling, the device

did not completed the operation successfully, and the system must write the reset command to

return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and

DQ5 did not go high. The system may continue to monitor the toggle bit and DQ5 through suc-

cessive read cycles, determining the status as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this case, the system must start at the beginning

of the algorithm when it returns to determine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal

pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase

cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was

previously programmed to “0.” Only an erase operation can change a “0” back to a “1.”

Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5

produces a “1.”

In all these cases, the system must write the reset command to return the device to the reading

the array (or to erase-suspend-read if the device was previously in the erase-suspend-program

mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether

or not erasure started. (The sector erase timer does not apply to the chip erase command.) If

additional sectors are selected for erasure, the entire time-out also applies after each additional

sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.”

If the time between additional sector erase commands from the system can be assumed to be

less than 50 µs, the system need not monitor DQ3(see Sector Erase Command Sequence).

After the sector erase command is written, the system should read the status of DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure that the device accepted the command sequence, and then

reads DQ3. If DQ3 is “1,” the Embedded Erase algorithm started; all further commands (except

Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts

additional sector erase commands. To ensure the command was accepted, the system software

should check the status of DQ3 prior to and following each subsequent sector erase command. If

DQ3 is high on the second status check, the last command might not have been accepted.

Table 37 shows the status of DQ3 relative to the other status bits.

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S29GL-M MirrorBit^TMFlash Family

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D a t a S h e e t

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 pro-

duces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return

the device to reading array data. See Write Buffer for more details.

Table 37. Write Operation Status

DQ7

(Note 2)

DQ5

(Note 1)

DQ2

(Note 2)

Status

DQ6

DQ3

DQ1 RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

N/A No toggle

0

N/A

0

1

Standard

Mode

Program

Suspend

Mode

1

Toggle

Program-Suspended Sector

Non-Program

Invalid (not allowed)

Program-

Suspend Read

Data

1

Suspended Sector

Erase-Suspended Sector

Non-Erase Suspended Sector

Erase-Suspend-Program

(Embedded Program)

1

No toggle

Toggle

0

Data

N/A

Toggle

N/A

1

Erase-

Erase

Suspend

Mode

Suspend Read

DQ7#

0

Busy (Note 3)

Abort (Note 4)

DQ7#

Toggle

0

N/A

0

1

0

Write-to-

Buffer

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation

exceeded the maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate

subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address

location.

4. DQ1 switches to ‘1’ when the device aborts the write-to-buffer operation

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

71

D a t a S h e e t

Absolute Maximum Ratings

Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground:

V

(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

CC

. . . . . . . . . . . . A9, OE#, ACC and RESET# (Note 2)–0.5 V to +12.5 V

All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V

CC

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may

overshoot V_SSto –2.0 V for periods of up to 20 ns. See Figure 9, Maximum Negative

Overshoot Waveform. Maximum DC voltage on input or I/Os is V_CC+ 0.5 V. During voltage

transitions, input or I/O pins may overshoot to V_CC+ 2.0 V for periods up to 20 ns. See Figure 10.

2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is –0.5 V. During voltage

transitions, A9, OE#, ACC, and RESET# may overshoot V_SSto –2.0 V for periods of up to 20 ns.

See Figure 9. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may

overshoot to +14.0V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should

not be greater than one second.

4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only; functional operation of the device at these or any other

conditions above those indicated in the operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating conditions for extended periods may affect

device reliability.

20 ns

+0.8 V

–0.5 V

–2.0 V

20 ns

Figure 9. Maximum Negative Overshoot Waveform

20 ns

V

CC

+2.0 V

V

CC

+0.5 V

2.0 V

20 ns

Figure 10. Maximum Positive Overshoot Waveform

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

A

Supply Voltages

V

for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V

for regulated voltage range. . . . . . . . . . . . . . . . . . . . . +3.0 V to +3.6 V

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

CC

IO

Note: Operating ranges define those limits between which the functionality of the

device is guaranteed.

72

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

DC Characteristics

CMOS Compatible

Parameter

Symbol

Parameter Description

(Notes)

Test Conditions

V_IN= V_SSto V_CC

Min

Typ

Max

Unit

,

I_LI

Input Load Current (1)

A9, ACC Input Load Current

±1.0

µA

V_CC= V_{CC max}

I_LIT

I_LR

V_CC= V_{CC max}; A9 = 12.5 V

V_CC= V_{CC max}; RESET# = 12.5 V

35

µA

Reset Leakage Current

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

Output Leakage Current

±1.0

µA

1 MHz

5

20

25

35

50

60

20

40

60

5 MHz (4)

5 MHz (5)

10 MHz (4)

10 MHz (5)

10 MHz

18

25

35

40

5

I_CC1

V_CCInitial Read Current (2, 3)

CE# = V_IL,OE# = V_IH

,

mA

I_CC2

I_CC3

I_CC4

I_CC5

I_CC6

V_CCIntra-Page Read Current (2, 3)

V_CCActive Write Current (3, 4)

V_CCStandby Current (3)

CE# = V_IL,OE# = V_IH

CE#, RESET# = V_CC± 0.3 V,

WP# = V_IH

RESET# = V_SS± 0.3 V, WP# = V_IH

V_IH= V_CC± 0.3 V;

-0.1< V_IL≤ 0.3 V, WP# = V_IH

mA

µA

40 MHz

10

50

1

5

V_CCReset Current (3)

Automatic Sleep Mode (3, 7)

V_IL

V_IH

V_HH

Input Low Voltage (1, 8)

Input High Voltage 1, 8)

Voltage for ACC Program Acceleration

Voltage for Autoselect and

Temporary Sector Unprotect

–0.5

0.7 V_CC

11.5

0.8

V_CC+ 0.5

12.5

V

V_CC= 2.7 –3.6 V

12.0

V_ID

11.5

12.5

0.45

V

V_OL

Output Low Voltage (8)

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

V_OH1

V_OH2

V_LKO

0.85 V_CC

V_CC–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (9)

2.5

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP# = V_ILis ±5.0 µA.

2. The I_CCcurrent listed is typically less than 3.5 mA/MHz, with OE# at V_IH

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

4. S29GL032M, S29GL064M

.

5. S29GL128M, S29GL256M

6. I_CCactive while Embedded Erase or Embedded Program is in progress.

7. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30

ns.

8. V_CCvoltage requirements.

9. Not 100% tested.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

73

D a t a S h e e t

Test Conditions

3.3 V

2.7 k

Ω

Device

Under

Test

C

6.2 kΩ

L

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Table 38. Test Specifications

Test Condition

All Speeds

Unit

Output Load

1 TTL gate

Output Load Capacitance, C_L

(including jig capacitance)

Input Rise and Fall Times

30

pF

5

ns

V

Input Pulse Levels

0.0 or V_CC

Input timing measurement reference levels

(See Note)

Output timing measurement reference levels

0.5 V_CC

V

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care,

Any Change Permitted

Changing, State Unknown

Center Line is High

Impedance State (High Z)

Does Not Apply

V

CC

0.5 V

Input

0.5 V

CC

Measurement Level

Output

CC

0.0 V

Figure 12. Input Waveforms and Measurement Levels

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S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

Read-Only Operations-S29GL256M Only

Parameter

Description

JEDEC Std.

Speed Options

Test Setup

Unit

10

100

30

11

100

30

t_AVAV

t_RCRead Cycle Time (Note 1)

Min

CE#, OE# = V_ILMax

OE# = V_IL

ns

t_AVQVt_ACCAddress to Output Delay

t_ELQV

t_CEChip Enable to Output Delay

t_PACCPage Access Time

Max

t_GLQV

t_EHQZ

t_GHQZ

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

t_DFOutput Enable to Output High Z (Note 1)

30

16

Output Hold Time From Addresses, CE# or OE#,

t_AXQX

t_OH

Min

0

ns

Whichever Occurs First

Read

t_OEHOutput Enable Hold Time (Note 1)

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 38 for test specifications.

Read-Only Operations-S29GL128M only

Parameter

Description

JEDEC Std.

Speed Options

Test Setup

Unit

90

25

10

100

30

t_AVAV

t_RCRead Cycle Time (Note 1)

Min

ns

t_AVQVt_ACCAddress to Output Delay

CE#, OE# = V_ILMax

OE# = V_IL

t_ELQV

t_CEChip Enable to Output Delay

t_PACCPage Access Time

Max

t_GLQV

t_EHQZ

t_GHQZ

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

t_DFOutput Enable to Output High Z (Note 1)

30

16

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

t_OEHOutput Enable Hold Time (Note 1)

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 38 for test specifications.

Read-Only Operations-S29GL064M Only

Parameter

Description

JEDEC Std.

Speed Options

Test Setup

Unit

90

Min 90

CE#, OE# = V_ILMax 90

10

100

30

11

110

30

t_AVAV

t_RCRead Cycle Time (Note 1)

ns

t_AVQVt_ACCAddress to Output Delay

t_ELQV

t_CEChip Enable to Output Delay

t_PACCPage Access Time

OE# = V_IL

Max 90

Max 25

Max

t_GLQV

t_EHQZ

t_GHQZ

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (See Note)

t_DFOutput Enable to Output High Z (See Note)

30

16

30

Max

16

Output Hold Time From Addresses, CE# or OE#,

t_AXQX

t_OH

Min

0

ns

Whichever Occurs First

Read

t_OEHOutput Enable Hold Time (See Note)

Toggle and

10

Data# Polling

Note: Not 100% tested.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

75

D a t a S h e e t

AC Characteristics

Read-Only Operations-S29GL032M only

Parameter

Speed Options

Description

Test Setup

Unit

JEDEC Std.

t_AVAVt_RCRead Cycle Time (Note 1)

t_AVQVt_ACCAddress to Output Delay

90

Min 90

CE#, OE# = V_ILMax 90

10

100

30

11

110

30

ns

t_ELQV

t_CEChip Enable to Output Delay

t_PACCPage Access Time

OE# = V_IL

Max 90

Max 25

Max

t_GLQV

t_EHQZ

t_GHQZ

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

t_DFOutput Enable to Output High Z (Note 1)

30

16

30

Max

16

Output Hold Time From Addresses, CE# or OE#,

t_AXQX

t_OH

Min

0

ns

Whichever Occurs First

Read

t_OEHOutput Enable Hold Time (Note 1)

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 38 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

76

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

Same Page

A23-A2

A1-A0*

Ad

Aa

Ab

t_PACC

Ac

t_PACC

t_ACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

Note: Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

Figure 14. Page Read Timings

Hardware Reset (RESET#)

Parameter

JEDEC Std.

All Speed

Options

Description

Unit

µs

RESET# Pin Low (During Embedded Algorithms) to Read Mode

(See Note)

RESET# Pin Low (NOT During Embedded Algorithms) to Read

Mode (See Note)

t_Ready

Max

20

Max

500

ns

t_RP

t_RH

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Input Low to Standby Mode (See Note)

RY/BY# Output High to CE#, OE# pin Low

t_RPD

t_RB

Note: Not 100% tested.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

77

D a t a S h e e t

AC Characteristics

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RH

t_RP

Figure 15. Reset Timings

78

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

Erase and Program Operations-S29GL256M Only

Parameter

Speed Options

Description

Unit

JEDEC

t_AVAV

Std.

t_WC

10

11

Write Cycle Time (Note 1)

Min

100

110

ns

t_AVWL

t_AS

Address Setup Time

0

15

45

0

45

0

20

0

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

Address Hold Time From CE# or OE# high during toggle bit polling Min

Data Setup Time

Data Hold Time

t_WLAX

t_DVWH

t_WHDX

Min

Typ

Min

Max

t_DH

t_CEPH

t_OEPH

t_GHWL

t_CS

CE# High during toggle bit polling

OE# High during toggle bit polling

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time

t_GHWL

t_ELWL

0

t_WHEH

t_WLWH

t_WHDL

t_CH

t_WP

t_WPH

CE# Hold Time

Write Pulse Width

Write Pulse Width High

35

30

240

60

54

0.5

250

50

Write Buffer Program Operation (Notes 2, 3)

t_WHWH1

t_WHWH2

t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

sec

ns

µs

ns

µs

t_VHH

t_VCS

t_BUSY

t_POLL

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

WE# High to RY/BY# Low

100

110

Program Valid before Status Polling

4

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information.

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command is written). If the

suspend command was issued after t_POLL, status data is available immediately after programming

resumes. See Figure 16.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

79

D a t a S h e e t

AC Characteristics

Erase and Program Operations-S29GL128M Only

Parameter

Speed Options

Description

Unit

JEDEC

t_AVAV

t_AVWL

Std.

t_WC

t_AS

90

10

Write Cycle Time (Note 1)

Address Setup Time

Min

Typ

Min

Max

90

100

ns

0

15

45

0

45

0

20

0

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

Address Hold Time From CE# or OE# high during toggle bit polling

Data Setup Time

t_WLAX

t_DVWH

t_WHDX

t_DH

Data Hold Time

t_CEPH

t_OEPH

t_GHWL

t_CS

CE# High during toggle bit polling

OE# High during toggle bit polling

Read Recovery Time Before Write (OE# High to WE# Low)

CE# Setup Time

t_GHWL

t_ELWL

0

t_WHEH

t_WLWH

t_WHDL

t_CH

t_WP

t_WPH

CE# Hold Time

Write Pulse Width

Write Pulse Width High

35

30

240

60

54

0.5

250

50

Write Buffer Program Operation (Notes 2, 3)

Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

Sector Erase Operation (Note 2)

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

t_WHWH1

t_WHWH2

t_WHWH1

µs

t_WHWH2

t_VHH

t_VCS

sec

ns

µs

ns

µs

t_BUSY

t_POLL

WE# High to RY/BY# Low

Program Valid before Status Polling

90

100

4

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 16.

80

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

Erase and Program Operations-S29GL064M Only

Parameter

Speed Options

Description

Unit

JEDEC

t_AVAV

Std.

t_WC

t_AS

90

Min 90

Min

10

100

0

11

110

Write Cycle Time (Note 1)

ns

t_AVWL

Address Setup Time

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

Address Hold Time From CE# or OE# high during toggle bit polling

Data Setup Time

Min

Typ

15

45

0

35

0

20

0

t_WLAX

t_DVWH

t_WHDX

t_DH

Data Hold Time

t_CEPHCE# High during toggle bit polling

t_OEPHOE# High during toggle bit polling

t_GHWLRead Recovery Time Before Write (OE# High to WE# Low)

t_CS

t_CH

t_GHWL

t_ELWL

t_WHEH

t_WLWH

t_WHDL

CE# Setup Time

CE# Hold Time

Write Pulse Width

Write Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

0

t_WP

t_WPH

35

30

240

60

54

0.5

250

50

100

4

t_WHWH1t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2t_WHWH2Sector Erase Operation (Note 2)

µs

sec

ns

µs

ns

µs

t_VHH

t_VCS

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

Min

Min 90

Max

t_BUSYWE# High to RY/BY# Low

t_POLLProgram Valid before Status Polling

110

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 16.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

81

D a t a S h e e t

AC Characteristics

Erase and Program Operations-S29GL032M Only

Parameter

Speed Options

Description

Unit

JEDEC

t_AVAV

Std.

t_WC

90

Min 90

Min

10

100

0

11

110

Write Cycle Time (Note 1)

Address Setup Time

ns

t_AVWL

t_AS

t_ASO

t_AH

t_AHT

t_DS

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

Address Hold Time From CE# or OE# high during toggle bit polling Min

Min

15

45

0

35

0

20

0

t_WLAX

t_DVWH

t_WHDX

Data Setup Time

Data Hold Time

Min

Typ

Min

t_DH

t_CEPH

t_OEPH

CE# High during toggle bit polling

OE# High during toggle bit polling

t_GHWL

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_GHWLRead Recovery Time Before Write (OE# High to WE# Low)

t_CS

t_CH

t_WP

t_WPH

CE# Setup Time

CE# Hold Time

Write Pulse Width

0

35

30

240

60

54

0.5

250

50

100

4

Write Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

t_WHWH1

t_WHWH2

t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

sec

ns

µs

ns

µs

t_VHH

t_VCS

t_BUSY

t_POLL

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

WE# High to RY/BY# Low

Min 90

Max

110

Program Valid before Status Polling

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 16.

82

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_POLL

t_WP

WE#

Data

t_WPH

t_CS

t_WHWH1

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 16. Program Operation Timings

V

V_HH

HH

V

or V

V_ILor V_IH

V

or V

IL

IH

V_ILor V_IH

IL

IH

ACC

t

t_VHH

VHH

t_VHH

VHH

Figure 17. Accelerated Program Timing Diagram

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

83

D a t a S h e e t

AC Characteristics

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write

Operation Status).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

t_RC

Addresses

VA

t_ACC

t_CE

VA

t_POLL

CE#

t_CH

t_OE

OE#

WE#

t_DF

t_OH

t_OEH

High Z

DQ7

Valid Data

Complement

True

High Z

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array

data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

84

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

AC Characteristics

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6 / DQ2

RY/BY#

Valid Data

(first read)

(second read)

(stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

WE#

Erase

Erase Suspend

Read

Suspend

Program

Complete

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to

toggle DQ2 and DQ6.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

Description

All Speed Options

JEDEC

Std

Unit

ns

µs

t_VIDRV_IDRise and Fall Time (See Note)

t_RSPRESET# Setup Time for Temporary Sector Unprotect

Min

500

4

Note: Not 100% tested.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

85

D a t a S h e e t

AC Characteristics

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 22. Temporary Sector Group Unprotect Timing Diagram

V

ID

IH

RESET#

SA, A6,

A3, A2,

A1, A0

Valid*

Status

Sector Group Protect or Unprotect

Verify

40h

Data

60h

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

86

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Alternate CE# Controlled Erase and Program Operations-S29GL256M

Parameter

JEDEC

Speed Options

Description

Unit

Std.

t_WC

t_AS

t_AH

t_DS

t_DH

10

11

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

Write Cycle Time (Note 1)

Min

100

110

ns

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

0

45

0

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

Sector Erase Operation (Note 2)

RESET# High Time Before Write

Program Valid before Status Polling

Min

Typ

Min

Max

0

ns

35

25

240

60

54

0.5

50

4

t_CPH

t_WHWH1

t_WHWH2

t_WHWH1

µs

t_WHWH2

t_RH

t_POLL

sec

ns

µs

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resume (that is, the program resume command has been written).

If the suspend command was issued after t_POLL, status data is available immediately after

programming resumes. See Figure 24.

Alternate CE# Controlled Erase and Program Operations-S29GL128M

Parameter

Speed Options

Description

Unit

JEDEC

Std.

t_WC

t_AS

t_AH

t_DS

10

11

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

Write Cycle Time (Note 1)

Min

Typ

Min

Max

100

110

ns

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

0

45

0

t_DH

t_GHEL

t_WS

t_WH

t_CP

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

0

35

25

240

60

54

0.5

50

4

t_CPH

Write Buffer Program Operation (Notes 2, 3)

t_WHWH1

t_WHWH2

t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

sec

ns

µs

t_RH

t_POLL

RESET# High Time Before Write

Program Valid before Status Polling (Note 4)

Notes:

1. Not 100% tested.

2. See See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 24.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

87

D a t a S h e e t

Alternate CE# Controlled Erase and Program Operations-S29GL064M

Parameter

Speed Options

Description

Unit

JEDEC

Std.

t_WC

t_AS

t_AH

t_DS

90

Min 90

Min

10

100

0

11

110

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_EHEL

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

ns

Min

Typ

Min

Max

45

35

0

t_DH

Data Hold Time

t_GHEL

t_WS

t_WH

t_CP

Read Recovery Time Before Write (OE# High to WE# Low)

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

0

35

25

240

60

54

0.5

50

4

t_CPH

Write Buffer Program Operation (Notes 2, 3)

t_WHWH1

t_WHWH2

t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

µs

sec

ns

µs

t_RH

t_POLL

RESET# High Time Before Write

Program Valid before Status Polling (Note 5)

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 24.

Alternate CE# Controlled Erase and Program Operations-S29GL032M

Parameter

Speed Options

10

Description

Unit

JEDEC

Std.

t_WC

t_AS

90

11

110

t_AVAV

t_AVWL

t_ELAX

t_DVEH

t_EHDX

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

100

0

45

35

0

ns

t_AH

t_DS

t_DH

Data Hold Time

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

CE# Pulse Width

CE# Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

Min

Typ

Min

Max

0

ns

35

25

240

60

54

0.5

50

4

t_CPH

t_WHWH1

t_WHWH2

t_WHWH1Single Word Program Operation (Note 2)

Accelerated Single Word Program Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

t_RH

t_POLL

µs

sec

ns

µs

RESET# High Time Before Write

Program Valid before Status Polling (Note 4)

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance for more information

3. For 1–16 words/1–32 bytes programmed.

4. If a program suspend command is issued within t_POLL, the device requires t_POLLbefore reading

status data, once programming resumes (that is, the program resume command has been

written). If the suspend command was issued after t_POLL, status data is available immediately

after programming resumes. See Figure 24.

88

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

PBA for program

SA for program buffer to flash

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_POLL

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

Data

t_RH

PBD for program 29 for program buffer to flash

55 for erase

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Illustration shows device in word mode.

Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

89

D a t a S h e e t

Erase and Programming Performance

Parameter

(Notes)

Typ

(Note 1)

Max

(Note 2)

Unit

Comments

Sector Erase Time

0.5

32

64

128

256

240

3.5

64

128

256

512

sec

Excludes 00h

programming

priortoerasure

(Note 6)

S29GL032M

S29GL064M

S29GL128M

S29GL256M

Chip Erase Time

sec

Total Write Buffer Program Time (3, 5)

Total Accelerated Effective Write Buffer Program Time

(4, 5)

µs

200

Excludes

system level

overhead

S29GL032M

S29GL064M

S29GL128M

S29GL256M

31.5

63

126

252

(Note 7)

Chip Program Time

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, V_CC= 3.0V, 10,000

cycles; checkerboard data pattern.

2. Under worst case conditions of 90°C; Worst case V_CC, 100,000 cycles.

3. Effective programming time (typ) is 15 μs (per word), 7.5 μs (per byte).

4. Effective accelerated programming time (typ) is 12.5 μs (per word), 6.3 μs (per byte).

5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-

byte write buffer operation.

6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h

before erasure.

7. System-level overhead is the time required to execute the command sequence(s) for the program

command. See Table 35 and Table 36 for further information on command definitions.

90

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

TSOP Pin and BGA Package Capacitance

For package types TA, TF, BA, BF, FA, FF (refer to Ordering Information Pages):

Parameter

Symbol

Parameter

Description

Test

Setup

Typ

Max

Unit

TSOP

BGA

TSOP

BGA

TSOP

BGA

6

7.5

5.0

12

6.5

9

pF

C_IN

C_OUT

C_IN2

Input Capacitance

Output Capacitance

Control Pin Capacitance

V_IN= 0

4.2

8.5

5.4

7.5

3.9

V_OUT= 0

V_IN= 0

4.7

For package types TB, TC, BB, BC, (refer to Ordering Information Pages):

Parameter

Symbol

Parameter

Description

Test

Setup

Typ

Max

Unit

TSOP

BGA

TSOP

BGA

TSOP

BGA

TSOP

BGA

8

8.5

8

20

15

10

12

10

25

20

pF

C_IN

C_OUT

C_IN2

C_IN3

Input Capacitance

Output Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Control Pin Capacitance

RESET# and WP#/ACC Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

91

D a t a S h e e t

Physical Dimensions

TS040—40-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

92

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

TSR040—40-Pin Standard/Reverse Thin Small Outline Package (TSOP)

REVERSE PIN OUT (TOP VIEW)

A2

3

0.10 C

1

N

SEE DETAIL B

-A-

-B-

5

E

e

9

N

2

N

2

+1

5

A1

D1

4

C

D

SEATING

PLANE

B

A

0.08MM (0.0031")

M

C

A-B

6

S

B

b

7

SEE DETAIL A

WITH PLATING

c1

(c)

7

b1

BASE METAL

R

SECTION B-B

e/2

c

GAGE LINE

0.25MM (0.0098") BSC

0˚

-X-

X = A OR B

PARALLEL TO

SEATING PLANE

L

DETAIL A

DETAIL B

NOTES:

Package

TSR 040

MO-142 (B) EC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

Jedec

1

2

3

4

MIN

NOM MAX

1.20

Symbol

NOT APPLICABLE.

A

A1

A2

b1

b

c1

c

D

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.15

0.05

0.95

0.17

0.10

1.00

0.20

1.05

0.23

0.27

0.16

0.21

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

0.22

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

19.80 20.00 20.20

18.30 18.40 18.50

9.90 10.00 10.10

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

D1

E

e

7

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

0.50 BASIC

L

0

R

N

0.50

0˚

0.60

3˚

0.70

5˚

8

9

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

0.08

0.20

40

3324 \ 16-038.10a

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

93

D a t a S h e e t

Physical Dimensions

TS048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)

STANDARD PIN OUT (TOP VIEW)

A2

2

0.10 C

1

N

SEE DETAIL B

-A-

-B-

5

E

e

9

N

2

N

2

+1

5

A1

D1

4

C

D

SEATING

PLANE

B

A

0.08MM (0.0031")

M

C

A-B

6

S

B

b

7

SEE DETAIL A

WITH PLATING

c1

(c)

7

b1

BASE METAL

R

SECTION B-B

e/2

c

GAGE LINE

0.25MM (0.0098") BSC

0˚

-X-

X = A OR B

PARALLEL TO

SEATING PLANE

L

DETAIL A

DETAIL B

NOTES:

Package

TS 048

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

MO-142 (B) EC

Jedec

1

2

3

4

MIN

NOM MAX

1.20

Symbol

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

NOT APPLICABLE.

A

A1

A2

b1

b

c1

c

D

0.15

0.05

0.95

0.17

0.10

1.00

0.20

1.05

0.23

0.27

0.16

0.21

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

0.22

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

19.80 20.00 20.20

18.30 18.40 18.50

11.90 12.00 12.10

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

D1

E

e

7

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

0.50 BASIC

L

0

R

N

0.50

0˚

0.60

3˚

0.70

5˚

8

9

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

0.08

0.20

48

3325 \ 16-038.10a

94

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

TSR048—48-Pin Standard/Reverse Thin Small Outline Package (TSOP)

REVERSE PIN OUT (TOP VIEW)

A2

3

0.10 C

1

N

SEE DETAIL B

-A-

-B-

5

E

e

9

N

2

N

2

+1

5

A1

D1

4

C

D

SEATING

PLANE

B

A

0.08MM (0.0031")

M

C

A-B

6

S

B

b

7

SEE DETAIL A

WITH PLATING

c1

(c)

7

b1

BASE METAL

R

SECTION B-B

e/2

c

GAGE LINE

0.25MM (0.0098") BSC

0˚

-X-

X = A OR B

PARALLEL TO

SEATING PLANE

L

DETAIL A

DETAIL B

NOTES:

Package

TSR 048

MO-142 (B) EC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (MM).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

Jedec

1

2

3

4

MIN

NOM MAX

1.20

Symbol

NOT APPLICABLE.

A

A1

A2

b1

b

c1

c

D

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.15

0.05

0.95

0.17

0.10

1.00

0.20

1.05

0.23

0.27

0.16

0.21

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

0.22

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15MM (.0059") PER SIDE.

19.80 20.00 20.20

18.30 18.40 18.50

11.90 12.00 12.10

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

D1

E

e

7

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

0.50 BASIC

L

0

R

N

0.50

0˚

0.60

3˚

0.70

5˚

8

9

LEAD COPLANARITY SHALL BE WITHIN 0.10MM (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

0.08

0.20

48

3326 \ 16-038.10a

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

95

D a t a S h e e t

Physical Dimensions

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)

NOTES:

PACKAGE

TS/TSR 56

JEDEC

MO-142 (B) EC

1

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

SYMBOL

MIN.

---

NOM.

---

MAX.

1.20

0.15

1.05

0.23

0.27

0.16

0.21

2

3

4

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

A

A1

A2

b1

b

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.05

0.95

0.17

0.10

---

1.00

0.20

0.22

---

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE

LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

c1

c

---

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b

DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN

PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

D

19.90

18.30

20.00

18.40

20.20

18.50

D1

E

e

13.90

14.00

14.10

7

THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

0.50 BASIC

L

0.50

0˚

0.60

3˚

0.70

5˚

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

O

R

N

0.08

---

0.20

9

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

56

3160\38.10A

96

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

LAA064—64-Ball Fortified Ball Grid Array (FBGA)

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

97

D a t a S h e e t

Physical Dimensions

LAC064—64-Pin 18 x 12 mm Package

D1

D

A

0.20

2X

C

eD

H

G

F

E

D

C

B

A

8

7

6

5

4

3

2

1

7

SE

eE

E

E1

A1 CORNER ID.

(INK OR LASER)

A1

CORNER

1.00 0.5

B

6

SD

0.20

2X

C

NXφb

φ 0.25 M C A

7

TOP VIEW

B

A1

φ 0.10 M

C

CORNER

BOTTOM VIEW

0.25

C

A

A2

A1

SEATING PLANE

C

0.15

C

SIDE VIEW

NOTES:

PACKAGE

JEDEC

LAC 064

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

18.00 mm x 12.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

NOM

---

MAX

NOTE

PROFILE HEIGHT

STANDOFF

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

1.40

---

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.40

0.60

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

BODY THICKNESS

BODY SIZE

D

18.00 BSC.

12.00 BSC.

7.00 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MATRIX FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

MD

ME

N

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

64

φb

0.50

0.60

0.70

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

eD

eE

1.00 BSC.

0.50 BSC.

NONE

BALL PITCH - D DIRECTION

BALL PITCH - E DIRECTION

SOLDER BALL PLACEMENT

8. NOT USED.

SD / SE

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

DEPOPULATED SOLDER BALLS

3243 \ 16-038.12d

98

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

FBA048—48-Pin 6.15 x 8.15 mm Package

Dwg rev AF; 10/99

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

99

D a t a S h e e t

Physical Dimensions

FBC048—48-Pin 8 x 9 mm Package

Dwg rev AF; 10/99

100

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

FBE063—63-Pin 12 x 11 mm Package

Dwg rev AF; 10/99

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

101

D a t a S h e e t

Physical Dimensions

FPT-48P-M19

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8˚

0.60 0.15

(.024 .006)

24

25

*

20.00 0.20

(.787 .008)

12.00 0.20

(.472 .008)

*18.40 0.20

(.724 .008)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting

height)

0.10 0.05

(.004 .002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ^–⁺⁰⁰^.^.⁰⁰⁸³

.007 –⁺.^.0⁰0⁰3¹

0.22 0.05

(.009 .002)

M

0.10(.004)

FPT-56P-M01

0.10 0.05

(.004 .002)

(Stand off)

LEAD No.

1

56

INDEX

0.22 0.05

(.009 .002)

M

0.10(.004)

¹14.00 0.10

*

(.551 .004)

0.50(.020)

28

29

Details of "A" part

1.10 –⁺0⁰.^.0¹5⁰

20.00 0.20(.787 .008)

²18.40 0.10(.724 .004)

.043 ⁺^–.^.⁰⁰⁰⁰²⁴

(Mounting height)

0˚~8˚

*

0.17 0.03

.007 .001

0.60 0.15

(.024 .006)

0.25(.010)

"A"

0.08(.003)

102

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Physical Dimensions

FBG048—48-Pin 8 x 6 mm Package

NOTES:

PACKAGE

JEDEC

FBG 048

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

8.00 mm x 6.00 mm NOM

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

0.95

0.28

---

NOM

1.08

MAX

1.20

0.48

---

NOTE

OVERALL THICKNESS

BALL HEIGHT

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.38

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

---

BODY THICKNESS

7.80

5.80

8.00

8.20

6.20

BODY SIZE

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

6.00

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MD

ME

N

5.60 BSC.

4.00 BSC.

8

BALL FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

ROW MATRIX SIZE D DIRECTION

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

BALL DIAMETER

6

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

48

φb

0.40

0.45

0.50

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

0.40 BSC.

NONE

BALL PITCH

SD / SE

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. NOT USED.

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.

3422\ 16-038.9m

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

103

D a t a S h e e t

Revision Summary

Revision A (January 29, 2004)

Initial Release.

Revision A1 (February 23, 2004)

Connection Diagrams

Removed 80-ball Fine-pitch BGA pinout.

Ordering Information

Added additional packing type.

Removed frame description from package material set.

Updated valid combinations to reflect the addition of new package type.

Added marking descriptions to all valid combination tables.

Word Program Command Sequence and Unlock Bypass

Command Sequence

Added these sections.

Figure 3, Write Buffer Programming Operation, Figure 4,

Program Operation

Updated figure.

Table 35, “Command Definitions( x16 Mode, BYTE# = VIH),” on

page 64

Updated table.

Added note 19.

Table 36, “Command Definitions (x8 Mode, BYTE# = VIL),” on

page 65

Updated table.

Added note 17.

Figure 7, Data# Polling Algorithm

Updated figure.

Erase and Program Operations and Alternate CE# Controlled

Erase and Program Operations

Updated T

description

WHWHI

Added Note 4.

Figure 16, Figure 18, Figure 20, Figure 24

Updated figure.

Physical Dimensions

Removed BGA-63P-M02 and BGA-80P-M01

Added the TS040 package

104

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Revision A2 (February 25, 2004)

Connection Diagrams

Removed the 40-pin reverse TSOP diagram.

Updated the 48-pin standard TSOP diagram.

Removed the 48-pin reverse TSOP diagram.

Removed the 56-pin reverse TSOP diagram.

Ordering Information

Removed all references to package type R.

Table 18 Autoselect Codes, (High Voltage Method)

Updated the R3, R4 column replacing -04 and -03 designators with -R4 and -R3 respectively.

Word Program Command Sequence

Included statements documenting word programming support for backward compatibility with

existing Flash drivers.

Physical Dimensions

Removed the BGA-80P-M02 diagram.

Revision A3 (February 26, 2004)

Distinctive Characteristics

Corrected typo in the Flexible Sector Architecture section.

Revision A4 (March 24, 2004)

CMOS Compatible

Removed V from Max for V

.

OL

CC

Erase and Program Operations-S29GL256M only

Corrected unit typos.

Erase and Program Operations-S29GL128M only

Corrected the minimum Data Setup Time.

Alternate CE# Controlled Erase and Program Operations-S29GL128M

Corrected the minimum CE# Pulse width.

TSOP Pin and BGA Package Capacitance: Pkg types TB, TC, BB, BC

Added C

IN3.

Connection Diagrams

40-pin standard TSOP: Corrected pin 30 to be V

.

IO

48-pin standard TSOP: Added superscripts to designators for pin 9, 13, 14, 15 and 47. Changed

pin 13 to A21. Added two notes below illustration.

56-pin standard TSOP: Added superscripts to designators for pin 1, 2 and 12. Changed pin 56 to

NC. Added three notes below illustration.

64-ball Fortified BGA: Corrected ball D8 to be V . Added superscripts to designators for ball D8,

IO

F7, and F1. Added two notes below illustration.

63-ball Fine-pitch BGA: Added superscript to designator for Ball H7. Added one note below illus-

tration. Added connection diagrams for S29GL064M (model R0) and S29GL032M (model R0).

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

105

D a t a S h e e t

Pin Description

Added V description.

IO

Logic Symbols

Added V on all models except R3 and R4.

IO

Figure 3 Write Buffer Programming Operation

Corrected the DQ locations and added callouts to notes one through three.

DC Characteristics

Corrected test conditions for I

.

CC6

Revision A5 (April 30, 2004)

Ordering Information - S29GL032M

Added R5 and R6 model numbers to the breakout table.

Updated the Valid Combinations for BGA packages table to reflect model numbers R5 and R6.

Ordering Information - S29GL064M

Revised R8 and R9 model numbers on the breakout table.

Updated the Valid Combinations for TSOP packages table.

Ordering Information - S29GL0128M

Added R8 and R9 model numbers to the breakout table.

Revised the Package Material Set options on the breakout table.

Updated the Valid Combinations for TSOP packages table.

Ordering Information - S29GL256M

Revised the Package Material Set options on the breakout table.

Connection Diagrams (56-Pin TSOP)

Added a callout to Note 3 for pin 15.

Device Geometry Definition table

Revised the data and description information for addresses: 28h/50h and

29h/52h.

Primary Vendor Specific Extended Query table

Revised the data and description information for addresses: 45h/8Ah (x16/x8)

Revised the data information for addresses: 4Ch/98h (x16/x8)

Erase and Programming Performance table

Revised notes 1 and 2 below the table.

Revision B0 (May 24, 2004)

Global

Converted to full datasheet status.

Figure 18, Autoselect Codes, (High Voltage Method)

Corrected typos in description.

Added values for R5, R6, R7 description for cycle 1-3.

Added R8 and R9 to Model Number.

106

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005

D a t a S h e e t

Revision B1 (August 2, 2004)

Ordering Information-S29GL032M

Added the following temperature range: “C = Commercial (0°C to +70°C)'.

Commercial temperature range options added for 90ns speeds.

Global Change

S29GL032M, S29GL064M, S29GL128M, S29GL236M ordering options pages:

Updated note 3 with the following “...TSOPs can be packed in Types 0 and 3; BGAs can be packed

in Types 0, 2, or 3.

Revision B2 (September 8, 2004)

Connection Diagram - 64-ball Fortified BGA

Modified note 4.

Logic Symbol-S29GL032M (Models R3, R4)

Added models R5 and R6 to the logic symbol.

Logic Symbol-S29GL064M (Models R1, R2)

Added models R8 & R9 to the logic symbol.

S29GL032M Valid Combinations

Corrected ordering part numbers for LAA064 packages.

Physical Dimensions

Renamed the BGA-48P-M20 package as the FBG048 package.

Ordering Information

Added footnotes to indicate TSOP Pb-free leadframe plating.

Revision B3 (October 9, 2004)

General

Updated all references to Figures, Tables, and Headings to reflect page number (active link)

Updated tables 20, 21, and 22

Updated tables 24, 25, and 26

S29GL064M Valid combination

Corrected ordering part numbers for TS056 packages

S29GL032M Sector Protection/Uprotection Address Tables

Corrected table titles

S29GL064M Sector Protection/Uprotection Address Tables

Corrected table titles

Primary Vendor-Specific Extended Query

Corrected CFI data at address 48h/90h to be 0001h

DC Characteristics

Updated note 2

Figure 15, Reset Timing

Added t

RH

December 13, 2005 S29GL-M_00_B5

S29GL-M MirrorBit^TMFlash Family

107

D a t a S h e e t

Revision B4 (January 10, 2005)

Secured Sector Flash Memory Region

Updated Secured Silicon Sector address table with addresses in x8-mode

DC Characteristics, CMOS Compatible

Corrected WP#/ACC input load current footnote

Document

Updated cross-references and format.

Valid Combination Tables

Added notes to the 128 Mb and 256 Mb combination tables.

Revision B5 (December 13, 2005)

Added Supersession text.

Corrected typos on connection diagrams and in CFI table.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by

Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided

as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement

of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the

use of the information in this document.

Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in

this publication are for identification purposes only and may be trademarks of their respective companies.

108

S29GL-M MirrorBit^TMFlash Family

S29GL-M_00_B5 December 13, 2005


型号：	S29GL032M11BAIR52
厂家：	SPANSION
描述：	Flash, 2MX16, 110ns, PBGA48, 8 X 6 MM, BGA-48
文件：	总110页 (文件大小：4891K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S29GL032M11BAIR52 [SPANSION]

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