S29GL128P11FAIR10 [SPANSION]
3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology; 3.0伏只页面模式闪存具有90纳米的MirrorBit工艺技术
| 型号： | S29GL128P11FAIR10 |
| 厂家： | 
SPANSION |
| 描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 文件： | 总77页 (文件大小：2742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29GL-P MirrorBit® Flash Family
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit
3.0 Volt-only Page Mode Flash Memory featuring
90 nm MirrorBit Process Technology
S29GL-P MirrorBit® Flash Family Cover Sheet
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.
Publication Number S29GL-P_00
Revision A
Amendment 7
Issue Date November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
S29GL-P MirrorBit® Flash Family
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit
3.0 Volt-only Page Mode Flash Memory featuring
90 nm MirrorBit Process Technology
Data Sheet (Preliminary)
General Description
The Spansion S29GL01G/512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These devices
offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer
that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time
than standard programming algorithms. This makes these devices ideal for today’s embedded applications that require higher
density, better performance and lower power consumption.
Distinctive Characteristics
Single 3V read/program/erase (2.7-3.6 V)
Offered Packages
– 56-pin TSOP
Enhanced VersatileI/O™ control
– 64-ball Fortified BGA
– All input levels (address, control, and DQ input levels) and outputs
are determined by voltage on V input. V range is 1.65 to V
Suspend and Resume commands for Program and Erase
IO
IO
CC
operations
90 nm MirrorBit process technology
Write operation status bits indicate program and erase
8-word/16-byte page read buffer
operation completion
32-word/64-byte write buffer reduces overall programming
Unlock Bypass Program command to reduce programming
time for multiple-word updates
time
Secured Silicon Sector region
Support for CFI (Common Flash Interface)
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
– Can be programmed and locked at the factory or by the customer
Persistent and Password methods of Advanced Sector
Protection
Uniform 64Kword/128KByte Sector Architecture
– S29GL01GP: One thousand twenty-four sectors
– S29GL512P: Five hundred twelve sectors
WP#/ACC input
– Accelerates programming time (when V is applied) for greater
throughput during system production
HH
– Protects first or last sector regardless of sector protection settings
– S29GL256P: Two hundred fifty-six sectors
– S29GL128P: One hundred twenty-eight sectors
Hardware reset input (RESET#) resets device
100,000 erase cycles per sector typical
20-year data retention typical
Ready/Busy# output (RY/BY#) detects program or erase
cycle completion
Publication Number S29GL-P_00
Revision A
Amendment 7
Issue Date November 8, 2007
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
D a t a S h e e t ( P r e l i m i n a r y )
Performance Characteristics
Maximum Read Access Times (ns)
Random Access
Page Access Time
CE# Access Time
(t
OE# Access Time
(t
Density
Voltage Range (1)
Regulated V
Time (t
)
(t
)
)
)
OE
ACC
PACC
CE
90
90
CC
128 & 256 Mb
Full V
100/110
25
100/110
110
25
25
25
CC
VersatileIO V
110
100
IO
Regulated V
100
CC
512 Mb
1 Gb
Full V
100 (2)/110
110 (2)/120
110
25
25
100 (2)/110
110 (2)/120
110
CC
VersatileIO V
IO
Regulated V
CC
Full V
120
120
CC
VersatileIO V
130
130
IO
Notes
1. Access times are dependent on V and V operating ranges.
CC
IO
See Ordering Information page for further details.
Regulated V : V = 3.0–3.6 V.
CC
CC
Full V : V = V = 2.7–3.6 V.
CC
CC
IO
VersatileIO V : V = 1.65–V , V = 3 V.
IO
IO
CC CC
2. Contact a sales representative for availability.
Current Consumption (typical values)
Random Access Read (f = 5 MHz)
30 mA
1 mA
50 mA
1 µA
8-Word Page Read (f = 10 MHz)
Program/Erase
Standby
Program & Erase Times (typical values)
Single Word Programming
Effective Write Buffer Programming (V ) Per Word
60 µs
15 µs
CC
Effective Write Buffer Programming (V ) Per Word
HH
13.5 µs
0.5 s
Sector Erase Time (64 Kword Sector)
4
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.
2.
3.
4.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Descriptions & Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Dimensions/Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Special Handling Instructions for BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TS056—56-Pin Standard Thin Small Outline Package (TSOP) . . . . . . . . . . . . . . . . . . . . . . 16
5.
Additional Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
5.2
5.3
5.4
Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Specification Bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Hardware and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contacting Spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.
7.
Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VersatileIOTM (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.
9.
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1
8.2
8.3
8.4
8.5
8.6
Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Persistent Protection Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Persistent Protection Bit Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Password Protection Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Hardware Data Protection Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1
9.2
9.3
9.4
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10. Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1 Factory Locked Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.2 Customer Lockable Secured Silicon Sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
5
D a t a S h e e t ( P r e l i m i n a r y )
12. Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.1 Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.2 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figures
Figure 3.1
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 8.1
Figure 8.2
Figure 8.3
S29GL-P Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
64-ball Fortified Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LAA064—64ball Fortified Ball Grid Array (FBGA), 11 x 13 mm . . . . . . . . . . . . . . . . . . . . . . .14
56-pin Standard TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Buffer Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
PPB Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11.3 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11.4 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11.5 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 11.6 Page Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 11.7 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 11.8 Power-up Sequence Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11.9 Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 11.10 Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 11.11 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 11.12 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 11.13 Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 11.14 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 11.15 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 65
Figure 13.1 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 13.2 Power-On Reset Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
7
D a t a S h e e t ( P r e l i m i n a r y )
Tables
Table 2.1
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 7.13
Table 7.14
Table 7.15
Table 7.16
Table 7.17
Table 7.18
Table 8.1
Table 8.2
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 13.1
Table 13.2
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
S29GL01GP Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
S29GL512P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
S29GL256P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
S29GL128P Sector & Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Autoselect Addresses in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Autoselect Entry in System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Single Word/Byte Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Write Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations . . . . . . . . . . . . . . .48
Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
S29GL-P DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
S29GL-P Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
S29GL-P Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
S29GL-P Alternate CE# Controlled Erase and Program Operations . . . . . . . . . . . . . . . . . . .64
Erase And Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
S29GL-P Memory Array Command Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
S29GL-P Sector Protection Command Definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
S29GL-P Memory Array Command Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
S29GL-P Sector Protection Command Definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Power-Up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
1. Ordering Information
The ordering part number is formed by a valid combination of the following:
S29GL01GP
12
F
F
I
01
0
PACKING TYPE
0
2
3
= Tray (standard; see (Note 4)
= 7” Tape and Reel
= 13” Tape and Reel
MODEL NUMBER (V range, protection when WP# =V
)
IL
IO
01 = V = V = 2.7 to 3.6 V, highest address sector protected
IO
CC
02 = V = V = 2.7 to 3.6 V, lowest address sector protected
IO
CC
V1 = V = 1.65 to V , V = 2.7 to 3.6 V, highest address sector protected
IO
CC CC
V2 = V = 1.65 to V , V = 2.7 to 3.6 V, lowest address sector protected
IO
CC CC
R1 = V = V = 3.0 to 3.6 V, highest address sector protected
IO
CC
R2 = V = V = 3.0 to 3.6 V, lowest address sector protected
IO
CC
TEMPERATURE RANGE
= Industrial (–40°C to +85°C)
I
PACKAGE MATERIALS SET
A
= Pb (Note 1)
F
= Pb-free
PACKAGE TYPE
T
= 56-pin Thin Small Outline Package (TSOP) Standard Pinout(TSO56)
F
= 64-ball Fortified Ball Grid Array, 1.0 mm pitch package (LAA064)
SPEED OPTION
90 = 90 ns
10 = 100 ns
11 = 110 ns
12 = 120 ns
13 = 130 ns
DEVICE NUMBER/DESCRIPTION
S29GL01GP, S29GL512P, S29GL256P, S29GL128P
3.0 Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured on 90 nm MirrorBit® process technology
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
9
D a t a S h e e t ( P r e l i m i n a r y )
Recommended Combinations
Recommended Combinations list configurations planned to be supported in volume for this device. Consult
your local sales office to confirm availability of specific recommended combinations and to check on newly
released combinations.
S29GL-P Valid Combinations
Speed
11
Package & Temperature
Model Number
R1, R2
01, 02
Packing Type
TAI (1)(2)
TFI (2)
12
0, 3 (4)
13
V1, V2
R1, R2
01, 02
S29GL01GP
11
FAI (1)(3)
FFI (3)
12
0, 2, 3 (4)
0, 3 (4)
13
V1, V2
R1, R2
01, 02
10
TAI (1)(2)
TFI (2)
10 (1), 11
11(1), 12
10
V1, V2
R1, R2
01, 02
S29GL512P
FAI (1)(3)
FFI (3)
10 (1), 11
11(1), 12
90
0, 2, 3 (4)
0, 3 (4)
V1, V2
R1, R2
01, 02
TAI (1)(2)
TFI (2)
10, 11
11
S29GL256P,
S29GL128P
V1, V2
R1, R2
01, 02
90
FAI (1)(3)
FFI (3)
10, 11
11
0, 2, 3 (4)
V1, V2
Notes
1. Contact a local sales representative for availability.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading “S29” and packing type designator from ordering part number.
4. Type 0 is standard. Specify other options as required.
10
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
2. Input/Output Descriptions & Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
Type
Description
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
A25–A0
Input
DQ14–DQ0
DQ15/A-1
I/O
I/O
Data input/output.
DQ15: Data input/output in word mode.
A-1: LSB address input in byte mode.
CE#
OE#
WE#
VCC
VIO
Input
Input
Chip Enable.
Output Enable.
Write Enable.
Device Power Supply.
Versatile IO Input.
Ground.
Input
Supply
Supply
Supply
VSS
NC
No Connect Not connected internally.
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
VIL, the device is actively erasing or programming. At High Z, the device is in ready.
RY/BY#
Output
Selects data bus width. At VIL, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active and DQ15/A-1 becomes the LSB address input. At VIH, the device is in
word configuration and data I/O pins DQ0-DQ15 are active.
BYTE#
Input
Input
RESET#
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect/Acceleration Input. At VIL, disables program and erase functions in the
outermost sectors. At VHH, accelerates programming; automatically places device in
unlock bypass mode. Should be at VIH for all other conditions. WP# has an internal pull-
WP#/ACC
RFU
Input
up; when unconnected, WP# is at VIH
.
Reserved
Reserved for future use.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
11
D a t a S h e e t ( P r e l i m i n a r y )
3. Block Diagram
Figure 3.1 S29GL-P Block Diagram
DQ15–DQ0
RY/BY#
V
CC
Sector Switches
V
SS
V
IO
Erase Voltage
Generator
Input/Output
Buffers
RESET#
WE#
WP#/ACC
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
STB
CE#
OE#
Logic
Y-Decoder
STB
Y-Gating
V
Detector
Timer
CC
Cell Matrix
X-Decoder
A
**–A0 (A-1)
Max
** A
GL01GP=A25, A
GL512P = A24, A
GL256P = A23, A
GL128P = A22
Max
Max
Max
Max
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29GL-P family.
4.1
4.2
Related Documents
The following documents contain information relating to the S29GL-P devices. Click on the title or go to
www.spansion.com download the PDF file, or request a copy from your sales office.
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
12
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figure 4.1 64-ball Fortified Ball Grid Array
Top View, Balls Facing Down
RFU on S29GL128P
RFU on S29GL256P
RFU on S29GL512P
A8
B8
C8
D8
E8
F8
G8
H8
RFU
RFU
A22
A23
VIO
VSS
A24
A25
A7
B7
C7
D7
E7
F7
G7
H7
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A6
A9
B6
A8
C6
D6
E6
F6
G6
H6
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
VCC
WE#
RESET#
A21
A19
DQ5
DQ12
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
RY/BY# WP#/ACC
A18
A20
DQ2
DQ10
DQ11
DQ3
A3
A7
B3
C3
A6
D3
A5
E3
F3
G3
H3
A17
DQ0
DQ8
DQ9
DQ1
A2
A3
B2
A4
C2
A2
D2
A1
E2
A0
F2
G2
H2
VSS
CE#
OE#
A1
B1
C1
D1
E1
F1
G1
H1
RFU
RFU
RFU
RFU
RFU
VIO
RFU
RFU
Do not connect to V or V
IL
SS
Note
RFU = No Connect (NC)
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
13
D a t a S h e e t ( P r e l i m i n a r y )
4.3
LAA064—64 ball Fortified Ball Grid Array, 11 x 13 mm
Figure 4.2 LAA064—64ball Fortified Ball Grid Array (FBGA), 11 x 13 mm
14
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figure 4.3 56-pin Standard TSOP (Top View)
NC on S29GL128P
NC on S29GL256P
NC on S29GL512P
A23
A22
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
9
56 A24
55 A25
54 A16
53 BYTE#
52 VSS
51 DQ15/A-1
50 DQ7
49 DQ14
48 DQ6
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 DQ11
41 DQ3
40 DQ10
39 DQ2
38 DQ9
37 DQ1
36 DQ8
35 DQ0
34 OE#
33 VSS
A8 10
A19 11
A20 12
WE# 13
RESET# 14
A21 15
WP#/ACC 16
RY/BY# 17
A18 18
A17 19
A7 20
A6 21
A5 22
A4 23
A3 24
A2 25
32 CE#
31 A0
A1 26
Do not connect to VIL or VSS
RFU 27
RFU 28
30 RFU
29 VIO
Note
RFU = No Connect (NC)
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
15
D a t a S h e e t ( P r e l i m i n a r y )
4.4
TS056—56-Pin Standard Thin Small Outline Package (TSOP)
Figure 4.4 56-Pin Thin Small Outline Package (TSOP), 14 x 20 mm
NOTES:
PACKAGE
TS 56
JEDEC
MO-142 (B) EC
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
SYMBOL
MIN.
---
NOM.
---
MAX.
1.20
0.15
1.05
0.23
0.27
0.16
0.21
2
3
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.05
0.95
0.17
0.17
0.10
0.10
---
1.00
0.20
0.22
---
4
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
c1
c
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
---
D
19.80
18.30
20.00
18.40
20.20
18.50
D1
6
7
8
THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
E
e
13.90
14.00
14.10
0.50 BASIC
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
L
0.50
0˚
0.60
-
0.70
8˚
O
R
N
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
---
56
0.20
3160\38.10A
16
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
5. Additional Resources
Visit www.spansion.com to obtain the following related documents:
5.1
Application Notes
The following is a list of application notes related to this product. All Spansion application notes are available
at http://www.spansion.com/support/technical_documents/application_notes.html
Using the Operation Status Bits in AMD Devices
Understanding Page Mode Flash Memory Devices
MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read
Common Flash Interface Version 1.4 Vendor Specific Extensions
MirrorBit® Flash Memory Write Buffer Programming and Page Buffer Read
Taking Advantage of Page Mode Read on the MCF5407 Coldfire
Migration to S29GL128N and S29GL256N based on 110nm MirrorBit® Technology
Optimizing Program/Erase Times
Practical Guide to Endurance and Data Retention
Configuring FPGAs using Spansion S29GL-N Flash
Connecting Spansion™ Flash Memory to a System Address Bus
Connecting Unused Data Lines of MirrorBit® Flash
Reset Voltage and Timing Requirements for MirrorBit® Flash
Versatile IO: DQ and Enhanced
5.2
5.3
Specification Bulletins
Contact your local sales office for details.
Hardware and Software Support
Downloads and related information on Flash device support is available at
www.spansion.com/support/index.html
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
Downloads and related information on simulation modeling and CAD modeling support is available at http://
www.spansion.com/support/simulation_models.html
VHDL and Verilog
IBIS
ORCAD
An FAQ (Frequently Asked Questions) list is available at
www.spansion.com/support/ses/index.html
5.4
Contacting Spansion
Obtain the latest list of company locations and contact information on our web site at
www.spansion.com/about/location.html
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
17
D a t a S h e e t ( P r e l i m i n a r y )
6. Product Overview
The S29GL-P family consists of 1 Gb, 512 Mb, 256 Mb and 128 Mb, 3.0-volt-only, page mode Flash devices
optimized for today’s embedded designs that demand a large storage array and rich functionality. These
devices are manufactured using 90 nm MirrorBit technology. These products offer uniform 64 Kword (128 Kb)
uniform sectors and feature VersatileIO control, allowing control and I/O signals to operate from 1.65 V to
VCC. Additional features include:
Single word programming or a 32-word buffer for an increased programming speed
Program Suspend/Resume and Erase Suspend/Resume
Advanced Sector Protection methods for protecting sectors as required
128 words/256 bytes of Secured Silicon area for storing customer and factory secured information. The
Secured Silicon Sector is One Time Programmable.
6.1
Memory Map
The S29GL-P devices consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 6.1–
Table 6.4.
Table 6.1 S29GL01GP Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
Sector
Range
Address Range (16-bit)
0000000h - 000FFFFh
:
Notes
SA00
:
Sector Starting Address
64 Kword/128 Kb
1024
SA1023
3FF0000H - 3FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA1022) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
Table 6.2 S29GL512P Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
Sector
Range
Address Range (16-bit)
0000000h - 000FFFFh
:
Notes
SA00
:
Sector Starting Address
64 Kword/128 Kb
512
SA511
1FF0000H - 1FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that the same pattern as all other sectors of
that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
Table 6.3 S29GL256P Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
Sector
Range
Address Range (16-bit)
0000000h - 000FFFFh
:
Notes
SA00
:
Sector Starting Address
64 Kword/128 Kb
256
SA255
0FF0000H - 0FFFFFFh
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA254) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
18
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table 6.4 S29GL128P Sector & Memory Address Map
Uniform Sector
Size
Sector
Sector
Range
Count
Address Range (16-bit)
0000000h - 000FFFFh
:
Notes
SA00
:
Sector Starting Address
64 Kword/128 Kb
128
SA127
07F0000 - 7FFFFF
Sector Ending Address
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
7. Device Operations
This section describes the read, program, erase, handshaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command registers (see Table 12.1 through Table 12.4). The command register itself does not
occupy any addressable memory location; rather, it is composed of latches that store the commands, along
with the address and data information needed to execute the command. The contents of the register serve as
input to the internal state machine and the state machine outputs dictate the function of the device. Writing
incorrect address and data values or writing them in an improper sequence may place the device in an
unknown state, in which case the system must pull the RESET# pin low or power cycle the device to return
the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation. Table 7.1 describes the required state of each
control pin for any particular operation.
Table 7.1 Device Operations
DQ8–DQ15
Addresses
Operation
CE#
OE# WE#
RESET#
WP#/ACC
(Note 1)
DQ0–DQ7 BYTE#= VIH BYTE#= VIL
Read
L
L
H
H
X
H
X
H
L
H
X
AIN
AIN
AIN
X
DOUT
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
DOUT
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
Accelerated Program
Standby
L
H
(Note 2)
L
L
H
VHH
H
VCC 0.3 V
X
H
X
VCC 0.3 V
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
L
X
X
X
X
X
Legend
L = Logic Low = V , H = Logic High = V , V = 11.5–12.5V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
HH
IN
IN
OUT
Notes
1. Addresses are AMax:A0 in word mode; A
:A-1 in byte mode.
Max
2. If WP# = V , on the outermost sector remains protected. If WP# = V , the outermost sector is unprotected. WP# has an internal pull-up; when unconnected,
IL
IH
WP# is at V . All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.)
IH
3.
D
or D
as required by command sequence, data polling, or sector protect algorithm.
OUT
IN
November 8, 2007 S29GL-P_00_A7
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19
D a t a S h e e t ( P r e l i m i n a r y )
7.2
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.3
7.4
VersatileIOTM (V ) Control
IO
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and
tolerates on all inputs and outputs (address, control, and DQ signals). VIO range is 1.65 to VCC. See Ordering
Information on page 9 for VIO options on this device.
For example, a VIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to
and from other 1.8 or 3 V devices on the same data bus.
Read
All memories require access time to output array data. In a read operation, data is read from one memory
location at a time. Addresses are presented to the device in random order, and the propagation delay through
the device causes the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from the
memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL.
WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-
DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output data.
The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#, assuming the tACC access time has been meet.
7.5
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 8 words/16 bytes. The appropriate page is selected by the higher address bits A(max)-A3.
Address bits A2-A0 in word mode (A2 to A-1 in byte mode) determine the specific word within a page. The
microprocessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the
locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is de-
asserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses
are obtained by keeping the “read-page addresses” constant and changing the “intra-read page” addresses.
20
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
7.6
Autoselect
The Autoselect mode provides manufacturer ID, Device identification, and sector protection information,
through identifier codes output from the internal register (separate from the memory array) on DQ7-DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be programmed
with its corresponding programming algorithm (see Table 7.3). The Autoselect codes can also be accessed
in-system.
There are two methods to access autoselect codes. One uses the autoselect command, the other applies VID
on address pin A9.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins must be as shown in Table 7.2.
To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect
command.
The Autoselect command sequence may be written to an address within a sector that is either in the read
or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or erasing.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the
sector was previously in Erase Suspend).
It is recommended that A9 apply VID after power-up sequence is completed. In addition, it is recommended
that A9 apply from VID to VIH/VIL before power-down the VCC/VIO.
See Table 12.1 on page 68 for command sequence details.
When verifying sector protection, the sector address must appear on the appropriate highest order address
bits (see Table 7.4 to Table 7.5). The remaining address bits are don't care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier code on
DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register.
November 8, 2007 S29GL-P_00_A7
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21
D a t a S h e e t ( P r e l i m i n a r y )
Table 7.2 Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
A14
to
Amax
to
A8
to
A5 A3
to to
BYTE# BYTE#
Description
CE# OE# WE# A16 A10 A9 A7 A6 A4 A2 A1 A0
= VIH
= VIL
DQ7 to DQ0
Manufacturer ID:
Spansion Product
L
L
H
X
X
X
VID
X
L
X
L
L
L
00
X
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
28h
H
H
L
L
H
X
VID
X
L
X
Cycle 3
H
H
H
22
X
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
23h
H
H
L
L
L
L
L
L
H
H
H
X
X
X
X
X
X
VID
VID
VID
X
X
X
L
L
L
X
X
X
Cycle 3
H
H
H
22
X
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
22h
H
H
Cycle 3
H
H
H
22
X
01h
Cycle 1
Cycle 2
L
L
H
L
22
22
X
X
7Eh
21h
H
H
Cycle 3
H
L
H
H
H
L
22
X
X
X
01h
Sector Group
Protection Verification
01h (protected),
00h (unprotected)
L
L
L
L
H
H
SA
X
X
X
VID
X
X
L
L
X
X
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects highest
address sector
99h (factory locked),
19h (not factory
locked)
VID
L
L
H
H
H
H
X
X
X
X
Secured Silicon Sector
Indicator Bit (DQ7),
WP# protects lowest
address sector
89h (factory locked),
09h (not factory
locked)
L
L
H
X
X
VID
X
L
X
Legend
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care. V = 11.5V to 12.5V
IL
IH
ID
Table 7.3 Autoselect Addresses in System
Description
Manufacturer ID
Device ID, Word 1
Address
Read Data (word/byte mode)
(Base) + 00h xx01h/1h
(Base) + 01h 227Eh/7Eh
2228h/28h (GL01GP)
2223h/23h (GL512P)
2222h/22h (GL256P)
2221h/21h (GL128P)
Device ID, Word 2
(Base) + 0Eh
Device ID, Word 3
Secure Device Verify
Sector Protect Verify
(Base) + 0Fh 2201h/01h
For S29GLxxxPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked.
For S29GLxxxPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked.
(Base) + 03h
(SA) + 02h
xx01h/01h = Locked, xx00h/00h = Unlocked
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S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table 7.4 Autoselect Entry in System
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation Byte Address Word Address
Data
Unlock Cycle 1
Unlock Cycle 2
Autoselect Command
Write
Write
Write
Base + AAAh
Base + 555h
Base + AAAh
Base + 555h
Base + 2AAh
Base + 555h
0x00AAh
0x0055h
0x0090h
Software Functions and Sample Code
Table 7.5 Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle
Operation
Write
Byte Address Word Address
base + XXXh base + XXXh
Data
Unlock Cycle 1
0x00F0h
Note
1. Any offset within the device works.
2. base = base address.
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer
to the Spansion Low Level Driver User’s Guide (available on www.spansion.com) for general information on
Spansion Flash memory software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)base_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
November 8, 2007 S29GL-P_00_A7
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23
D a t a S h e e t ( P r e l i m i n a r y )
7.7
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in
detail in the following sections.
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing address,
command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on
the 1st rising edge of WE# or CE#.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without
first writing unlock cycles within the command sequence. See Section 7.7.8 for details on the Unlock Bypass
function.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode.
The system can determine the status of the program operation by reading the DQ status bits. Refer to the
Write Operation Status on page 36 for information on these status bits.
An “0” cannot be programmed back to a “1.” A succeeding read shows that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program/Erase are ignored except the
Suspend commands.
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in
progress.
A hardware reset and/or power removal immediately terminates the Program/Erase operation and the
Program/Erase command sequence should be reinitiated once the device has returned to the read mode
to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word programming
operation. See Write Buffer Programming on page 26 when using the write buffer.
Programming to the same word address multiple times without intervening erases is permitted.
7.7.1
Single Word Programming
Single word programming mode is one method of programming the Flash. In this mode, four Flash command
write cycles are used to program an individual Flash address. The data for this programming operation could
be 8 or 16-bits wide.
While the single word programming method is supported by most Spansion devices, in general Single Word
Programming is not recommended for devices that support Write Buffer Programming. See Table 12.1
on page 68 for the required bus cycles and Figure 7.1 for the flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by reading
the DQ status bits. Refer to Write Operation Status on page 36 for information on these status bits.
During programming, any command (except the Suspend Program command) is ignored.
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in
progress.
A hardware reset immediately terminates the program operation. The program command sequence should
be reinitiated once the device has returned to the read mode, to ensure data integrity.
Programming to the same address multiple times continuously (for example, “walking” a bit within a word)
is permitted.
24
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figure 7.1 Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
Program Data to Address:
PA, PD
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Polling Status
= Busy?
No
Yes
Polling Status
= Done?
Error condition
No
(Exceeded Timing Limits)
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
25
D a t a S h e e t ( P r e l i m i n a r y )
Software Functions and Sample Code
Table 7.6 Single Word/Byte Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Byte Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
0055h
00A0h
Data
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Write
Write
Write
Note
Base = Base Address.
The following is a C source code example of using the single word program function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Program Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write unlock cycle 1
*/
*/
*/
*/
/* write unlock cycle 2
/* write program setup command
/* write data to be programmed
*( (UINT16 *)pa )
= data;
/* Poll for program completion */
7.7.2
Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation.
This results in a faster effective word programming time than the standard “word” programming algorithms.
The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in
which programming occurs. At this point, the system writes the number of “word locations minus 1” that are
loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how
many write buffer addresses are loaded with data and therefore when to expect the “Program Buffer to Flash”
confirm command. The number of locations to program cannot exceed the size of the write buffer or the
operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system
programs 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the first address/data
pair to be programmed, and selects the “write-buffer-page” address. All subsequent address/data pairs must
fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses AMAX–A5.
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write buffer.
(This means Write Buffer Programming cannot be performed across multiple “write-buffer-pages.” This also
means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to
load programming data outside of the selected “write-buffer-page”, the operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the
write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter is
decremented for every data load operation. Also, the last data loaded at a location before the “Program Buffer
to Flash” confirm command is the data programmed into the device. It is the software's responsibility to
comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each
data load operation, NOT for each unique write-buffer-address location. Once the specified number of write
buffer locations have been loaded, the system must then write the “Program Buffer to Flash” command at the
Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation.
The Write Operation Status bits should be used while monitoring the last address location loaded into the
write buffer. This eliminates the need to store an address in memory because the system can load the last
address location, issue the program confirm command at the last loaded address location, and then check
the write operation status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to
determine the device status during Write Buffer Programming.
26
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume
commands. Upon successful completion of the Write Buffer Programming operation, the device returns to
READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address”
during the “write buffer data loading” stage of the operation.
Writing anything other than the Program to Buffer Flash Command after the specified number of “data
load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”), DQ6 =
TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A “Write-to-
Buffer-Abort reset” command sequence is required when using the write buffer Programming features in
Unlock Bypass mode. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable
when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices
are capable of handling multiple write buffer programming operations on the same write buffer address range
without intervening erases.
Use of the write buffer is strongly recommended for programming when multiple words are to be
programmed.
November 8, 2007 S29GL-P_00_A7
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27
D a t a S h e e t ( P r e l i m i n a r y )
Software Functions and Sample Code
Table 7.7 Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Word Address
Base + 555h
Base + 2AAh
Data
1
2
3
4
Unlock
Unlock
00AAh
0055h
0025h
Write
Write Buffer Load Command
Write Word Count
Write
Sector Address
Sector Address
Write
Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words (1 to 64 bytes).
5 to 36
Last
Load Buffer Word N
Write Buffer to Flash
Write
Write
Program Address, Word N
Sector Address
Word N
0029h
Notes
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to
37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Write Buffer Programming Command
*/
/* NOTES: Write buffer programming limited to 16 words. */
/*
/*
/*
/*
All addresses to be written to the flash in
one operation must be within the same flash
page. A flash page begins at addresses
evenly divisible by 0x20.
*/
*/
*/
*/
UINT16 *src = source_of_data;
/* address of source data
/* flash destination address
/* word count (minus 1)
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
UINT16 *dst = destination_of_data;
UINT16 wc
= words_to_program -1;
*/
*/
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)sector_address )
*( (UINT16 *)sector_address )
= 0x0025;
= wc;
/* write write buffer load command */
/* write word count (minus 1) */
for (i=0;i<=wc;i++)
{
*dst++ = *src++; /* ALL dst MUST BE in same Write Buffer */
}
*( (UINT16 *)sector_address )
/* poll for completion */
= 0x0029;
/* write confirm command
*/
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write unlock cycle 1
*/
*/
*/
/* write unlock cycle 2
/* write buffer abort reset
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S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figure 7.2 Write Buffer Programming Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address SA, Data 25h
Load Word Count to Program
Program Data to Address:
SA, wc
wc = number of words – 1
Yes
Confirm command:
wc = 0?
No
SA = 0x29h
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Write Next Word,
Decrement wc:
wc = wc – 1
No
Write Buffer
Abort Desired?
Yes
Yes
Polling Status
Write to a Different
Sector Address to Cause
Write Buffer Abort
= Done?
No
No
Error?
Yes
Yes
Write Buffer
Abort?
No
RESET. Issue Write Buffer
Abort Reset Command
PASS. Device is in
read mode.
FAIL. Issue reset command
to return to read array mode.
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7.7.3
Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 12.1 on page 68 and
Figure 7.3.) The device does not require the system to preprogram a sector prior to erase. The Embedded
Erase algorithm automatically programs and verifies the entire memory to an all zero data pattern prior to
electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-
out period, additional sector addresses may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The time between these
additional cycles must be less than 50 µs. Any sector erase address and command following the exceeded
time-out (50µs) may or may not be accepted. Any command other than Sector Erase or Erase Suspend
during the time-out period resets that sector to the read mode. The system can monitor DQ3 to determine if
the sector erase timer has timed out (See Section 7.8.6.) The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
When the Embedded Erase algorithm is complete, the sector returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2
in the erasing sector. Refer to Section 7.8 for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that sector has returned to reading array
data, to ensure the sector is properly erased.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without
first writing unlock cycles within the command sequence. See Section 7.7.8 for details on the Unlock Bypass
function.
Figure 7.3 illustrates the algorithm for the erase operation. Refer to Section 11.7.5 for parameters and timing
diagrams.
Software Functions and Sample Code
Table 7.8 Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Base + AAAh
Base + 555h
Sector Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Sector Address
Data
00AAh
0055h
0080h
00AAh
0055h
0030h
1
2
3
4
5
6
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Sector Erase Command
Write
Unlimited additional sectors may be selected for erase; command(s) must be written within 50 µs.
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level
Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
*/
*/
*/
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
*( (UINT16 *)sector_address )
= 0x0030;
/* write sector erase command
*/
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 7.3 Sector Erase Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Select
Additional
Sectors?
No
Yes
Write Additional
Sector Addresses
• Each additional cycle must be written within tSEA timeout
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
• No limit on number of sectors
Yes
Last Sector
Selected?
No
• Commands other than Erase Suspend or selecting additional
sectors for erasure during timeout reset device to reading array
data
Poll DQ3.
DQ3 = 1?
No
Yes
Perform Write Operation
Status Algorithm
(see Figure 7.4)
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes
Done?
No
No
Error condition (Exceeded Timing Limits)
DQ5 = 1?
Yes
PASS. Device returns
to reading array.
FAIL. Write reset command
to return to reading array.
Notes
1. See Table 12.1 on page 68 for erase command sequence.
2. See DQ3: Sector Erase Timeout State Indicator on page 39 for information on the sector erase timeout.
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7.7.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 12.1 on page 68. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to
electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not
required to provide any controls or timings during these operations. The Command Definitions on page 67
shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer
to “Write Operation Status” for information on these status bits.
The Unlock Bypass feature allows the host system to send program commands to the Flash device without
first writing unlock cycles within the command sequence. See Section 7.7.8 for details on the Unlock Bypass
function.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased.
Software Functions and Sample Code
Table 7.9 Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Unlock
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Base + AAAh
Base + 555h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
Data
00AAh
0055h
0080h
00AAh
0055h
0010h
1
2
3
4
5
6
Unlock
Write
Setup Command
Unlock
Write
Write
Unlock
Write
Chip Erase Command
Write
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level
Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
*/
*/
*/
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
*/
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7.7.5
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. The sector address is required when writing this
command. This command is valid only during the sector erase operation, including the minimum tSEA time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during
the chip erase operation.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of 20 µs (5 µs typical) to suspend the erase operation. However, when the Erase Suspend
command is written during the sector erase time-out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system
can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status
information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. Refer to Table 7.35 for information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the program operation using write operation status bits, just as
in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to
Write Buffer Programming on page 26 and the Autoselect on page 21 for details.
To resume the sector erase operation, the system must write the Erase Resume command. The address of
the erase-suspended sector is required when writing this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Software Functions and Sample Code
Table 7.10 Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Base + XXXh
Base + XXXh
00B0h
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)base_addr ) = 0x00B0;
/* write suspend command
*/
Table 7.11 Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Sector Address
Data
1
Write
Sector Address
0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)sector_addr ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
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7.7.6
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a
“Write to Buffer” programming operation so that data can read from any non-suspended sector. When the
Program Suspend command is written during a programming process, the device halts the programming
operation within 15 µs maximum (5 µs typical) and updates the status bits. Addresses are “don't-cares” when
writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any non-
suspended sector. The Program Suspend command may also be issued during a programming operation
while an erase is suspended. In this case, data may be read from any addresses not within a sector in Erase
Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use
the proper command sequences to enter and exit this region.
The system may also write the Autoselect Command Sequence when the device is in Program Suspend
mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored
in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend
mode, and is ready for another valid operation. See Autoselect on page 21 for more information.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the write operation status bits, just as in the standard
program operation. See Write Operation Status on page 36 for more information.
The system must write the Program Resume command (address bits are “don't care”) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Program Resume command
are ignored. Another Program Suspend command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 7.12 Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle
Operation
Word Address
Data
1
Write
Base + XXXh
00B0h
The following is a C source code example of using the program suspend function. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr ) = 0x00B0;
/* write suspend command
*/
Table 7.13 Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle
Operation
Write
Word Address
Data
1
Base + XXXh
0030h
The following is a C source code example of using the program resume function. Refer to the Spansion Low
Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr ) = 0x0030;
/* write resume command
*/
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7.7.7
Accelerated Program
Accelerated single word programming and write buffer programming operations are enabled through the
WP#/ACC pin. This method is faster than the standard program command sequences.
Note
The accelerated program functions must not be used more than 10 times per sector.
If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note
that if a “Write-to-Buffer-Abort Reset” is required while in Unlock Bypass mode, the full 3-cycle RESET
command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion
of the embedded program operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC to VHH
.
The WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device
damage may result.
It is recommended that WP#/ACC apply VHH after power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from VHH to VIH/VIL before powering down VCC/VIO.
7.7.8
Unlock Bypass
This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal
four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. The Command Definitions on page 67 shows the requirements for
the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort
Reset, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must
issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the sector address
and the data 90h. The second cycle need only contain the data 00h. The sector then returns to the read
mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general
information on Spansion Flash memory software development guidelines.
Table 7.14 Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Unlock
Operation
Write
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
00AAh
0055h
0020h
1
2
3
Unlock
Write
Entry Command
Write
/* Example: Unlock Bypass Entry Command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0020;
/* write unlock cycle 1
*/
*/
*/
/* write unlock cycle 2
/* write unlock bypass command
/* At this point, programming only takes two write cycles.
/* Once you enter Unlock Bypass Mode, do a series of like
/* operations (programming or sector erase) and then exit
/* Unlock Bypass Mode before beginning a different type of
/* operations.
*/
*/
*/
*/
*/
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Table 7.15 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Write
Word Address
Base +xxxh
Data
00A0h
1
2
Program Setup Command
Program Command
Write
Program Address
Program Data
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode!
*/
/* write program setup command
/* write data to be programmed
*( (UINT16 *)base_addr ) = 0x00A0;
*/
*( (UINT16 *)pa )
= data;
*/
*/
/* Poll until done or error.
/* If done and more to program, */
/* do above two cycles again. */
Table 7.16 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Reset Cycle 1
Reset Cycle 2
Operation
Write
Word Address
Data
0090h
0000h
1
2
Base +xxxh
Base +xxxh
Write
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr ) = 0x0090;
*( (UINT16 *)base_addr ) = 0x0000;
7.8
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
7.8.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last
word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling
status on any word other than the last word to be programmed in the write-buffer-page returns false status
information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# polling on DQ7 is active, then that sector returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
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D a t a S h e e t ( P r e l i m i n a r y )
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read
cycles.
See the following for more information: Table 7.17, shows the outputs for Data# Polling on DQ7. Figure 7.4,
shows the Data# Polling algorithm; and Figure 11.7, shows the Data# Polling timing diagram.
Figure 7.4 Write Operation Status Flowchart
START
Read 1
(Note 6)
YES
Program
Operation
Complete
DQ7=valid
data?
NO
YES
YES
Read 2
Read 3
Read 1
DQ5=1?
Read3= valid
data?
NO
NO
Read 2
Read 3
Program
Operation
Failed
YES
Write Buffer
Programming?
YES
NO
Programming
Operation?
NO
Device BUSY,
Re-Poll
(Note 3)
(Note 5)
(Note 1)
YES
(Note 1)
(Note 2)
YES
DQ6
toggling?
DQ6
DEVICE
ERROR
TIMEOUT
toggling?
NO
(Note 4)
NO
YES
Read1
DQ1=1?
YES
NO
Device BUSY,
Re-Poll
DQ2
toggling?
NO
Read 2
Read 3
Device BUSY,
Re-Poll
Erase
Device in
Erase/Suspend
Mode
Operation
Complete
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
YES
Write Buffer
Operation Failed
Read3 DQ1=1
AND DQ7 ?
Valid Data?
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
NO
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Device BUSY,
Re-Poll
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7.8.2
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address that is
being programmed or erased causes DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100μs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 36).
If a program address falls within a protected sector, DQ6 toggles for approximately 1μs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
Algorithm is complete.
See the following for additional information: Figure 7.4, Figure 11.13 on page 63, and Table 7.17.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in
state.
7.8.3
7.8.4
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system
reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and mode information. Refer to Table 7.17 to compare
outputs for DQ2 and DQ6. See Figure 11.14 on page 63 for additional information.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the
toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The
system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read
cycles, the system determines that the toggle bit is still toggling, the system also should note whether the
value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 39). If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases
operation. If it is still toggling, the device did not complete the operation successfully, and the system must
write the reset command to return to reading array data. The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at
the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 7.4 for
more details.
Note
When verifying the status of a write operation (embedded program/erase) of a memory sector, DQ6 and DQ2
toggle between high and low states in a series of consecutive and contiguous status read cycles. In order for
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this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with
read accesses to other memory sectors. If it is not possible to temporarily prevent reads to other memory
sectors, then it is recommended to use the DQ7 status bit as the alternative method of determining the active
or inactive status of the write operation.
7.8.5
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully
completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a location that was
previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the
device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits
that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is
masked during the programming operation. Under valid DQ5 conditions, the system must write the reset
command to return to the read mode (or to the erase-suspend-read mode if a sector was previously in the
erase-suspend-program mode).
7.8.6
DQ3: Sector Erase Timeout State Indicator
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than tSEA, then the system need not monitor DQ3.
See Sector Erase on page 30 for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To
ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Table 7.17 shows the status of DQ3 relative to the other status bits.
7.8.7
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset” command sequence to return the device to reading
array data. See Write Buffer Programming on page 26 for more details.
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Table 7.17 Write Operation Status
DQ7
DQ5
DQ2
RY/
Status
(Note 2)
DQ6
(Note 1) DQ3
(Note 2)
DQ1
0
BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Program-Suspended
DQ7#
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Standard
Mode
N/A
Invalid (not allowed)
Data
1
1
1
1
0
Program
Suspend
Mode
Program-
Sector
Suspend
Non-Program
Read
Suspended Sector
Erase-Suspended
1
No toggle
Toggle
0
N/A
Toggle
N/A
N/A
N/A
Erase-
Sector
Suspend
Erase
Suspend
Mode
Non-Erase
Read
Data
Suspended Sector
Erase-Suspend-Program
(Embedded Program)
DQ7#
0
N/A
Busy (Note 3)
Abort (Note 4)
DQ7#
DQ7#
Toggle
Toggle
0
0
N/A
N/A
N/A
N/A
0
1
0
0
Write-to-
Buffer
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
Refer toDQ5: Exceeded Timing Limits on page 39 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
7.9
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device. Table 6.2–Table 6.3 indicate the address space that each sector occupies. The device
address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits
required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current specification for
the write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
7.9.1
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. This feature allows the host system to detect when data is ready to be read by simply
monitoring the RY/BY# pin, which is a dedicated output and controlled by CE# (not OE#).
7.9.2
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading
array data.
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but not at
VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the
system to read the boot-up firmware from the Flash memory upon a system reset. See Figure 11.7
on page 58 and Figure 11.8 on page 59 for timing diagrams.
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7.9.3
Software Reset
Software reset is part of the command set (see Table 12.1 on page 68) that also returns the device to array
read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle was not
successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
5. after any aborted operations
Software Functions and Sample Code
Table 7.18 Reset
(LLD Function = lld_ResetCmd)
Cycle
Operation
Byte Address
Word Address
Data
Reset Command
Write
Base + xxxh
Base + xxxh
00F0h
Note
Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver
User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software
development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the sectors to the read and address bits are ignored.
Reset commands are ignored during program and erase operations.
The reset command may be written between the cycles in a program command sequence before
programming begins (prior to the third cycle). This resets the sector to which the system was writing to the
read mode.
If the program command sequence is written to a sector that is in the Erase Suspend mode, writing the
reset command returns that sector to the erase-suspend-read mode.
The reset command may be written during an Autoselect command sequence.
If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command
returns that sector to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the “Write to Buffer
Abort Reset” command sequence to RESET the device to reading array data. The standard RESET
command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command
sequence [see Command Definitions on page 67 for details].
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8. Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations
in any or all sectors and can be implemented through software and/or hardware methods, which are
independent of each other. This section describes the various methods of protecting data stored in the
memory array. An overview of these methods in shown in Figure 8.1.
Figure 8.1 Advanced Sector Protection/Unprotection
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
WP#/ACC = VIL
(Highest or Lowest
Sector Locked)
Persistent Method
Password Method
(DQ1)
(DQ2)
64-bit Password
(One Time Protect)
1. Bit is volatile, and defaults to “1” on reset.
PPB Lock Bit1,2,3
2. Programming to “0” locks all PPBs to their
current state.
0 = PPBs Locked
1 = PPBs Unlocked
3. Once programmed to “0”, requires hardware
reset to unlock.
Persistent
Protection Bit
(PPB)4,5
Dynamic
Protection Bit
(DYB)6,7,8
Memory Array
Sector 0
Sector 1
Sector 2
PPB 0
PPB 1
PPB 2
DYB 0
DYB 1
DYB 2
Sector N-2
Sector N-1
Sector N3
PPB N-2
PPB N-1
PPB N
DYB N-2
DYB N-1
DYB N
3. N = Highest Address Sector.
4. 0 = Sector Protected,
1 = Sector Unprotected.
6. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
7. Protect effective only if PPB Lock Bit is
unlocked and corresponding PPB is “1”
(unprotected).
8. Volatile Bits: defaults to user choice upon
power-up (see ordering options).
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8.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors
are unprotected, unless otherwise chosen through the DYB ordering option (see Ordering Information
on page 9). The device programmer or host system must then choose which sector protection method to use.
Programming (setting to “0”) any one of the following two one-time programmable, non-volatile bits locks the
part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 8.1 Lock Register
DQ15-3
DQ2
DQ1
DQ0
Password Protection Mode
Lock Bit
Persistent Protection Mode
Lock Bit
Secured Silicon Sector
Protection Bit
Don’t Care
For programming lock register bits refer to Table 12.2 on page 69 and Table 12.4 on page 71.
Notes
1. If the password mode is chosen, the password must be programmed before setting the
corresponding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes
for Sector 0 are disabled, while reads from other sectors are allowed until exiting this mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode
Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following three states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB
lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Section 8.2–Section 8.5.
8.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as
the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore
do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. While programming PPB for a sector, array data can be read from any other sector, except Sector
0 (used for Data# Polling) and the sector in which sector PPB is being programmed.
3. Entry command disables reads and writes for the sector selected.
4. Reads within that sector return the PPB status for that sector.
5. All Reads must be performed using the read mode.
6. The specific sector address (A25-A16 GL01GP, A24-A16 GL512P, A23-A16 GL256P, A22-A16
GL128P) are written at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out
without programming or erasing the PPB.
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8. There are no means for individually erasing a specific PPB and no specific sector address is
required for this operation.
9. Exit command must be issued after the execution which resets the device to read mode and re-
enables reads and writes for Sector 0.
10.The programming state of the PPB for a given sector can be verified by writing a PPB Status Read
Command to the device as described by the flow chart shown in Figure 8.2.
Figure 8.2 PPB Program Algorithm
Enter PPB
Command Set.
Addr = BA
Program PPB Bit.
Addr = SA
Read Byte Twice
Addr = SA0
No
DQ6 =
Toggle?
Yes
No
DQ5 = 1?
Wait 500 µs
Yes
Read Byte Twice
Addr = SA0
No
Read Byte.
Addr = SA
DQ6 =
Toggle?
Yes
No
DQ0 =
'0' (Pgm.)?
FAIL
Yes
Issue Reset
Command
PASS
Exit PPB
Command Set
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8.2.1
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only
control the protection scheme for unprotected sectors that have their PPBs cleared (erased to “1”). By issuing
the DYB Set or Clear command sequences, the DYBs are set (programmed to “0”) or cleared (erased to “1”),
thus placing each sector in the protected or unprotected state respectively. This feature allows software to
easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when
changes are needed.
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed. When the
parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset, the
DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectorsmay be
modified depending upon the PPB state of that sector (see Table 8.2).
3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen
(programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic
state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of
the sectors respectively. However, if there is a need to change the status of the persistently locked
sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting
the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the
desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates
normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early
in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the PPB and DYB
bits have the same function when WP#/ACC = VHH as they do when ACC =VIH.
8.3
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to “0”), it
locks all PPBs and when cleared (programmed to “1”), allows the PPBs to be changed. There is only one
PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password protection
mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the
desired settings.
8.4
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection
Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password
requirement, after power up and reset, the PPB Lock Bit is set “0” to maintain the password mode of
operation. Successful execution of the Password Unlock command by entering the entire password clears the
PPB Lock Bit, allowing for sector PPBs modifications.
Notes
1. There is no special addressing order required for programming the password. Once the Password
is written and verified, the Password Mode Locking Bit must be set in order to prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a
cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
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5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and
further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and
Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10.The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a
hacker from running through all the 64-bit combinations in an attempt to correctly match a
password.
11.Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to
the device.
12.Password verification is only allowed during the password programming operation.
13.All further commands to the password region are disabled and all operations are ignored.
14.If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB
Lock Bit.
15.Entry command sequence must be issued prior to any of any operation and it disables reads and
writes for Sector 0. Reads and writes for other sectors excluding Sector 0 are allowed.
16.If the user attempts to program or erase a protected sector, the device ignores the command and
returns to read mode.
17.A program or erase command to a protected sector enables status polling and returns to read
mode without having modified the contents of the protected sector.
18.The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing
individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Figure 8.3 Lock Register Program Algorithm
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
XXXh = Address don’t care
Program Lock Register Data
Address XXXh, Data A0h
Address XXXh*, Data PD
Program Data (PD): See text for Lock Register definitions
Caution: Lock register can only be progammed once.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Done?
No
No
DQ5 = 1?
Error condition (Exceeded Timing Limits)
Yes
PASS. Write Lock Register
Exit Command:
FAIL. Write rest command
to return to reading array.
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
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8.5
Advanced Sector Protection Software Examples
Table 8.2 Sector Protection Schemes: DYB, PPB and PPB Lock Bit Combinations
Unique Device PPB Lock Bit
0 = locked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
1 = unlocked
Sector Protection Status
Protected through PPB
Protected through PPB
Unprotected
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
Any Sector
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
x
x
1
0
x
x
0
1
Protected through DYB
Protected through PPB
Protected through PPB
Protected through DYB
Unprotected
Table 8.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the
sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB
Lock Bit can only be unlocked (reset to “1”) through a hardware reset or power cycle. See also Figure 8.1 for
an overview of the Advanced Sector Protection feature.
8.6
Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP#/ACC is at VIL, the either the highest or lowest sector is locked (device specific).
There are additional methods by which intended or accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes these methods:
8.6.1
WP#/ACC Method
The Write Protect feature provides a hardware method of protecting one outermost sector. This function is
provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection
method.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the
highest or lowest sector independently of whether the sector was protected or unprotected using the method
described in Advanced Sector Protection/Unprotection on page 42.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to
be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether
they were last protected or unprotected.
The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal pull-up;
when unconnected, WP# is set at VIH.
Note
If WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased.
See Table 11.6 on page 55 for details.
8.6.2
Low V Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down.
CC
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO
.
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8.6.3
8.6.4
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9. Power Conservation Modes
9.1
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#
inputs are both held at VCC 0.3 V. The device requires standard access time (tCE) for read access, before it
is ready to read data. If the device is deselected during erasure or programming, the device draws active
current until the operation is completed. ICC4 in “DC Characteristics” represents the standby current
specification
9.2
9.3
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. ICC6 in Section 11.6
represents the automatic sleep mode current specification.
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at VSS 0.3 V, the device draws ICC reset current (ICC5). If RESET# is held at VIL but
not within VSS 0.3 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high
impedance state. (With the exception of RY/BY#.)
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10. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification
through an Electronic Serial Number (ESN). The Secured Silicon Sector is 128 words in length and all
Secured Silicon reads outside of the 128-word address range returns invalid data. The Secured Silicon
Sector Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Secured Silicon
Sector is locked when shipped from the factory.
Please note the following general conditions:
On power-up, or following a hardware reset, the device reverts to sending commands to the normal
address space.
Reads outside of sector SA0 return memory array data.
Sector SA0 is remapped from memory array to Secured Silicon Sector array.
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command
must be issued to exit Secured Silicon Sector Mode.
The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or
Embedded Erase algorithm.
The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Table 10.1 Secured Silicon Sector Addresses
Secured Silicon Sector
Address Range
000000h–000007h
000008h–00007Fh
Customer Lockable ESN Factory Locked
ExpressFlash Factory Locked
ESN or determined by customer
Determined by customer
ESN
Determined by
customer
Unavailable
10.1 Factory Locked Secured Silicon Sector
The Factory Locked Secured Silicon Sector is always protected when shipped from the factory and has the
Secured Silicon Sector Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to the field.
These devices are available pre-programmed with one of the following:
A random, 8 Word secure ESN only within the Secured Silicon Sector (at addresses 000000H - 000007H)
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services. Spansion
programs the customer's code, with or without the random ESN. The devices are then shipped from the
Spansion factory with the Secured Silicon Sector permanently locked. Contact your local representative for
details on using Spansion programming services.
10.2 Customer Lockable Secured Silicon Sector
The Customer Lockable Secured Silicon Sector is always shipped unprotected (DQ7 set to “0”), allowing
customers to utilize that sector in any manner they choose. If the security feature is not required, the Secured
Silicon Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Secured Silicon Sector area is protected, the Secured Silicon Sector Indicator Bit is permanently
set to “0.”
The Secured Silicon Sector can be read any number of times, but can be programmed and locked only
once. The Secured Silicon Sector lock must be used with caution as once locked, there is no procedure
available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when the Secured
Silicon Sector is enabled.
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S29GL-P MirrorBit® Flash Family
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Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon
Sector Region command sequence which return the device to the memory array at sector 0.
10.3 Secured Silicon Sector Entry/Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon
Sector command sequence. The device continues to access the Secured Silicon Sector region until the
system issues the four-cycle Exit Secured Silicon Sector command sequence.
See Command Definitions on page 67 [Secured Silicon Sector Command Table, Appendix
Table 12.1 on page 68 through Table 12.4 on page 71 for address and data requirements for both command
sequences.
The Secured Silicon Sector Entry Command allows the following commands to be executed
Read customer and factory Secured Silicon areas
Program the customer Secured Silicon Sector
After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured
Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode
of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until
power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program,
and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available soon on
www.spansion.com) for general information on Spansion Flash memory software development guidelines.
Table 10.2 Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Data
00AAh
0055h
0088h
Unlock Cycle 1
Unlock Cycle 2
Entry Cycle
Write
Write
Note
Base = Base Address.
/* Example: SecSi Sector Entry Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write unlock cycle 1
*/
*/
*/
/* write unlock cycle 2
/* write Secsi Sector Entry Cmd
Table 10.3 Secured Silicon Sector Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Word Address
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Word Address
Data
00AAh
Unlock Cycle 1
Unlock Cycle 2
Program Setup
Program
Write
0055h
Write
00A0h
Write
Data Word
Note
Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
November 8, 2007 S29GL-P_00_A7
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Table 10.4 Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Cycle
Operation
Write
Byte Address
Base + AAAh
Base + 555h
Base + AAAh
Base + AAAh
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 000h
Data
00AAh
0055h
0090h
0000h
Unlock Cycle 1
Unlock Cycle 2
Exit Cycle 3
Exit Cycle 4
Write
Write
Write
Note
Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write unlock cycle 1
/* write unlock cycle 2
*/
*/
/* write SecSi Sector Exit cycle 3 */
/* write SecSi Sector Exit cycle 4 */
11. Electrical Specifications
11.1 Absolute Maximum Ratings
Description
Rating
Storage Temperature, Plastic Packages
Ambient Temperature with Power Applied
–65°C to +150°C
–65°C to +125°C
All Inputs and I/Os except as noted below
(Note 1)
–0.5 V to VCC + 0.5 V
VCC (Note 1)
VIO
–0.5 V to +4.0 V
–0.5V to +4.0V
–0.5 V to +12.5 V
200 mA
Voltage with Respect to Ground
A9 and ACC (Note 2)
Output Short Circuit Current (Note 3)
Notes
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot V to –2.0 V for periods of up
SS
to 20 ns. See Figure 11.1. Maximum DC voltage on input or I/Os is V + 0.5 V. During voltage transitions inputs or I/Os may overshoot to
CC
V
+ 2.0 V for periods up to 20 ns. See Figure 11.2.
CC
2. Minimum DC input voltage on pins A9 and ACC is -0.5V. During voltage transitions, A9 and ACC may overshoot V to –2.0 V for periods
SS
of up to 20 ns. See Figure 11.1. Maximum DC voltage on pins A9 and ACC is +12.5 V, which may overshoot to 14.0 V for periods up to 20
ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0 .8 V
–0 .5 V
–2 .0 V
20 ns
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S29GL-P MirrorBit® Flash Family
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Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
+2.0 V
20 ns
20 ns
11.2 Operating Ranges
Specifications
Range
–40°C to +85°C
Ambient Temperature (TA), Industrial (I) Device
+2.7 V to 3.6 V or
+3.0 V to 3.6 V
Supply Voltages
VCC
VIO
VIO Supply Voltages
+1.65 V to VCC
Notes
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
2. See also Ordering Information on page 9.
3. For valid V /V range combinations, see Ordering Information on page 9. The I/Os do not operate at 3 V when V = 1.8 V.
CC IO
IO
11.3 Test Conditions
Figure 11.3 Test Setup
Device
Under
Test
CL
November 8, 2007 S29GL-P_00_A7
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D a t a S h e e t ( P r e l i m i n a r y )
Table 11.1 Test Specifications
Test Condition
All Speeds
1 TTL gate
Unit
Output Load
Output Load Capacitance, CL
(including jig capacitance)
30
5
pF
Input Rise and Fall Times
ns
V
Input Pulse Levels
0.0–VIO
0.5VIO
0.5 VIO
Input timing measurement reference levels (See Note)
Output timing measurement reference levels
Note
V
V
If V < V , the reference level is 0.5 V .
IO
CC
IO
11.4 Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
11.5 Switching Waveforms
Figure 11.4 Input Waveforms and Measurement Levels
VIO
0.5 VIO
Input
Measurement Level
0.5 VIO
Output
0.0 V
Note
If V < V , the input measurement reference level is 0.5 V .
IO
IO
CC
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11.6 DC Characteristics
Table 11.2 S29GL-P DC Characteristics (CMOS Compatible)
Parameter
Symbol
Parameter Description
(Notes)
Test Conditions
IN = VSS to VCC
Min
Typ
Max
2.0
1.0
35
Unit
WP/ACC
Others
µA
V
ILI
Input Load Current (1)
VCC = VCC max
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC = VCC max; A9 = 12.5 V
µA
µA
VOUT = VSS to VCC , VCC = VCC max
1.0
20
CE# = VIL, OE# = VIH, VCC = VCCmax, f = 1 MHz
CE# = VIL, OE# = VIH, VCC = VCCmax, f = 5 MHz
CE# = VIL, OE# = VIH, VCC = VCCmax, f = 10 MHz
CE# = VIL, OE# = VIH
6
30
60
0.2
1
ICC1
VCC Active Read Current (1)
55
mA
110
10
IIO2
VIO Non-Active Output
mA
mA
CE# = VIL, OE# = VIH, VCC = VCCmax, f = 10 MHz
CE# = VIL, OE# = VIH, VCC = VCCmax, f = 33 MHz
10
ICC2
VCC Intra-Page Read Current (1)
5
20
VCC Active Erase/
Program Current (2, 3)
ICC3
CE# = VIL, OE# = VIH, VCC = VCCmax
50
90
mA
µA
CE#, RESET# = VCC 0.3 V,
OE# = VIH, VCC = VCCmax
ICC4
VCC Standby Current
1
5
VIL = VSS + 0.3 V/-0.1V,
V
CC = VCCmax; VIL = VSS + 0.3 V/-0.1V,
ICC5
ICC6
VCC Reset Current
250
1
500
5
µA
µA
RESET# = VSS 0.3 V
V
V
CC = VCCmax, VIH = VCC 0.3 V,
Automatic Sleep Mode (4)
IL = VSS + 0.3 V/-0.1V, WP#/ACC = VIH
WP#/ACC
pin
10
50
20
ACC Accelerated
Program Current
CE# = VIL, OE# = VIH,
VCC = VCCmax, WP#/ACC = VHH
IACC
mA
VCC pin
80
VIL
VIH
Input Low Voltage (5)
Input High Voltage (5)
–0.1
0.7 x VIO
11.5
0.3 x VIO
VIO + 0.3
12.5
V
V
V
VHH
Voltage for Program Acceleration VCC = 2.7 –3.6 V
Voltage for Autoselect and
VCC = 2.7 –3.6 V
VID
11.5
12.5
V
Temporary Sector Unprotect
VOL
VOH
VLKO
Output Low Voltage (5)
IOL = 100 µA
IOH = -100 µA
0.15 x VIO
V
V
V
Output High Voltage (5)
Low VCC Lock-Out Voltage (3)
0.85 x VIO
2.3
2.5
Notes
1. The I current listed is typically less than 2 mA/MHz, with OE# at V
.
CC
IH
2.
3. Not 100% tested.
4. Automatic sleep mode enables the lower power mode when addresses remain stable tor t
I
active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
CC
+ 30 ns.
ACC
5.
6.
V
V
= 1.65–3.6 V
IO
= 3 V and V = 3V or 1.8V. When V is at 1.8V, I/O pins cannot operate at 3V.
CC
IO
IO
November 8, 2007 S29GL-P_00_A7
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11.7 AC Characteristics
11.7.1
S29GL-P Read-Only Operations
Table 11.3 S29GL-P Read-Only Operations
Parameter
Speed Options
Description
(Notes)
JEDEC
Std.
Test Setup
IO = VCC = 2.7 V
VIO = 1.65 V to VCC
90
100 110 120 130 Unit
V
–
100 110 120
–
,
tAVAV
tRC
Read Cycle Time
Min
Max
Max
–
–
110 120 130
ns
ns
ns
VCC = 3 V
VIO = VCC = 3.0 V
90
–
100 110
–
–
–
V
IO = VCC = 2.7 V
100 110 120
VIO = 1.65 V to VCC
,
tAVQV
tACC Address to Output Delay (1)
–
–
110 120 130
VCC = 3 V
VIO = VCC = 3.0 V
90
–
100 110
–
–
–
V
IO = VCC = 2.7 V
100 110 120
VIO = 1.65 V to VCC
,
tELQV
tCE
Chip Enable to Output Delay (2)
–
–
110 120 130
VCC = 3 V
VIO = VCC = 3.0 V
90
100 110
–
–
tPACC Page Access Time
Max
Max
Max
Max
25
25
20
20
ns
ns
ns
ns
tGLQV
tEHQZ
tGHQZ
tOE
tDF
tDF
Output Enable to Output Delay
Chip Enable to Output High Z (3)
Output Enable to Output High Z (3)
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
tAXQX
tOH
Min
Min
Min
Min
0
0
ns
ns
ns
ns
Read
Output Enable Hold Time
tOEH
Toggle and
(3)
10
35
Data# Polling
tCEH Chip Enable Hold Time
Read
Notes
1. CE#, OE# = V
IL
2. OE# = V
IL
3. Not 100% tested.
4. See Figure 11.3 and Table 11.1 for test specifications.
5. Unless otherwise indicated, AC specifications for 110 ns speed options are tested with V = V = 2.7 V. AC specifications for 110 ns speed options are tested
IO
CC
with V = 1.8 V and V = 3.0 V.
IO
CC
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 11.5 Read Operation Timings
tRC
Addresses Stable
Addresses
CE#
tACC
tCEH
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 11.6 Page Read Timings
Same Page
Amax
:
A3
A2
:
A0
Ad
Aa
Ab
tPACC
Ac
tPACC
(See Note)
tPACC
tACC
Data Bus
Qa
Qb
Qc
Qd
CE#
OE#
Note
Figure 11.6 shows word mode. Addresses are A2:A-1 for byte mode.
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11.7.2
Hardware Reset (RESET#)
Table 11.4 Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Speed
Unit
RESET# Pin Low (During Embedded Algorithms) to
Read Mode or Write mode
tReady
Min
Min
35
µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode or Write mode
tReady
35
µs
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
35
200
10
0
µs
ns
µs
ns
Reset High Time Before Read
RESET# Low to Standby Mode
RY/BY# Recovery Time
Figure 11.7 Reset Timings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
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D a t a S h e e t ( P r e l i m i n a r y )
Table 11.5 Power-up Sequence Timings
Parameter
Description
Speed
Unit
Reset Low Time from rising edge of VCC (or last Reset pulse) to
rising edge of RESET#
tVCS
Min
35
µs
Reset Low Time from rising edge of VIO (or last Reset pulse) to
rising edge of RESET#
tVIOS
tRH
Min
Min
35
µs
ns
Reset High Time before Read
200
Notes
1.
V
< V + 200 mV.
CC
IO
2.
V
and V ramp must be synchronized during power up.
IO
CC
3. If RESET# is not stable for t
or t
:
VCS
VIOS
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4.
V
maximum power-up current (RST=V ) is 20 mA.
C
C
I
L
Figure 11.8 Power-up Sequence Timings
V
CC
V
V
min
min
CC
V
IO
IO
t
RH
CE#
t
VIOS
t
VCS
RESET#
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11.7.3
S29GL-P Erase and Program Operations
Table 11.6 S29GL-P Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
tASO
tAH
tAHT
tDS
Description
90
100
100
110
110
0
120 130 Unit
120 130
Write Cycle Time (Note 1)
Min
Min
Min
Min
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tAVWL
Address Setup Time
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
45
0
tWLAX
Address Hold Time From CE# or OE# high during toggle bit polling Min
tDVWH
tWHDX
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
30
0
tDH
tCEPH CE# High during toggle bit polling
20
20
0
tOEPH Output Enable High during toggle bit polling
tGHWL Read Recovery Time Before Write (OE# High to WE# Low)
tGHWL
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
0
CE# Hold Time
0
tWP
Write Pulse Width
35
30
480
15
tWPH
Write Pulse Width High
Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation (Notes 2, 4) Per Word
Accelerated Effective Write Buffer Program Operation
(Notes 2, 4)
tWHWH1 tWHWH1
Per Word
Typ
13.5
µs
Program Operation (Note 2)
Word
Word
Typ
Typ
Typ
Min
Min
Max
Max
60
54
µs
µs
Accelerated Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
0.5
250
35
sec
ns
tVHH
tVCS
VHH Rise and Fall Time (Note 1)
VCC Setup Time (Note 1)
µs
tBUSY Erase/Program Valid to RY/BY# Delay
tSEA Sector Erase Timeout
90
ns
50
µs
Notes
1. Not 100% tested.
2. See Section 11.6 for more information.
3. For 1–32 words/1–64 bytes programmed.
4. Effective write buffer specification is based upon a 32-word/64-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 110 ns speed option are tested with
V
= V = 2.7 V. AC specifications for 110 ns speed options are tested with V = 1.8 V and V = 3.0 V.
CC IO CC
IO
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 11.9 Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
2. Illustration shows device in word mode.
Figure 11.10 Accelerated Program Timing Diagram
VHH
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Notes
1. Not 100% tested.
2. CE#, OE# = V
IL
3. OE# = V
IL
4. See Figure 11.3 and Table 11.1 for test specifications.
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Figure 11.11 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 36.)
2. These waveforms are for the word mode
Figure 11.12 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ6–DQ0
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Notes
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2.
t
for data polling is 45 ns when V = 1.65 to 2.7 V and is 35 ns when V = 2.7 to 3.6 V
OE
IO
IO
3. CE# does not need to go high between status bit reads
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Figure 11.13 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
CE#
tAHT
tASO
tCEPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ2 and DQ6
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note
A = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
CE# does not need to go high between status bit reads
Figure 11.14 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note
DQ2 toggles only when read at an address within an erase-suspended sector. The system can use OE# or CE# to toggle DQ2 and DQ6.
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11.7.4
S29GL-P Alternate CE# Controlled Erase and Program Operations
Table 11.7 S29GL-P Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
Description
JEDEC
tAVAV
Std.
tWC
tAS
tASO
tAH
tAHT
tDS
(Notes)
90
Min 90
Min
100
110
110
0
120 130 Unit
Write Cycle Time (Note 1)
100
120 130
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVWL
Address Setup Time
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
Min
15
45
0
tELAX
Min
Address Hold Time From CE# or OE# high during toggle bit polling
Data Setup Time
Min
tDVEH
tEHDX
Min
30
0
tDH
Data Hold Time
Min
tCEPH
CE# High during toggle bit polling
Min
20
20
tOEPH OE# High during toggle bit polling
Min
Read Recovery Time Before Write
tGHEL
tGHEL
Min
0
ns
(OE# High to WE# Low)
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
0
0
ns
ns
ns
ns
µs
µs
CE# Pulse Width
CE# Pulse Width High
35
30
480
15
tCPH
tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3)
Effective Write Buffer Program Operation (Notes 2, 4)
Per Word Typ
Per Word Typ
Effective Accelerated Write Buffer Program Operation
(Notes 2, 4)
13.5
µs
Program Operation (Note 2)
Accelerated Programming Operation (Note 2)
tWHWH2 tWHWH2 Sector Erase Operation (Note 2)
Word
Word
Typ
Typ
Typ
60
54
µs
µs
0.5
sec
Notes
1. Not 100% tested.
2. See AC Characteristics on page 56 for more information.
3. For 1–32 words/1–64 bytes programmed.
4. Effective write buffer specification is based upon a 32-word/64-byte write buffer operation.
5. Unless otherwise indicated, AC specifications are tested with V = 1.8 V and V = 3.0 V.
IO
CC
64
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Figure 11.15 Alternate CE# Controlled Write (Erase/Program) Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. Figure 11.15 indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Waveforms are for the word mode.
is the data written to the device.
OUT
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
65
D a t a S h e e t ( P r e l i m i n a r y )
11.7.5
Erase And Programming Performance
Table 11.8 Erase And Programming Performance
Typ
(Note 1)
Max
(Note 2)
Parameter
Unit
Comments
Sector Erase Time
Chip Erase Time
0.5
64
3.5
256
sec
S29GL128P
S29GL256P
S29GL512P
S29GL01GP
Excludes 00h programming
prior to erasure (Note 5)
128
256
512
480
512
sec
1024
2048
Total Write Buffer Time (Note 3)
µs
µs
Total Accelerated Write Buffer Programming Time
(Note 3)
432
Excludes system level
overhead (Note 6)
S29GL128P
123
246
492
984
S29GL256P
Chip Program Time (Note 4)
S29GL512P
sec
S29GL01GP
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V V , 10,000 cycles, checkerboard pattern.
CC
2. Under worst case conditions of -40°C, V = 3.0 V, 100,000 cycles.
CC
3. Effective write buffer specification is based upon a 32-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum
program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 12.1–12.4.
11.7.6
TSOP Pin and BGA Package Capacitance
Table 11.9 Package Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN = 0
Typ
6
Max
10
Unit
pF
CIN
COUT
CIN2
Output Capacitance
Control Pin Capacitance
Separated Control Pin
Separated Control Pin
VOUT = 0
VIN = 0
10
8
12
pF
10
pF
RESET#, WP#/ACC
CE#
V
IN = 0
42
22
45
pF
VIN = 0
25
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
66
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
12. Appendix
This section contains information relating to software control or interfacing with the Flash device. For
additional information and assistance regarding software, see Section 5. For the latest information, explore
the Spansion web site at www.spansion.com.
12.1 Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Tables 12.1–12.4 define the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence can place the device in an unknown state. A reset
command is then required to return the device to reading array data.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
67
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.1 S29GL-P Memory Array Command Definitions, x16
Bus Cycles (Notes 1–5)
First
Addr
Second
Third
Fourth
Fifth
Addr
Sixth
Command (Notes)
Data
RD
F0
Addr
Data
Addr
Data
Addr
Data
Data
Addr
Data
Read (6)
Reset (7)
1
1
4
4
4
RA
XXX
555
555
555
Manufacturer ID
AA
AA
AA
2AA
2AA
2AA
55
55
55
555
555
555
90
90
90
X00
X01
01
Device ID (8)
227E
(10)
X0E
(8)
X0F
(8)
Sector Protect Verify (10)
[SA]X02
Secure Device Verify (11)
4
555
AA
2AA
55
555
90
X03
(11)
CFI Query (12)
1
4
3
1
3
3
2
2
2
2
6
6
1
1
3
4
55
98
AA
AA
29
Program
555
555
SA
2AA
2AA
55
55
555
SA
A0
25
PA
SA
PD
Write to Buffer
WC
WBL
PD
WBL
PD
Program Buffer to Flash (Confirm)
Write-to-Buffer-Abort Reset (13)
Enter
555
555
XXX
XXX
XXX
XXX
555
555
XXX
XXX
555
555
AA
AA
A0
80
2AA
2AA
PA
55
55
PD
30
10
00
55
55
555
555
F0
20
Program (14)
Sector Erase (14)
SA
Chip Erase (14)
80
XXX
XXX
2AA
2AA
Reset (15)
90
Chip Erase
AA
AA
B0
30
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (16)
Erase Resume/Program Resume (17)
Secured Silicon Sector Entry
Secured Silicon Sector Exit (18)
AA
AA
2AA
2AA
55
55
555
555
88
90
XX
00
Legend
X = Don’t care
RA = Address of the memory to be read.
PD = Data to be programmed at location PA. Data latches on the rising edge
of the WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or erased.
PA = Address of the memory location to be programmed. Addresses latch on
the falling edge of the WE# or CE# pulse, whichever happens later.
Address bits A
–A16 uniquely select any sector.
max
WBL = Write Buffer Location. The address must be within the same write
buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
Notes
1. See Table 7.1 on page 19 for description of bus operations.
11. The data value for DQ7 is “1” for a serialized, protected Secured Silicon
Sector region and “0” for an unserialized, unprotected region. See
Table 7.3 on page 22 for data and definitions.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
12. Command is valid when device is ready to read array data or when device
is in autoselect mode.
5. Address bits A
:A16 are don’t cares for unlock and command cycles,
MAX
13. Command sequence returns device to reading array after being placed in
a Write-to-Buffer-Abort state. Full command sequence is required if
resetting out of abort while in Unlock Bypass mode.
unless SA or PA required. (A
is the Highest Address pin.).
MAX
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when
device is in the autoselect mode, or if DQ5 goes high (while the device is
providing status data).
14. The Unlock-Bypass command is required prior to the Unlock-Bypass-
Program command.
15. The Unlock-Bypass-Reset command is required to return to reading array
data when the device is in the unlock bypass mode.
8. See Table 7.2 on page 22 for device ID values and definitions.
9. The fourth, fifth, and sixth cycles of the autoselect command sequence are
read cycles.
16. The system can read and program/program suspend in non-erasing
sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
10. The data is 00h for an unprotected sector and 01h for a protected sector.
See Autoselect on page 21 for more information. This is same as PPB
Status Read except that the protect and unprotect statuses are inverted
here.
17. The Erase Resume/Program Resume command is valid only during the
Erase Suspend/Program Suspend modes.
18. The Exit command returns the device to reading the array.
68
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.2 S29GL-P Sector Protection Command Definitions, x16
Bus Cycles (Notes 1–5)
First/Seventh
Second
Third
Fourth
Fifth
Data
Sixth
Command (Notes)
Command Set Entry
Program (6)
Addr
555
XXX
77h
XXX
555
XXX
00
Data
AA
Addr
Data
55
Addr
Data
Addr
Data
Addr
Addr
Data
3
2
1
2
3
2
4
2AA
XXX
555
40
A0
DATA
Read (6)
DATA
90
Command Set Exit (7, 8)
Command Set Entry
Password Program (9)
Password Read (10)
XXX
2AA
00
55
AA
555
60
A0
PWA x PWD x
PWD0
25
01
00
PWD 1
03
02
00
PWD 2
PWD 0
03
01
PWD 3
PWD 1
00
02
PWD 2
03
PWD 3
Password Unlock (10)
7
00
29
Command Set Exit (7, 8)
PPB Command Set Entry
PPB Program (11, 12)
All PPB Erase (13)
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
XXX
555
XXX
XXX
SA
90
XXX
2AA
SA
00
55
00
30
AA
555
C0
A0
80
00
PPB Status Read (12)
PPB Command Set Exit (7, 8)
PPB Lock Command Set Entry
PPB Lock Set (12)
RD (0)
90
XXX
555
XXX
XXX
XXX
555
XXX
XXX
SA
XXX
2AA
XXX
00
55
00
AA
555
555
50
E0
A0
PPB Lock Status Read (12)
PPB Lock Command Set Exit (7, 8)
DYB Command Set Entry
DYB Set (11, 12)
RD (0)
90
XXX
2AA
SA
00
55
00
01
AA
A0
DYB Clear (12)
A0
SA
DYB Status Read (12)
DYB Command Set Exit (7, 8)
RD (0)
90
XXX
XXX
00
Legend
X = Don’t care
PWD = Password word0, word1, word2, and word3.
x
RD(0) = Read data.
SA = Sector Address. Address bits A
PWD = Password
Notes
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection
Mode Lock Bit.
–A16 uniquely select any sector.
max
1. See Table 7.1 on page 19 for description of bus operations.
7. The Exit command returns the device to reading the array.
2. All values are in hexadecimal.
8. If any Command Set Entry command was written, an Exit command must
be issued to reset the device into read mode.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
9. For PWDx, only one portion of the password can be programmed per each
“A0” command.
5. Address bits A
:A16 are don’t cares for unlock and command cycles,
MAX
10. Note that the password portion can be entered or read in any order as long
as the entire 64-bit password is entered or read.
unless SA or PA required. (A
is the Highest Address pin.)
MAX
6. All Lock Register bits are one-time programmable. Program state = “0” and
the erase state = “1.” The Persistent Protection Mode Lock Bit and the
Password Protection Mode Lock Bit cannot be programmed at the same
time or the Lock Register Bits Program operation aborts and returns the
device to read mode. Lock Register bits that are reserved for future use
default to “1’s.” The Lock Register is shipped out as “FFFF’s” before Lock
Register Bit program execution.
11. If ACC = V , sector protection matches when ACC = V
HH
.
IH
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before
erasure.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
69
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.3 S29GL-P Memory Array Command Definitions, x8
Bus Cycles (Notes 1–5)
First
Addr
Second
Third
Fourth
Fifth
Sixth
Command (Notes)
Data
RD
F0
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (6)
Reset (7)
1
1
4
4
4
RA
XXX
AAA
AAA
AAA
Manufacturer ID
AA
AA
AA
555
555
555
55
55
55
AAA
AAA
AAA
90
90
90
X00
X02
01
Device ID (8)
XX7E
(10)
X1C
(8)
X1E
(8)
Sector Protect Verify (10)
[SA]X04
Secure Device Verify (11)
4
AAA
AA
555
55
AAA
90
X06
(11)
CFI Query (12)
1
4
3
1
3
3
2
2
2
2
6
6
1
1
3
4
AA
98
AA
AA
29
Program
AAA
AAA
SA
555
555
55
55
AAA
SA
A0
25
PA
SA
PD
Write to Buffer
WC
WBL
PD
WBL
PD
Program Buffer to Flash (confirm)
Write-to-Buffer-Abort Reset (13)
Enter
AAA
AAA
XXX
XXX
XXX
XXX
AAA
AAA
XXX
XXX
AAA
AAA
AA
AA
A0
80
555
555
PA
55
55
PD
30
10
00
55
55
555
F0
20
AAA
Program (14)
Sector Erase (14)
SA
Chip Erase (14)
80
XXX
XXX
555
555
Reset (15)
90
Chip Erase
AA
AA
B0
30
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
SA
10
30
Sector Erase
Erase Suspend/Program Suspend (16)
Erase Resume/Program Resume (17)
Secured Silicon Sector Entry
Secured Silicon Sector Exit (18)
AA
AA
555
555
55
55
AAA
AAA
88
90
XX
00
Legend
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising edge
of the WE# or CE# pulse, whichever happens first.
RA = Address of the memory to be read.
SA = Address of the sector to be verified (in autoselect mode) or erased.
RD = Data read from location RA during read operation.
Address bits A
–A16 uniquely select any sector.
max
PA = Address of the memory location to be programmed. Addresses latch on
the falling edge of the WE# or CE# pulse, whichever happens later.
WBL = Write Buffer Location. The address must be within the same write
buffer page as PA.
WC = Word Count is the number of write buffer locations to load minus 1.
Notes
1. See Table 7.1 on page 19 for description of bus operations.
11. The data value for DQ7 is “1” for a serialized, protected Secured Silicon
Sector region and “0” for an unserialized, unprotected region. See
Table 7.3 on page 22 for data and definitions.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
12. Command is valid when device is ready to read array data or when device
is in autoselect mode.
5. Address bits A
:A16 are don’t cares for unlock and command cycles,
MAX
13. Command sequence returns device to reading array after being placed in
a Write-to-Buffer-Abort state. Full command sequence is required if
resetting out of abort while in Unlock Bypass mode.
unless SA or PA required. (A
is the Highest Address pin.).
MAX
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when
device is in the autoselect mode, or if DQ5 goes high (while the device is
providing status data).
14. The Unlock-Bypass command is required prior to the Unlock-Bypass-
Program command.
15. The Unlock-Bypass-Reset command is required to return to reading array
data when the device is in the unlock bypass mode.
8. See Table 7.2 on page 22 for device ID values and definitions.
9. The fourth, fifth, and sixth cycles of the autoselect command sequence are
read cycles.
16. The system can read and program/program suspend in non-erasing
sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
10. The data is 00h for an unprotected sector and 01h for a protected sector.
See Autoselect on page 21 for more information. This is same as PPB
Status Read except that the protect and unprotect statuses are inverted
here.
17. The Erase Resume/Program Resume command is valid only during the
Erase Suspend/Program Suspend modes.
18. The Exit command returns the device to reading the array.
70
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.4 S29GL-P Sector Protection Command Definitions, x8
Bus Cycles (Notes 1–5)
First/Seventh
Second/Eighth
Third
Fourth
Fifth
Sixth
Command (Notes)
Command Set Entry
Bits Program (6)
Addr
AAA
XXX
00
Data
AA
Addr
555
Data
55
Addr
Data
Addr
Data
Addr
Data
Addr
Data
3
2
1
2
3
2
AAA
40
A0
XXX
DATA
Read (6)
DATA
90
Command Set Exit (7, 8)
Command Set Entry
Password Program (9)
XXX
AAA
XXX
00
XXX
555
00
55
AA
AAA
02
60
A0
PWA x PWD x
PWD0
PWD 6
25
01
07
PWD 1
PWD 7
03
PWD 2
03
PWD 3
04
PWD 4
05
03
PWD 5
PWD 3
Password Read (10)
Password Unlock (10)
8
06
00
00
00
06
PWD 0
PWD 6
01
07
PWD 1
PWD 7
02
00
PWD 2
29
11
04
PWD 4
90
05
PWD 5
00
Command Set Exit (7, 8)
PPB Command Set Entry
PPB Program (11, 12)
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
XXX
AAA
XXX
XXX
SA
XXX
55
AA
55
AAA
C0
A0
SA
00
00
All PPB Erase (13)
80
30
PPB Status Read (12)
RD(0)
90
PPB Command Set Exit (7, 8)
PPB Lock Command Set Entry
PPB Lock Bit Set (12)
XXX
AAA
XXX
XXX
XXX
AAA
XXX
XXX
SA
XXX
555
00
55
00
AA
AAA
AAA
50
E0
A0
XXX
PPB Lock Status Read (12)
PPB Lock Command Set Exit (7, 8)
DYB Command Set Entry
DYB Set (11, 12)
RD(0)
90
XXX
555
SA
00
55
00
01
AA
A0
DYB Clear (12)
A0
SA
DYB Status Read (12)
RD(0)
90
DYB Command Set Exit (7, 8)
XXX
XXX
00
Legend
X = Don’t care
PWD = Password word0, word1, word2, and word3.
x
RD(0) = Read data.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection
Mode Lock Bit.
SA = Sector Address. Address bits A
PWD = Password
–A16 uniquely select any sector.
max
Notes
1. See Table 7.1 on page 19 for description of bus operations.
7. The Exit command returns the device to reading the array.
2. All values are in hexadecimal.
8. If any Command Set Entry command was written, an Exit command must
be issued to reset the device into read mode.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
9. For PWDx, only one portion of the password can be programmed per each
“A0” command.
5. Address bits A
:A16 are don’t cares for unlock and command cycles,
MAX
10. Note that the password portion can be entered or read in any order as long
as the entire 64-bit password is entered or read.
unless SA or PA required. (A
is the Highest Address pin.)
MAX
6. All Lock Register bits are one-time programmable. Program state = “0” and
the erase state = “1.” The Persistent Protection Mode Lock Bit and the
Password Protection Mode Lock Bit cannot be programmed at the same
time or the Lock Register Bits Program operation aborts and returns the
device to read mode. Lock Register bits that are reserved for future use
default to “1’s.” The Lock Register is shipped out as “FFFF’s” before Lock
Register Bit program execution.
11. If ACC = V , sector protection matches when ACC = V
HH
.
IH
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before
erasure.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
71
D a t a S h e e t ( P r e l i m i n a r y )
12.2 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h any time the device is ready to read array data. The system can read CFI information at the addresses
given in Tables 12.6–12.8). All reads outside of the CFI address range, returns non-valid data. Reads from
other sectors are allowed, writes are not. To terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12.6–12.8.
The system must write the reset command to return the device to reading array data.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion
Low Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash
memory software development guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)base_addr + 0x55 ) = 0x0098;
/* write CFI entry command
/* write cfi exit command
*/
/* Example: CFI Exit command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
*/
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-A and
JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
Table 12.5 CFI Query Identification String
Addresses
(x16)
Addresses
(x8)
Data
Description
Query Unique ASCII string “QRY”
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
72
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.6 System Interface String
Addresses (x16)
Addresses (x8)
Data
Description
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
36h
38h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0027h
0036h
0000h
0000h
0006h
0006h
0009h
0013h
0003h
0005h
0003h
0002h
VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 mV
VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 mV
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 12.7 Device Geometry Definition
Addresses (x16)
Addresses (x8)
Data
Description
001Bh
001Ah
Device Size = 2N byte
27h
4Eh
0019h
0018h
1B = 1 Gb, 1A= 512 Mb, 19 = 256 Mb, 18 = 128 Mb
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0006h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device (01h = uniform device, 02h = boot
device)
2Ch
58h
0001h
Erase Block Region 1 Information
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
(refer to the CFI specification or CFI publication 100)
00FFh, 0003h, 0000h, 0002h =1 Gb
00FFh, 0001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
73
D a t a S h e e t ( P r e l i m i n a r y )
Table 12.8 Primary Vendor-Specific Extended Query
Addresses (x16)
Addresses (x8)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0014h
Process Technology (Bits 7-2) 0101b = 90 nm MirrorBit
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0001h
0000h
0008h
0000h
0000h
0002h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
Simultaneous Operation
00 = Not Supported, X = Number of Sectors
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
00B5h
00C5h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
WP# Protection
4Fh
50h
9Eh
A0h
00xxh
0001h
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP#
protect
Program Suspend
00h = Not Supported, 01h = Supported
74
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
13. Advance Information on S29GL-R 65 nm MirrorBit Hardware
Reset (RESET#) and Power-up Sequence
Table 13.1 Hardware Reset (RESET#)
Parameter
Description
Limit
Min
Time
35
Unit
µs
t
RESET# Low to CE# Low
RESET# Pulse Width
RPH
t
Min
200
200
ns
RP
t
Time between RESET# (high) and CE# (low)
Min
ns
RH
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Figure 13.1 Reset Timings
tRP
RESET#
CE#
tRH
tRPH
Note
The sum of t and t must be equal to or greater than t .
RPH
RP
RH
Table 13.2 Power-Up Sequence Timings
Parameter
Description
Limit
Min
Min
Min
Min
Min
Time
300
300
35
Unit
µs
t
V
V
Setup Time to first access
Setup Time to first access
VCS
CC
t
µs
VIOS
IO
t
RESET# Low to CE# Low
µs
RPH
t
RESET# Pulse Width
200
200
ns
RP
t
Time between RESET# (high) and CE# (low)
ns
RH
Notes
1.
V
< V + 200 mV.
CC
IO
2.
V
and V ramp must be in sync during power-up. If RESET# is not stable for 500 µs, the following conditions may occur: the device
IO
CC
does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V power up current is 20 mA (RESET# =V ).
CC
IL
Figure 13.2 Power-On Reset Timings
VCC
VIO
tVIOS
t VCS
tRP
RESET#
CE#
tRH
tRPH
Note
The sum of t and t must be equal to or greater than t .
RP
RH
RPH
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
75
D a t a S h e e t ( P r e l i m i n a r y )
14. Revision History
Section
Description
Revision A0 (October 29, 2004)
Initial Release.
Revision A1 (October 20, 2005)
Global
Revised all sections of document.
Revision A2 (October 19, 2006)
Revised all sections of document. Reformatted document to new template. Changed speed options
for S29GL01GP.
Global
Revision A3 (November 21, 2006)
AC Characteristics
Erase and Program Operations table: Changed tBUSY to a maximum specification.
Revision A4 (December 18, 2006)
Changed tACC, tCE specifications on 128 Mb, 256 Mb, and 512 Mb devices. Added 90 and 100 ns
speed options.
Global
Write Buffer Programming, Sector
Erase
Write Buffer Programming Operation, Sector Erase Operation figures: Deleted “Wait 4 ms” box from
flowcharts.
Password Protection Method
Read-only Operations table
Lock Register Program Algorithm figure: Deleted “Wait 4 ms” box from flowchart.
Modified tRC, tACC, tCE, tOE specifications.
Program and Erase Operations tables
Changed tDS specification, deleted write cycle time note.
TSOP Pin and BGA Capacitance table Changed all specifications in table.
Revision A5 (May 18, 2007)
Changed data sheet status to Preliminary.
Global
Deleted references to requirement for external WP# pullup.
Performance Characteristics
Hardware Reset
Max. Read Access Times table: Added note.
Deleted note from section.
AC Characteristics
Reset Timings figure: Deleted note.
S29GL-P Sector Protection Command Definitions tables: Changed “Global Non-Volatile Freeze” to
“Global Volatile Freeze”.
Command Definitions tables
DC Characteristics
CMOS Compatible table: Changed ICC1 maximum current for 5 MHz and MHz test conditions.
Page Read Timings figure
Revision A6 (October 23, 2007)
Performance Characteristics
Ordering Information
64-Ball Fortified BGA
56-Pin TSOP
Corrected address range for top waveform.
Changed speed options for S29GL512P
Corrected samples OPN valid combinations; changed speed options for S29GL512P
Clarified ball “D1” connection
Clarified pin “30” connection
Autoselect
Added recommendation statement
Accelerated Program
Persistent Protection Bits
Added recommendation statement
Removed “Erase” from title and flow chart
Sections “Factory Locked Secured Silicon Sector” & “Customer Lockable Secured Silicon Sector”:
clarified shipping options
Secured Silicon Sector
Power-up Sequence Timing
Changed tRH from “Max” to “Min” value
Advance Information on S29GL-R
65 nm MirrorBit Hardware Reset
(RESET#) and Power-up Sequence
Added section
Global
Fixed cross-references that were not live hyperlinks.
Revision A7 (November 8, 2007)
Advance Information on S29GL-R 65
nm MirrorBit Hardware Reset (RESET#) Changed timing specs and waveforms
and Power-up Sequence
76
S29GL-P MirrorBit® Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a S h e e t ( P r e l i m i n a r y )
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2004–2007 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HD-
SIM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational
purposes only and may be trademarks of their respective owners.
November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit® Flash Family
77
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