S29JL064J70BFI003 [SPANSION]
Flash, 4MX16, 70ns, PBGA48, 8.15 X 6.15 MM, LEAD FREE, FBGA-48;
| 型号： | S29JL064J70BFI003 |
| 厂家： | 
SPANSION |
| 描述： | Flash, 4MX16, 70ns, PBGA48, 8.15 X 6.15 MM, LEAD FREE, FBGA-48 |
| 文件： | 总61页 (文件大小：2023K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S29JL064J
64 Megabit (8M x 8-Bit/4M x 16-Bit)
CMOS 3.0 Volt-Only, Simultaneous Read/Write Flash
Memory
S29JL064J Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29JL064J_00
Revision 05
Issue Date December 16, 2011
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V range. Changes may also include those needed to clarify a
IO
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S29JL064J
S29JL064J_00_05 December 16, 2011
S29JL064J
64 Megabit (8M x 8-Bit/4M x 16-Bit)
CMOS 3.0 Volt-Only, Simultaneous Read/Write Flash
Memory
Data Sheet
Distinctive Characteristics
Ultra low power consumption (typical values)
Architectural Advantages
Simultaneous Read/Write operations
– 2 mA active read current at 1 MHz
– 10 mA active read current at 5 MHz
– 200 nA in standby or automatic sleep mode
– Data can be continuously read from one bank while executing
erase/program functions in another bank
Cycling endurance: 1 million cycles per sector typical
Data retention: 20 years typical
– Zero latency between read and write operations
Flexible bank architecture
– Read may occur in any of the three banks not being programmed or
erased
Software Features
Supports Common Flash Memory Interface (CFI)
– Four banks may be grouped by customer to achieve desired bank
divisions
Erase suspend/erase resume
Boot sectors
– Suspends erase operations to read data from, or program data to, a
sector that is not being erased, then resumes the erase operation
– Top and bottom boot sectors in the same device
– Any combination of sectors can be erased
Data# polling and toggle bits
Manufactured on 0.11 µm Process Technology
– Provides a software method of detecting the status of program or
erase operations
Secured Silicon Region: Extra 256-byte sector
– Factory locked and identifiable: 16 bytes available for secure,
random factory Electronic Serial Number; verifiable as factory
locked through autoselect function
Unlock bypass program command
– Reduces overall programming time when issuing multiple program
command sequences
– Customer lockable: One-time programmable only. Once locked,
data cannot be changed
Hardware Features
Ready/Busy# output (RY/BY#)
Zero power operation
– Sophisticated power management circuits reduce power consumed
during inactive periods to nearly zero
– Hardware method for detecting program or erase cycle completion
Hardware reset pin (RESET#)
Compatible with JEDEC standards
– Pinout and software compatible with single-power-supply flash
standard
– Hardware method of resetting the internal state machine to the read
mode
WP#/ACC input pin
– Write protect (WP#) function protects sectors 0, 1, 140, and 141,
regardless of sector protect status
– Acceleration (ACC) function accelerates program timing
Package Options
48-ball Fine-pitch BGA
48-pin TSOP
Sector Protection
– Hardware method to prevent any program or erase operation within
a sector
Performance Characteristics
High performance
– Temporary Sector Unprotect allows changing data in protected
sectors in-system
– Access time as fast as 55 ns
– Program time: 7 µs/word typical using accelerated programming
function
General Description
The S29JL064J is a 64 Mbit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608
bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed
to be programmed in-system with the standard 3.0 volt V supply, and can also be programmed in standard EPROM
CC
programmers. The device is available with an access time of 55, 60, 70 ns and is offered in a 48-ball FBGA or 48-pin TSOP
package. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and
write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and
write functions. Internally generated and regulated voltages are provided for the program and erase operations.
Publication Number S29JL064J_00
Revision 05
Issue Date December 16, 2011
D a t a S h e e t
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
Simultaneous Read/Write Operations with Zero Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 S29JL064J Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.
3.
4.
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
48-pin TSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
48-ball FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.
6.
7.
8.
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Simultaneous Read/Write Operations with Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.10 Boot Sector/Sector Block Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.11 Write Protect (WP#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.12 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.13 Secured Silicon Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.14 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.4 Enter Secured Silicon Region/Exit Secured Silicon Region Command Sequence . . . . . . . . 32
10.5 Byte/Word Program Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.6 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.7 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.8 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.1 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.2 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.3 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.4 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.5 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.6 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.7 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14.1 CMOS Compatible. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14.2 Zero-Power Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
16. Key To Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
17. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
17.1 Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
17.2 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.3 Word/Byte Configuration (BYTE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.4 Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
17.5 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
17.6 Alternate CE# Controlled Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 54
18. Erase and Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
19. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
20. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.1 TS 048—48-Pin Standard TSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
20.2 VBK048—48-Pin FBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
21. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
December 16, 2011 S29JL064J_00_05
S29JL064J
5
D a t a S h e e t
Figures
Figure 4.1
Figure 4.2
Figure 8.1
Figure 8.2
Figure 8.3
48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
48-ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temporary Sector Unprotect Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
In-System Sector Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Secured Silicon Region Protect Verify. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10.1 Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10.2 Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11.1 Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11.2 Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12.2 Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14.1
I
Current vs. Time (Showing Active and Automatic Sleep Currents) . . . . . . . . . . . . . . . . 44
CC1
Figure 14.2 Typical I
vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CC1
Figure 15.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 16.1 Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 17.1 Read Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17.2 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17.3 BYTE# Timings for Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17.4 BYTE# Timings for Write Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17.5 Program Operation Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17.6 Accelerated Program Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17.7 Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17.8 Back-to-back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17.9 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 17.10 Toggle Bit Timings (During Embedded Algorithms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 17.11 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 17.12 Temporary Sector Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings . . . . . . . . . . . . . . . . . . 55
6
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Tables
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Table 8.6
Table 8.7
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 10.1
Table 11.1
Table 15.1
S29JL064J Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
S29JL064J Sector Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bank Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Secured Silicon Region Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
S29JL064J Autoselect Codes, (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection . . . . . . . . . . . 22
WP#/ACC Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
S29JL064J Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Test Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
December 16, 2011 S29JL064J_00_05
S29JL064J
7
D a t a S h e e t
1. Simultaneous Read/Write Operations with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space
into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector
addresses are fixed, system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can improve overall system performance by allowing a host
system to program or erase in one bank, then immediately and simultaneously read from the other bank, with
zero latency. This releases the system from waiting for the completion of program or erase operations.
The S29JL064J is organized as a dual boot device with both top and bottom boot sectors.
Bank
Mbits
Sector Sizes
Eight 8 kbyte/4 kword,
Fifteen 64 kbyte/32 kword
Bank 1
8 Mb
Bank 2
Bank 3
24 Mb
24 Mb
Forty-eight 64 kbyte/32 kword
Forty-eight 64 kbyte/32 kword
Eight 8 kbyte/4 kword,
Fifteen 64 kbyte/32 kword
Bank 4
8 Mb
1.1
S29JL064J Features
The Secured Silicon Region is an extra 256 byte sector capable of being permanently locked by Spansion
or customers. The Secured Silicon Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been
customer locked, and permanently set to 0 if the part has been factory locked. This way, customer lockable
parts can never be used to replace a factory locked part.
Factory locked parts provide several options. The Secured Silicon Region may store a secure, random 16
byte ESN (Electronic Serial Number), customer code (programmed through Spansion programming
services), or both. Customer Lockable parts may utilize the Secured Silicon Region as bonus space, reading
and writing like any other flash sector, or may permanently lock their own code there.
The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash command set
standard. Commands are written to the command register using standard microprocessor write timings.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
The host system can detect whether a program or erase operation is complete by using the device status
bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been
completed, the device automatically returns to the read mode.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low V detector that automatically inhibits write operations
CC
during power transitions. The hardware sector protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is not selected for erasure. True background erase can
thus be achieved. If a read is needed from the Secured Silicon Region (One Time Program area) after an
erase suspend, then the user must use the proper command sequence to enter and exit this region.
The device offers two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode. The system can also place the device into the standby
mode. Power consumption is greatly reduced in both modes.
8
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
2. Product Selector Guide
Part Number
S29JL064J
Speed Option
Standard Voltage Range: V
= 2.7–3.6V
55
55
55
25
60
60
60
25
70
70
70
30
CC
Max Access Time (ns), tACC
CE# Access (ns), tCE
OE# Access (ns), tOE
3. Block Diagram
V
V
CC
OE# BYTE#
SS
Mux
Bank 1
Bank 1 Address
A21–A0
X-Decoder
Bank 2 Address
RY/BY#
Bank 2
X-Decoder
A21–A0
RESET#
STATE
CONTROL
&
Status
WE#
CE#
DQ15–DQ0
COMMAND
REGISTER
BYTE#
Control
Mux
WP#/ACC
DQ0–DQ15
X-Decoder
Bank 3
Bank 3 Address
X-Decoder
Bank 4
A21–A0
Bank 4 Address
Mux
December 16, 2011 S29JL064J_00_05
S29JL064J
9
D a t a S h e e t
4. Connection Diagrams
4.1
48-pin TSOP Package
Figure 4.1 48-Pin Standard TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
9
A20
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
OE#
VSS
CE#
A0
4.2
48-ball FBGA Package
Figure 4.2 48-ball FBGA
A6
B6
C6
D6
E6
F6
G6
H6
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE# RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
A3 B3
C3
D3
E3
F3
G3
H3
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
CE#
OE#
VSS
10
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
5. Pin Description
A21–A0
DQ14–DQ0
DQ15/A-1
CE#
22 Address pins
15 Data Inputs/Outputs (x16-only devices)
DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode)
Chip Enable, Active Low
OE#
Output Enable, Active Low
WE#
Write Enable, Active Low
WP#/ACC
RESET#
BYTE#
Hardware Write Protect/Acceleration Pin
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit mode, Active Low
Ready/Busy Output, Active Low
RY/BY#
3.0 volt-only single power supply (see Product Selector Guide on page 9 for speed options and voltage
supply tolerances)
VCC
VSS
Device Ground
Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the
connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board
(PCB).
NC
Do Not Use. A device internal signal may be connected to the package connector. The connection may be used by
Spansion for test or other purposes and is not intended for connection to any host system signal. Any DNU signal
related function will be inactive when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for PCB signal routing channels.
Do not connect any host system signal to these connections.
DNU
RFU
Reserved for Future Use. No device internal signal is currently connected to the package connector but there is
potential future use for the connector for a signal. It is recommended to not use RFU connectors for PCB routing
channels so that the PCB may take advantage of future enhanced features in compatible footprint devices.
December 16, 2011 S29JL064J_00_05
S29JL064J
11
D a t a S h e e t
6. Logic Symbol
22
A21–A0
16 or 8
DQ15–DQ0
(A-1)
CE#
OE#
WE#
WP#/ACC
RESET#
BYTE#
RY/BY#
12
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
7. Ordering Information
The order number is formed by a valid combination of the following:
S29JL064J
55
T
F
I
00
0
Packing Type
0
= Tray
3
= 13-inch Tape and Reel
Model Number (Additional Ordering Options)
00 = Standard Configuration
Temperature Range
I
= Industrial (–40°C to +85°C)
Package Material Set
F
= Pb-free
H
= Low-halogen, Pb-free
Package Type
B
= Fine-pitch Ball Grid Array (FBGA) Package
T
= Thin Small Outline Package (TSOP) Standard Pinout
Speed Option
55 = 55 ns
60 = 60 ns
70 = 70 ns
Product Family
S29JL064J: 3.0 Volt-only, 64 Mbit (4 M x 16-bit/8 M x 8-bit) Simultaneous Read/
Write Flash Memory Manufactured on 110 nm process technology
S29JL064J Valid Combinations
Device Number/
Description
PackageType
& Material
Speed (ns)
Temperature Range Model Number Packing Type Package Description
TF
TS048
TSOP
FBGA
S29JL064J
55, 60, 70
I
00
0, 3 (1)
BH
VBK048
Note:
1. Packing type 0 is standard. Specify other options as required.
December 16, 2011 S29JL064J_00_05
S29JL064J
13
D a t a S h e e t
8. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Table 8.1 S29JL064J Device Bus Operations
DQ15–DQ8
WP#/
ACC
Addresses
(Note 1)
BYTE#
= VIH
DQ7–
DQ0
Operation
CE#
L
OE#
L
WE#
H
RESET#
BYTE# = VIL
Read
Write
H
H
L/H
AIN
AIN
DOUT
DIN
DOUT
DIN
DQ14–DQ8 = High-Z,
DQ15 = A-1
L
H
L
(Note 3)
VCC
0.3V
±
VCC ±
0.3V
Standby
X
X
L/H
X
High-Z
High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
L
SA, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
L
X
H
H
X
L
L
VID
VID
VID
L/H
X
X
X
X
DIN
DIN
DIN
Sector Unprotect
(Note 2)
SA, A6 = H,
A1 = H, A0 = L
(Note 3)
(Note 3)
Temporary Sector
Unprotect
X
AIN
DIN
High-Z
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 11.5–12.5V
VHH = 9.0 0.5V
X = Don’t Care
SA = Sector Address
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes:
1. Addresses are A21:A0 in word mode (BYTE# = VIH), A21:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Boot Sector/Sector Block
Protection and Unprotection on page 22.
3. If WP#/ACC = VIL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on
whether they were last protected or unprotected using the method described in Boot Sector/Sector Block Protection and Unprotection
on page 22. If WP#/ACC = VHH, all sectors will be unprotected.
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are
active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
14
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
8.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to V . CE# is the power
IL
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V . The BYTE# pin determines whether the device outputs array data in words or bytes.
IH
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for
read access until the command register contents are altered.
Refer to Read-Only Operations on page 46 for timing specifications and to Figure 17.1 on page 46 for the
timing diagram. I
array data.
in DC Characteristics on page 43 represents the active current specification for reading
CC1
8.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to V , and OE# to V .
IL
IH
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or
words. Refer to Word/Byte Configuration on page 14 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Byte/
Word Program Command Sequence on page 32 has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 8.3 on page 20
indicates the address space that each sector occupies. Similarly, a sector address is the address bits
required to uniquely select a sector. Command Definitions on page 31 has details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
The device address space is divided into four banks. A bank address is the address bits required to uniquely
select a bank.
I
in the DC Characteristics on page 43 represents the active current specification for the write mode. AC
CC2
Characteristics on page 46 contains timing specification tables and timing diagrams for write operations.
8.3.1
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at
the factory.
If the system asserts V on this pin, the device automatically enters the aforementioned Unlock Bypass
HH
mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the
time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V from the WP#/ACC pin returns the device to normal
HH
operation. Note that V must not be asserted on WP#/ACC for operations other than accelerated
HH
programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result. See Write Protect (WP#) on page 23 for related
information.
8.3.2
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system
can then read autoselect codes from the internal register (which is separate from the memory array) on
DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 21 and
Autoselect Command Sequence on page 32 for more information.
December 16, 2011 S29JL064J_00_05
S29JL064J
15
D a t a S h e e t
8.4
8.5
Simultaneous Read/Write Operations with Zero Latency
This device is capable of reading data from one bank of memory while programming or erasing in another
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being erased). Figure 17.8 on page 51 shows how read and write
cycles may be initiated for simultaneous operation with zero latency. I
and I
in the DC Characteristics
CC6
CC7
on page 43 represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
0.3V.
CC
(Note that this is a more restricted voltage range than V .) If CE# and RESET# are held at V , but not within
IH
IH
V
0.3V, the device will be in the standby mode, but the standby current will be greater. The device
CC
requires standard access time (t ) for read access when the device is in either of these standby modes,
CE
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
I
in DC Characteristics on page 43 represents the standby current specification.
CC3
8.6
8.7
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
Characteristics on page 43 represents the automatic sleep mode current specification.
+ 30 ns. The automatic sleep mode is independent of the
ACC
in DC
CC5
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t , the device immediately terminates any operation in
RP
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
0.3V, the device
SS
draws CMOS standby current (I
will be greater.
). If RESET# is held at V but not within V
0.3V, the standby current
CC4
IL
SS
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of t
(during Embedded Algorithms). The
READY
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
(not during Embedded Algorithms). The system can read data t after the
READY
RH
RESET# pin returns to V .
IH
Refer to Hardware Reset (RESET#) on page 47 for RESET# parameters and to Figure 17.2 on page 47 for
the timing diagram.
16
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
8.8
Output Disable Mode
When the OE# input is at V , output from the device is disabled. The output pins are placed in the high
IH
impedance state.
Table 8.2 S29JL064J Sector Architecture (Sheet 1 of 4)
Sector Address
A21–A12
Sector Size
(kbytes/kwords)
(x8)
(x16)
Address Range
Bank
Sector
SA0
Address Range
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001110xxx
0001111xxx
8/4
8/4
000000h–001FFFh
002000h–003FFFh
004000h–005FFFh
006000h–007FFFh
008000h–009FFFh
00A000h–00BFFFh
00C000h–00DFFFh
00E000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
00000h–00FFFh
01000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–04FFFh
05000h–05FFFh
06000h–06FFFh
07000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
SA1
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
Bank 1
December 16, 2011 S29JL064J_00_05
S29JL064J
17
D a t a S h e e t
Table 8.2 S29JL064J Sector Architecture (Sheet 2 of 4)
Sector Address
A21–A12
Sector Size
(kbytes/kwords)
(x8)
(x16)
Address Range
Bank
Sector
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Address Range
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
0011001xxx
0011010xxx
0011011xxx
0011000xxx
0011101xxx
0011110xxx
0011111xxx
0100000xxx
0100001xxx
0100010xxx
0101011xxx
0100100xxx
0100101xxx
0100110xxx
0100111xxx
0101000xxx
0101001xxx
0101010xxx
0101011xxx
0101100xxx
0101101xxx
0101110xxx
0101111xxx
0110000xxx
0110001xxx
0110010xxx
0110011xxx
0110100xxx
0110101xxx
0110110xxx
0110111xxx
0111000xxx
0111001xxx
0111010xxx
0111011xxx
0111100xxx
0111101xxx
0111110xxx
0111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3FFFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Bank 2
18
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Table 8.2 S29JL064J Sector Architecture (Sheet 3 of 4)
Sector Address
A21–A12
Sector Size
(kbytes/kwords)
(x8)
(x16)
Address Range
Bank
Sector
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
Address Range
1000000xxx
1000001xxx
1000010xxx
1000011xxx
1000100xxx
1000101xxx
1000110xxx
1000111xxx
1001000xxx
1001001xxx
1001010xxx
1001011xxx
1001100xxx
1001101xxx
1001110xxx
1001111xxx
1010000xxx
1010001xxx
1010010xxx
1010011xxx
1010100xxx
1010101xxx
1010110xxx
1010111xxx
1011000xxx
1011001xxx
1011010xxx
1011011xxx
1011100xxx
1011101xxx
1011110xxx
1011111xxx
1100000xxx
1100001xxx
1100010xxx
1100011xxx
1100100xxx
1100101xxx
1100110xxx
1100111xxx
1101000xxx
1101001xxx
1101010xxx
1101011xxx
1101100xxx
1101101xxx
1101110xxx
1101111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
400000h–40FFFFh
410000h–41FFFFh
420000h–42FFFFh
430000h–43FFFFh
440000h–44FFFFh
450000h–45FFFFh
460000h–46FFFFh
470000h–47FFFFh
480000h–48FFFFh
490000h–49FFFFh
4A0000h–4AFFFFh
4B0000h–4BFFFFh
4C0000h–4CFFFFh
4D0000h–4DFFFFh
4E0000h–4EFFFFh
4F0000h–4FFFFFh
500000h–50FFFFh
510000h–51FFFFh
520000h–52FFFFh
530000h–53FFFFh
540000h–54FFFFh
550000h–55FFFFh
560000h–56FFFFh
570000h–57FFFFh
580000h–58FFFFh
590000h–59FFFFh
5A0000h–5AFFFFh
5B0000h–5BFFFFh
5C0000h–5CFFFFh
5D0000h–5DFFFFh
5E0000h–5EFFFFh
5F0000h–5FFFFFh
600000h–60FFFFh
610000h–61FFFFh
620000h–62FFFFh
630000h–63FFFFh
640000h–64FFFFh
650000h–65FFFFh
660000h–66FFFFh
670000h–67FFFFh
680000h–68FFFFh
690000h–69FFFFh
6A0000h–6AFFFFh
6B0000h–6BFFFFh
6C0000h–6CFFFFh
6D0000h–6DFFFFh
6E0000h–6EFFFFh
6F0000h–6FFFFFh
200000h–207FFFh
208000h–20FFFFh
210000h–217FFFh
218000h–21FFFFh
220000h–227FFFh
228000h–22FFFFh
230000h–237FFFh
238000h–23FFFFh
240000h–247FFFh
248000h–24FFFFh
250000h–257FFFh
258000h–25FFFFh
260000h–267FFFh
268000h–26FFFFh
270000h–277FFFh
278000h–27FFFFh
280000h–28FFFFh
288000h–28FFFFh
290000h–297FFFh
298000h–29FFFFh
2A0000h–2A7FFFh
2A8000h–2AFFFFh
2B0000h–2B7FFFh
2B8000h–2BFFFFh
2C0000h–2C7FFFh
2C8000h–2CFFFFh
2D0000h–2D7FFFh
2D8000h–2DFFFFh
2E0000h–2E7FFFh
2E8000h–2EFFFFh
2F0000h–2FFFFFh
2F8000h–2FFFFFh
300000h–307FFFh
308000h–30FFFFh
310000h–317FFFh
318000h–31FFFFh
320000h–327FFFh
328000h–32FFFFh
330000h–337FFFh
338000h–33FFFFh
340000h–347FFFh
348000h–34FFFFh
350000h–357FFFh
358000h–35FFFFh
360000h–367FFFh
368000h–36FFFFh
370000h–377FFFh
378000h–37FFFFh
Bank 3
December 16, 2011 S29JL064J_00_05
S29JL064J
19
D a t a S h e e t
Table 8.2 S29JL064J Sector Architecture (Sheet 4 of 4)
Sector Address
A21–A12
Sector Size
(kbytes/kwords)
(x8)
(x16)
Address Range
Bank
Sector
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Address Range
1110000xxx
1110001xxx
1110010xxx
1110011xxx
1110100xxx
1110101xxx
1110110xxx
1110111xxx
1111000xxx
1111001xxx
1111010xxx
1111011xxx
1111100xxx
1111101xxx
1111110xxx
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
700000h–70FFFFh
710000h–71FFFFh
720000h–72FFFFh
730000h–73FFFFh
740000h–74FFFFh
750000h–75FFFFh
760000h–76FFFFh
770000h–77FFFFh
780000h–78FFFFh
790000h–79FFFFh
7A0000h–7AFFFFh
7B0000h–7BFFFFh
7C0000h–7CFFFFh
7D0000h–7DFFFFh
7E0000h–7EFFFFh
7F0000h–7F1FFFh
7F2000h–7F3FFFh
7F4000h–7F5FFFh
7F6000h–7F7FFFh
7F8000h–7F9FFFh
7FA000h–7FBFFFh
7FC000h–7FDFFFh
7FE000h–7FFFFFh
380000h–387FFFh
388000h–38FFFFh
390000h–397FFFh
398000h–39FFFFh
3A0000h–3A7FFFh
3A8000h–3AFFFFh
3B0000h–3B7FFFh
3B8000h–3BFFFFh
3C0000h–3C7FFFh
3C8000h–3CFFFFh
3D0000h–3D7FFFh
3D8000h–3DFFFFh
3E0000h–3E7FFFh
3E8000h–3EFFFFh
3F0000h–3F7FFFh
3F8000h–3F8FFFh
3F9000h–3F9FFFh
3FA000h–3FAFFFh
3FB000h–3FBFFFh
3FC000h–3FCFFFh
3FD000h–3FDFFFh
3FE000h–3FEFFFh
3FF000h–3FFFFFh
Bank 4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note:
The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH).
Table 8.3 Bank Address
Bank
A21–A19
000
1
2
3
4
001, 010, 011
100, 101, 110
111
Table 8.4 Secured Silicon Region Addresses
(x8)
(x16)
Device
Sector Size
Address Range
Address Range
S29JL064J
256 bytes
000000h–0000FFh
000000h–00007Fh
20
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
8.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V on address pin A9. Address pins
ID
must be as shown in Table 8.5. In addition, when verifying sector protection, the sector address must appear
on the appropriate highest order address bits (see Table 8.3 on page 20). Table 8.5 shows the remaining
address bits that are don’t care. When all necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes
can also be accessed in-system through the command register, for instances when the S29JL064J is erased
or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in Table 10.1 on page 36. Note that if a Bank Address (BA) on address bits A21, A20, and A19 is
asserted during the third write cycle of the autoselect command, the host system can read autoselect data
from that bank and then immediately read array data from another bank, without exiting the autoselect mode.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 10.1 on page 36. This method does not require V . Refer to
ID
Autoselect Command Sequence on page 32 for more information.
Table 8.5 S29JL064J Autoselect Codes, (High Voltage Method)
DQ15 to DQ8
A11
to
DQ7
to
A21
to
A8
to
A5
to
BYTE# BYTE#
Description
CE# OE# WE#
A12
A10
A9
A7
A6
A4
A3
A2
A1
A0
= VIH
= VIL
DQ0
Manufacturer ID:
Spansion Products
L
L
L
L
L
L
L
L
H
H
H
H
BA
BA
SA
BA
X
X
X
X
VID
X
X
X
X
L
X
X
X
X
L
L
L
L
X
X
01h
Read Cycle 1
Read Cycle 2
Read Cycle 3
L
L
L
L
H
H
L
H
H
L
H
H
H
L
22h
22h
22h
7Eh
02h
01h
VID
VID
VID
X
X
X
H
Sector Protection
Verification
01h (protected),
00h (unprotected)
L
L
L
H
L
X
81h (Factory Locked),
41h (Customer
Locked),
Secured Silicon
Indicator Bit (DQ6,
DQ7)
L
L
L
H
H
X
01h (Not Locked)
Legend
L = Logic Low = VIL
H = Logic High = VIH
BA = Bank Address
SA = Sector Address
X = Don’t care.
December 16, 2011 S29JL064J_00_05
S29JL064J
21
D a t a S h e e t
8.10 Boot Sector/Sector Block Protection and Unprotection
Note: For the following discussion, the term sector applies to both boot sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are protected or unprotected at the same time (see
Table 8.6).
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors. Sector protection/unprotection can be implemented via two methods.
Table 8.6 S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 1 of 2)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A21–A12
Sector/Sector Block Size
8 kbytes
0000000000
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
0000001XXX,
0000010XXX,
0000011XXX,
SA8–SA10
192 (3x64) kbytes
SA11–SA14
SA15–SA18
SA19–SA22
SA23–SA26
SA27-SA30
SA31-SA34
SA35-SA38
SA39-SA42
SA43-SA46
SA47-SA50
SA51-SA54
SA55–SA58
SA59–SA62
SA63–SA66
SA67–SA70
SA71–SA74
SA75–SA78
SA79–SA82
SA83–SA86
SA87–SA90
SA91–SA94
SA95–SA98
SA99–SA102
SA103–SA106
SA107–SA110
SA111–SA114
SA115–SA118
SA119–SA122
SA123–SA126
SA127–SA130
00001XXXXX
00010XXXXX
00011XXXXX
00100XXXXX
00101XXXXX
00110XXXXX
00111XXXXX
01000XXXXX
01001XXXXX
01010XXXXX
01011XXXXX
01100XXXXX
01101XXXXX
01110XXXXX
01111XXXXX
10000XXXXX
10001XXXXX
10010XXXXX
10011XXXXX
10100XXXXX
10101XXXXX
10110XXXXX
10111XXXXX
11000XXXXX
11001XXXXX
11010XXXXX
11011XXXXX
11100XXXXX
11101XXXXX
11110XXXXX
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
256 (4x64) kbytes
22
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Table 8.6 S29JL064J Boot Sector/Sector Block Addresses for Protection/Unprotection (Sheet 2 of 2)
Sector
A21–A12
Sector/Sector Block Size
1111100XXX,
1111101XXX,
1111110XXX
SA131–SA133
192 (3x64) kbytes
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1111111000
1111111001
1111111010
1111111011
1111111100
1111111101
1111111110
1111111111
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
Sector Protect/Sector Unprotect requires V on the RESET# pin only, and can be implemented either in-
ID
system or via programming equipment. Figure 8.2 on page 25 shows the algorithms and Figure 17.13
on page 54 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually re-protected. To change data in protected
sectors efficiently, the temporary sector unprotect function is available. See Temporary Sector Unprotect
on page 24.
The device is shipped with all sectors unprotected. Optional Spansion programming service enable
programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office
for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 21 for
details.
8.11 Write Protect (WP#)
The Write Protect function provides a hardware method of protecting without using V . This function is one of
ID
two provided by the WP#/ACC pin.
If the system asserts V on the WP#/ACC pin, the device disables program and erase functions in sectors 0,
IL
1, 140, and 141, independently of whether those sectors were protected or unprotected using the method
described in Boot Sector/Sector Block Protection and Unprotection on page 22.
If the system asserts V on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were
IH
last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on
whether they were last protected or unprotected using the method described in Boot Sector/Sector Block
Protection and Unprotection on page 22.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may
result.
Table 8.7 WP#/ACC Modes
WP# Input Voltage
Device Mode
VIL
Disables programming and erasing in SA0, SA1, SA140, and SA141
Enables programming and erasing in SA0, SA1, SA140, and SA141, dependent on whether they were last
protected or unprotected.
VIH
VHH
Enables accelerated programming (ACC). See Accelerated Program Operation on page 15.
December 16, 2011 S29JL064J_00_05
S29JL064J
23
D a t a S h e e t
8.12 Temporary Sector Unprotect
Note: For the following discussion, the term sector applies to both sectors and sector blocks. A sector block
consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 8.6
on page 22).
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Temporary Sector Unprotect mode is activated by setting the RESET# pin to V . During this mode, formerly
ID
protected sectors can be programmed or erased by selecting the sector addresses. Once V is removed
ID
from the RESET# pin, all the previously protected sectors are protected again. Figure 8.1 shows the
algorithm, and Figure 17.12 on page 53 shows the timing diagrams, for this feature. If the WP#/ACC pin is at
V , sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode.
IL
Figure 8.1 Temporary Sector Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 140, and 141 will remain protected).
2. All previously protected sectors are protected once again.
24
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 8.2 In-System Sector Protect/Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
unprotect address
No
No
First Write
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
No
from RESET#
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
December 16, 2011 S29JL064J_00_05
S29JL064J
25
D a t a S h e e t
8.13 Secured Silicon Region
The Secured Silicon Region feature provides a Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Region is 256 bytes in length,
and may shipped unprotected, allowing customers to utilize that sector in any manner they choose, or may
shipped locked at the factory (upon customer request). The Secured Silicon Indicator Bit data will be 81h if
factory locked, 41h if customer locked, or 01h if neither. Refer to Table 8.5 on page 21 for more details.
The system accesses the Secured Silicon Region through a command sequence (see Enter Secured Silicon
Region/Exit Secured Silicon Region Command Sequence on page 32). After the system has written the Enter
Secured Silicon Region command sequence, it may read the Secured Silicon Region by using the addresses
normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit
Secured Silicon Region command sequence, or until power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note
that the ACC function and unlock bypass modes are not available when the Secured Silicon Region is
enabled.
8.13.1
Factory Locked: Secured Silicon Region Programmed and Protected At the
Factory
In a factory locked device, the Secured Silicon Region is protected when the device is shipped from the
factory. The Secured Silicon Region cannot be modified in any way. The device is preprogrammed with both a
random number and a secure ESN. The 8-word random number is at addresses 000000h–000007h in word
mode (or 000000h–00000Fh in byte mode). The secure ESN is programmed in the next 8 words at addresses
000008h–00000Fh (or 000010h–00001Fh in byte mode). The device is available preprogrammed with one of
the following:
A random, secure ESN only
Customer code through Spansion programming services
Both a random, secure ESN and customer code through Spansion programming services
Contact an your local sales office for details on using Spansion programming services.
8.13.2
Customer Lockable: Secured Silicon Region NOT Programmed or Protected
At the Factory
If the security feature is not required, the Secured Silicon Region can be treated as an additional Flash
memory space. The Secured Silicon Region can be read any number of times, but can be programmed and
locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not
available when programming the Secured Silicon Region.
Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 8.2 on page 25, except that RESET# may be at either V or
IH
V . This allows in-system protection of the Secured Silicon Region without raising any device pin to a high
ID
voltage. Note that this method is only applicable to the Secured Silicon Region.
To verify the protect/unprotect status of the Secured Silicon Region, follow the algorithm shown in
Figure 8.3 on page 27.
Once the Secured Silicon Region is locked and verified, the system must write the Exit Secured Silicon
Region command sequence to return to reading and writing the remainder of the array.
The Secured Silicon Region lock must be used with caution since, once locked, there is no procedure
available for unlocking the Secured Silicon Region and none of the bits in the Secured Silicon Region
memory space can be modified in any way.
26
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 8.3 Secured Silicon Region Protect Verify
START
If data = 00h,
RESET# =
Secure Silicon Region
VIH or VID
is unprotected.
If data = 01h,
Secure Silicon Region
Wait 1 ms
is protected.
Write 60h to
any address
Remove VIH or VID
from RESET#
Write 40h to Secure
Silicon Region address
Secured Silicon Region
with A6 = 0,
A1 = 1, A0 = 0
exit command
Secure Silicon Region
Read from Secure
Silicon Region address
Protect Verify
complete
with A6 = 0,
A1 = 1, A0 = 0
8.14 Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 10.1 on page 36 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during V power-up and power-down transitions, or from system
CC
noise.
8.14.1
Low VCC Write Inhibit
When V is less than V
, the device does not accept any write cycles. This protects data during V
CC
LKO
CC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets to the read mode. Subsequent writes are ignored until V is greater than V . The
CC
LKO
system must provide the proper signals to the control pins to prevent unintentional writes when V is greater
CC
than V
.
LKO
8.14.2
8.14.3
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
CE# and WE# must be a logical zero while OE# is a logical one.
8.14.4
Power-Up Write Inhibit
If WE# = CE# = V and OE# = V during power up, the device does not accept commands on the rising
IL
IH
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
December 16, 2011 S29JL064J_00_05
S29JL064J
27
D a t a S h e e t
9. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system
can read CFI information at the addresses given in Table 9.1 on page 28 to Table 9.4 on page 30. To
terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible
when the device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command when the device is in the autoselect mode via the
command register only (high voltage method does not apply). The device enters the CFI query mode, and the
system can read CFI data at the addresses given in Table 9.1 on page 28 to Table 9.4 on page 30. The
system must write the reset command to return to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales
office for copies of these documents.
Table 9.1 CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Table 9.2 System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Bh
1Ch
36h
38h
0027h
VCC Max. (write/erase)
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0003h
0000h
0009h
000Fh
0004h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
28
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Table 9.3 Device Geometry Definition
Addresses
(Word
Addresses
Mode)
(Byte Mode)
Data
Description
27h
4Eh
0017h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to the CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
December 16, 2011 S29JL064J_00_05
S29JL064J
29
D a t a S h e e t
Table 9.4 Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0033h
Major version number, ASCII (reflects modifications to the silicon)
Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (Bits 1-0)
0 = Required,
45h
46h
8Ah
8Ch
000Ch
0002h
1 = Not Required
Process Technology (Bits 7-2)
0011 = 0.11 µm Floating Gate
Erase Suspend
0 = Not Supported,
1 = To Read Only,
2 = To Read & Write
Sector Protect
47h
48h
8Eh
90h
0001h
0001h
0 = Not Supported,
X = Number of sectors per group
Sector Temporary Unprotect
00 = Not Supported,
01 = Supported
Sector Protect/Unprotect scheme
01 =29F040 mode,
49h
92h
0004h
02 = 29F016 mode,
03 = 29F400,
04 = 29LV800 mode
Simultaneous Operation
4Ah
4Bh
94h
96h
0077h
0000h
00 = Not Supported,
X = Number of Sectors (excluding Bank 1)
Burst Mode Type
00 = Not Supported,
01 = Supported
Page Mode Type
00 = Not Supported,
01 = 4 Word Page,
02 = 8 Word Page
4Ch
98h
0000h
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
0085h
0095h
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
00h = Uniform device,
01h = 8 x 8 kbyte Sectors, Top And Bottom Boot with Write Protect,
02h = Bottom Boot Device,
4Fh
9Eh
0001h
03h = Top Boot Device,
04h= Both Top and Bottom
Program Suspend
50h
57h
A0h
AEh
0000h
0004h
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero,
X = Number of Banks
Bank 1 Region Information
58h
59h
5Ah
5Bh
B0h
B2h
B4h
B6h
0017h
0030h
0030h
0017h
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
30
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
10. Command Definitions
Writing specific address and data sequences into the command register initiates device operations.
Table 10.1 on page 36 defines the valid register command sequences. Writing incorrect address and data
values or writing them in the improper sequence may place the device in an unknown state. A reset command
is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to AC Characteristics on page 46 for timing
diagrams.
10.1 Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-
read mode, after which the system can read data from any non-erase-suspended sector within the same
bank. The system can read array data using the standard read timing, except that if it reads at an address
within erase-suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception. See Erase
Suspend/Erase Resume Commands on page 35 for more information.
The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation, or if the bank is in the autoselect mode. See Reset
Command on page 31 for more information.
See Requirements for Reading Array Data on page 15 for more information. Read-Only Operations
on page 46 provides the read parameters, and Figure 17.1 on page 46 shows the timing diagram.
10.2 Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the bank to which the system was writing to the read mode. If the program
command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command
returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the bank to the
read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Please note that the RY/BY#
signal remains low until this reset is issued.
December 16, 2011 S29JL064J_00_05
S29JL064J
31
D a t a S h e e t
10.3 Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes,
and determine whether or not a sector is protected. The autoselect command sequence may be written to an
address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may
not be written while the device is actively programming or erasing in another bank.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect
mode. The system may read any number of autoselect codes without re-initiating the command sequence.
Table 10.1 on page 36 shows the address and data requirements. To determine sector protection
information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 8.3
on page 20 shows the address range and bank number associated with each sector.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
10.4 Enter Secured Silicon Region/Exit Secured Silicon Region Command
Sequence
The system can access the Secured Silicon Region by issuing the three-cycle Enter Secured Silicon Region
command sequence. The device continues to access the Secured Silicon Region until the system issues the
four-cycle Exit Secured Silicon Region command sequence. The Exit Secured Silicon Region command
sequence returns the device to normal operation. The Secured Silicon Region is not accessible when the
device is executing an Embedded Program or embedded Erase algorithm. Table 10.1 on page 36 shows the
address and data requirements for both command sequences. See also Secured Silicon Region on page 26 for
further information. Note that the ACC function and unlock bypass modes are not available when the Secured
Silicon Region is enabled.
10.5 Byte/Word Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming
is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not required to provide further controls or timings.
The device automatically provides internally generated program pulses and verifies the programmed cell
margin. Table 10.1 on page 36 shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses
are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or
RY/BY#. Refer to Write Operation Status on page 37 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program operation. The program command sequence should be
reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured
Silicon Region, autoselect, and CFI functions are unavailable when a program operation is in progress.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
0 back to a 1. Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status
bits to indicate the operation was successful. However, a succeeding read will show that the data is still 0.
Only erase operations can convert a 0 to a 1.
32
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
10.5.1
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to a bank faster than using the
standard program command sequence. The unlock bypass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 10.1 on page 36 shows the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. (See Table 10.1 on page 36).
The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V
HH
on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write
the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/
ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V for any operation other
HH
than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left
floating or unconnected; inconsistent behavior of the device may result.
Figure 10.1 on page 33 illustrates the algorithm for the program operation. Refer to Erase and Program
Operations on page 49 for parameters, and Figure 17.5 on page 50 for timing diagrams.
Figure 10.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment Address
Last Address?
Yes
Programming
Completed
Note:
1. See Table 10.1 on page 36 for program command sequence.
December 16, 2011 S29JL064J_00_05
S29JL064J
33
D a t a S h e e t
10.6 Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 10.1 on page 36 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/
BY#. Refer to Write Operation Status on page 37 for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured
Silicon Region, autoselect, and CFI functions are unavailable when an erase operation is in progress.
Figure 10.2 on page 35 illustrates the algorithm for the erase operation. Refer to Erase and Program
Operations on page 49 for parameters, and Figure 17.7 on page 51 for timing diagrams.
10.7 Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command. Table 10.1 on page 36 shows the
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. However, these additional erase
commands are only one bus cycle long and should be identical to the sixth cycle of the standard erase
command explained above. Loading the sector erase buffer may be done in any sequence, and the number
of sectors may be from one sector to all sectors. The time between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-
out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. If any command other than 30h, B0h, F0h is input during the time-out period, the normal
operation will not be guaranteed. The system must rewrite the command sequence and any additional
addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising
edge) in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7,
DQ6, DQ2, or RY/BY# in the erasing bank. Refer to Write Operation Status on page 37 for information on
these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable
when an erase operation is in progress.
Figure 10.2 on page 35 illustrates the algorithm for the erase operation. Refer to Erase and Program
Operations on page 49 for parameters, and Figure 17.7 on page 51 for timing diagrams.
34
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 10.2 Erase Operation
START
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 10.1 on page 36 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
10.8 Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. The bank address must contain one of the sectors
currently selected for erase.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of 35 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system
can read data from or program data to any sector not selected for erasure. (The device erase suspends all
sectors selected for erasure.) It is not recommended to program the Secured Silicon Region after an erase
suspend, as proper device functionality cannot be guaranteed. Reading at any address within erase-
suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer to Write Operation Status
on page 37 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode.
The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in
the standard Byte Program operation. Refer to Write Operation Status on page 37 for more information.
In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in
the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. Refer to Autoselect Mode on page 21 and Autoselect
Command Sequence on page 32 for details.
To resume the sector erase operation, the system must write the Erase Resume command. The bank
address of the erase-suspended bank is required when writing this command. Further writes of the Resume
command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
December 16, 2011 S29JL064J_00_05
S29JL064J
35
D a t a S h e e t
Table 10.1 S29JL064J Command Definitions
Bus Cycles (Notes 2–5)
Third Fourth
Addr Addr
Command
Sequence
(Note 1)
First
Addr
Second
Fifth
Addr
Sixth
Addr
Data
RD
Addr
Data
Data
Data
Data
Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
555
AAA
555
AAA
555
F0
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
2AA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
Manufacturer ID
4
6
4
AA
AA
AA
55
55
55
90
90
90
(BA)X00
01
7E
(BA)X01
(BA)X02
(BA)X03
(BA)X06
(SA)X02
(BA)X0E
(BA)X1C
(BA)X0F
(BA)X1E
Device ID (Note 9)
02
01
Secured Silicon Region
Factory Protect (Note 10)
81/41/
01
Boot Sector/Sector Block Word
Protect Verify
(Note 11)
4
AA
55
90
00/01
Byte
AAA
555
(BA)AAA
(SA)X04
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
BA
2AA
555
2AA
555
2AA
555
2AA
555
PA
555
AAA
555
Enter Secured Silicon Region
3
4
4
3
AA
AA
AA
AA
55
55
55
55
88
90
A0
20
Exit Secured Silicon Region
Program
XXX
PA
00
AAA
555
PD
AAA
555
Unlock Bypass
AAA
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
2
2
A0
90
PD
00
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
6
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Byte
Word
Byte
AAA
Sector Erase (Note 17)
SA
AAA
AAA
Erase Suspend (Note 14)
Erase Resume (Note 15)
1
1
B0
30
BA
Word
Byte
55
CFI Query (Note 16)
1
98
AA
Legend
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. Refer to Table 8.3 on page 20 for
information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A21–A19 uniquely select a bank.
Notes:
1. See Table 8.1 on page 14 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect
mode, or if DQ5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or
Secured Silicon Region factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the
same until a reset command is given. See Autoselect Command Sequence on page 32 for more information.
9. The device ID must be read across the fourth, fifth, and sixth cycles.
10.The data is 81h for factory locked, 41h for customer locked, and 01h for not factory/customer locked.
36
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
11.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
12.The Unlock Bypass command is required prior to the Unlock Bypass Program command.
13.The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode.
14.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation, and requires the bank address.
15.The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
16.Command is valid when device is ready to read array data or when device is in autoselect mode.
17.Additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical to the sixth
cycle of the sector erase command sequence (SA / 30).
11. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 11.1 on page 42 and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or has been completed.
11.1 DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 3 ms, then the bank returns to the read mode. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the
status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at
DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycles. Just prior to the completion of an
Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for
x8-only device) while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid
data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on DQ15–DQ0 (or DQ7–DQ0 for x8-only
device) will appear on successive read cycles.
Table 11.1 on page 42 shows the outputs for Data# Polling on DQ7. Figure 11.1 on page 38 shows the Data#
Polling algorithm. Figure 17.9 on page 52 shows the Data# Polling timing diagram.
December 16, 2011 S29JL064J_00_05
S29JL064J
37
D a t a S h e e t
Figure 11.1 Data# Polling Algorithm
34!24
2EADå$1ꢀn$1ꢅ
!DDRåꢁå6!
9ES
$1ꢀåꢁå$ATAꢂ
.O
.O
$1ꢃåꢁåꢄꢂ
9ES
2EADå$1ꢀn$1ꢅ
!DDRåꢁå6!
9ES
$1ꢀåꢁå$ATAꢂ
.O
0!33
&!),
Notes:
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
11.2 RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
.
CC
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one
of the banks is in the erase-suspend-read mode.
Table 11.1 on page 42 shows the outputs for RY/BY#.
When DQ5 is set to “1”, RY/BY# will be in the BUSY state, or “0”.
38
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
11.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 3 ms, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 37).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
December 16, 2011 S29JL064J_00_05
S29JL064J
39
D a t a S h e e t
Figure 11.2 Toggle Bit Algorithm
START
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
No
Toggle Bit
= Toggle?
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ7–DQ0)
Address = VA
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See the
subsections on DQ6 and DQ2 for more information.
11.4 DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 11.1 on page 42 to compare
outputs for DQ2 and DQ6.
Figure 11.2 on page 40 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 40
explains the algorithm. See also DQ6: Toggle Bit I on page 39. Figure 17.10 on page 52 shows the toggle bit
timing diagram. Figure 17.11 on page 53 shows the differences between DQ2 and DQ6 in graphical form.
40
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
11.5 Reading Toggle Bits DQ6/DQ2
Refer to Figure 11.2 on page 40 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system
can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or
erase operation. If it is still toggling, the device did not completed the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 11.2 on page 40).
11.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully
completed.
The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1.
Under both these conditions, the system must write the reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
11.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
also Sector Erase Command Sequence on page 34.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is 0, the device will accept additional sector erase commands. To
ensure the command has been accepted, the system software should check the status of DQ3 prior to and
following each subsequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. The RDY/BSY# pin will be in the BUSY state under this condition.
Table 11.1 on page 42 shows the status of DQ3 relative to the other status bits.
December 16, 2011 S29JL064J_00_05
S29JL064J
41
D a t a S h e e t
Table 11.1 Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
DQ7#
Toggle
Toggle
Toggle
0
0
0
No toggle
Toggle
0
0
0
Standard
Mode
in busy erasing sector
0
0
Embedded Erase
Algorithm
in not busy erasing sector
1
No toggle
Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Erase
Suspend
Mode
Erase-Suspend-Read
Non-Erase Suspended
Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in
progress. The device outputs array data if the system addresses a non-busy bank.
12. Absolute Maximum Ratings
Storage Temperature, Plastic Packages
–65°C to +150°C
–65°C to +125°C
Ambient Temperature with Power Applied
Voltage with Respect to Ground
VCC (Note 1)
–0.5V to +4.0V
–0.5V to +12.5V
–0.5V to +9.5V
–0.5V to VCC +0.5V
200 mA
A9 and RESET# (Note 2)
WP#/ACC
All other pins (Note 1)
Output Short Circuit Current (Note 3)
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0V for periods of
up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5V. See Figure 12.1 on page 42. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0V for periods up to 20 ns. See Figure 12.2 on page 42.
2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5V. During voltage transitions, A9, OE#, WP#/ACC, and
RESET# may overshoot VSS to –2.0V for periods of up to 20 ns. See Figure 12.1 on page 42. Maximum DC input voltage on pin A9 is
+12.5V which may overshoot to +14.0V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5V which may overshoot
to +12.0V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 12.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 12.2 Maximum Positive Overshoot Waveform
20 ns
V
CC+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
42
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
13. Operating Ranges
Industrial (I) Devices
Ambient Temperature (T )
–40°C to +85°C
2.7V to 3.6V
A
V
CC
Supply Voltages
for standard voltage range
CC
V
Operating ranges define those limits between which the functionality of the device is guaranteed.
14. DC Characteristics
14.1 CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
Test Conditions
VIN = VSS to VCC
Min
Typ
Max
Unit
,
ILI
± 1.0
µA
VCC = VCC max
VCC = VCC max, OE# = VIH; A9 or
RESET# = 12.5V
ILIT
A9 and RESET# Input Load Current
35
µA
VOUT = VSS to VCC
VCC = VCC max, OE# = VIH
,
ILO
ILR
Output Leakage Current
Reset Leakage Current
± 1.0
µA
µA
VCC = VCC max; RESET# = 12.5V
35
16
4
5 MHz
10
2
CE# = VIL, OE# = VIH, Byte
Mode
1 MHz
5 MHz
1 MHz
ICC1
VCC Active Read Current (Notes 1, 2)
mA
10
2
16
4
CE# = VIL, OE# = VIH, Word
Mode
ICC2
ICC3
ICC4
VCC Active Write Current (Notes 2, 3)
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE# = VIL, OE# = VIH, WE# = VIL
CE#, RESET# = VCC ± ± 0.3V
RESET# = VSS ± ± 0.3V
15
0.2
0.2
30
5
mA
µA
µA
5
VIH = VCC ± 0.3V;
VIL = VSS ± ± 0.3V
ICC5
Automatic Sleep Mode (Notes 2, 4)
0.2
5
µA
Byte
Word
Byte
Word
21
21
21
21
45
45
45
45
CE# = VIL
OE# = VIH, 1 MHz
CE# = VIL
,
ICC6
VCC Active Read-While-Program Current (2)
mA
,
ICC7
VCC Active Read-While-Erase Current (2)
mA
mA
OE# = VIH, 1 MHz
VCC Active Program-While-Erase-Suspended Current
(Notes 2, 5)
ICC8
CE# = VIL, OE# = VIH
17
35
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for WP#/ACC Sector Protect/Unprotect and
Program Acceleration
VHH
VID
V
CC = 3.0V 10ꢀ
8.5
8.5
9.5
V
V
Voltage for Autoselect and Temporary Sector
Unprotect
VCC = 3.0V ± 10ꢀ
12.5
0.45
VOL
Output Low Voltage
IOL = 2.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
VOH1
VOH2
VLKO
0.85 VCC
VCC–0.4
1.8
Output High Voltage
Low VCC Lock-Out Voltage (Note 5)
2.0
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH
.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.
5. Not 100% tested.
December 16, 2011 S29JL064J_00_05
S29JL064J
43
D a t a S h e e t
14.2 Zero-Power Flash
Figure 14.1 I
Current vs. Time (Showing Active and Automatic Sleep Currents)
CC1
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note:
Addresses are switching at 1 MHz
Figure 14.2 Typical I
vs. Frequency
CC1
12
10
8
3.6V
2.7V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note:
T = 25°C
44
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
15. Test Conditions
Figure 15.1 Test Setup
Device
Under
Test
C
L
Table 15.1 Test Specifications
Test Condition
Output Load Capacitance, CL
55, 60
70
Unit
pF
ns
V
30
100
Input Rise and Fall Times (Note 1)
Input Pulse Levels
5
0.0 or VCC
0.5 VCC
Input timing measurement reference levels
Output timing measurement reference levels
V
0.5 VCC
V
Note:
1. Input rise and fall times are 0-100%.
16. Key To Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High-Z)
Figure 16.1 Input Waveforms and Measurement Levels
3.0V
1.5V
1.5V
Input
Measurement Level
Output
0.0V
December 16, 2011 S29JL064J_00_05
S29JL064J
45
D a t a S h e e t
17. AC Characteristics
17.1 Read-Only Operations
Parameter
Speed Options
JEDEC Std.
Description
Read Cycle Time (Note 1)
Test Setup
55
60
70
Unit
tAVAV
tAVQV
tRC
Min
55
55
55
60
70
70
ns
CE#,
OE# = VIL
tACC Address to Output Delay
Max
60
60
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL Max
70
30
ns
ns
ns
ns
Output Enable to Output Delay
Max
Max
Max
25
Chip Enable to Output High-Z (Notes 1, 3)
Output Enable to Output High-Z (Notes 1, 3)
16
16
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold Time
(Note 1)
tOEH
Toggle and
5
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 15.1 on page 45 and Table 15.1 on page 45 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus
driven to VCC/2 is taken as tDF
.
Figure 17.1 Read Operation Timings
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
High-Z
High-Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
46
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
17.2 Hardware Reset (RESET#)
Parameter
JEDEC Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to Read
Mode (See Note)
tReady
tReady
Max
Max
35
µs
RESET# Pin Low (NOT During Embedded Algorithms) to
Read Mode (See Note)
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
35
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note:
Not 100% tested.
Figure 17.2 Reset Timings
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
December 16, 2011 S29JL064J_00_05
S29JL064J
47
D a t a S h e e t
17.3 Word/Byte Configuration (BYTE#)
Parameter
Speed Options
JEDEC
Std.
ELFL/tELFH
tFLQZ
Description
55
60
5
70
Unit
ns
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output High-Z
BYTE# Switching High to Output Active
Max
Max
Min
16
60
ns
tFHQV
55
70
ns
Figure 17.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
DQ14–DQ0
DQ15/A-1
tELFL
Data Output
(DQ14–DQ0)
Data
Output
BYTE#
Switching
from word
to byte
Address
Input
DQ15
Output
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ14–DQ0)
Data
DQ14–DQ0
DQ15/A-1
Address
Input
DQ15
Output
tFHQV
Figure 17.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
48
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
17.4 Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std
tWC
tAS
Description
55
60
60
0
70 Unit
Write Cycle Time (Note 1)
Address Setup Time
Min
Min
Min
Min
55
70
ns
ns
ns
ns
tAVWL
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
35
tWLAX
30
30
40
40
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
35
0
ns
ns
ns
Data Hold Time
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
ns
CE# Hold Time
tWP
Write Pulse Width
25
25
25
25
0
30
30
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
Byte
6
tWHWH1
tWHWH1
Programming Operation (Note 2)
µs
µs
Word
6
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
Typ
4
tWHWH2
tVCS
Sector Erase Operation (Note 2)
VCC Setup Time (Note 1)
Typ
Min
Min
Max
Max
0.5
50
0
sec
µs
ns
ns
µs
tRB
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
Erase Suspend Latency
tBUSY
tESL
90
35
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance on page 56 for more information.
December 16, 2011 S29JL064J_00_05
S29JL064J
49
D a t a S h e e t
Figure 17.5 Program Operation Timings
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.6 Accelerated Program Timing Diagram
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
50
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 17.7 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
Read Status Data
tAS
SA
tWC
VA
Addresses
CE#
2AAh
VA
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 37).
2. These waveforms are for the word mode.
Figure 17.8 Back-to-back Read/Write Cycle Timings
tWC
Valid PA
tWC
tRC
tWC
Valid PA
tAH
Valid RA
Valid PA
Addresses
tCPH
tACC
tCE
CE#
OE#
tCP
tOE
tOEH
tGHWL
tWP
WE#
Data
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# or CE2# Controlled Write Cycles
December 16, 2011 S29JL064J_00_05
S29JL064J
51
D a t a S h e e t
Figure 17.9 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
True
DQ0–DQ6
Status Data
True
Valid Data
Status Data
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 17.10 Toggle Bit Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCPH
tOEH
WE#
OE#
tOEPH
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array
data read cycle.
52
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 17.11 DQ2 vs. DQ6
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
17.5 Temporary Sector Unprotect
Parameter
JEDEC
Std
tVIDR
tVHH
tRSP
Description
VID Rise and Fall Time (See Note)
All Speed Options
Unit
ns
Min
Min
Min
500
250
4
VHH Rise and Fall Time (See Note)
ns
RESET# Setup Time for Temporary Sector Unprotect
µs
RESET# Hold Time from RY/BY# High for Temporary
Sector Unprotect
tRRB
Min
4
µs
Note:
Not 100% tested.
Figure 17.12 Temporary Sector Unprotect Timing Diagram
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
December 16, 2011 S29JL064J_00_05
S29JL064J
53
D a t a S h e e t
Figure 17.13 Sector/Sector Block Protect and Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector Group Protect/Unprotect
Verify
40h
Data
60h
60h
1 µs
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
CE#
WE#
OE#
Note:
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
17.6 Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
tAVAV
Std.
tWC
tAS
Description
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
55
60
60
0
70
Unit
ns
Min
Min
Min
Min
Min
55
70
tAVWL
tELAX
tDVEH
tEHDX
ns
tAH
tDS
tDH
30
30
35
35
0
40
40
ns
ns
Data Hold Time
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
0
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
25
25
25
25
6
40
30
tCPH
Byte
Programming Operation
(Note 2)
tWHWH1
tWHWH1
µs
Word
6
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
tWHWH2
Typ
Typ
4
µs
Sector Erase Operation (Note 2)
0.5
sec
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance on page 56 for more information.
54
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Figure 17.14 Alternate CE# Controlled Write (Erase/Program) Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
December 16, 2011 S29JL064J_00_05
S29JL064J
55
D a t a S h e e t
18. Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
Comments
Sector Erase Time
Chip Erase Time
0.5
71
5
Excludes 00h programming
prior to erasure (Note 3)
Excludes system level
overhead (Note 4)
Byte Program Time
6
80
µs
Word Program Time
Accelerated Byte/Word Program Time
Notes:
6
4
80
70
µs
µs
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 100,000 cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7V, 1,000,000 cycles.
3. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10.1
on page 36 for further information on command definitions.
5. The device has a minimum program and erase cycle endurance of 100,000 cycles per sector.
19. Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
VIN = 0
Max
8.5
Unit
pF
CIN
Input Capacitance (applies to A21-A0, DQ15-DQ0)
Output Capacitance (applies to DQ15-DQ0, RY/BY#)
COUT
VOUT = 0
5.5
pF
Control Pin Capacitance
(applies to CE#, WE#, OE#, WP#/ACC, RESET#, BYTE#)
CIN2
VIN = 0
12
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
56
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
20. Physical Dimensions
20.1 TS 048—48-Pin Standard TSOP
NOTES:
PACKAGE
TS/TSR 48
JEDEC
MO-142 (D) DD
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982)
SYMBOL
MIN
---
NOM
---
MAX
1.20
0.15
1.05
0.23
0.27
0.16
0.21
20.20
18.50
12.10
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
19.80
18.30
11.90
---
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
1.00
0.20
0.22
---
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTUSION IS 0.15mm (.0059") PER SIDE.
c1
c
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR
PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT
LEAD TO BE 0.07mm (0.0028").
---
D
20.00
18.40
12.00
0.50 BASIC
0.60
---
D1
E
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm (.0039") AND 0.25mm (0.0098") FROM THE LEAD TIP.
e
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM
THE SEATING PLANE.
L
0.50
0˚
0.70
8
Θ
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
R
0.08
---
0.20
N
48
3664 \ f16-038.10 \ 11.6.7
December 16, 2011 S29JL064J_00_05
S29JL064J
57
D a t a S h e e t
20.2 VBK048—48-Pin FBGA
NOTES:
PACKAGE
JEDEC
VBK 048
N/A
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
SYMBOL
MIN
NOM
---
MAX
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
D
---
1.00
---
OVERALL THICKNESS
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
0.18
---
BALL HEIGHT
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
8.15 BSC.
6.15 BSC.
5.60 BSC.
4.00 BSC.
8
BODY SIZE
E
BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
D1
E1
BALL FOOTPRINT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
BALL FOOTPRINT
MD
ME
N
ROW MATRIX SIZE D DIRECTION
ROW MATRIX SIZE E DIRECTION
TOTAL BALL COUNT
BALL DIAMETER
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
6
48
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
φb
e
0.33
---
0.43
0.80 BSC.
0.40 BSC.
---
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
SD / SE
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g1001.2 \ f16-038.25 \ 07.13.10
58
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
21. Revision History
.
Section
Description
Revision 01 (June 21, 2010)
Initial revision.
Revision 02 (September 1, 2010)
Updated the data sheet designation from Advanced Information to Preliminary.
Global
Corrected spelling, capitalization, and grammatical errors.
Simultaneous Read/Write Operations
with Zero Latency
Added clarification that JL064J is only offered as a dual boot device with both top and bottom boot
sectors.
Ordering Information
Device Bus Operation
Clarified that Note 1 applies to the Packing Type column.
The note for the Addresses column should be Note 1, not Note 2.
Changed “Refer to AC Characteristics on page 46” to “Refer to Hardware Reset (RESET#) on page
47”.
RESET#: Hardware Reset Pin
Clarified the Secured Silicon Indicator Bit data based on factory and customer lock status.
Secured Silicon Region
Removed forward looking statements regarding factory locking features as they are supported in
this device.
Clarified that once in the CFI query mode, the system must write the reset command to return to
reading array data.
Common Flash Memory Interface (CFI)
Enter Secured Silicon Region/Exit
Secured Silicon Region Command
Sequence
Removed the incorrect generalizing statement that the Secured Silicon Region always contains an
ESN.
Added clarification that “It is not recommended to program the Secured Silicon Region after an
erase suspend, as proper device functionality cannot be guaranteed.”
Erase Suspend/Erase Resume
Commands
In Table 10.1, corrected the Secured Silicon Region Factory Protect fourth cycle data from 81/01 to
81/41/01.
Erase and Programming Performance
Pin Capacitance
Added Note 5 regarding minimum program and erase cycle endurance.
Changed section title from “TSOP Pin Capacitance” to “Pin Capacitance”.
Updated values to reflect maximum capacitances for both TSOP and BGA.
Removed typical capacitance values.
Added specific pin clarifications to parameter descriptions.
Physical Dimensions
Updated the VBK048 package outline drawing.
Revision 03 (April 7, 2011)
Updated the data sheet designation from Preliminary to Full Production (no designation on
document).
Global
Added warning that keeping CE# at VIL from power up through the first reset could cause
erroneuous data on the first read.
RESET#: Hardware Reset Pin
Clarified that during an embedded program or erase, if DQ5 goes high then RY/BY# will remain low
until a reset is issued
Reset Command
Absolute Maximum Ratings
DC Characteristics
Corrected the maximum value of WP#/ACC voltage with respect to ground from +10.5V to +9.5V
Corrected voltage for autoselect and temporary sector unprotect (VID) minimum value from 11.5V to
8.5V
Changed the format of the input pulse levels and input and output timing measurement reference
levels to match the JL032J data sheet format
Test Conditions
Added note to “Reset Timings” figure clarifying that CE# should only go low after RESET# has gone
high.
Hardware Reset (RESET#)
December 16, 2011 S29JL064J_00_05
S29JL064J
59
D a t a S h e e t
Section
Description
Revision 04 (August 24, 2011)
Removed warning that keeping CE# at VIL from power up through the first reset could cause
erroneuous data on the first read.
RESET#: Hardware Reset Pin
Sector Erase Command Sequence
Command Definitions Table
Added clarification regarding additional sector erase commands during time-out period.
Added Note 17 to clarify additional sector erase commands during time-out period.
Removed note to the “Reset Timings” figure clarifying that CE# should only go low after RESET#
has gone high.
Hardware Reset (RESET#)
Erase and Programming Performance
Physical Dimensions
Updated Byte Program Time and Word Program Time to 80 µs.
Package drawings updated to latest version.
Revision 05 (December 16, 2011)
Global
Corrected all references in the text to the sector erase time-out period from 80 µs to 50 µs.
60
S29JL064J
S29JL064J_00_05 December 16, 2011
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2010-2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
December 16, 2011 S29JL064J_00_05
S29JL064J
61
相关型号：
S29NS-N_07
256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory
SPANSION
©2020 ICPDF网 联系我们和版权申明